LINER LTC3546 Dual synchronous, 3a/1a or 2a/2a configurable step-down dc/dc regulator Datasheet

LTC3546
Dual Synchronous, 3A/1A
or 2A/2A Configurable
Step-Down DC/DC Regulator
Description
Features
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VIN Range: 2.25V to 5.5V
VOUT Range: 0.6V to 5V
Programmable Frequency Operation; 2.25MHz, or
Adjustable Between 0.75MHz to 4MHz
Low RDS(ON) Internal Switches
High Efficiency: Up to 96%
No Schottky Diodes Required
Short-Circuit Protected
Current Mode Operation for Excellent Line and Load
Transient Response
Low Ripple Burst Mode Operation (30mVP-P),
IQ = 160µA
Ultralow Shutdown Current: IQ < 1µA
Low Dropout Operation: 100% Duty Cycle
Power Good Output For Each Channel
Externally or Internally Programmable Burst Level
External or Internal Soft-Start or Supply Tracking
Available in Thermally Enhanced 28-Lead
(4mm × 5mm) QFN and TSSOP Packages
Applications
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The LTC®3546 is a dual, constant-frequency, synchronous
step down DC/DC converter for medium power applications.
The design consists of 2A and 1A primary output switches.
In addition to the 2A/1A capability, a 1A dependant output
switch can be externally connected to either of the primary
outputs to produce 3A/1A dual regulator or 2A/2A dual
regulator configurations.
Supply operation is from 2.25V to 5.5V. The switching frequency can be set to 2.25MHz, adjustable from
0.75MHz to 4MHz, or synchronized to an external clock.
Each output is adjustable from 0.6V to 5V and has output
tracking on power-up. Internal synchronous low RDS(ON)
power switches provide high efficiency without external
Schottky diodes.
User-selectable modes (Burst Mode® operation, pulse
skipping and forced continuous) allow a trade-off between
ripple noise and power efficiency. Burst Mode operation
provides high efficiency at light loads. Pulse-skipping
mode provides low ripple noise at light loads.
The device is capable of low dropout configurations and
both channels can operate at 100% duty cycle. In shutdown, the device draws <1µA.
Netbooks/Ultra-Mobile PCs
PC Cards
Wireless and DSL Modems
Point of Load DC/DC Conversion
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 5481178, 6611131, 6304066, 6498466, 6580258.
Typical Application
CIN
22µF
VOUT2 Efficiency (Burst Mode Operation)
VIN1 VCCA VCCD VIN2
100
SYNC/MODE
VOUT2
2.5V, 3A
PGOOD1
PGOOD2
0.56µH
SW2B
100pF
SW1D
VIN
68µF
30.1k VIN
RUN2
LTC3546
VFB2
VFB1
BMC2
BMC1
TRACK/SS2
TRACK/SS1
PHASE
13k
PGND2
VIN
22µF
VIN
30.1k
30.1k
FREQ
ITH2
10pF
RUN1
PGND1
13k
10pF
EXPOSED PAD
85
80
70
0.001
1000pF
1000pF
1
EFFICIENCY
0.1
0.01
POWER LOSS
0.001
75
ITH1
GNDA
90
10
3546 TA01a
POWER LOSS (W)
100pF
100
SW1D CONNECTED TO SW2
VIN = 3.6V
95 VOUT = 2.5V
VOUT1
1.2V, 1A
SW1
SW2A
95.3k
1.22µH
EFFICIENCY (%)
VIN
3.6V TO
5.5V
1
0.01
0.1
LOAD CURRENT (A)
10
0.0001
3546 TA01b
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1
LTC3546
Absolute Maximum Ratings
(Note 1)
VIN1, VIN1D, VIN2, VCCA, VCCD Voltages.......... –0.3V to 6V
SYNC/MODE, SW1, SW1D, SW2A, SW2B,
RUN1, RUN2, VFB1, VFB2, PHASE, FREQ,
ITH1, ITH2, TRACK/SS1, TRACK/SS2, BMC1,
BMC2 Voltages................. –0.3V to (VIN1 or VIN2) + 0.3V
Maximum Difference Between Any of
VIN1, VIN1D, VIN2, VCCA, VCCD ...................................0.3V
PGOOD1, PGOOD2 Voltage........................... –0.3V to 6V
Operating Junction Temperature Range
(Notes 2, 6, 7)......................................... –40°C to 125°C
Storage Temperature Range.................... –65°C to 125°C
Pin Configuration
TOP VIEW
PGOOD1
27 FREQ
PGOOD2
3
26 PGOOD1
28 27 26 25 24 23
BMC2
4
25 BMC1
TRACK/SS2
5
24 TRACK/SS1
VFB2
6
23 VFB1
ITH2
7
VCCD
8
RUN2
9
FREQ
SYNC/MODE
GNDA
28 GNDA
2
VCCA
VCCA
1
PGOOD2
BMC2
SYNC/MODE
TOP VIEW
1
22 BMC1
TRACK/SS2 2
21 TRACK/SS1
VFB2 3
20 VFB1
ITH2 4
19 ITH1
29
VCCD 5
18 PHASE
RUN2 6
17 RUN1
VIN2 7
16 PGND2
VIN1 8
15 PGND1
PGND1D
SW1
SW1D
SW2B
VIN1D
SW2A
9 10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
29
22 ITH1
21 PHASE
20 RUN1
VIN2 10
19 PGND2
VIN1 11
18 PGND1
VIN1D 12
17 PGND1D
SW2A 13
16 SW1
SW2B 14
15 SW1D
FE PACKAGE
28-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 29) IS GNDD
TJMAX = 125°C, θJA = 25°C/W
EXPOSED PAD (PIN 29) IS GNDD MUST BE SOLDERED TO PCB
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3546EUFD#PBF
LTC3546EUFD#TRPBF
3546
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 85°C
LTC3546IUFD#PBF
LTC3546IUFD#TRPBF
3546
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3546EFE#PBF
LTC3546EFE#TRPBF
LTC3546FE
28-Lead Plastic TSSOP
–40°C to 85°C
LTC3546IFE#PBF
LTC3546IFE#TRPBF
LTC3546FE
28-Lead Plastic TSSOP
–40°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3546EUFD
LTC3546EUFD#TR
3546
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 85°C
LTC3546IUFD
LTC3546IUFD#TR
3546
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3546EFE
LTC3546EFE#TR
LTC3546FE
28-Lead Plastic TSSOP
–40°C to 85°C
LTC3546IFE
LTC3546IFE#TR
LTC3546FE
28-Lead Plastic TSSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
3546fc
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LTC3546
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = VCCA = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN1, VIN1D,
VIN2, VCCA,
VCCD
Operating Voltage Range
VIN1 = VIN1D = VIN2 = VCCA = VCCD
2.25
IFB1, IFB2
Feedback Pin Input Current
(Note 3)
VFB1, VFB2
Feedback Voltage
(Note 3)
ΔVLINEREG
Reference Voltage Line Regulation
%/V is The Percentage Change in VOUT
with a Change in VIN
VIN = 2.25V to 5.5V (Note 3)
ΔVLOADREG
Output Voltage Load Regulation
ITH1, ITH2 = 0.36V (Note 3)
ITH1, ITH2 = 0.84V (Note 3)
gm(EA)
Error Amplifier Transconductance
(Note 3)
VTRACK/SS1,
VTRACK/SS2
Tracking Voltage Offset
VTRACK/SS1,2 = 0.3V
ITRACK/SS1,
ITRACK/SS2
Tracking Current Source
VTRACK/SS1,2 = 0V
IS
Input DC Supply Current (Note 4)
fOSC
l
0.588
l
l
TYP
MAX
V
±0.1
µA
0.6
0.612
V
0.04
0.2
%/V
0.02
–0.02
0.2
–0.2
%
%
1400
0.8
UNITS
5.5
µS
15
mV
1.15
1.5
µA
Active Mode
VFB1 = VFB2 = 0.55V, VMODE = VIN,
VRUN1 = VRUN2 = VIN
600
990
µA
Half Active Mode (VRUN1 = VIN, VRUN2 = 0)
VFB1 = 0.55V, VMODE = VIN, VRUN1 = VIN,
VRUN2 = 0V
400
800
µA
Half Active Mode (VRUN1 = 0, VRUN2 = VIN)
VFB2 = 0.55V, VMODE = VIN, VRUN1 = 0V,
VRUN2 = VIN
400
800
µA
Both Channels in Sleep Mode
VFB1 = VFB2 = 0.75V, VMODE = VIN,
VRUN1 = VRUN2 = VIN
160
300
µA
Shutdown
VRUN1 = VRUN2 = 0V
0.2
1
µA
Oscillator Frequency
VFREQ: RT = VIN
VFREQ: RT = 143k
VFREQ: Resistor (Note 5)
1.8
1.2
0.75
2.25
1.5
2.9
1.8
4
l
MHz
MHz
MHz
ILIM1
Peak Switch Current Limit on SW1 (1A)
BMC1 = VIN, VITH1 = 1.4V
BMC1 = 0.4V, VITH1 = 0V
1.4
1.6
0.45
A
A
ILIM2
Peak Switch Current Limit on SW2A/B (2A) BMC2 = VIN, VITH1 = 1.4V
BMC2 = 0.4V, VITH1 = 0V
2.8
3.2
0.9
A
A
ILIM1+1D
Peak Switch Current Limit on
SW1 + SW1D (2A)
SW1 Externally Connected to SW1D
BMC1 = VIN (Note 8)
BMC1 = 0.4V (Note 8)
2.5
3.2
1.6
A
A
ILIM2+1D
Peak Switch Current Limit on
SW2A/B + SW1D (3A)
SW2A/B Externally Connected to SW1D
BMC2 = VIN (Note 8)
BMC2 = 0.4V (Note 8)
3.75
4.8
2.4
A
A
RDS(ON)1
SW1 Top Switch On-Resistance (1A)
SW1 Bottom Switch On-Resistance
VIN2 = 3.6V
VIN2 = 3.6V
0.19
0.18
Ω
Ω
RDS(ON)1D
SW1D Top Switch On-Resistance (1A)
SW1D Bottom Switch On-Resistance
VIN2 = 3.6V
VIN2 = 3.6V
0.19
0.17
Ω
Ω
RDS(ON)2
SW2A/B Top Switch On-Resistance (2A)
SW2A/B Bottom Switch On-Resistance
VIN1 = 3.6V
VIN1 = 3.6V
0.096
0.085
Ω
Ω
ISW1(LKG)
Switch Leakage Current SW1
VIN = 6V
VITH1 = 0V
VRUN1 = 0V
0.01
1
µA
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3
LTC3546
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = VCCA = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
TYP
MAX
ISW1D(LKG)
Switch Leakage Current SW1D
VIN = 6V
VITH1 = VITH2 = 0V
VRUN1 = VRUN2 = 0V
MIN
0.01
1
µA
ISW2A/B(LKG)
Switch Leakage Current SW2A/B
VIN = 6V
VITH2 = 0V
VRUN2 = 0V
0.01
1
µA
VUVLO
Undervoltage Lockout Threshold
VIN1, VIN2, VCCA, VCCD Rising
VIN1, VIN2, VCCA, VCCD Falling
2.14
1.97
2.2
2.03
V
V
TPGOOD1
Threshold for Power Good
Percentage Deviation from Regulated VFB1
(Typically 0.6V).
VFB1 Ramping Up, VSYNC/MODE = 0V
–8
%
TPGOOD2
Threshold for Power Good
Percentage Deviation from Regulated VFB2
(Typically 0.6V).
VFB2 Ramping Up, VSYNC/MODE = 0V
–8
%
RPGOOD1
Power Good Pull-Down On-Resistance
132
300
Ω
RPGOOD2
Power Good Pull-Down On-Resistance
132
300
Ω
tSS
Soft-Start Internal Time.
0.8
1.2
1.9
ms
0.3
0.8
1.2
V
±0.01
±1
µA
0.5
V
VFB from 0% to 95%, VTRACK/SS Is Floating
VRUN1, VRUN2, RUN1, RUN2, and PHASE Threshold
VPHASE
IRUN1, IRUN2,
IPHASE
2.03
1.86
RUN1, RUN2, and PHASE Leakage Current VIN = 6V, VPHASE = 3V, VRUN1 = VRUN2 = 3V
VTLSYNC/MODE SYNC/MODE Threshold Voltage Low to Put
the Part into Pulse-Skipping Mode
VTHSYNC/MODE SYNC/MODE Threshold Voltage High to
Put the Part into Burst Mode Operation
VSYNC/MODE
SYNC/MODE Threshold for Clock
Synchronization
ISYNC/MODE
SYNC/MODE Leakage Current
VTHFREQ
FREQ Threshold Voltage High
IBMC1, IBMC2
BMC1, BMC2 Leakage Current
VIN – 0.5
0.3
VIN = 6V, VSYNC/MODE = 3V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3546 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3546E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3546I is guaranteed
to meet performance specifications over the full –40°C to 125°C operating
junction temperature range. The maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 3: The LTC3546 is tested in feedback loop which servos VFB1 to the
midpoint for the error amplifier (VITH1 = 0.6V) and VFB2 to the midpoint for
the error amplifier (VITH2 = 0.6V).
4
V
0.8
1.2
V
±0.01
±1
µA
±0.4
µA
VIN – 0.85
VIN = 6V, VBMC = 3V
UNITS
V
Note 4: Total supply current is higher due to the internal gate charge being
delivered at the switching frequency.
Note 5: Variable frequency operation with resistor is guaranteed by design
and is subject to duty cycle limitations.
Note 6: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 7: TJ is calculated from the ambient temperature, TA, and power
dissipation, PD, according to the following formula:
TJ = TA + (PD • 34°C/W)
Note 8: Minimum current limit is guaranteed by design and correlation to
the RDS(ON)1D, ILIM1 and ILIM2 measurements.
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LTC3546
Typical Performance Characteristics
OUT1 Pulse-Skipping Mode
Operation
OUT1 Burst Mode Operation
VOUT
20mV/DIV
ILOAD
500mA/DIV
2µs/DIV
OUT1 Forced Continuous Mode
Operation
VOUT
20mV/DIV
VOUT
20mV/DIV
ILOAD
250mA/DIV
ILOAD
250mA/DIV
3546 G02
1µs/DIV
3546 G03
1µs/DIV
3546 G04
SW1D CONNECTED TO SW1
VIN = 3.6V
VOUT = 1.8V
ILOAD = 300mA
SW1D CONNECTED TO SW1
VIN = 3.6V
VOUT = 1.2V
ILOAD = 100mA
SW1D CONNECTED TO SW1
VIN = 3.6V
VOUT = 1.2V
ILOAD = 100mA
OUT1 Burst Mode Operation
OUT1 Pulse-Skipping Mode
Operation
OUT1 Forced Continuous Mode
Operation
VOUT
20mV/DIV
ILOAD
200mA/DIV
1µs/DIV
VOUT
20mV/DIV
VOUT
20mV/DIV
ILOAD
250mA/DIV
ILOAD
250mA/DIV
3546 G05
1µs/DIV
VOUT
20mV/DIV
ILOAD
500mA/DIV
3546 G08
OUT2 Forced Continuous Mode
Operation
VOUT
20mV/DIV
VOUT
20mV/DIV
ILOAD
500mA/DIV
ILOAD
500mA/DIV
1µs/DIV
SW1D CONNECTED TO SW2
VIN = 3.6V
VOUT = 1.8V
ILOAD = 200mA
3546 G07
SW1D CONNECTED TO SW2
VIN = 3.6V
VOUT = 1.2V
ILOAD = 50mA
OUT2 Pulse-Skipping Mode
Operation
OUT2 Burst Mode Operation
SW1D CONNECTED TO SW2
VIN = 3.6V
VOUT = 2.5V
ILOAD = 500mA
1µs/DIV
SW1D CONNECTED TO SW2
VIN = 3.6V
VOUT = 1.2V
ILOAD = 100mA
SW1D CONNECTED TO SW2
VIN = 3.6V
VOUT = 1.8V
ILOAD = 200mA
1µs/DIV
3546 G06
3546 G09
1µs/DIV
3546 G10
SW1D CONNECTED TO SW2
VIN = 3.6V
VOUT = 1.8V
ILOAD = 100mA
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LTC3546
Typical Performance Characteristics
ILOAD
500mA/DIV
ILOAD
250mA/DIV
OUT1 Efficiency vs Load Current
85
85
75
1
80
75
60
0.001
10
3546 G14
80
75
Burst Mode
OPERATION
PULSE SKIP
FORCED
CONTINUOUS
1
75
60
0.001
1
10
96
96
3546 G17
400mA
90
88
86
2A
10
3546 G16
94
92
88
86
84
82
82
3.75 4.25
VIN (V)
4.75
5.25
3546 G18
200mA
90
84
3.25
1
SW1D CONNECTED TO SW2
98 VOUT = 1.8V
94
2.75
0.1
ILOAD (A)
OUT1 Efficiency vs VIN
100
80
2.25
0.01
3546 G15
100
92
Burst Mode
OPERATION
PULSE SKIP
FORCED
CONTINUOUS
65
EFFICIENCY (%)
EFFICIENCY (%)
85
0.1
ILOAD (A)
80
70
SW1D CONNECTED TO SW1
98 VOUT = 1.8V
90
0.01
85
OUT1 Efficiency vs VIN
SW1D CONNECTED TO SW1
95 VIN = 3.6V
VOUT = 2.5V
60
0.001
0.1
0.01
ILOAD (A)
OUT2 Efficiency vs Load Current
65
Burst Mode
OPERATION
PULSE SKIP
FORCED
CONTINUOUS
65
100
70
90
70
Burst Mode
OPERATION
PULSE SKIP
FORCED
CONTINUOUS
0.1
ILOAD (A)
SW1D CONNECTED TO SW2
95 VIN = 3.6V
VOUT = 2.5V
EFFICIENCY (%)
80
0.01
OUT2 Efficiency vs Load Current
100
SW1D CONNECTED TO SW2
VIN = 3.6V
90 V
OUT = 1.8V
EFFICIENCY (%)
EFFICIENCY (%)
SW1D CONNECTED TO SW1
VIN = 3.6V
90 V
OUT = 1.8V
60
0.001
SW1D CONNECTED TO SW1
VIN = 3.6V
VOUT = 1.8V
ILOAD = 100mA
OUT1 Efficiency vs Load Current
95
3546 G13
1µs/DIV
SW1D CONNECTED TO SW1
VIN = 3.6V
VOUT = 1.8V
ILOAD = 200mA
95
65
3546 G12
1µs/DIV
SW1D CONNECTED TO SW1
VIN = 3.6V
VOUT = 2.5V
ILOAD = 300mA
70
ILOAD
250mA/DIV
3546 G11
1µs/DIV
EFFICIENCY (%)
VOUT
20mV/DIV
VOUT
20mV/DIV
VOUT
20mV/DIV
6
OUT2 Forced Continuous Mode
Operation
OUT2 Pulse-Skipping Mode
Operation
OUT2 Burst Mode Operation
80
2.25
1A
2.75
3.25
3.75 4.25
VIN (V)
4.75
5.25
3546 G19
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LTC3546
Typical Performance Characteristics
OUT2 Efficiency vs VIN
100
98
98
96
96
94
94
600mA
92
EFFICIENCY (%)
90
88
3A
86
OUT2 Efficiency vs VIN
VOUT
100mV/DIV
400mA
92
90
88
86
84
82 SW1D CONNECTED TO SW2
VOUT = 2.5V
80
2.25 2.75 3.25 3.75 4.25
VIN (V)
82 SW1D CONNECTED TO SW1
VOUT = 2.5V
80
2.25 2.75 3.25 3.75 4.25
VIN (V)
5.25
3546 G20
OUT1 Load Step
4.75
SW1D CONNECTED TO SW1
VIN = 3.6V
VOUT = 1.2V
ILOAD = 200mA TO 1.9A
5.25
3546 G21
OUT2 Load Step
VOUT
100mV/DIV
ILOAD
250mA/DIV
VOUT
100mV/DIV
ILOAD
1A/DIV
100µs/DIV
ILOAD
1A/DIV
3546 G23
100µs/DIV
SW1D CONNECTED TO SW2
VIN = 3.6V
VOUT = 1.2V
ILOAD = 100mA TO 0.9A
3546 G24
OUT1 Efficiency vs Frequency
SW1D CONNECTED TO SW1
VIN = 3.6V
VOUT = 1.8V
ILOAD = 200mA TO 1.9A
OUT2 Efficiency vs Frequency
OUT1 Efficiency vs Frequency
95
95
94
94
94
93
93
93
92
92
92
EFFICIENCY (%)
95
90
89
88
SW1D CONNECTED TO SW1
87 V = 3.6V
IN
86 VOUT = 1.8V
ILOAD = 400mA
85
0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (MHz)
3.5
4.0
91
90
89
88
SW1D CONNECTED TO SW2
87 V = 3.6V
IN
86 VOUT = 1.8V
ILOAD = 200mA
85
0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (MHz)
3546 G25
100µs/DIV
SW1D CONNECTED TO SW2
VIN = 3.6V
VOUT = 1.8V
ILOAD = 300mA TO 2.9A
91
3546 G22
100µs/DIV
OUT2 Load Step
VOUT
100mV/DIV
EFFICIENCY (%)
ILOAD
1A/DIV
2A
84
4.75
OUT1 Load Step
EFFICIENCY (%)
EFFICIENCY (%)
100
3.5
3546 G26
4.0
3546 G27
91
90
89
88
SW1D CONNECTED TO SW2
87 V = 3.6V
IN
86 VOUT = 2.5V
ILOAD = 600mA
85
0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (MHz)
3.5
4.0
3546 G28
3546fc
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7
LTC3546
Typical Performance Characteristics
OUT1 RDS(ON) vs VIN
0.24
94
0.115
0.23
93
0.110
0.22
92
0.105
91
0.100
89
88
SW1D CONNECTED TO SW1
87 V = 3.6V
IN
86 VOUT = 2.5V
ILOAD = 400mA
85
0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (MHz)
4.0
3546 G29
0.090
0.16 SW1D CONNECTED TO SW2
TA = 27°C
0.15
2.0 2.5 3.0 3.5 4.0
VIN (V)
0.120
0.050
2.0
2.5
3.0
3.5 4.0
VIN (V)
0.095
0.090
N-CHANNEL IMP
0.080
4.5
5.0
5.5
3546 G32
Frequency Variation vs
Temperature
4.0
PEAK CURRENT (A)
3.0
–1
–2
–3
2.5
–5
0.5
0
55
50
75
TEMPERATURE (°C)
4.5
5.0
5.5
100
125
3546 G35
FREQ 143k TO GND
FREQ TO VIN
–2
–4
–6
–10
2.0
2.5
3546 G33
3.0
3.5 4.0
VIN (V)
4.5
5.0
5.5
3546 G34
OUT2 Minimum Peak Current
vs VBMC2
6
VIN = 3.6V
VIN = 3.6V
5
SW1D TO SW2
SW1D TO SW1
1.5
1.0
3546 G31
–8
2.0
–4
5.5
0
3.5
0
5.0
2
OUT1 Minimum Peak Current
vs VBMC1
FREQ 143k TO GND
FREQ TO VIN
–25
P-CHANNEL IMP
0.075 SW1D CONNECTED TO SW1
TA = 27°C
0.070
2.0 2.5 3.0 3.5 4.0
VIN (V)
4.5
Frequency Variation vs VIN
6
FREQUENCY VARIATION (%)
RDS(ON) (Ω)
RDS(ON) (Ω)
3546 G30
4
0.100
0.085
N-CHANNEL IMP
FREQUENCY VARIATION (%)
5.5
OUT2 RDS(ON) vs VIN
0.105
0.055
–6
–50
5.0
0.115
0.060
1
4.5
0.110
P-CHANNEL IMP
N-CHANNEL IMP
0.075 SW1D CONNECTED TO SW1
TA = 27°C
0.070
2.0 2.5 3.0 3.5 4.0
VIN (V)
0.070
2
0.18
N-CHANNEL IMP
0.17
SW1D CONNECTED TO SW2
TA = 27°C
0.065
0.19
0.080
OUT2 RDS(ON) vs VIN
0.075
P-CHANNEL IMP
0.20
PEAK CURRENT (A)
0.080
0.095
0.085
3.5
0.21
P-CHANNEL IMP
RDS(ON) (Ω)
90
8
OUT1 RDS(ON) vs VIN
0.120
RDS(ON) (Ω)
EFFICIENCY (%)
OUT2 Efficiency vs Frequency
95
SW1D TO SW2
4
3
2
SW1D TO SW1
1
0
0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95
VBMC1 (V)
3546 G36
0
0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95
VBMC1 (V)
3546 G37
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LTC3546
Pin Functions
(UFD/FE)
BMC2 (Pin 1/Pin 4): Burst Mode Clamp for Channel 2.
Connecting this pin to an external voltage between 0V and
0.6V sets the Burst Mode clamp level. If this pin is pulled
to VCCA, an internal Burst Mode clamp level is used. This
pin should be tied to GND when Burst Mode operation is
not selected.
SW2B (Pin 11/Pin 14): Half of the switch node connection to the inductor for Channel 2 SW2A and SW2B must
be externally tied together. This pin swings from VIN2 to
PGND2.
TRACK/SS2 (Pin 2/Pin 5): Tracking input for Channel 2
output or optional external soft-start input. VOUT2 will track
an external voltage at this pin. Leaving this pin floating
allows VOUT2 to start-up using the internal soft-start. An
external soft-start can be programmed by connecting a
capacitor between this pin and ground. External soft-start
ramp time must be greater than the internal soft-start time
of 1.2ms. Refer to the Applications Information section
for more details.
SW1D (Pin 12/Pin 15): The Dependent Switch Node
Connection. The pin is externally connected to SW1 for
a 2A/2A regulator or to SW2A/B for a 3A/1A regulator.
Internal circuitry detects which pin SW1D is externally
connected to, SW1 or SW2A/B. This pin swings from
VIN1D to PGND1D. SW1D switching will be controlled
by the output switch to which it is connected, i.e., SW1
or SW2A/SW2B. The dependant 1A power stage can be
disabled by floating the SW1D pin. The SW1D pin must
never be connected to VIN or GND. When disabled, SW1D
is pulled high internally.
VFB2 (Pin 3/Pin 6): Feedback voltage from external resistive divider from the Channel 2 regulator output. Nominal
voltage for this pin is 0.6V.
SW1 (Pin 13/Pin 16): The switch node connection to the
Inductor for the Channel 1 regulator. This pin swings from
VIN1 to PGND1.
ITH2 (Pin 4/Pin 7): Error Amplifier Compensation for Channel 2 Regulator. Peak current increases with an increase
in the voltage on this pin. Nominal voltage range for this
pin is 0V to 1.5V.
PGND1D (Pin 14/Pin 17): Ground for SW1D Switching
N-Channel Driver.
VCCD (Pin 5/Pin 8): Supply Pin for Internal Digital Circuitry.
RUN2 (Pin 6/Pin 9): Low Level Logic Input. Enable for
Channel 2. When pulled high, regulator is running. When
at 0V, regulator is off. When both RUN1 and RUN2 are at
0V the part is in shutdown.
VIN2 (Pin 7/Pin 10): Supply pin for 2A P-channel switch
which connects from VIN2 to SW2A/B.
VIN1 (Pin 8/Pin 11): Supply pin for 1A P-channel switch
which connects from VIN1 to SW1.
VIN1D (Pin 9/Pin 12): Supply pin for 1A dependent P-channel switch which connects from VIN1D to SW1D.
SW2A (Pin 10/Pin 13): Half of the switch node connection to the inductor for Channel 2. SW2A and SW2B must
be externally tied together. This pin swings from VIN2 to
PGND2.
PGND1 (Pin 15/Pin 18): Ground for SW1 Switching NChannel Driver.
PGND2 (Pin 16/Pin 19): Ground for SW2A and SW2B
Switching N-Channel Driver.
RUN1 (Pin 17/Pin 20): Low Level Logic Input. Enable for
Channel 1. When pulled high, regulator is running. When
at 0V, regulator is off. When both RUN1 and RUN2 are at
0V the part is in shutdown.
PHASE (Pin 18/Pin 21): Low Level Logic Input. Selects
Channel 2 regulator switching phase with respect to
Channel 1 regulator switching. When pulled high, the
SW1 regulator and the SW2A/B regulator are in phase.
When PHASE is at 0V the SW1 regulator and the SW2A/B
regulator are switching 180° out-of-phase.
ITH1 (Pin 19/Pin 22): Error Amplifier Compensation for
Channel 1. Peak current increases with an increase in the
voltage on this pin. Nominal voltage range for this pin is
0V to 1.5V.
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9
LTC3546
Pin Functions
(UFD/FE)
VFB1 (Pin 20/Pin 23): Feedback voltage from external
resistive divider from Channel 1 output. Nominal voltage
for this pin is 0.6V.
When using external synchronization this pin compensates
the internal PLL. Typical compensation components are a
200k resistor in series with a 100pF capacitor.
TRACK/SS1 (Pin 21/Pin 24): Tracking input for Channel 1
output or optional external soft-start input. VOUT1 will track
an external voltage at this pin. Leaving this pin floating
allows VOUT1 to start-up using the internal soft-start. An
external soft-start can be programmed by connecting a
capacitor between this pin and ground. External soft-start
ramp time must be greater than the internal soft-start time
of 1.2ms. Refer to the Applications Information section
for more details.
GNDA (Pin 25/Pin 28): Ground Pin for Internal Analog
Circuitry.
BMC1 (Pin 22/Pin 25): Burst Mode Clamp for Channel 1.
Connecting this pin to an external voltage between 0V and
0.6V sets the Burst Mode clamp level. If this pin is pulled
to VCCA, an internal Burst Mode clamp level is used. This
pin should be tied to GND when Burst Mode operation is
not selected.
PGOOD1 (Pin 23/Pin 26): Power Good Pin for the 1A
Regulator. This common drain logic output is pulled to
GND when the output voltage of Channel 1 is below –8%
of regulation.
FREQ (Pin 24/Pin 27): Frequency Set Pin. When FREQ is
at VCCA, the internal oscillator runs at 2.25MHz. When a
resistor is connected from this pin to GNDA, the internal
oscillator frequency can be varied from 0.75MHz to 4MHz.
10
VCCA (Pin 26/Pin 1): Supply Pin for Internal Analog Circuitry.
SYNC/MODE (Pin 27/Pin 2): Combination Mode Selection and Oscillator Synchronization Pin. This pin controls
the operation of the device. When the voltage on the
SYNC/MODE pin is > (VIN – 0.5V), Burst Mode operation
is selected for both regulators. When the voltage on the
SYNC/MODE pin is <0.5V, pulse-skipping mode is selected
for both regulators. When the SYNC/MODE pin is held at
VIN/2, forced continuous mode is selected for both regulators. The oscillation frequency can be synchronized to an
external oscillator applied to this pin. When synchronized
to an external clock, pulse-skipping mode is selected.
PGOOD2 (Pin 28/Pin 3): Power Good Pin for Channel 2
This common drain logic output is pulled to GND when the
output voltage of Channel 2 is below –8% of regulation.
GNDD (Exposed Pad Pin 29/Exposed Pad Pin 29): Digital
Ground. Connect to Electrical Ground for substrate and
internal digital circuitry. Solder to PCB for rated thermal
performance.
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LTC3546
Functional Diagram
ITH1
BMC1
1A REGULATOR
ITH LIMIT
+
+
–
VFB1
–
–
VB
0.552V
VIN1
+
SLOPE
COMPENSATION
+
SW1
ANTI-SHOOT
THRU
–
+
+
LOGIC
0.63V
–
–
RUN1
–
VCCA
1.15µA
TRACK/SS1
INTERNAL
SOFT-START
PGND1
+
PGOOD1
MUX
VOLTAGE
REFERENCE
PHASE
SYNC/MODE
OSCILLATOR
FREQ
VIN1D
VCCA
1A DEPENDENT
SWITCHES
GNDA
DEPENDENT SWITCH
AUTO DETECT AND CONTROL
SW1D
ANTI-SHOOT
THRU
MUX
VCCD
PGND1D
GNDD
PGOOD2
VCCA
1.15µA
INTERNAL
SOFT-START
TRACK/SS2
PGND2
+
MUX
–
RUN2
0.63V
–
–
LOGIC
+
+
SW2A
–
0.552V
VFB2
SW2B
ANTI-SHOOT
THRU
+
VB
SLOPE
COMPENSATION
+
–
–
–
+
ITH LIMIT
ITH2
BMC2
+
2A REGULATOR
VIN2
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11
LTC3546
Operation
The LTC3546 uses a constant-frequency, current mode architecture. Both channels share the same clock frequency. The
PHASE pin sets whether the channels are running in-phase,
or 180° out-of-phase. The operating frequency is determined
by connecting the FREQ pin to VIN for 2.25MHz operation or
by connecting a resistor from FREQ to GNDA for frequencies
between 0.75MHz to 4MHz. A 143k resistor to GNDA will set
the frequency to 1.5MHz. The part can also be synchronized
to an external clock through the SYNC/MODE pin. To suit
a variety of applications, the selectable SYNC/MODE pin
allows the user to trade-off noise for efficiency.
The output voltages are set by external dividers returned
to the VFB1 and VFB2 pins. An error amplifier compares the
divided output voltage with a reference voltage of 0.6V and
adjusts an internal peak inductor current setting accordingly. Peak inductor current during Burst Mode operation
can also be set externally through the BMC1 and BMC2
pins. Undervoltage comparators will pull the PGOOD1 or
PGOOD2 outputs low when their respective outputs drop
below –8% of the set output voltage.
The TRACK/SS pins allow for controlled start-up via an
externally or internally generated voltage ramp. It can also
track an externally applied voltage.
A 1A dependent switch, SW1D, can be externally connected
to the SW1 output or the SW2A/SW2B output. Internal
circuitry auto detects which output SW1D is connected
to and controls them accordingly. With this flexibility, the
LTC3546 can be configured as either a 2A/2A dual regulator (when SW1D is connected to SW1) or as a 3A/1A dual
regulator (when SW1D is connected to SW2A/SW2B).
Main Control Loop
For each regulator, during normal operation, the P-channel MOSFET power switch is turned on at the beginning
of a clock cycle when the VFB voltage is below the 0.6V
reference voltage. The current into the inductor and the
load increases until the current limit is reached. The switch
turns off and energy stored in the inductor flows through
the bottom N-channel MOSFET switch into the load until
the next clock cycle.
12
The peak inductor current is controlled by the voltage on the
ITH pin, which is the output of the 2.5MHz bandwidth error
amplifier. The error amplifier compares the VFB pin to the
0.6V reference. When the load current increases, the VFB
voltage decreases slightly below the reference. This decrease
causes the error amplifier to increase the ITH voltage until the
average inductor current matches the new load current.
The main control loop is shut down by pulling the RUN pin
to ground. When the RUN pin is pulled high, the control
loop goes through start-up. Start-up is dependent on the
TRACK/SS pin. If TRACK/SS is left floating, an internal
soft-start is enabled which will ramp up the output voltage to the desired level in 1.2ms. The output voltage will
track the voltage on its associated TRACK/SS pin. If the
TRACK/SS pin is connected through a resistor divider
from another supply, such as the output voltage from
the other LTC3546 regulator, the output voltage will track
this supply thus allowing the LTC3546 output voltage to
track the other supply start-up. If a capacitor is connected
from the TRACK/SS pin to ground, when RUN goes high,
an internal 1.15µA current source will charge the external
capacitor controlling the output voltage start-up. Care must
be taken to make sure the external start-up ramp time is
greater than the 1.2ms internal start-up time.
Low Current Operation
Three modes are available to control the operation of the
LTC3546 at low currents. All three modes automatically
switch from continuous operation to the selected mode
when the load current is low.
To optimize efficiency, Burst Mode operation can be selected.
When the load is relatively light, the LTC3546 automatically
switches into Burst Mode operation in which the switches
operate intermittently based on load demand. By running
cycles periodically, the switching losses which are dominated by the gate charge losses of the power MOSFETs are
minimized. The main control loop is interrupted when the
output voltage reaches the desired regulated value.
A voltage comparator with hysteresis trips when ITH is below
0.24V, shutting off the switches and reducing the power.
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LTC3546
Operation
The output capacitor and the inductor supply the power
to the load until ITH exceeds 0.31V, turning on the switch
and the main control loop which starts another cycle.
continuous operation, an overvoltage comparator monitors
the VFB pin and decreases the current limit whenever an
overvoltage condition is detected (VFB > 0.63V).
The Burst Mode peak inductor current can be set externally
via the BMC pin. When this pin is set somewhere between
0V to 0.6V, the voltage on this pin controls the Burst Mode
clamp level. When the BMC pin is pulled to VIN, an internal
Burst Mode clamp level is used.
The SYNC/MODE pin selects what mode the LTC3546 is in.
The SYNC/MODE pin sets the mode for both regulators.
For lower output voltage ripple at low currents, pulseskipping mode can be used. In this mode, the LTC3546
continues to switch at constant frequency down to very low
currents, where it will eventually begin skipping pulses.
Finally, in forced continuous mode, the inductor current
is constantly cycled which creates a fixed output voltage
ripple at all output current levels. This feature is desirable in
telecommunications since the noise is a constant frequency
and is thus easy to filter out. Another advantage of this mode
is that the regulator is capable of both sourcing current into
a load and sinking some current from the output. In forced
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which
is the dropout condition. In the dropout condition, the
PMOS switch is turned on continuously with the output
voltage being equal to the input voltage minus the voltage drops across the internal P-channel MOSFETs and
inductors.
Low Supply Operation
The LTC3546 incorporates an undervoltage lockout circuit
which shuts down the part when the input voltage drops
below about 2.14V to prevent unstable operation.
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13
LTC3546
Applications Information
A general LTC3546 application circuit is shown in Figure 7.
External component selection is driven by the load requirement, and begins with the selection of the inductors L1,
and L2. Once L1 and L2 are chosen, CIN, COUT1, and COUT2
can be selected.
Assuming a worst-case minimum on-time of 150ns, this
can be calculated as:
Operating Frequency
The minimum frequency is limited by leakage and noise
coupling due to the large resistance of RT.
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency, fO, of the LTC3546 is determined
by pulling the FREQ pin to VIN, for 2.25MHz operation, by
connecting an external resistor from FREQ to ground, or
by driving an external clock signal into SYNC/MODE.
When using an external resistor to set the oscillator frequency use the following equation:
2.51•1011
RT =
(Ω) – 20kΩ
fO
for 0.75MHz ≤ fO ≤ 4MHz. Or use Figure 1 to select the
value for RT.
The maximum operating frequency is also constrained
by the minimum on-time (typically 70ns) and duty cycle,
especially when forced continuous mode is selected.
⎛ V
⎞
fO(MAX) ≈ 6.67 ⎜ OUT ⎟ (MHz )
⎝ VIN(MAX) ⎠
Inductor Selection
Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current ΔIL decreases with
higher inductance and increases with higher VIN or VOUT.
ΔIL =
VOUT ⎛ VOUT ⎞
1−
fO •L ⎜⎝
VIN ⎟⎠
Accepting larger values of ΔIL allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.
A reasonable starting point for setting ripple current is ΔIL
= 0.35ILOAD(MAX), where ILOAD(MAX) is the maximum output
current. The largest ripple ΔIL occurs at the maximum
input voltage. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
L≥
⎞
VOUT ⎛
V
1− OUT ⎟
⎜
fO • ΔIL ⎝ VIN(MAX) ⎠
500
450
400
RT (kΩ)
350
300
250
200
150
100
50
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
FREQUENCY (MHz)
3546 F01
Figure 1. Frequency vs RT
14
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LTC3546
Applications Information
Burst Mode Operation Considerations
Inductor Core Selection
There are two factors that determine the load current at which
the LTC3546 enters Burst Mode operation: the inductor value
and the BMC pin voltage. The transition from low current
operation begins when the peak inductor current falls below
a level set by the burst clamp. Lower inductor values result in
higher ripple current which causes Burst Mode operation to
occur at lower load currents. Lower inductor values will also
cause a dip in efficiency in the upper range of low current
operation. Lower inductor values will also cause the burst
frequency to increase in Burst Mode operation.
Different core materials and shapes will change the size/current relationship of an inductor. Toroid or shielded pot cores
in ferrite or permalloy materials are small and don’t radiate
much energy, but generally cost more than powdered iron
core inductors with similar electrical characteristics. The
choice of which style inductor to use often depends more
on the price vs size requirements of any radiated field/EMI
requirements than on what the LTC3546 requires to operate. Table 1 shows some typical surface mount inductors
that work well in LTC3546 applications.
The burst clamp level can be set by the voltage on the BMC
pin. If BMC is tied to VIN, an internally set level is used. A
BMC pin voltage between 0V and 0.6V will set the burst
clamp level (see charts OUT1 Minimum Peak Current vs
VBMC1 and OUT2 Minimum Peak Current vs VBMC2 in the
Typical Performance Characteristics section). Generally, a
higher clamp level results in improved light load efficiency
and higher output voltage ripple, while a lower clamp level
results in small output voltage ripple at the expense of
efficiency. The BMC pin should be connected to ground
when Burst Mode operation is not selected.
Input Capacitor (CIN) Selection
In continuous mode, the input current of the converter can
be approximated by the sum of two square waves with
duty cycles of approximately VOUT1/VIN and VOUT2/VIN. To
prevent large voltage transients, a low equivalent series
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. Some capacitors have a derating spec for maximum RMS current. If the capacitor
being used has this requirement it is necessary to calculate
Table 1.
MANUFACTURER
PART NUMBER
VALUE (µH)
MAX DC CURRENT (A)
DCR
DIMENSIONS L × W × H (mm)
Würth Elektronik
WE-PD2 MS
7447745012
1.2
4.6
0.017
5.2 × 5.8 × 2
Würth Elektronik
WE-PD2 MS
74477450056
0.56
6.5
0.0078
5.2 × 5.8 × 2
Vishay
IHLP-1616AB-11
1.2
3.75
0.068
4.06 × 4.45 × 1.20
Vishay
IHLP-1616AB-11
0.47
6
0.019
4.06 × 4.45 × 1.20
Coilcraft
LPS6225-122
1.2
5.4
0.04
6.2 × 6.2 × 2.5
Coilcraft
DO1813H-561
0.56
7.7
0.01
6.10 × 8.89 × 5.00
SD20-1R2
1.2
2.55
0.0275
5.2 × 5.2 × 2
SD20-R47
0.47
4
0.02
5.2 × 5.2 × 2
CDRH3D23NP-1R5NC
1
2.8
0.025
3.8 × 3.8 × 2.3
Coiltronics
Coiltronics
Sumida
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15
LTC3546
Applications Information
the maximum RMS current. The RMS current calculation
is different if the part is used in-phase or out-of-phase.
For in-phase, there are two different equations:
VOUT1 > VOUT2:
IRMS =
(
) (
)
(
) (
)
2 •I1•I2 •D2 (1–D1) +I22 D2 –D22 +I12 D1–D12
VOUT2 > VOUT1:
IRMS =
2 •I1•I2 •D1(1–D2) +I22 D2 –D22 +I12 D1–D12
Where:
When D1 = D2, then the equation simplifies to:
IRMS = (I1+I2) D(1–D)
The selection of COUT1 and COUT2 is driven by the required
ESR to minimize voltage ripple and load step transients.
Typically, once the ESR requirement is satisfied, the
capacitance is adequate for filtering. The output ripple
(ΔVOUT) is determined by:
⎛
⎞
1
ΔVOUT ≈ ΔIL ⎜ ESR+
8• fO •COUT ⎟⎠
⎝
or
VOUT ( VIN – VOUT )
VIN
where the maximum average output currents I1 and
I2 equals the peak current minus half the peak-to-peak
ripple current:
ΔI
I1=ILIM1 – L1
2
ΔI
I2 =ILIM2 – L2
2
These formula have a maximum at VIN = 2VOUT, where
IRMS = (I1 + I2)/2. This simple worst-case is commonly
used to determine the worst-case IRMS.
For out-of-phase (PHASE pin is at ground), the ripple
current can be lower than the in-phase.
In the out-of-phase case, the maximum IRMS does not occur when VOUT1 = VOUT2. The maximum typically occurs
16
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours lifetime. This makes
it advisable to further derate the capacitor, or choose a
capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet the
size or height requirements of the design. An additional
0.1µF to 1µF ceramic capacitor is also recommended on
VIN for high frequency decoupling, when not using an all
ceramic capacitor solution.
Output Capacitor (COUT1 and COUT2) Selection
V
V
D1= OUT1 and D2 = OUT2
VIN
VIN
IRMS = (I1+I2)
when VOUT1 – VIN/2 = VOUT2 and when VOUT2 – VIN/2 =
VOUT1. As a good rule of thumb, the amount of worst-case
ripple is about 75% of the worst-case ripple in the in-phase
mode. Note, that when VOUT1 = VOUT2 = VIN/2 and I1 = I2,
the ripple is at its minimum.
where fO = operating frequency, COUT = output capacitance
and ΔIL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ΔIL increases
with input voltage.
Once the ESR requirements for COUT have been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitors are all available in surface mount packages.
The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any
aluminum electrolytic at a somewhat higher price. Special
polymer capacitors, such as Sanyo POSCAP, offer very
low ESR, but have a lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
3546fc
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LTC3546
Applications Information
density, but it has a larger ESR and it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surface tantalums, available in case heights ranging from
2mm to 4mm. Aluminum electrolytic capacitors have a
significantly larger ESR, and are often used in extremely
cost-sensitive applications provided that consideration
is given to ripple current ratings and long term reliability.
Ceramic capacitors have the lowest ESR and cost but also
have the lowest capacitance density, high voltage and
temperature coefficient and exhibit audible piezoelectric
effects. In addition, the high Q of ceramic capacitors along
with trace inductance can lead to significant ringing. Other
capacitor types include the Panasonic specialty polymer
(SP) capacitors.
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Because the
LTC3546 control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size. When choosing the input and output
ceramic capacitors, choose the X5R or X7R dielectric
formulations. These dielectrics have the best temperature
and voltage characteristics of all the ceramics for a given
value and size.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
disrupt circuit operation or damage the part.
to support the load. The time required for the feedback
loop to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4
cycles are required to respond to a load step, but only in
the first cycle does the output drop linearly. The output
droop, VDROOP, is usually about 2 to 3 times the linear
droop of the first cycle. Thus, a good place to start is with
the output capacitor size of approximately:
COUT ≈ 2.5
ΔIOUT
fOVDROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since impedance to
the supply is very low. A 10µF ceramic capacitor is usually
enough for these conditions.
Setting the Output Voltage
The LTC3546 generates a 0.6V reference voltage between
the feedback pin, VFB1 and VFB2, and the signal ground.
The output voltage is set by a resistive divider according
to the following formula:
⎛ R1⎞
VOUT1 ≈ 0.6V ⎜ 1+ ⎟
⎝ R2 ⎠
⎛ R3 ⎞
VOUT2 ≈ 0.6V ⎜ 1+ ⎟
⎝ R4 ⎠
Resistor locations are shown in Figure 2.
VOUT1
CFF1
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
VOUT2
R1
R3
CFF2
LTC3546
VFB1
R2
VFB2
3546 F02
R4
Figure 2. Setting Output Voltages
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17
LTC3546
Applications Information
Keeping the current small (<20µA) in these resistors
maximizes efficiency, but making the current too small
may allow stray capacitance to cause noise problems and
reduce the phase margin of the error amp loop.
To improve the frequency response, a feedforward capacitor
CFF may also be used. Typical values used here are 10pf to
100pf. Great care should be taken to route the VFB node away
from noise sources, such as the inductor or an SW line.
Shutdown, Soft-Start and Tracking Start-Up
The LTC3546 start-up works by comparing two inputs, an
internal 1.2ms linear soft-start ramp and the TRACK/SS
pin. Whichever input is lower in voltage is the controlling
voltage used for start-up. The internal start-up ramps
to 0.6V in 1.2ms. If a slower start-up is desired, the
TRACK/SS pin has a 1.15µA pull up current so a start-up
ramp rate can be programmed with an external capacitor,
or a voltage divider from another signal can be applied
to the TRACK/SS pin.
During start-up the controlling voltage must rise above
120mV before the output will start switching.
When the RUN pin is low, both the internal 1.2ms soft-start
ramp and the TRACK/SS pin are pulled to ground. When
the RUN pin is pulled high, both the internal soft-start ramp
and the TRACK/SS pin are released. From the time when
the RUN pin is asserted until the controlling voltage reaches
0.6V, the regulator is in the start-up state. In this state, the
error amplifier will compare the feedback signal at VFB to
the controlling voltage (the lower of either the TRACK/SS
voltage or the internal ramp voltage) and the regulator
will force them to be equal. In this state, the mode of the
regulator is forced to pulse skipping. The regulator will
continue in this manner until the voltage on the controlling voltage rises above 0.6V. Once the controlling ramp
signal is above 0.6V the error amplifier uses the internal
0.6V reference and the operational mode will switch to
the mode set by the SYNC/MODE pin.
If the TRACK/SS pin is ramped down after start-up, the
error amplifier will compare the feedback signal at VFB
to the voltage on the TRACK/SS pin once the TRACK/SS
voltage drops 6% below the internal reference voltage of
0.6V (0.564V). The regulator will try to force the VFB voltage
18
to equal the TRACK/SS voltage if there is sufficient load
current to pull the output low at this rate, otherwise the
output will ramp down at the discharge rate of the output
capacitor. Once the TRACK/SS voltage drops below about
100mV all switching functions cease and the regulator is
forced back into pulse-skipping mode. The operational
mode while TRACK/SS is ramping down is set by the
MODE/SYNC pin.
To use the internal 1.2ms linear soft-start controlling
voltage leave the TRACK/SS pin floating. By floating the
TRACK/SS pin the internal 1.15µA pull up current will pull
the TRACK/SS pin up faster than the internal 1.2ms ramp.
Care must be taken to insure the TRACK/SS ramp up time
(from 0V to 0.6V) is much shorter than the internal 1.2ms
ramp time. Parasitic capacitance on this pin should be
much smaller than:
CPARASITICTRACK/SS <<
1.15µA•1.2ms
0.6V
or
CPARASITICTRACK/SS << 2.3nF
An externally controlled soft-start ramp is obtained when
an external capacitor is connected from the TRACK/SS
pin to ground and its ramp rate is slower than the internal
soft-start ramp. In this configuration, soft-start times longer
than 1.2ms can be achieved. When RUN is pulled high, the
internal 1.15µA current source charges the external capacitor linearly from 0V. While the TRACK/SS pin is below 0.6V
the error amplifier forces the regulator to drive the VFB pin to
the voltage on the TRACK/SS pin. Once the VFB pin reaches
0.6V the regulator switches to the internal 0.6V reference.
The ramp-up time for the output is calculated as:
tRAMP =
CTRACK/SS •0.6V
1.15µA
For this equation to be valid, the ramp time must be greater
than 1.2ms thus:
CTRACK/SS ≥
1.15µA•1.2ms
0.6V
or
CTRACK/SS ≥ 2.3nF
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LTC3546
Applications Information
The LTC3546 can also track an external voltage during
startup by using an external voltage divider to the TRACK/SS
pin, and also insuring that the ramp rate on the TRACK/SS
pin is slower than the internal 1.2ms ramp rate.
OUTPUT VOLTAGE
VX
As indicated in Figure 3, a resistor divider from an external
voltage can be connected to the TRACK/SS pin to allow
the start-up of VOUT to ratiometrically track an external
voltage VX.
VOUT
TIME
For VTRACKSS < 0.6V
Figure 4. Coincident Tracking
R2X
R1+R2
•
R1X +R2X
R2
VX
VX
VOUT
R1X
R1
OUTPUT VOLTAGE
VOUT = VX •
LTC3546
VTRACK/SS
R2X
VFB
3546 F03
3546 F04
R2
VOUT
Figure 3. Tracking External Voltages
Coincident tracking is where VOUT = VX during startup. To
implement coincident tracking R1X in Figure 3 is set to the
same value as R1 and R2X to the value of R2. Coincident
tracking is illustrated in Figure 4. The voltage at TRACK/SS
when VX is at its final value should be ≥0.8V (sufficient
margin above the 0.6V reference voltage).
Ratiometric tracking is where VOUT ≠ VX during startup
but rather, it is set to some fractional value of VX. To
implement ratiometric tracking (as illustrated in Figure
5), set R1X in Figure 3 to the same value as R1 and R2X
to the value of R2 + ΔR. The ΔR added to R2 should be
sufficient so that the TRACK/SS voltage is ≥ 0.8V when
VX is at its final value.
The internal 1.15µA pull up current on TRACK/SS can cause
a tracking error at VOUT when using a resistor divider on
TRACK/SS. For example, if a 59k resistor is chosen for
R2X, the R2X current will be about 10µA (0.6V/59k). In this
case, the 1.15µA internal current source will cause about
11% (1.15µA/10µA) tracking error, which is about 66mV
referred to VFB. This is acceptable for most applications.
If a better tracking accuracy is required, the value of R2X
can be reduced or the 1.15µA current can be taken into
account in the equations.
TIME
3546 F05
Figure 5. Ratiometric Tracking
Table 2 summarizes the different states in which the
TRACK/SS can be used.
Table 2. The States of the TRACK/SS Pin
TRACK/SS PIN
RESULT
Capacitor to Ground
External Soft-Start
Floating
Internal Soft-Start
Resistor Divider
VOUT Tracking an External Voltage VX
Regardless of the mode implemented, the TRACK/SS pin
should never be pulled high externally as this will result
in excessive current during shutdown.
The LTC3546 can smoothly handle starting up into a prebiased output. The tracking function will pick up from the
pre-biased voltage and ramp the output up from there.
Mode Selection
The SYNC/MODE pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connecting
this pin to VIN enables Burst Mode operation for both reg3546fc
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19
LTC3546
Applications Information
ulators. This mode provides the best low current efficiency
at the cost of a higher output voltage ripple. When SYNC/
MODE is connected to ground, pulse-skipping operation is
selected for both regulators. This mode provides a lower
output voltage and current ripple at the cost of low current
efficiency. Applying VIN/2 results in forced continuous mode
for both regulators. This mode creates a fixed output ripple
and is capable of sinking some current (about 1/2 • ΔIL).
Since the switching noise is constant in this mode, it is also
the easiest to filter out. During initial start-up, pulse-skipping
mode is forced until the PGOOD pin goes high.
The LTC3546 can also be synchronized to an external
clock signal by the SYNC/MODE pin. An internal phase
locked loop locks to the incoming signal to provide for
180° out-of-phase operation as well as correct slope
compensation. With external synchronization the FREQ
pin is used for externally compensating the internal phase
locked loop. Typical values used for compensation are 200k
and 100pf, as shown in Figure 6. During synchronization,
the regulator operating mode is forced to pulse skipping.
The P-channel switch turn on is synchronized to the rising
edge of the external clock.
When using an external clock, with the PHASE pin low, the
switching of the two channels occur 180° out-of-phase.
LTC3546
FREQ
3546 F06
200k
100pF
Figure 6. PLL Compensation
Checking Transient Response
The ITH pin compensation allows the transient response
to be optimized for a wide range of loads and output
capacitors. The availability of the ITH pin not only allows
optimization of the control loop behavior but also provides a DC-coupled and AC filtered closed loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
20
estimated using the percentage of overshoot seen at this
pin, or by examining the rise time at this pin.
The ITH external components shown in the Figure 9 circuit
will provide an adequate starting point for most applications. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because of various types and values determine the loop
feedback factor gain and phase. An output current pulse
of 20% to 100% of full load current having a rise time
of 1µs to 10µs will produce output voltage and ITH pin
waveforms that will give a sense of overall loop stability
without breaking the feedback loop.
Switching regulators take several cycles to respond to
a step in load current. When a load step occurs, VOUT
immediately shifts by an amount equal to ΔILOAD • ESR,
where ESR is the effective series resistance of COUT. The
ΔILOAD also begins to charge or discharge COUT generating
a feedback error signal used by the regulator to return
VOUT to its steady-state value. During this recovery time,
VOUT can be monitored for overshoot or ringing that would
indicate a stability problem.
The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. The gain of the loop increases with RITH and the
bandwidth of the loop increases with decreasing CITH. If
RITH is increased by the same factor that CITH is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, feedforward capacitors,
CFF1 and CFF2, can be added to improve the high frequency
response, as shown in Figure 9. Capacitor CFF1 provides
phase lead by creating a high frequency zero with R1
which improves the phase margin for the 1A SW1 channel. Capacitor CFF2 provides phase lead by creating a high
frequency zero with R3 which improves the phase margin
for the 3A SW1D/SW2 channel.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
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LTC3546
Applications Information
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage VIN drops toward VOUT, the load step capability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capability near dropout should use a different topology such as
SEPIC, Zeta, or single inductor, positive buck boost.
In some applications, a more severe transient can be caused
by switching in loads with large (>1µF) input capacitors.
The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the load
switch driver. A hot swap controller is designed specifically
for this purpose and usually incorporates current limiting,
short-circuit protection, and soft starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (P1 + P2 + P3+…)
where P1, P2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3546 circuits: 1) LTC3546 VIN current,
2) switching losses, 3) I2R losses, 4) other losses.
1. The VIN current is the DC supply current given in the
electrical characteristics which excludes MOSFET
driver and control currents. VIN current results in a
small (<0.1%) loss that increases with VIN, even at
no-load.
2. The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge moves from
VIN to ground. The resulting charge over the switching
period is a current out of VIN that is typically much larger
than the DC bias current. The gate charge losses are
proportional to VIN and thus their effects will be more
pronounced at higher supply voltages.
3. I2R losses are calculated from the DC resistances of
the internal switches, RSW, and the external inductor,
RL. In continuous mode, the average output current
flowing through inductor L is “chopped” between the
internal top and bottom switches. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
Where RL is the resistance of the inductor.
4. Other hidden losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. It is very
important to include these “system” level losses in
the design of a system. The internal battery and fuse
resistance losses can be minimized by making sure
that CIN has adequate charge storage and very low
ESR at the switching frequency. Other losses including
diode conduction losses during dead-time and inductor
core losses generally account for less than 2% total
additional loss.
Thermal Considerations
The LTC3546 requires the backplane metal (Pin 29) to be
well soldered to the PC board. This gives the UFD package exceptional thermal properties, compared to similar
packages of this size, making it difficult in normal opera3546fc
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21
LTC3546
Applications Information
tion to exceed the maximum junction temperature of the
part. In a majority of applications, the LTC3546 does not
dissipate much heat due to its high efficiency. However, in
applications where the LTC3546 is running at high ambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both switches
in both regulators will be turned off and the SW nodes will
become high impedance.
To avoid the LTC3546 from exceeding the maximum junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
TRISE = PD • θJA
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
As an example, consider the case when the LTC3546 is
in dropout in both regulators at an input voltage of 3.3V
with load currents of 3A (SW1D externally connected to
SW2) and 1A. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance
of the 3A P-channel switch parallel combination of SW2
and SW1D is 0.06Ω and the RDS(ON) of the 1A P-channel
switch is 0.18Ω. The power dissipated by the part is:
PD = I12 RDS(ON)1 + I22 RDS(ON)2
PD
= 32 • 0.064 + 12 • 0.19
PD = 0.77W
TJ = 111.2°C
22
Design Example
As a design example, consider using the LTC3546 in a
portable application with a Li-Ion battery. The battery
provides a VIN = 2.25V to 4.2V. One output requires 1.8V
at 2.5A in active mode, and 1mA in standby mode. The
other output requires 1.2V at 800mA in active mode,
and 500µA in stand-by mode. Since both loads still need
power in stand-by, Burst Mode operation is selected for
good low load efficiency.
First, determine what frequency should be used. Higher
frequency results in a lower inductor value for a given ΔIL
(ΔIL is estimated as 0.35ILOAD(MAX)). Reasonable values
for wire wound surface mount inductors are in the 1µH
and up. Look at the different frequencies with the ΔIL =
0.35ILOAD(MAX).
CONVERTER OUTPUT
ILOAD(MAX)
ΔIL
SW2/SW1D, 1.2V
2.5A
875mA
SW1, 1.8V
800mA
280mA
Using the 1.5MHz frequency setting (FREQ = 143k to GNDA)
we get the following equations for L1 and L2.
L1=
1.2V
⎛ 1.2V ⎞
• ⎜ 1−
⎟ = 2µH
1.5MHz • 280mA ⎝ 4.2V ⎠
L2 =
1.8V
⎛ 1.8V ⎞
• ⎜ 1−
⎟ = 0.78µH
1.5MHz • 875mA ⎝ 4.2V ⎠
Use 1µH and 2.2µH.
The UFD package junction-to-ambient thermal resistance,
θJA, is about 34°C/W. Therefore, the junction temperature
of the regulator operating in a 85°C ambient temperature
is approximately:
TJ = 0.77 • 34 + 85
This junction temperature is obtained from an RDS(ON) at
25°C. At 125°C the RDS(ON) increases by about 30%. This
will put the junction temperature at 122°C. If the supply is
lower, like 2.25V, the RDS(ON) is higher still. Special care
needs to be taken if the part is expected to be operating
in dropout so that the maximum junction temperature of
125°C is not exceeded.
COUT selection is typically based on load step rather
than the ripple requirements. The minimum required
capacitance will increase with a decrease in compensation loop bandwidth and/or increases in maximum load
step or output voltage tolerance. A good starting point is
about 22µF per ampere of output current for a nominal
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LTC3546
Applications Information
operating frequency of 1.5MHz and assumes roughly a
300mA/A load step.
22µF
280mA
• 0.8A •
= 20.5µF
300mA
A
• 0.8A
A
22µF
875mA
COUT1 =
• 2.5A •
= 64.2µF
300mA
A
• 2.5A
A
COUT1 =
2. All, or part, of CIN should connect from Pin 9 to Pin 14
on the same side of the PC board as the chip and as
close to the chip as possible, where the SW traces will go
directly under the capacitor. CIN provides the AC current
to the internal power MOSFETs and their drivers.
The closest values are 22µF and 68µF.
3. Are the respective COUT, L closely connected? The (–)
plate of COUT1 returns current to PGND1, and the (–)
plate of COUT2 returns current to the PGND2. The (–)
plate of CIN should also return current to PGND1 and
PGND2.
The output voltages can now be programmed by choosing the values of R1, R2, R3, and R4. To maintain high
efficiency, the current in these resistors should be kept
small. Choosing 2µA with the 0.6V feedback voltages
makes R2 and R4 equal to 300k. A close standard 1%
resistor is 301k. This then makes R1 = 300k. A close
standard 1% is 301k. R3 then equals 600k. A close 1%
resistor is 604k.
4. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT1 and a ground line terminated near GNDA. The resistor divider R3 and R4,
must be connected between the (+) plate of COUT2 and
the ground connection terminated to the GNDA pin.
The feedback signals VFB1 and VFB2 should be routed
away from noise components and traces, such as the
SW lines, and its trace should be minimized.
The compensation should be optimized for these components by examining the load step response but a good
place to start for the LTC3546 is with a 13kΩ and 1000pF
filter on both ITH1 and ITH2. The output capacitor may
need to be increased depending on the actual transient
during a load step.
5. When using the RFREQ resistor, the ground connection
of the resistor should be terminated to the GNDA pin.
When using the internal PLL, the ground connection of
the R-C compensation network should be terminated
to the GNDA pin.
The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate speed.
Figure 9 shows a complete schematic for this design.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3546. These items are also illustrated graphically
in the layout diagram of Figure 7. Check the following in
your layout.
1. Make sure SW1, SW2A, SW2B and SW1D are connected
on the PC board through a wide piece of copper.
6. Keep sensitive components away from the SW pins.
The input capacitor CIN, the compensation capacitors
CFF1, CFF2, CITH1, and CITH2 and all resistors R1, R2,
R3, R4, RITH1 and RITH2 should be routed away from
the SW traces and the inductors L1 and L2.
7. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the SGND pin at one
point which is then connected to the PGND1/PGND2/
PGND1D/GNDD pins.
8. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to the Exposed Pad (Pin 29).
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23
LTC3546
Applications Information
VIN
2.25V TO 5.5V
VOUT2
1.8V, 2A
COUT2
47µF
CIN
22µF
R5
100k
VIN1 VCCA VCCD VIN2
R6
100k
SYNC/MODE
L2
0.56µH
PGOOD2
CFF2
100pF
VIN
SW2A
SW1
SW2B
SW1D
RUN2
VFB2
R3
R4
60.4k 30.1k
VIN
LTC3546
BMC2
VOUT1
1.2V, 2A
CFF1
100pF
VIN
VFB1
COUT1
47µF
R1
R2
30.1k 30.1k
VIN
TRACK/SS1
FREQ
PHASE
ITH2
PGND2
RUN1
BMC1
TRACK/SS2
RITH2
13k
L1
0.56µH
PGOOD1
ITH1
GNDA
PGND1
CITH2
1000pF
RITH1
13k
CITH1
1000pF
EXPOSED PAD
RFREQ
143k
3546 F07
Figure 7. Typical Schematic for 2A/2A Regulator
24
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LTC3546
Applications Information
5V VIN
C5
22µF, X5R
VCC
R7
100k
C1
22µF, X5R
×2
PGOOD1
PGOOD2
SYNC/MODE
R8
100k
VOUT2
2.5V/2A
RUN1
RUN2
L1
1.0µH
C6
10pF
R1
316k
R6
5.1k
C4
470pF
SW2A
SW1
SW2B
SW1D
VFB2
R3
100k
R9
90.9k
L2
1.0µH
LTC3546
FREQ
ITH2
TRACK/SS2
C9
0.1µF
BMC2 GND
C7
33pF
VFB1
R4
100k
PHASE
ITH1
TRACK/SS1
BMC1
R2
200k
C8
0.1µF
VOUT1
1.8V/2A
C2
22µF, X5R
×2
R5
8.2k
C3
330pF
3546 F08
fSW = 2.25MHz
Figure 8. A 2.25MHz Fixed Frequency 2A/2A Regulator
3546fc
For more information www.linear.com/3546
25
LTC3546
Applications Information
VIN
2.25V TO 5.5V
VOUT2
2.5V, 3A
COUT2
33µF
x2
CIN
22µF
R5
100k
R6
100k
VIN1 VCCA VCCD VIN2
SYNC/MODE
L2
0.56µH
PGOOD2
SW2A
CFF2
100pF
L1
1.2µH
PGOOD1
SW1
SW2B
SW1D
VIN
RUN2
VFB2
R3
R4
95.3k 30.1k
VIN
LTC3546
BMC2
COUT1
22µF
R1
R2
30.1k 59k
VIN
FREQ
ITH2
PGND2
VIN
VFB1
TRACK/SS1
PHASE
RITH2
13k
RUN1
BMC1
TRACK/SS2
VOUT1
1.8V, 1A
CFF1
100pF
ITH1
GNDA
RITH1
13k
CITH1
1000pF
PGND1
CITH2
1000pF
RFREQ
143k
EXPOSED PAD
3546 F09
Figure 9. Typical Schematic for 3A/1A Regulator
OUT2 Efficiency (Burst Mode Operation)
95
10
SW1D CONNECTED TO SW2
VIN = 3.6V
95 VOUT = 2.5V
1
90
90
EFFICIENCY
85
80
0.1
0.01
POWER LOSS
75
70
0.001
0.01
0.1
LOAD CURRENT (A)
1
100
EFFICIENCY (%)
100
10
1
EFFICIENCY
85
80
0.001
75
0.0001
70
0.001
3546 F09b
26
100
0.1
0.01
POWER LOSS
POWER LOSS (W)
100
POWER LOSS (W)
EFFICIENCY (%)
OUT1 Efficiency (Burst Mode Operation)
0.001
1
0.01
0.1
LOAD CURRENT (A)
10
0.0001
3546 F09c
3546fc
For more information www.linear.com/3546
LTC3546
Package Description
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.50 REF
2.65 ± 0.05
3.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
(2 SIDES)
R = 0.05
TYP
0.75 ± 0.05
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
3.50 REF
3.65 ± 0.10
2.65 ± 0.10
(UFD28) QFN 0506 REV B
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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For more information www.linear.com/3546
27
LTC3546
Package Description
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 2726 25 24 23 22 21 20 19 18 1716 15
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
SEE NOTE 4
0.45 ±0.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
6.40
2.74
(.252)
(.108)
BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
28
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.25
REF
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3546fc
For more information www.linear.com/3546
LTC3546
Revision History
(Revision history begins at Rev C)
REV
DATE
DESCRIPTION
C
03/13
Modified Typical App Circuit VIN Range
PAGE NUMBER
1
Clarified Electrical Characteristics Notes for Temp Ranges
3, 4
Clarified BMC, BMC1 and GNDD pin operation
9, 10
3546fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection ofFor
its circuits
as described herein
will not infringe on existing patent rights.
more information
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29
LTC3546
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ThinSOT is a trademark of Linear Technology Corporation.
30 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/3546
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/3546
3546fc
LT 0313 REV C • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2009