Sample & Buy Product Folder Support & Community Tools & Software Technical Documents SN54HC14, SN74HC14 SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 SNx4HC14 Hex Schmitt-Trigger Inverters 1 Features 3 Description • • • • • • • These Schmitt-trigger devices contain six independent inverters. They perform the Boolean function Y = A in positive logic. 1 Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up to 10 LSTTL Loads Low Power Consumption, 20-μA Max ICC Typical tpd = 11 ns ±4-mA Output Drive at 5 V Low Input Current of 1 μA Max On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters. Device Information(1) PART NUMBER SNx4HC14 2 Applications • • • • • • • Microwave Oven Mice Printers AC Inverter Drives UPS AC Servo Drives Other Motor Drives PACKAGE BODY SIZE (NOM) CDIP (14) 7.62 mm x 19.94 mm CFP (14) 7.11 mm x 9.11 mm LCCC (20) 8.89 mm x 8.89 mm SOIC (14) 6.00 mm x 8.65 mm SSOP (14) 367.00 mm x 367.00 mm PDIP (14) 7.94 mm x 10.35 mm SO (14) 7.80 mm x 10.20 mm TSSOP (14) 6.40 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) A Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54HC14, SN74HC14 SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 9 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 5 5 5 5 6 6 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Operating Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 8 Detailed Description .............................................. 9 9.1 Overview ................................................................... 9 9.2 Functional Block Diagram ......................................... 9 9.3 Feature Description................................................... 9 9.4 Device Functional Modes.......................................... 9 10 Application and Implementation........................ 10 10.1 Application Information.......................................... 10 10.2 Typical Application ................................................ 10 11 Power Supply Recommendations ..................... 11 12 Layout................................................................... 12 12.1 Layout Guidelines ................................................. 12 12.2 Layout Example .................................................... 12 13 Device and Documentation Support ................. 13 13.1 13.2 13.3 13.4 13.5 13.6 Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 13 13 13 13 13 13 14 Mechanical, Packaging, and Orderable Information ........................................................... 13 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (September 2015) to Revision I Page • Changed part number from SN54HC08 to SN54HC14 in Switching Characteristics table.................................................... 6 • Changed part number from SN74HC08 to SN74HC14 in Switching Characteristics table.................................................... 6 Changes from Revision G (January 2014) to Revision H Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Added Military Disclaimer to Features list. ............................................................................................................................. 1 • Added Applications ................................................................................................................................................................. 1 Changes from Revision F (December 2010) to Revision G • 2 Page Updated document to new TI data sheet format - no specification changes. ........................................................................ 1 Submit Documentation Feedback Copyright © 1982–2016, Texas Instruments Incorporated Product Folder Links: SN54HC14 SN74HC14 SN54HC14, SN74HC14 www.ti.com SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 5 Device Comparison Table PART NUMBER PACKAGE BODY SIZE (NOM) SN54HC14J CDIP (14) 7.62 mm x 19.94 mm SNJ54HC14W CFP (14) 7.11 mm x 9.11 mm SNJ54HC14FK LCCC (20) 8.89 mm x 8.89 mm SN74HC14DR SOIC (14) 6.00 mm x 8.65 mm SN74HC14DBR SSOP (14) 367.00 mm x 367.00 mm SN74HC14N PDIP (14) 7.94 mm x 10.35 mm SN74HC14NSR SO (14) 7.80 mm x 10.20 mm SN74HC14PW TSSOP (14) 6.40 mm x 5.00 mm Copyright © 1982–2016, Texas Instruments Incorporated Product Folder Links: SN54HC14 SN74HC14 Submit Documentation Feedback 3 SN54HC14, SN74HC14 SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 www.ti.com 6 Pin Configuration and Functions J, W, D, DB, N, NS, or PW Package 14-Pin CDIP, CFP, SOIC, SSOP, SO, or TSSOP Top View 14 2 13 3 12 4 11 5 10 6 9 7 1Y 1A NC VCC 6A 1 VCC 6A 6Y 5A 5Y 4A 4Y 8 2A NC 2Y NC 3A 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 6Y NC 5A NC 5Y 3Y GND NC 4Y 4A 1A 1Y 2A 2Y 3A 3Y GND FK Package 20-Pin LCCC Top View Pin Functions PIN CDIP, CFP, SOIC, SSOP, SO, TSSOP LCCC 1A 1 2 I Channel 1 input 1Y 2 3 O Channel 1 output 2A 3 4 I Channel 2 input 2Y 4 6 O Channel 2 output 3A 5 8 I Channel 3 input 3Y 6 9 O Channel 3 output GND 7 10 — Ground 4Y 8 12 O Channel 4 output 4A 9 13 I Channel 4 input 5Y 10 14 O Channel 5 output 5A 11 16 I Channel 5 input 6Y 12 18 O Channel 6 output 6A 13 19 I Channel 6 input VCC 14 20 — Power supply — No internal connection NAME I/O DESCRIPTION 1 5 NC (1) — 7 11 15 17 (1) 4 NC – No internal connection Submit Documentation Feedback Copyright © 1982–2016, Texas Instruments Incorporated Product Folder Links: SN54HC14 SN74HC14 SN54HC14, SN74HC14 www.ti.com SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage (2) MIN MAX UNIT –0.5 7 V IIK Input clamp current VI < 0 or VI > VCC ±20 mA IOK Output clamp current (2) VO < 0 ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA mA Continuous current through VCC or GND ±50 Tj Junction temperature 150 Tstg Storage temperature (1) (2) –65 °C 150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 7.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±1500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions (1) See . SN54HC14 MIN NOM 5 SN74HC14 MAX MIN NOM 5 MAX UNIT VCC Supply voltage 2 6 2 6 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V TA Operating free-air temperature –55 125 –40 85 °C (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. 7.4 Thermal Information SNx4HC14 THERMAL METRIC (1) RθJA (1) Junction-to-ambient thermal resistance D (SOIC) DB (SSOP) N (PDIP) NS (SO) PW (TSSOP) 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 86 96 80 76 113 UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 1982–2016, Texas Instruments Incorporated Product Folder Links: SN54HC14 SN74HC14 Submit Documentation Feedback 5 SN54HC14, SN74HC14 SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 www.ti.com 7.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VT+ VT− VT+ − VT− IOH = –20 μA VOH VI = VIH or VIL IOH = –4 mA IOH = –5.2 mA IOL = 20 μA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II VI = VCC or 0 ICC VI = VCC or 0, IO = 0 TA = 25°C MIN TYP MAX SN74HC14 MIN MIN MAX MAX 2V 0.7 1.2 1.5 0.7 1.5 0.7 1.5 4.5 V 1.55 2.5 3.15 1.55 3.15 1.55 3.15 6V 2.1 3.3 4.2 2.1 4.2 2.1 4.2 2V 0.3 0.6 1 0.3 1 0.3 1 4.5 V 0.9 1.6 2.45 0.9 2.45 0.9 2.45 6V 1.2 2 3.2 1.2 3.2 1.2 3.2 2V 0.2 0.6 1.2 0.2 1.2 0.2 1.2 4.5 V 0.4 0.9 2.1 0.4 2.1 0.4 2.1 6V 0.5 1.3 2.5 0.5 2.5 0.5 2.5 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 UNIT V V V V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 2 40 20 μA 10 10 10 pF 6V Ci SN54HC14 2 V to 6 V 3 V 7.6 Switching Characteristics over operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 3) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A tt Y Y VCC TA = 25°C MIN SN54HC14 MIN SN74HC14 TYP MAX MAX MIN MAX 2V 55 125 190 155 4.5 V 12 25 38 31 6V 11 21 22 26 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 UNIT ns ns 7.7 Operating Characteristics TA = 25°C Cpd 6 PARAMETER TEST CONDITIONS Power dissipation capacitance per inverter No load Submit Documentation Feedback TYP 20 UNIT pF Copyright © 1982–2016, Texas Instruments Incorporated Product Folder Links: SN54HC14 SN74HC14 SN54HC14, SN74HC14 www.ti.com SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 7.8 Typical Characteristics 14.5 70 14 60 50 TPD (ns) TPD (ns) 13.5 13 12.5 30 20 12 11.5 -100 40 10 0 -50 0 50 Temperature 100 150 0 2 D001 Figure 1. TPD vs Temperature at 4.5 V, 25°C 4 VCC 6 8 D002 Figure 2. TPD vs VCC at 25°C Copyright © 1982–2016, Texas Instruments Incorporated Product Folder Links: SN54HC14 SN74HC14 Submit Documentation Feedback 7 SN54HC14, SN74HC14 SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 www.ti.com 8 Parameter Measurement Information From Output Under Test Test Point Input 90% In-Phase Output 90% tr tPHL tPLH LOAD CIRCUIT 50% 10% 50% 0V CL= 50 pF (see Note A) Input VCC 50% 0V 90% VOH 50% 10% Out-of-Phase Output VOL tf tPLH tPHL 90% 50% 10% tf VOLTAGE WAVEFORMS INPUT RISE AND FALL TIMES 90% tr VCC 50% 10% 50% 10% 50% 10% 90% tf VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES Figure 3. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 1982–2016, Texas Instruments Incorporated Product Folder Links: SN54HC14 SN74HC14 SN54HC14, SN74HC14 www.ti.com SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 9 Detailed Description 9.1 Overview These Schmitt-trigger devices contain six independent inverters. They perform the Boolean function Y = A in positive logic. Schmitt-trigger inputs are designed to provide a minimum separation between positive and negative switching thresholds. This allows for noisy or slow inputs that would cause problems such as oscillation or excessive current draw with normal CMOS inputs. 9.2 Functional Block Diagram A Y Figure 4. Logic Diagram (Positive Logic) 9.3 Feature Description The wide operating range of the device allows it to be used in a variety of systems that use different logic levels. The outputs can drive up to 10 LSTTL loads each. The device has very low power consumption, with 20-μA Max ICC. Typical propagation delay is also low at 11 ns. The balanced drive outputs can source or sink 4 mA at 5-V VCC. The input leakage current is 1 μA Max. 9.4 Device Functional Modes Table 1 lists the functional modes of the SNx4HC14. Table 1. Function Table (Each Inverter) INPUTS A OUTPUT Y H L L H Copyright © 1982–2016, Texas Instruments Incorporated Product Folder Links: SN54HC14 SN74HC14 Submit Documentation Feedback 9 SN54HC14, SN74HC14 SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The SNx4HC14 device is a Schmitt-trigger input CMOS device that can be used for a multitude of inverting buffer type functions. The application shown here takes advantage of the Schmitt-trigger inputs to produce a delay for a logic output. 10.2 Typical Application INPUT 1A 1Y R1 2A 2Y OUTPUT C1 Figure 5. Simplified Application Schematic 10.2.1 Design Requirements This device uses CMOS technology. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. Parallel output drive can create fast edges into light loads so consider routing and load conditions to prevent ringing. 10.2.2 Detailed Design Procedure This circuit is designed around an RC network that produces a slow input to the second inverter. The RC time constant, τ, is calculated from: τ = R×C The delay time for this circuit will be between 1.2τ and 0.42τ. It should be noted that the delay will be consistent for each device, but since the switching threshold is only guaranteed between a minimum and maximum value, the output pulse length will vary between devices. These values were calculated by using the minimum and maximum guaranteed VT+ values. The resistor value should be chosen such that the maximum current from/to the SNx4HC14 is 4 mA. • Recommended input conditions: – Schmitt-trigger inputs allow for slow inputs. – Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions. • Recommended output conditions: – Load currents should not exceed 4 mA per output. 10 Submit Documentation Feedback Copyright © 1982–2016, Texas Instruments Incorporated Product Folder Links: SN54HC14 SN74HC14 SN54HC14, SN74HC14 www.ti.com SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 Typical Application (continued) 10.2.3 Application Curve 5.0 4.5 4.0 3.0 2.5 VT+ Typical VT+ Voltage (V) 3.5 2.0 1.5 1.0 Max Delay Time = 1.202 VC Min Delay Time = 0.422 VOUT 0.5 0.0 t0 t0 + 2 t0 + 22 t0 + 32 t0 + 42 t0 + 52 Time Figure 6. Ideal Capacitor Voltage and Output Voltage With Positive Switching Threshold Range Representation. 11 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1-µF capacitor. If there are multiple VCC terminals, then TI recommends a 0.01-µF or 0.022-µF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close as possible to the power terminal for best results. Copyright © 1982–2016, Texas Instruments Incorporated Product Folder Links: SN54HC14 SN74HC14 Submit Documentation Feedback 11 SN54HC14, SN74HC14 SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 www.ti.com 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices, inputs should never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever makes more sense or is more convenient. Floating outputs is generally acceptable, unless the part is a transceiver. 12.2 Layout Example Figure 7. Layout Recommendation 12 Submit Documentation Feedback Copyright © 1982–2016, Texas Instruments Incorporated Product Folder Links: SN54HC14 SN74HC14 SN54HC14, SN74HC14 www.ti.com SCLS085I – DECEMBER 1982 – REVISED FEBRUARY 2016 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation For related documentation, please see the following: Implications of Slow or Floating CMOS Inputs, SCBA004 13.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54HC05 Click here Click here Click here Click here Click here SN74HC05 Click here Click here Click here Click here Click here 13.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 1982–2016, Texas Instruments Incorporated Product Folder Links: SN54HC14 SN74HC14 Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-8409101VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8409101VC A SNV54HC14J 5962-8409101VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8409101VD A SNV54HC14W 84091012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84091012A SNJ54HC 14FK 8409101CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8409101CA SNJ54HC14J 8409101DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8409101DA SNJ54HC14W JM38510/65702BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65702BCA JM38510/65702BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65702BDA M38510/65702BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65702BCA M38510/65702BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65702BDA SN54HC14J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC14J SN74HC14D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC14 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2016 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74HC14DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14DRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14DT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14DTG4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type -40 to 85 SN74HC14N TBD Call TI Call TI -40 to 85 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TBD Call TI Call TI -40 to 85 SN74HC14N3 OBSOLETE PDIP N 14 SN74HC14NE4 ACTIVE PDIP N 14 SN74HC14NSLE OBSOLETE SO NS 14 SN74HC14NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 SN74HC14PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SN74HC14PWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 Addendum-Page 2 SN74HC14N Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2016 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74HC14PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC14 SNJ54HC14FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84091012A SNJ54HC 14FK SNJ54HC14J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8409101CA SNJ54HC14J SNJ54HC14W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8409101DA SNJ54HC14W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2016 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN54HC14, SN54HC14-SP, SN74HC14 : • Catalog: SN74HC14, SN54HC14 • Automotive: SN74HC14-Q1, SN74HC14-Q1 • Military: SN54HC14 • Space: SN54HC14-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jan-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC14DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HC14DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC14DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC14DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 SN74HC14DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 SN74HC14DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC14DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC14PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC14PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jan-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC14DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74HC14DR SOIC D 14 2500 333.2 345.9 28.6 SN74HC14DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC14DR SOIC D 14 2500 364.0 364.0 27.0 SN74HC14DRG3 SOIC D 14 2500 364.0 364.0 27.0 SN74HC14DRG4 SOIC D 14 2500 333.2 345.9 28.6 SN74HC14DT SOIC D 14 250 367.0 367.0 38.0 SN74HC14PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC14PWT TSSOP PW 14 250 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. 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