ICST ICS951412YGLFT System clock chip for ati rs480 k8-based system Datasheet

ICS951412
Integrated
Circuit
Systems, Inc.
System Clock Chip for ATI RS480 K8-based Systems
Recommended Application:
ATI RS480 systems using AMD K8 processors
Pin Configuration
Features:
•
2 - Programmable Clock Request pins for SRC
clocks
•
Spread Spectrum for EMI reduction
•
Outputs may be disabled via SMBus
•
External crystal load capacitors for maximum
frequency accuracy
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
ICS951412
X1
X2
VDD48
USB_48MHz
GND
NC
SCLK
SDATA
**FS2
**CLKREQA#
**CLKREQB#
SRCCLKT7
SRCCLKC7
VDDSRC
GNDSRC
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
GNDSRC
VDDSRC
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
GNDSRC
ATIGCLKT1
ATIGCLKC1
Output Features:
•
3 - 14.318 MHz REF clocks
•
1 - USB_48MHz USB clock
•
1 - HyperTransport 66 MHz clock seed
•
1 - PCI 33 MHz clock seed
•
2 - Pairs of AMD K8 clocks
•
6 - Pairs of SRC/PCI Express* clocks
•
2 - Pairs of ATIG (SRC/PCI Express) clocks
VDDREF
GND
**FS0/REF0
**FS1/REF1
REF2
VDDPCI
PCICLK0
GNDPCI
VDDHTT
HTTCLK0
GNDHTT
CPUCLK8T0
CPUCLK8C0
VDDCPU
GNDCPU
CPUCLK8T1
CPUCLK8C1
VDDA
GNDA
IREF
GNDSRC
VDDSRC
SRCCLKT0
SRCCLKC0
VDDATI
GNDATI
ATIGCLKT0
ATIGCLKC0
Note: Pins preceeded by '**' have a 120 Kohm Internal Pull Down resistor
56 Pin SSOP/TSSOP
Functionality
Power Groups
Pin Number
VDD
GND
56
55
Description
FS2
FS1
FS0
Xtal, REF
0
0
0
0
1
CPU
MHz
Hi-Z
HTT
MHz
Hi-Z
PCI
MHz
Hi-Z
51
49
PCICLK output
0
X
X/3
X/6
48
46
HTTCLK output
0
1
0
180.00
60.00
30.00
43
14, 21,
32,35
39
42
15, 20,
26,31,36
38
CPU Outputs
0
1
1
220.00
73.12
36.56
1
0
0
100.00
66.66
33.33
SRC outputs
1
0
1
133.33
66.66
33.33
Analog, CPU PLL
1
1
1
200.00
66.66
33.33
3
5
USB_48MHz output
0883G—12/08/04
*Other names and brands may be claimed as the property of others.
ICS951412
Pin Descriptions
PIN
#
PIN NAME
PIN
TYPE
1
2
3
4
5
6
7
8
9
X1
X2
VDD48
USB_48MHz
GND
NC
SCLK
SDATA
**FS2
IN
OUT
PWR
OUT
PWR
N/A
IN
I/O
IN
10
**CLKREQA#
IN
11
**CLKREQB#
IN
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SRCCLKT7
SRCCLKC7
VDDSRC
GNDSRC
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
GNDSRC
VDDSRC
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
GNDSRC
ATIGCLKT1
ATIGCLKC1
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
DESCRIPTION
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Power pin for the 48MHz output.3.3V
48.00MHz USB clock
Ground pin.
No Connection.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Frequency select pin.
Output enable for PCI Express (SRC) outputs. SMBus selects which
outputs are controlled.
0 = enabled, 1 = tri-stated
Output enable for PCI Express (SRC) outputs. SMBus selects which
outputs are controlled.
0 = enabled, 1 = tri-stated
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Ground pin for the SRC outputs
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Ground pin for the SRC outputs
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Ground pin for the SRC outputs
True clock of differential SRC clock pair.
Complementary clock of differential SRC clock pair.
0883G—12/08/04
2
ICS951412
Pin Descriptions (Continued)
PIN
#
29
30
31
32
33
34
35
36
ATIGCLKC0
ATIGCLKT0
GNDATI
VDDATI
SRCCLKC0
SRCCLKT0
VDDSRC
GNDSRC
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
Complementary clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Ground for ATI Gclocks, nominal 3.3V
Power supply ATI Gclocks, nominal 3.3V
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Ground pin for the SRC outputs
37
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
GNDA
VDDA
CPUCLK8C1
CPUCLK8T1
GNDCPU
VDDCPU
CPUCLK8C0
CPUCLK8T0
GNDHTT
HTTCLK0
VDDHTT
GNDPCI
PCICLK0
VDDPCI
REF2
**FS1/REF1
**FS0/REF0
GND
VDDREF
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
OUT
PWR
PWR
OUT
PWR
OUT
I/O
I/O
PWR
PWR
Ground pin for the PLL core.
3.3V power for the PLL core.
Complementary clock of differential 3.3V push-pull K8 pair.
True clock of differential 3.3V push-pull K8 pair.
Ground pin for the CPU outputs
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential 3.3V push-pull K8 pair.
True clock of differential 3.3V push-pull K8 pair.
Ground pin for the HTT outputs
3.3V Hyper Transport output
Supply for HTT clocks, nominal 3.3V.
Ground pin for the PCI outputs
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin.
Ref, XTAL power supply, nominal 3.3V
PIN NAME
TYPE
DESCRIPTION
0883G—12/08/04
3
ICS951412
General Description
The ICS951412 is a main clock synthesizer chip that provides all clocks required for ATI RS480-based systems.
An SMBus interface allows full control of the device.
Block Diagram
REF(2:0)
X1
X2
XTAL
OSC.
USB_48MHz
FIXED PLL
DIVIDER
PCICLK0
HTTCLK0
SRCCLK(7:3,0)
MAIN PLL
DIVIDERS
ATIGCLK(1:0)
CPUCLK8(1:0)
FS(2:0)
CLKREQA#
CLKREQB#
SEL75#/100
SDATA
SCLK
CONTROL
LOGIC
IREF
Skew Characteristics
Parameter
Description
Tsk_CPU_CPU
Tsk_CPU_PCI
Tsk_PCI_PCI
Tsk_PCI33-HT66
time independent
skew
not dependent on
V, T changes
Tsk_CPU_HT66
Tsk_CPU_HT66
Tsk_CPU_CPU
Tsk_CPU_PCI
Tsk_PCI_PCI
Tsk_PCI33-HT66
Tsk_CPU_HT66
Tsk_CPU_HT66
time variant skew
varies over
V, T changes
Test Conditons
measured at x-ing of CPU,
measured at x-ing of CPU,
1.5V of PCI clock
measured between rising
edge at 1.5V
measured between rising
edge at 1.5V
measured between rising
edge at 1.5V
measured at x-ing of CPU,
1.5V of PCI clock
measured at x-ing of CPU,
measured at x-ing of CPU,
1.5V of PCI clock
measured between rising
edge at 1.5V
measured between rising
edge at 1.5V
measured between rising
edge at 1.5V
measured at x-ing of CPU,
1.5V of PCI clock
Skew
Window
250
Unit
ps
2000
ps
500
ps
500
ps
2000
ps
500
200
ps
ps
200
ps
200
ps
200
ps
200
ps
200
ps
0883G—12/08/04
4
ICS951412
General SMBus serial interface information
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
0883G—12/08/04
5
Not acknowledge
stoP bit
ICS951412
Table1: CPU Frequency Selection Table
CPU
CPU
Bit2 Bit1 Bit0 CPU
FS4
FS3
FS2 FS1 FS0 (MHz)
(B0:b4) (B0:b3)
0
0
0
0
0
Hi-Z
0
0
0
0
1
X/6
0
0
0
1
0
180.00
0
0
0
1
1
220.00
0
0
1
0
0
100.00
0
0
1
0
1
133.33
0
0
1
1
0
166.67
0
0
1
1
1
200.00
0
1
0
0
0
186.00
0
1
0
0
1
214.00
0
1
0
1
0
190.00
0
1
0
1
1
210.00
0
1
1
0
0
102.00
0
1
1
0
1
136.00
0
1
1
1
0
170.00
0
1
1
1
1
204.00
1
0
0
0
0
169.58
1
0
0
0
1
229.43
1
0
0
1
0
179.55
1
0
0
1
1
219.45
1
0
1
0
0
99.75
1
0
1
0
1
133.00
1
0
1
1
0
166.25
1
0
1
1
1
199.50
1
1
0
0
0
185.54
1
1
0
0
1
106.73
1
1
0
1
0
189.53
1
1
0
1
1
209.48
1
1
1
0
0
101.75
1
1
1
0
1
135.66
1
1
1
1
0
169.58
1
1
1
1
1
203.49
0883G—12/08/04
6
HTT66 PCI33
(MHz) (MHz)
Hi-Z
X/12
60.00
73.33
66.67
66.67
66.67
66.67
62.00
71.33
63.33
70.00
68.00
68.00
68.00
68.00
56.53
76.48
59.85
73.15
66.50
66.50
66.50
66.50
61.85
71.16
63.18
69.83
67.83
67.83
67.83
67.83
Hi-Z
X/24
30.00
36.67
33.33
33.33
33.33
33.33
31.00
35.67
31.67
35.00
34.00
34.00
34.00
34.00
28.26
38.24
29.93
36.58
33.25
33.25
33.25
33.25
30.92
35.58
31.59
34.91
33.92
33.91
33.92
33.92
Spread
%
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
ICS951412
SMBus Table: Frequency Select Register
Byte 0
Pin #
Name
Control Function
Type
Latched Input or SMBus
RW
Frequency Select
Bit 7
-
FS Source
Bit 6
Bit 5
Bit 4
Bit 3
-
SS_EN
Reserved
FS4
FS3
PLL Spread Enable
Reserved
Freq Select Bit 4
Freq Select Bit 3
RW
RW
RW
RW
Bit 2
-
FS2
Freq Select Bit 2
RW
Bit 1
-
FS1
Freq Select Bit 1
RW
Bit 0
-
FS0
Freq Select Bit 0
RW
0
1
PWD
Latched
Inputs
SMBus
0
OFF
Reserved
ON
Reserved
0
X
0
0
See Table 1: CPU
Frequency Selection
Latched
Latched
Latched
Note: Byte 0 Bit 6, Byte 0 Bit 4 and Byte 5 Bit 4 must be set to '1' to fully enable spread.
SMBus Table: Output Control Register
Byte 1
Pin #
Name
Control Function
PCICLK0
Output Enable
50
Bit 7
47
HTTCLK0
Output Enable
Bit 6
4
USB_48MHz
Output Enable
Bit 5
54
REF0
Output Enable
Bit 4
53
REF1
Output Enable
Bit 3
52
REF2
Output Enable
Bit 2
45,44
CPUCLK8(0)
Output Enable
Bit 1
41,40
CPUCLK8(1)
Output Enable
Bit 0
SMBus Table: CLKREQB# Output Control Register
Pin #
Name
Control Function
Byte 2
CLKREQB# Controls
12,13
REQBSRC7
Bit 7
SRC7
CLKREQB# Controls
16,17
REQBSRC6
Bit 6
SRC6
CLKREQB# Controls
18,19
REQBSRC5
Bit 5
SRC5
CLKREQB# Controls
REQBSRC4
22,23
Bit 4
SRC4
CLKREQB# Controls
REQBSRC3
24,25
Bit 3
SRC3
Reserved
Reserved
Bit 2
Reserved
Reserved
Bit 1
CLKREQB# Controls
34,33
REQBSRC0
Bit 0
SRC0
0883G—12/08/04
7
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
Type
0
Does not
control
Does not
control
Does not
control
Does not
control
Does not
control
Reserved
Reserved
Does not
control
1
PWD
Controls
0
Controls
0
Controls
0
Controls
0
Controls
0
Reserved
Reserved
X
X
Controls
0
RW
RW
RW
RW
RW
RW
RW
RW
ICS951412
SMBus Table: SRCCLK(7:3,0), CLKREQA# Output Control Register
Byte 3
Pin #
Name
Control Function
Type
0
12,13
SRCCLK7
RW
Disable
Bit 7
Master Output control. RW
16,17
SRCCLK6
Disable
Bit 6
Enables
or
disables
18,19
SRCCLK5
RW
Disable
Bit 5
output,
regardless
of
22,23
SRCCLK4
RW
Disable
Bit 4
CLKREQ# inputs.
24,25
SRCCLK3
RW
Disable
Bit 3
34,33
SRCCLK0
RW
Disable
Bit 2
CLKREQA# Controls
Does not
24,25
REQASRC3
RW
Bit 1
SRC3
control
CLKREQA# Controls
Does not
34,33
REQASRC0
RW
Bit 0
control
SRC0
SMBus Table: SRCCLK(3,0), ATIGCLK Output Control Register
Byte 4
Pin #
Name
Control Function
Type
0
CLKREQA# Controls
Does not
12,13
REQASRC7
RW
Bit 7
SRC7
control
CLKREQA# Controls
Does not
16,17
REQASRC6
RW
Bit 6
SRC6
control
CLKREQA# Controls
Does not
REQASRC5
RW
18,19
Bit 5
SRC5
control
CLKREQA# Controls
Does not
REQASRC4
RW
22,23
Bit 4
SRC4
control
Output Enable
27,28
ATIGCLK1
RW
Disabled
Bit 3
These outputs cannot be
controlled by CLKREQ#
30,29
ATIGCLK0
RW
Disabled
Bit 2
pins.
Reserved
Reserved
RW Reserved
Bit 1
USB_48Str
48MHz Strength Control RW
1X
4
Bit 0
1
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
Controls
0
Controls
0
1
PWD
Controls
0
Controls
0
Controls
0
Controls
0
Enabled
1
Enabled
1
Reserved
2X
0
0
Note: Do NOT simultaneously select CLKREQA# and CLKREQB# to control an SRC output.
Behavior of the device is undefined under these conditions.
SMBus Table: Output Drive and ATIG Frequency Control Register
Byte 5
Pin #
Name
Control Function
Type
52
REF2Str
REF2
Strength
Control
RW
Bit 7
Reserved
Reserved
RW
Bit 6
Reserved
Reserved
RW
Bit 5
SRC SSEN
SRC Spread Enable
RW
Bit 4
Reserved
Reserved
RW
Bit 3
Reserved
Reserved
RW
Bit 2
Reserved
Reserved
RW
Bit 1
Reserved
Reserved
RW
Bit 0
0883G—12/08/04
8
0
1X
Reserved
Reserved
Disable
Reserved
Reserved
Reserved
Reserved
1
2X
Reserved
Reserved
Enable
Reserved
Reserved
Reserved
Reserved
PWD
0
0
0
0
0
0
0
0
ICS951412
SMBus Table: Device ID Register
Byte 6
Pin #
Name
DevID 7
Bit 7
DevID 6
Bit 6
DevID 5
Bit 5
DevID 4
Bit 4
DevID 3
Bit 3
DevID 2
Bit 2
DevID 1
Bit 1
DevID 0
Bit 0
SMBus Table: Vendor ID Register
Pin #
Name
Byte 7
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
SMBus Table: Byte Count Register
Pin #
Name
Byte 8
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
Device ID MSB
Device ID 6
Device ID 5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID LSB
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
0
0
0
1
0
0
1
0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
X
X
X
X
0
0
0
1
Revision ID
VENDOR ID
(0001 = ICS)
Control Function
Byte Count
Programming b(7:0)
Bytes 9 to 21 are reserved
0883G—12/08/04
9
Type
0
1
RW
RW
RW Writing to this register
RW will configure how many
RW bytes will be read back,
default is 9 bytes.
RW
RW
RW
PWD
0
0
0
0
1
0
0
1
ICS951412
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +3.8 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
1
Input Low Voltage
VIL
3.3 V +/-5%
VSS - 0.3
0.8
V
1
Input High Current
IIH
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
all outputs driven
VDD = 3.3 V
-5
5
uA
1
-5
uA
1
-200
uA
1
7
5
6
5
mA
MHz
nH
pF
pF
pF
3
1
1
1
1
3
ms
1,2
33
5.5
0.4
kHz
V
V
mA
1
1
1
1
IIL1
Input Low Current
IIL2
Operating Current
Input Frequency3
Pin Inductance1
Input Capacitance1
Clk Stabilization1,2
Modulation Frequency
SMBus Voltage
Low-level Output Voltage
Current sinking at VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time3
SCLK/SDATA
Clock/Data Fall Time3
IDD3.3OP
Fi
Lpin
CIN
COUT
CINX
TSTAB
VDD
VOL
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-assertion
of PD# to 1st clock
Triangular Modulation
TYP
300
14.31818
30
2.7
@ IPULLUP
IPULLUP
MAX
4
UNITS NOTES
TRI2C
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
TFI2C
(Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
1
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
2
0883G—12/08/04
10
ICS951412
Electrical Characteristics - K8 Push Pull Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load
PARAMETER
SYMBOL
CONDITIONS
Rising Edge Rate
δV/δt
Falling Edge Rate
δV/δt
Measured at the AMD64 processor's
test load. 0 V +/- 400 mV (differential
measurement)
Differential Voltage
Change in VDIFF_DC
Magnitude
VDIFF
VCM
Change in Common
Mode Voltage
∆VCM
Jitter, Cycle to cycle
tjcyc-cyc
2
10
V/ns
1
2
10
V/ns
1
V
1
mV
1
V
1
200
mV
1
100 200
ps
1
0.4
∆VDIFF
Common Mode Voltage
MIN TYP MAX UNITS NOTES
-150
Measured at the AMD64 processor's
test load. (single-ended measurement)
150
1.05 1.25 1.45
-200
Measurement from differential
wavefrom. Maximum difference of cycle
time between 2 adjacent cycles.
1.25 2.3
0
Measured using the JIT2 software
package with a Tek 7404 scope.
TIE (Time Interval Error) measurement
tja
Jitter, Accumulated
-1000
1000
technique:
Sample resolution = 50 ps,
Sample Duration = 10 µs
Measurement from differential
dt3
45
53
Duty Cycle
wavefrom
Average value during switching
RON
Output Impedance
35
55
transition. Used for determining series 15
termination value.
Measurement from differential
tsrc-skew
250
Group Skew
wavefrom
1
Guaranteed by design and characterization, not 100% tested in production.
2
All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz
3
Spread Spectrum is off
0883G—12/08/04
11
1,2,3
%
1
Ω
1
ps
1
ICS951412
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
Current Source Output
Impedance
Zo
VO = Vx
3000
Voltage High
VHigh
Statistical measurement on
single ended signal using
oscilloscope math function.
Measurement on single ended
signal using absolute value.
660
Voltage Low
VLow
Max Voltage
Min Voltage
Vovs
Vuds
Crossing Voltage (abs) Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Tabsmin
tr
tf
d-tr
d-tf
MAX
UNITS NOTES
Ω
850
1
1,3
mV
-150
150
1150
-300
250
Variation of crossing over all
edges
see Tperiod min-max values
75.00 MHz nominal
75.00 MHz spread
100.00 MHz nominal
100.00 MHz spread
116.67 MHz nominal
116.67 MHz spread
133.33 MHz nominal
133.33 MHz spread
@100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
TYP
-300
8.5684
8.5684
9.9970
9.9970
13.3303
13.3303
7.4972
7.4972
9.8720
175
175
1,3
mV
1
1
350
550
mV
1
12
140
mV
1
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
1,2
1
1
1
1
300
8.5744
8.6244
10.0000 10.0030
10.0530
13.3333 13.3363
13.3863
7.5002 7.5032
7.5532
8.5714
30
30
700
700
125
125
Measurement from differential
45
55
%
1
wavefrom
Measurement from differential
tsrc-skew
Group Skew
250
ps
wavefrom
Measurement from differential
tjcyc-cyc
100
ps
1
Jitter, Cycle to cycle
wavefrom
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Duty Cycle
dt3
0883G—12/08/04
12
ICS951412
Electrical Characteristics - PCI33, HTT66 Clocks
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
PCI33 Clock period
Tperiod
HTT66 Clock period
Tperiod
Output High Voltage
Output Low Voltage
VOH
VOL
-300
29.9910
29.9910
14.9955
14.9955
2.4
Output High Current
IOH
Output Low Current
IOL
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
66.67MHz output nominal
66.67MHz output spread
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V
[email protected] MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
Jitter, Cycle to cycle
δV/δt
δV/δt
tr1
tf1
dt1
tsk1
tjcyc-cyc
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
1
1
0.5
0.5
45
1
TYP
MAX
300
30.0090
30.1598
15.0045
15.0799
0.55
-33
-33
30
38
4
4
2
2
55
500
180
UNITS NOTES
ppm
ns
ns
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
ns
ns
%
ps
ps
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF
is at 14.31818MHz
2
0883G—12/08/04
13
1,2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
ICS951412
Electrical Characteristics - 48MHz, USB
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
VOL
-200
20.8257
2.4
Output High Current
IOH
see Tperiod min-max values
48.00MHz output nominal
IOH = -1 mA
IOL = 1 mA
V OH @ MIN = 1.0 V
[email protected] MAX = 3.135 V
VOL @MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
Output Low Current
IOL
Edge Rate
Edge Rate
δV/δt
δV/δt
tr1
tf1
dt1
tjcyc-cyc
Rise Time
Fall Time
Duty Cycle
Jitter, Cycle to cycle
1
TYP
MAX
200
20.8340
38
2
2
ppm
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
1,2
2
1
1
1
1
1
1
1
1
2
2
55
180
ns
ns
%
ps
1
1
1
1
0.55
-33
-33
30
1
1
1
1
45
1.43
1.33
48
UNITS Notes
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF
is at 14.31818MHz
2
0883G—12/08/04
14
ICS951412
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
VOL
Output High Current
IOH
Output Low Current
IOL
Edge Rate
Edge Rate
Rise Time
Fall Time
Skew
Duty Cycle
δV/δt
δV/δt
tr1
tf1
tsk1
dt1
Jitter, Cycle to cycle
tjcyc-cyc
CONDITIONS
MIN
see Tperiod min-max values
-300
14.318MHz output nominal
69.8270
IOH = -1 mA
2.4
IOL = 1 mA
V OH @MIN = 1.0 V,
V
-29
@MAX
=
3.135
V
OH
VOL @MIN = 1.95 V,
VOL
29
@MAX = 0.4 V
Rising edge rate
1
Falling edge rate
1
VOL = 0.4 V, VOH = 2.4 V
1
VOH = 2.4 V, VOL = 0.4 V
1
VT = 1.5 V
VT = 1.5 V
45
VT = 1.5 V
1
TYP
MAX
UNITS
NOTES
300
69.8550
0.4
ppm
ns
V
V
1
2
1
1
-23
mA
1
27
mA
1
4
4
2
2
500
55
V/ns
V/ns
ns
ns
ps
%
1
1
1
1
1
1
700
ps
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is
at 14.31818MHz
2
0883G—12/08/04
15
ICS951412
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
L1 length, Route as non
-coupled 50 ohm trace.
0.5 max
L2 length, Route as non
-coupled 50 ohm trace.
0.2 max
L3 length, Route as non
-coupled 50 ohm trace.
0.2 max
Rs
33
Rt
49.9
Down Device Differential Routing
L4 length, Route as coupled
microstrip 100 ohm
differential trace.
L4 length, Route as coup
led stripline 100 ohm
differential trace.
Differential Routing to PCI Express Connector
L4 length, Route as coupled
microstrip 100 ohm
differential trace.
L4 length, Rout e as coupled stripline 100 ohm
differential trace.
L1
Unit
inch
inch
inch
ohm
ohm
Figure
2, 3
2, 3
2, 3
2, 3
2, 3
Dimension or Value
2 min to 16 max
Unit
inch
2
1.8 min to 14.4 max
inch
2
Dimension or Value
0.25 to 14 max
Unit
inch
3
0.225 min to 12.6
max
inch
3
Figure
L2
L4
Rs
L1’
L4’
L2’
Rs
Fig.1
Figure
Rt
HSCL Output
Buffer
Rt
L3’
L1
PCI Ex
REF_CLK
Test Load
L3
L2
L4
Rs
L1’
Fig.2
L4’
L2’
Rs
Rt
HSCL Output
Buffer
L3’
L1
Rt
PCI Ex Board
Down Device
REF_CLK Input
L3
L2
L4
Rs
L4’
L1’
L2’
Rs
Fig.3
Rt
HSCL Output
Buffer
L3’
0883G—12/08/04
16
Rt
L3
PCI Ex
Add In Board
REF_CLK Input
ICS951412
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS951412
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of PowerOn reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0883G—12/08/04
17
ICS951412
56-Lead, 300 mil Body, 25 mil, SSOP
c
N
SYMBOL
L
E1
INDEX
AREA
E
1 2
α
h x 45°
D
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
A
N
A1
-Ce
A
A1
b
c
D
E
E1
e
h
L
N
a
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
SEATING
PLANE
b
.10 (.004) C
56
D mm.
MIN
18.31
D (inch)
MAX
18.55
MIN
.720
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS951412yFLFT
Example:
ICS XXXX y F - LF T
Designation for tape and reel packaging
Lead Free (if required)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0883G—12/08/04
18
MAX
.730
ICS951412
c
N
L
E1
INDEX
AREA
E
1 2
a
D
A
A2
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
a
0°
8°
0°
8°
aaa
-0.10
-.004
VARIATIONS
A1
-Ce
b
SEATING
PLANE
aaa C
N
56
D mm.
MIN
13.90
D (inch)
MAX
14.10
MIN
.547
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS951412yGLFT
Example:
ICS XXXX y G - LF T
Designation for tape and reel packaging
Lead Free (if required)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0883G—12/08/04
19
MAX
.555
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