ON NTB45N06 Power mosfet 45 amps, 60 volts nâ channel toâ 220 and d2pak Datasheet

NTP45N06, NTB45N06
Power MOSFET
45 Amps, 60 Volts
N–Channel TO–220 and D2PAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
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Features
•
•
•
•
•
•
•
•
45 AMPERES
60 VOLTS
RDS(on) = 26 mΩ
Higher Current Rating
Lower RDS(on)
Lower VDS(on)
Lower Capacitances
Lower Total Gate Charge
Tighter VSD Specification
Lower Diode Reverse Recovery Time
Lower Reverse Recovery Stored Charge
N–Channel
D
Typical Applications
•
•
•
•
G
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
4
S
4
1
2
3
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 10 MΩ)
Gate–to–Source Voltage
– Continuous
– Non–Repetitive (tp10 ms)
Drain Current
– Continuous @ TA = 25°C
– Continuous @ TA = 100°C
– Single Pulse (tp10 µs)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1.)
Total Power Dissipation @ TA = 25°C (Note 2.)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, RG = 25 Ω,
IL(pk) = 40 A, L = 0.3 mH, VDS = 60 Vdc)
Symbol
Value
Unit
VDSS
VDGR
60
Vdc
60
Vdc
March, 2001 – Rev. 0
2
3
MARKING DIAGRAMS
& PIN ASSIGNMENTS
Vdc
VGS
VGS
20
30
ID
ID
IDM
PD
45
30
150
Adc
125
0.83
3.2
2.4
W
W/°C
W
W
TJ, Tstg
–55 to
+175
°C
EAS
240
mJ
4
Drain
4
Drain
Apk
1. When surface mounted to an FR4 board using 1″ pad size,
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in2).
 Semiconductor Components Industries, LLC, 2001
1
D2PAK
CASE 418B
STYLE 2
TO–220AB
CASE 221A
STYLE 5
1
NTB45N06
LLYWW
NTP45N06
LLYWW
1
Gate
3
Source
2
Drain
1
Gate
NTx45N06
LL
Y
WW
2
Drain
3
Source
= Device Code
= Location Code
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
NTP45N06
TO–220AB
50 Units/Rail
NTB45N06
D2PAK
50 Units/Rail
NTB45N06T4
D2PAK
800/Tape & Reel
Publication Order Number:
NTP45N06/D
NTP45N06, NTB45N06
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Thermal Resistance
– Junction–to–Case
– Junction–to–Ambient (Note 3.)
– Junction–to–Ambient (Note 4.)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Symbol
Value
Unit
RθJC
RθJA
RθJA
1.2
46.8
63.2
°C/W
TL
260
°C
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
–
70
57
–
–
–
–
–
–
1.0
10
–
–
±100
2.0
–
2.8
7.2
4.0
–
–
21
26
–
–
0.93
0.93
1.4
–
gFS
–
16.6
–
mhos
Ciss
–
1224
1725
pF
Coss
–
345
485
Crss
–
76
160
td(on)
–
10
25
tr
–
101
200
td(off)
–
33
70
tf
–
106
220
QT
–
33
46
Q1
–
6.4
–
Q2
–
15
–
VSD
–
–
1.08
0.93
1.2
–
Vdc
trr
–
53.1
–
ns
ta
–
36
–
tb
–
16.9
–
QRR
–
0.087
When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in2).
When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2).
Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
Switching characteristics are independent of operating junction temperatures.
–
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Note 5.)
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
µAdc
nAdc
ON CHARACTERISTICS (Note 5.)
Gate Threshold Voltage (Note 5.)
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain–to–Source On–Resistance (Note 5.)
(VGS = 10 Vdc, ID = 22.5 Adc)
RDS(on)
Static Drain–to–Source On–Voltage (Note 5.)
(VGS = 10 Vdc, ID = 45 Adc)
(VGS = 10 Vdc, ID = 22.5 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (Note 5.) (VDS = 8.0 Vdc, ID = 12 Adc)
Vdc
mV/°C
mOhm
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vd
Vdc, VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 6.)
Turn–On Delay Time
Rise Time
(VDD = 30 Vdc, ID = 45 Adc,
VGS = 10 Vdc, RG = 9.1 Ω) (Note 5.)
Turn–Off Delay Time
Fall Time
Gate Charge
Vd ID = 45 Adc,
Ad
(VDS = 48 Vdc,
VGS = 10 Vdc) (Note 5.)
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 45 Adc, VGS = 0 Vdc) (Note 5.)
(IS = 45 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 45 Adc,
Ad VGS = 0 Vdc,
Vd
dIS/dt = 100 A/µs) (Note 5.)
Reverse Recovery Stored Charge
3.
4.
5.
6.
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2
µC
NTP45N06, NTB45N06
90
90
VGS = 10 V
VGS = 7 V
VGS = 9 V
70
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
80
VGS = 6.5 V
60
VGS = 6 V
VGS = 8 V
50
VGS = 7.5 V
40
VGS = 5.5 V
30
VGS = 5 V
20
VGS = 4.5 V
10
VDS > = 10 V
80
70
60
50
40
30
TJ = 25°C
20
TJ = 100°C
10
TJ = –55°C
0
0
0
4
5
1
2
3
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
6
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
Figure 1. On–Region Characteristics
0.05
VGS = 10 V
0.042
0.034
TJ = 100°C
0.026
TJ = 25°C
0.018
0.01
TJ = –55°C
0
10
20
30
40
50
60
70
80
90
ID, DRAIN CURRENT (AMPS)
0.032
0.03
0.028
0.026
0.024
VGS = 10 V
0.022
0.02
0.018
VGS = 15 V
0
20
30
40
50
60
70
90
80
Figure 4. On–Resistance vs. Drain Current and
Gate Voltage
10000
2.2
VGS = 0 V
ID = 22.5 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
10
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance vs. Gate–to–Source
Voltage
2
8
1.8
TJ = 150°C
1000
1.6
1.4
1.2
TJ = 125°C
100
1
TJ = 100°C
0.8
0.6
–50 –25
10
0
25
50
75
100
125
150
175
0
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–to–Source Leakage Current
vs. Voltage
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3
60
3600
3200
TJ = 25°C
Ciss
2800
C, CAPACITANCE (pF)
VGS = 0 V
VDS = 0 V
Crss
2400
2000
1600
Ciss
1200
800
Coss
400
Crss
0
10
5 VGS 0 VDS 5
10
15
20
25
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
NTP45N06, NTB45N06
12
QT
10
VGS
8
Q1
6
Q2
4
2
ID = 45
TJ = 25°C
0
0
4
8
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE
(VOLTS)
100
tr
IS, SOURCE CURRENT (AMPS)
t, TIME (ns)
24
28
32
36
50
VDS = 30 V
ID = 45 A
VGS = 10 V
tf
td(off)
td(on)
10
1
10
VGS = 0 V
TJ = 25°C
40
30
20
10
0
0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 1 1.04
100
RG, GATE RESISTANCE (Ω)
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
dc
10 ms
10
1 ms
1
0.1
0.10
RDS(on) Limit
Thermal Limit
Package Limit
1
100 µs
10
100
Figure 10. Diode Forward Voltage vs. Current
EAS, SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
ID, DRAIN CURRENT (AMPS)
20
Figure 8. Gate–to–Source and
Drain–to–Source Voltage vs. Total Charge
1000
100
16
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
1
12
280
ID = 45 A
240
200
160
120
80
40
0
25
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
175
NTP45N06, NTB45N06
r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED)
1
Normalized to RθJC at Steady State
0.1
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t, TIME (s)
Figure 13. Thermal Response
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
10
Normalized to RθJA at Steady State,
1″ square Cu Pad, Cu Area 1.127 in2,
3 x 3 inch FR4 board
1
0.1
0.01
0.001
0.00001
0.0001
0.001
0.1
0.01
1
t, TIME (s)
Figure 14. Thermal Response
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5
10
100
1000
NTP45N06, NTB45N06
PACKAGE DIMENSIONS
TO–220 THREE–LEAD
TO–220AB
CASE 221A–09
ISSUE AA
SEATING
PLANE
–T–
B
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
----0.080
STYLE 5:
PIN 1.
2.
3.
4.
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6
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
----2.04
NTP45N06, NTB45N06
PACKAGE DIMENSIONS
D2PAK
CASE 418B–03
ISSUE D
C
E
V
–B–
4
A
1
2
3
S
–T–
SEATING
PLANE
K
J
G
D 3 PL
0.13 (0.005)
H
M
T B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM
A
B
C
D
E
G
H
J
K
S
V
INCHES
MIN
MAX
0.340
0.380
0.380
0.405
0.160
0.190
0.020
0.035
0.045
0.055
0.100 BSC
0.080
0.110
0.018
0.025
0.090
0.110
0.575
0.625
0.045
0.055
STYLE 2:
PIN 1.
2.
3.
4.
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7
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65
10.29
4.06
4.83
0.51
0.89
1.14
1.40
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
14.60
15.88
1.14
1.40
NTP45N06, NTB45N06
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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NTP45N06/D