Intersil ISL9104 500ma 4.3mhz low iq high efficiency synchronous Datasheet

500mA 4.3MHz Low IQ High Efficiency Synchronous
Buck Converter
ISL9104, ISL9104A
Features
The ISL9104, ISL9104A is a 500mA, 4.3MHz step-down
regulator, which is ideal for powering low-voltage
microprocessors in compact devices such as PDAs and cellular
phones. It is optimized for generating low output voltages
down to 0.8V. The supply voltage range is from 2.7V to 6V
allowing the use of a single Li+ cell, three NiMH cells or a
regulated 5V input. It has guaranteed minimum output current
of 500mA. A high switching frequency of 4.3MHz pulse-width
modulation (PWM) allows using small external components.
Under light load condition, the device operates at low IQ skip
mode with typical 20µA quiescent current for highest light
load efficiency to maximize battery life, and it automatically
switches to fixed frequency PWM mode under heavy load
condition.
• High Efficiency Integrated Synchronous Buck Regulator with
up to 93% Efficiency
The ISL9104, ISL9104A includes a pair of low ON-resistance
P-Channel and N-Channel internal MOSFETs to maximize
system efficiency and minimize the external component count.
100% duty-cycle operation allows less than 300mV dropout
voltage at 500mA.
The ISL9104, ISL9104A offers internal digital soft-start,
enable for power sequence, overcurrent protection and
thermal shutdown functions. In addition, the ISL9104,
ISL9104A offers a quick bleeding function that discharges the
output capacitor when the IC is disabled.
The ISL9104, ISL9104A is offered in a 1.6x1.6mm µTDFN
package. The complete converter occupies less than 0.5CM2.
Applications
• 2.7V to 6.0V Supply Voltage
• 4.3MHz PWM Switching Frequency
• 500mA Guaranteed Output Current
• 3% Output Accuracy Over-Temperature and Line for Fixed
Output Options
• 20µA Quiescent Supply Current in Skip Mode
• Less than 1µA Logic Controlled Shutdown Current
• 100% Maximum Duty Cycle for Lowest Dropout
• Ultrasonic Switching Frequency at Skip Mode to Prevent
Audible Frequency Noise (For ISL9104A Only)
• Discharge Output Capacitor when Disabled
• Internal Digital Soft-Start
• Peak Current Limiting, Short Circuit Protection
• Over-Temperature Protection
• Chip Enable
• Small 6 Pin 1.6mmx1.6mm µTDFN Package
• Pb-Free (RoHS Compliant)
Related Literature
• See AN1522, “ISL9104xxxxEVAL1Z, ISL9104AxxxxEVAL1Z
Evaluation Board Application Manual”
• Single Li-ion Battery-Powered Equipment
• Mobile Phones and MP3 Players
• PDAs and Palmtops
• WCDMA Handsets
• Portable Instruments
Pin Configuration
100
VIN 1
6 SW
EN 2
5 GND
NC 3
4 FB
95
90
EFFICIENCY (%)
ISL9104, ISL9104A
(6 LD 1.6x1.6 µTDFN)
TOP VIEW
85
80
75
70
65
VIN = 2.7V
VOUT = 1.8V
L = 1µH
60
55
50
1
10
100
1000
IOUT (mA)
FIGURE 1. EFFICIENCY vs OUTPUT CURRENT
September 21, 2011
FN6829.5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2008, 2009, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL9104, ISL9104A
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
VIN
Input supply voltage. Typically connect a 10µF ceramic capacitor to ground.
2
EN
Regulator enable pin. Enable the device when driven to high. Shut down the chip and discharge
output capacitor when driven to low. Do not leave this pin floating.
3
NC
No connect; leave floating.
4
FB
Buck converter output feedback pin. For adjustable output version, its typical value is 0.8V and
connect it to the output through a resistor divider for desired output voltage; for fixed output version,
directly connect this pin to the converter output.
5
GND
Ground connection.
6
SW
Switching node connection. Connect to one terminal of inductor.
Typical Applications
ISL9104, ISL9104A ADJUSTABLE OUTPUT
L
1.0µH
INPUT: 2.7V TO 6V
OUTPUT
UP TO 500mA
SW
VIN
C2
4.7µF
C1
4.7µF
R1
100k
C3
47pF
R2
100k
ENABLE
EN
DISABLE
FB
GND
ISL9104, ISL9104A FIXED OUTPUT
L
1.0µH
INPUT: 2.7V TO 6V
VIN
OUTPUT
UP TO 500mA
SW
C2
4.7µF
C1
4.7µ F
ENABLE
FB
EN
DISABLE
GND
FIGURE 2. TYPICAL APPLICATIONS DIAGRAM
Note: For adjustable output version, the internal feedback resistor divider is disabled and the FB pin is directly connected to the error
amplifier.
2
FN6829.5
September 21, 2011
ISL9104, ISL9104A
PARTS
DESCRIPTION
MANUFACTURERS
PART NUMBER
SPECIFICATIONS
SIZE
L
Inductor
KEMET
LB3218-T1R0MK
1.0µH/1.0A/60mΩ
3.2mmx1.8mmx1.8mm
C1, C2
Input and output
capacitor
Murata
GRM188R60J475KE19D
4.7µF/6.3V, X5R
0603
C3
Capacitor
KEMET
C0402C470J5GACTU
47pF/50V
0402
R1, R2
Resistor
Various
-
100kΩ, SMD, 1%
0402
Ordering Information
PART NUMBER
(Notes 1, 3, 4)
PART
MARKING
OUTPUT VOLTAGE
(V) (Note 2)
ULTRASONIC
FUNCTION
TEMP RANGE
(°C)
PACKAGE
Tape and Reel
(Pb-Free)
PKG
DWG. #
ISL9104IRUNZ-T
K6
3.3
NO
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104IRUJZ-T
K7
2.8
NO
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104IRUFZ-T
K8
2.5
NO
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104IRUDZ-T
K9
2.0
NO
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104IRUCZ-T
L0
1.8
NO
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104IRUBZ-T
L1
1.5
NO
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
L6.1.6x1.6
ISL9104IRUWZ-T
L2
1.2
NO
-40 to +85
6 Ld µTDFN
ISL9104IRUAZ-T
L3
ADJ
NO
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104AIRUNZ-T
L4
3.3
YES
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104AIRUJZ-T
L5
2.8
YES
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104AIRUFZ-T
L6
2.5
YES
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104AIRUDZ-T
L7
2.0
YES
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104AIRUCZ-T
L8
1.8
YES
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104AIRUBZ-T
L9
1.5
YES
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104AIRUWZ-T
M0
1.2
YES
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104AIRUAZ-T
M1
ADJ
YES
-40 to +85
6 Ld µTDFN
L6.1.6x1.6
ISL9104AIRUAEVAL1Z
Evaluation Board
ISL9104AIRUBEVAL1Z
Evaluation Board
ISL9104AIRUCEVAL1Z
Evaluation Board
ISL9104AIRUDEVAL1Z
Evaluation Board
ISL9104AIRUFEVAL1Z
Evaluation Board
ISL9104AIRUJEVAL1Z
Evaluation Board
ISL9104AIRUNEVAL1Z
Evaluation Board
ISL9104AIRUWEVAL1Z
Evaluation Board
ISL9104IRUAEVAL1Z
Evaluation Board
ISL9104IRUBEVAL1Z
Evaluation Board
ISL9104IRUCEVAL1Z
Evaluation Board
ISL9104IRUDEVAL1Z
Evaluation Board
ISL9104IRUFEVAL1Z
Evaluation Board
ISL9104IRUJEVAL1Z
Evaluation Board
ISL9104IRUNEVAL1Z
Evaluation Board
ISL9104IRUWEVAL1Z
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. Other output voltage options may be available upon request, please contact Intersil for more details.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL9104, ISL9104A. For more information on MSL please see techbrief
TB363.
3
FN6829.5
September 21, 2011
ISL9104, ISL9104A
Absolute Maximum Ratings
Thermal Information
VIN, EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SW to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FB to GND (for adjustable version) . . . . . . . . . . . . . . . . . . . . . .
FB to GND (for fixed output version). . . . . . . . . . . . . . . . . . . . .
-0.3V to 6.5V
-1.5V to 6.5V
-0.3V to 2.7V
-0.3V to 3.6V
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 6.0V
Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . up to 500mA
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
θJA (°C/W)
Thermal Resistance (Typical, Note 5)
1.6x1.6 µTDFN Package . . . . . . . . . . . . . . . . . . . . . . . . .
160
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating
conditions and the typical specifications are measured at the following conditions: TA = +25°C, VIN = VEN = 3.6V, L = 1.0µH, C1 = 4.7µF,
C2 = 4.7µF, IOUT = 0A (see “Typical Applications” on page 2). Boldface limits apply over the operating temperature range,
-40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
-
2.5
2.7
V
50
150
-
mV
SUPPLY
Undervoltage Lockout Threshold (UVLO)
VUVLO
TA = +25°C, Rising
UVLO Hysteresis
Quiescent Supply Current (for ISL9104
adjustable output voltage only)
IVIN1
In skip mode, no load at the output, no switch,
VIN = 6.0V
-
20
34
µA
Quiescent Supply Current (for ISL9104A
adjustable output only)
IVIN2
In skip mode, no load at the output, no switch,
VIN = 6.0V
-
32
45
µA
In skip mode, no load at the output, VIN = 6.0V
-
84
-
µA
VIN = 6.0V, EN = LOW
-
0.05
1
µA
TA = 0°C to +85°C
-2
-
+2
%
-2.5
-
+2.5
%
Quiescent Supply Current (for ISL9104A 1.5V
fixed output)
Shut Down Supply Current
ISD
OUTPUT REGULATION
FB Voltage Accuracy (for adjustable output only)
FB Voltage
VFB
FB Bias Current (for adjustable output only)
IFB
0.8
V
VFB = 0.75V
-
5
100
nA
Output Voltage Accuracy (for fixed output
voltage only)
PWM Mode
-3
-
3
%
Line Regulation
VIN = VO + 0.5V to 6V (minimal 2.7V)
-
0.2
-
%/V
Load Regulation
VIN =3.6V, IO = 150mA to 500mA
-
0.0009
-
%/mA
VIN = 3.6V, IO = 200mA
-
0.45
0.6
Ω
VIN = 2.7V, IO = 200mA
-
0.55
0.72
Ω
VIN = 3.6V, IO = 200mA
-
0.4
0.52
Ω
VIN = 2.7V, IO = 200mA
-
0.5
0.65
Ω
-
100
-
Ω
0.75
1.00
1.35
A
-
100
-
%
SW
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
N-Channel Bleeding MOSFET ON-Resistance
P-Channel MOSFET Peak Current Limit
Maximum Duty Cycle
4
IPK
VIN = 4.2V
FN6829.5
September 21, 2011
ISL9104, ISL9104A
Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating
conditions and the typical specifications are measured at the following conditions: TA = +25°C, VIN = VEN = 3.6V, L = 1.0µH, C1 = 4.7µF,
C2 = 4.7µF, IOUT = 0A (see “Typical Applications” on page 2). Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
-
0.01
2
µA
3.6
4.3
4.9
MHz
SW Minimum On-Time
-
65
-
ns
Soft-Start-Up Time
-
1.0
-
ms
Logic Input Low
-
-
0.4
V
Logic Input High
1.4
-
-
V
Logic Input Leakage Current
-
0.1
1
µA
Thermal Shutdown
-
130
-
°C
Thermal Shutdown Hysteresis
-
30
-
°C
PARAMETER
SYMBOL
SW Leakage Current
TEST CONDITIONS
SW at Hi-Z state
PWM Switching Frequency
fS
VIN = 3.6V, TA = -20°C to +85°C
EN
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Typical Operating Performance
100
100
VIN = 2.7V
90
90
80
70
VIN = 4.9V
VIN = 3.8V
60
EFFICIENCY (%)
EFFICIENCY (%)
80
50
40
30
30
10
0.2
0.3
LOAD CURRENT (A)
0.4
0
0
0.5
FIGURE 3. EFFICIENCY vs LOAD CURRENT (VOUT = 1.5V)
VIN = 5.5V
40
20
0.1
VIN = 4.5V
50
10
0
VIN = 3.5V
60
20
0
0.1
0.2
0.3
LOAD CURRENT (A)
0.4
0.5
FIGURE 4. EFFICIENCY vs LOAD CURRENT (VOUT = 2.5V)
1.630
30
1.625
25
T = +85°C
1.620
T = +25°C
VO (V)
QUIESCENT CURRENT (µA)
70
20
LOAD CURRENT RISING
1.615
1.610
15
1.605
LOAD CURRENT FALLING
T = -45°C
10
2.70
1.600
3.25
3.80
4.35
4.90
5.45
6.00
INPUT VOLTAGE (V)
FIGURE 5. INPUT QUIESCENT CURRENT vs VIN (VOUT = 2.5V)
5
0
100
200
300
IOUT (mA)
400
500
FIGURE 6. OUTPUT VOLTAGE vs LOAD CURRENT (VIN = 3.6V,
VOUT = 1.6V)
FN6829.5
September 21, 2011
ISL9104, ISL9104A
Typical Operating Performance (Continued)
2.505
5V/DIV
2.500
LOAD CURRENT RISING
VSW
VO (V)
2.495
1V/DIV
2.490
VOUT
2.485
200mA/DIV
LOAD CURRENT FALLING
2.480
5V/DIV
2.475
0
100
200
300
IOUT(mA)
400
FIGURE 8. SOFT-START TO PFM MODE (VIN = 3.6V,
VOUT = 1.5V, IOUT = 0.001mA)
5V/DIV
VSW
VSW
2V/DIV
1V/DIV
VOUT
VOUT
200mA/DIV
500mA/DIV
IL
IL
5V/DIV
5V/DIV
EN
EN
FIGURE 9. SOFT-START TO PWM MODE (VIN = 3.6V,
VOUT = 1.5V, IOUT = 500mA)
5V/DIV
EN
500
FIGURE 7. OUTPUT VOLTAGE vs LOAD CURRENT (V IN = 4.0V,
VOUT = 2.5V)
5V/DIV
IL
FIGURE 10. SOFT-START TO PFM MODE (VIN = 3.6V, VOUT = 2.5V,
IOUT = 0.001mA)
5V/DIV
VSW
VSW
20mV/DIV
20mV/DIV
VOUT (AC-COUPLED)
VOUT (AC-COUPLED)
20mA/DIV
20mA/DIV
Io
FIGURE 11. LOAD TRANSIENT IN PFM MODE (VIN = 3.6V,
VOUT = 1.5V, 5mA TO 30mA)
6
Io
FIGURE 12. LOAD TRANSIENT IN PFM MODE (VIN = 3.6V,
VOUT = 1.5V, 30mA TO 5mA)
FN6829.5
September 21, 2011
ISL9104, ISL9104A
Typical Operating Performance (Continued)
5V/DIV
5V/DIV
VSW
20mV/DIV
20mV/DIV
VOUT (AC-COUPLED)
VOUT (AC-COUPLED)
20mA/DIV
20mA/DIV
Io
FIGURE 13. LOAD TRANSIENT IN PFM MODE (VIN = 3.6V,
VOUT = 2.5V, 5mA TO 30mA)
5V/DIV
VSW
FIGURE 14. LOAD TRANSIENT IN PFM MODE (VIN = 3.6V,
VOUT = 2.5V, 30mA TO 5mA)
5V/DIV
VSW
50mV/DIV
50mV/DIV
Io
VSW
VOUT (AC-COUPLED)
VOUT (AC-COUPLED)
200mA/DIV
200mA/DIV
Io
FIGURE 15. LOAD TRANSIENT FROM PFM TO PWM MODE
(VIN = 3.6V, VOUT = 1.5V, 5mA TO 300mA)
5V/DIV
Io
FIGURE 16. LOAD TRANSIENT FROM PWM TO PFM MODE
(VIN = 3.6V, VOUT = 1.5V, 300mA TO 5mA)
5V/DIV
VSW
VSW
50mV/DIV
50mV/DIV
VOUT (AC COUPLED)
VOUT (AC COUPLED)
200mA/DIV
200mA/DIV
Io
FIGURE 17. LOAD TRANSIENT FROM PFM TO PWM MODE
(VIN = 3.6V, VOUT = 2.5V, 5mA TO 300mA)
7
Io
FIGURE 18. LOAD TRANSIENT FROM PWM TO PFM MODE
(VIN = 3.6V, VOUT = 2.5V, 300mA TO 5mA)
FN6829.5
September 21, 2011
ISL9104, ISL9104A
Typical Operating Performance (Continued)
5V/DIV
5V/DIV
VSW
VSW
20mV/DIV
20mV/DIV
VOUT (AC COUPLED)
500mA/DIV
VOUT
500mA/DIV
Io
FIGURE 19. LOAD TRANSIENT IN PWM MODE (V IN = 3.6V,
VO = 1.5V, 200mA TO 500mA)
5V/DIV
Io
FIGURE 20. LOAD TRANSIENT IN PWM MODE (VIN = 3.6V,
VO = 1.5V, 500mA TO 200mA)
5V/DIV
VSW
VSW
20mV/DIV
20mV/DIV
VOUT (AC COUPLED)
VOUT (AC COUPLED)
500mA/DIV
500mA/DIV
Io
FIGURE 21. LOAD TRANSIENT IN PWM MODE (VIN = 3.6V,
VO = 2.5V, 200mA TO 500mA)
8
Io
FIGURE 22. LOAD TRANSIENT IN PWM MODE (VIN = 3.6V,
VO = 2.5V, 500mA TO 200mA)
FN6829.5
September 21, 2011
ISL9104, ISL9104A
Block Diagram
SHUTDOWN
SHUTDOWN
SOF
SOFTT
STAR
START
T
OSCILLATOR
BANDGAP
VREF
+
EN
VIN
+
EAMP
PWM/PFM
COMP
LOGIC
CONTROLLER
PROTECTION
SW
DRIVER
SLOPE
COMP
X
GND
FB
*NOTE
BLEEDING
FET
100Ω
+
+
OCP
CSA
VREF1
SCP
VREF3
+
+
SKIP
VREF2
ZERO-CROSS
SENSING
*NOTE: FOR FIXED OUTPUT OPTIONS ONLY
NOTE: For Adjustable output version, the internal feedback resistor divider is disabled and the FB pin is directly connected
to the error amplifier.
FIGURE 23. FUNCTIONAL BLOCK DIAGRAM
Theory of Operation
PWM Control Scheme
The ISL9104, ISL9104A is a step-down switching regulator
optimized for battery-powered handheld applications. The
regulator operates at typical 4.3MHz fixed switching frequency
under heavy load condition to allow small external inductor and
capacitors to be used for minimal printed-circuit board (PCB)
area. At light load, the regulator can automatically enter the skip
mode (PFM mode) to reduce the switching frequency to minimize
the switching loss and to maximize the battery life. The quiescent
current under skip mode under no load and no switch condition
is typically only 20µA. The supply current is typically only 0.05µA
when the regulator is disabled.
The ISL9104, ISL9104A uses the peak-current-mode pulse-width
modulation (PWM) control scheme for fast transient response
and pulse-by-pulse current limiting. Figure 23 shows the circuit
functional block diagram. The current loop consists of the
oscillator, the PWM comparator COMP, current sensing circuit,
and the slope compensation for the current loop stability. The
current sensing circuit consists of the resistance of the P-Channel
MOSFET when it is turned on and the Current Sense Amplifier
(CSA). The control reference for the current loops comes from the
Error Amplifier (EAMP) of the voltage loop.
9
FN6829.5
September 21, 2011
ISL9104, ISL9104A
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the P-Channel MOSFET starts ramping
up. When the sum of the CSA output and the compensation
slope reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
P-Channel MOSFET and to turn on the N-Channel MOSFET. The
N-MOSFET remains on till the end of the PWM cycle. Figure 24
shows the typical operating waveforms during the normal PWM
operation. The dotted lines illustrate the sum of the slope
compensation ramp and the CSA output.
vEAMP
vCSA
d
iL
vOUT
FIGURE 24. PWM OPERATION WAVEFORMS
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a 0.8V
reference voltage to the voltage control loop. The feedback signal
comes from the FB pin. The soft-start block only affects the
operation during the start-up and will be discussed separately in
“Soft-Start” on page 11. The EAMP is a transconductance
amplifier, which converts the voltage error signal to a current
output. The voltage loop is internally compensated by a RC
network. The maximum EAMP voltage output is precisely
clamped to the bandgap voltage.
Skip Mode (PFM Mode)
Under light load condition, ISL9104, ISL9104A automatically
enters a pulse-skipping mode to minimize the switching loss by
reducing the switching frequency. Figure 25 illustrates the skip
mode operation. A zero-cross sensing circuit (as shown in Figure
23) monitors the current flowing through SW node for zero
crossing. When it is detected to cross zero for 16-consecutive
cycles, the regulator enters the skip mode. During the 16consecutive cycles, the inductor current could be negative. The
counter is reset to zero when the sensed current flowing through
SW node does not cross zero during any cycle within the 16consecutive cycles. Once ISL9104, ISL9104A enters the skip
mode, the pulse modulation starts being controlled by the SKIP
comparator shown in Figure 23. Each pulse cycle is still
synchronized by the PWM clock. The P-Channel MOSFET is turned
on at the rising edge of clock and turned off when its current
reaches ~20% of the peak current limit. As the average inductor
current in each cycle is higher than the average current of the
load, the output voltage rises cycle over cycle. When the output
voltage is sensed to reach 1.5% above its nominal voltage, the
P-Channel MOSFET is turned off immediately and the inductor
current is fully discharged to zero and stays at zero. The output
voltage reduces gradually due to the load current discharging the
output capacitor. When the output voltage drops to the nominal
voltage, the P-Channel MOSFET will be turned on again,
repeating the previous operations.
The regulator resumes normal PWM mode operation when the
output voltage is sensed to drop below 1.5% of its nominal
voltage value.
Enable
The enable (EN) pin allows user to enable or disable the converter
for purposes such as power-up sequencing. With EN pin pulled to
high, the converter is enabled and the internal reference circuit
wakes up first and then the soft start-up begins. When EN pin is
pulled to logic low, the converter is disabled, both P-Channel
MOSFET and N-Channel MOSFETS are turned off, and the output
capacitor is discharged through internal discharge path.
16 CYCLES
CLOCK
20% PEAK CURRENT LIMIT
IL
0
1.015*VOUT_NOMINAL
VOUT
VOUT_NOMINAL
FIGURE 25. SKIP MODE OPERATION WAVEFORMS
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ISL9104, ISL9104A
Overcurrent Protection
The overcurrent protection is provided on ISL9104, ISL9104A when
overload condition happens. It is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 23 on page 9.
When the current at P-Channel MOSFET is sensed to reach the
current limit, the OCP comparator is trigged to turn off the
P-Channel MOSFET immediately.
Short-Circuit Protection
ISL9104, ISL9104A has a Short-Circuit Protection (SCP)
comparator, which monitors the FB pin voltage for output shortcircuit protection. When the output voltage is sensed to be lower
than a certain threshold, the SCP comparator reduces the PWM
oscillator frequency to a much lower frequency to protect the IC
from being damaged.
Undervoltage Lockout (UVLO)
When the input voltage is below the Undervoltage Lock Out
(UVLO) threshold, ISL9104, ISL9104A is disabled.
Soft-Start
The soft-start feature eliminates the in-rush current during the circuit
start-up. The soft-start block outputs a ramp reference to both the
voltage loop and the current loop. The two ramps limit the inductor
current rising speed as well as the output voltage speed so that the
output voltage rises in a controlled fashion.
Low Dropout Operation
The ISL9104, ISL9104A features low dropout operation to maximize
the battery life. When the input voltage drops to a level that
ISL9104, ISL9104A can no longer operate under switching
regulation to maintain the output voltage, the P-Channel MOSFET is
completely turned on (100% duty cycle). The dropout voltage under
such condition is the product of the load current and the
ON-resistance of the P-Channel MOSFET. Minimum required input
voltage VIN under this condition is the sum of output voltage plus the
voltage drop cross the inductor and the P-Channel MOSFET switch.
Thermal Shut Down
The ISL9104, ISL9104A provides built-in thermal protection
function. The thermal shutdown threshold temperature is
+130°C (typ) with a 30°C (typ) hysteresis. When the internal
temperature is sensed to reach +130°C, the regulator is
completely shut down and as the temperature drops to +100°C
(typ), the ISL9104, ISL9104A resumes operation starting from
the soft-start.
Applications Information
Inductor and Output Capacitor Selection
To achieve better steady state and transient response, ISL9104,
ISL9104A typically uses a 1.0µH inductor. The peak-to-peak
inductor current ripple can be expressed in Equation 1:
VO ⎞
⎛
V O • ⎜ 1 – --------⎟
V
⎝
IN⎠
ΔI = -----------------------------------L • fS
In Equation 1, usually the typical values can be used but to have
a more conservative estimation, the inductance should consider
the value with worst case tolerance; and for switching frequency
fS, the minimum fS from the “Electrical Specifications” table on
page 4 can be used.
To select the inductor, its saturation current rating should be at
least higher than the sum of the maximum output current and
half of the delta calculated from Equation 1. Another more
conservative approach is to select the inductor with the current
rating higher than the P-Channel MOSFET peak current limit.
Another consideration is the inductor DC resistance since it
directly affects the efficiency of the converter. Ideally, the
inductor with the lower DC resistance should be considered to
achieve higher efficiency.
Inductor specifications could be different from different
manufacturers so please check with each manufacturer if
additional information is needed.
For the output capacitor, a ceramic capacitor can be used
because of the low ESR values, which helps to minimize the
output voltage ripple. A typical value of 4.7µF/6.3V ceramic
capacitor should be enough for most of the applications and the
capacitor should be X5R or X7R.
Input Capacitor Selection
The main function for the input capacitor is to provide decoupling
of the parasitic inductance and to provide filtering function to
prevent the switching current from flowing back to the battery rail.
A 4.7µF/6.3V ceramic capacitor (X5R or X7R) is a good starting
point for the input capacitor selection.
Output Voltage Setting Resistor Selection
For ISL9104, ISL9104A adjustable output option, the voltage
resistors, R1 and R2, as shown in Figure 2, set the desired output
voltage values. The output voltage can be calculated using
Equation 2:
R 1⎞
⎛
V O = V FB • ⎜ 1 + -------⎟
R
⎝
2⎠
(EQ. 2)
where VFB is the feedback voltage (typically it is 0.8V). The
current flowing through the voltage divider resistors can be
calculated as VO/(R1 + R2), so larger resistance is desirable to
minimize this current. On the other hand, the FB pin has leakage
current that will cause error in the output voltage setting. The
leakage current has a typical value of 0.1µA. To minimize the
accuracy impact on the output voltage, select the R2 no larger
than 200kΩ.
For adjustable output versions, C3 (shown in Figure 2 on page 2)
is highly recommended for improving stability and achieving
better transient response.
Table 1 provides the recommended component values for some
output voltage options.
(EQ. 1)
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ISL9104, ISL9104A
TABLE 1. RECOMMENDED IISL9104, ISL9104A ADJUSTABLE OUTPUT
VERSION CIRCUIT CONFIGURATION vs VOUT
VOUT (V)
L (µH)
C2 (µF)
R1 (kΩ)
C3 (pF)
R2 (kΩ)
0.8
1.0
4.7
0
N/A
N/A
1.0
1.0
4.7
44.2
100
178
1.2
1.0
4.7
80.6
47
162
1.5
1.0
4.7
84.5
47
97.6
1.8
1.0
4.7
100
47
80.6
2.5
1.0
4.7
100
47
47.5
2.8
1.0
4.7
100
47
40.2
3.3
1.0
4.7
102
47
32.4
Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well, especially under the high
current high switching frequency condition.
For ISL9104, ISL9104A, the power loop is composed of the
output inductor L, the output capacitor COUT, the SW pin and the
PGND pin. It is necessary to make the power loop as small as
possible and the connecting traces among them should be
direct, short and wide; the same type of traces should be used to
connect the VIN pin, the input capacitor CIN and its ground.
The switching node of the converter, the SW pin, and the traces
connected to this node are very noisy, so keep the voltage
feedback trace and other noise sensitive traces away from these
noisy traces.
The input capacitor should be placed as close as possible to the
VIN pin. The ground of the input and output capacitors should be
connected as close as possible as well. In addition, a solid ground
plane is helpful for EMI performance.
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ISL9104, ISL9104A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
CHANGE
04/08/2011
FN6829.5
Converted to new Intersil Template
Added Efficiency Curve to page 1.
Added Related Literature to page 1.
Updated Ordering Information with Eval Boards.
Added Rev History and Products information.
11/24/2009
FN6829.4
Updated ordering information by removing coming soon from parts with Voltage Output of 2.8V, 2.0V and 1.8V
and added MSL note. Updated Electrical Spec conditions by adding Boldface limit text and bolding MIN and MAX
columns. Removed over-temp note from conditions in Electrical spec and placed at end of table as note. Placed
pinout descriptions in a table and placed after pinout.
07/09/2009
FN6829.3
Changed P-Channel MOSFET Peak Current Limit Max Value from "1.25A” to “1.35A”.
06/24/2009
FN6829.2
Removed coming soon in ordering information from parts ISL9104IRUWZ-T
and ISL9104AIRUWZ-T. Updated Voltage option Note in ordering information to match verbiage that is in
ISL9103, ISL9103A.
Test condition for P-Channel MOSFET Peak Current Limit updated from “VIN = 3.6” to "VIN = 4.2V"
05/29/2009
FN6829.1
Added to conditions of SW Leakage Current - "SW at Hi-Z state”.
12/23/2008
FN6829.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL9104, ISL9104A
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN6829.5
September 21, 2011
ISL9104, ISL9104A
Package Outline Drawing
L6.1.6x1.6
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD COL PLASTIC PACKAGE (UTDFN COL)
Rev 1, 11/07
2X 1.00
1.60
A
6
PIN 1
INDEX AREA
PIN #1 INDEX AREA
6
B
4X 0.50
1
3
5X 0 . 40 ± 0 . 1
1X 0.5 ±0.1
1.60
(4X)
0.15
4
6
0.10 M C A B
TOP VIEW
4 0.25 +0.05 / -0.07
BOTTOM VIEW
( 6X 0 . 25 )
SEE DETAIL "X"
( 1X 0 .70 )
0 . 55 MAX
0.10 C
C
BASE PLANE
(1.4 )
SIDE VIEW
SEATING PLANE
0.08 C
0 . 2 REF
C
( 5X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
( 4X 0 . 5 )
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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FN6829.5
September 21, 2011