ICS650-36 Networking & PCI Clock Source Description Features The ICS650-36 is a low cost frequency generator designed to support networking and PCI applications. Using analog/digital Phase Locked-Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal input of 25 MHz to produce four output clocks supporting LAN, PCI, and 100M SDRAM functions. • • • • • • The device also has a power down feature that tri-states the clock outputs and turns off the PLL when the PDTS pin is taken low. • • • • Packaged in 16-pin TSSOP Available in Pb (lead) free package Replaces multiple crystals and oscillators Input crystal or clock frequency of 25 MHz Fixed reference output frequency of 25 MHz Selectable output frequencies of 33.3, 33.333, 50, 66.666, 100, and 125 MHz Duty cycle of 40/60 Operating voltage of 3.3 V Advanced, low-power CMOS process Industrial and commercial temperature ranges Block Diagram VDD 3 S2:0 Select/ Control Circuit 3 X1/ICLK 25 MHz crystal input X2 CLK1 PLL2 CLK2 PLL3 CLK3 Crystal Oscillator/ Clock Buffer REF 3 External capacitors may be required. GND PDTS 1 MDS 650-36 D I n t e gra te d C i r c u i t S ys t e m s PLL1 ● 5 25 Race Street, San Jose, CA 9 5126 (all outputs and PLLs) Revision 030206 ● tel (408 ) 2 97-12 01 ● www.icst.co m ICS650-36 Networking & PCI Clock Source Pin Assignment CLK Output Selection Table S2 S1 S0 REF CLK1 CLK2 CLK3 X2 1 16 VDD 0 0 0 OFF 33.30 50 125 X1 2 15 GND 0 0 1 ON 33.333 33.333 125 GND 3 14 REF 0 1 0 ON 33.333 66.666 125 CLK3 4 13 S0 0 1 1 ON 66.666 66.666 125 PDTS S2 5 12 VDD 1 0 0 ON 33.333 50 125 6 11 CLK1 1 0 1 ON 33.333 50 100 GND 1 1 0 ON 33.333 66.666 100 S1 1 1 1 ON 33.30 50 125 CLK2 7 10 VDD 8 9 Note: All frequencies are in MHz. 16-pin (173 mil) TSSOP Pin Descriptions Pin Number Pin Name Pin Type 1 X2 Output 2 X1 Input Crystal connection. Connect to 25 MHz crystal or clock input. 3 GND Power Connect to ground. 4 CLK3 Output Selectable clock output. See table above for frequency. Weak internal pull-down when tri-state. PDTS Input 6 S2 Input 7 CLK2 Output Selectable clock output. See table above for frequency. Weak internal pull-down when tri-state. 8 VDD Power Connect to +3.3 V. 9 S1 Input Select pin. Selects clock output frequency from table above. Internal pull-up resistor. 10 GND Power Connect to ground. 11 CLK1 Output Selectable clock output. See table above for frequency. Weak internal pull-down when tri-state. 12 VDD Power Connect to +3.3 V. 13 S0 Input Select pin. Selects clock output frequency from table above. Internal pull-up resistor. 5 Crystal connection. Connect to 25 MHz crystal input or float for clock. Powers down entire chip and tri-states outputs when low. Internal pull-up resistor. Select pin. Selects clock output frequency from table above. Internal pull-up resistor. 2 MDS 650-36 D In te grated C ircuit Syste ms Pin Description ● 525 R ace Street, San Jose, CA 9 5126 Revision 030206 ● tel (40 8) 29 7-120 1 ● w ww.i c s t. c o m ICS650-36 Networking & PCI Clock Source Pin Number Pin Name Pin Type Pin Description 14 REF Output Reference 25 MHz clock output. Weak internal pull-down when tri-state. 15 GND Power Connect to ground. 16 VDD Power Connect to +3.3 V. External Components Decoupling Capacitor As with any high performance mixed-signal IC, the ICS650-36 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between each VDD and the PCB ground plane. Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. PCB Layout Recommendations Observed the following guidelines for optimum device performance and lowest output phase noise: 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) Place the 33Ω series termination resistor (if needed) close to the clock output to minimize EMI. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS650-36. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. 3 MDS 650-36 D In te grated C ircuit Syste ms The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2 = 20]. ● 525 R ace Street, San Jose, CA 9 5126 Revision 030206 ● tel (40 8) 29 7-120 1 ● w ww.i c s t. c o m ICS650-36 Networking & PCI Clock Source Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS650-36. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD -0.5 V to 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70°C Ambient Operating Temperature (industrial) -40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Power Supply Voltage (measured in respect to GND) Max. Units 0 +70 °C -40 +85 °C +3.465 V +3.135 +3.3 4 MDS 650-36 D In te grated C ircuit Syste ms Typ. ● 525 R ace Street, San Jose, CA 9 5126 Revision 030206 ● tel (40 8) 29 7-120 1 ● w ww.i c s t. c o m ICS650-36 Networking & PCI Clock Source DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C Parameter Symbol Conditions Min. Typ. Max. Units 3.135 3.3 3.465 V Operating Voltage VDD Supply Current IDD No load, PDTS=1 25 mA IDDPD No load, PDTS=0 100 µA Power Down Current Input High Voltage VIH PDTS, S2:0 Input Low Voltage VIL PDTS, S2:0 Output High Voltage VOH IOH = -4 mA VDD-0.3 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA Short Circuit Current IOS Clock outputs Input Capacitance, inputs 2 V 0.8 0.4 V V ±65 mA CIN 5 pF Nominal Output Impedance ZOUT 20 Ω Internal Pull-up Resistor RPU PDTS, S2:0 500 kΩ Internal Pull-down Resistor RPD Outputs 250 kΩ Typ. Max. Units AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C Parameter Symbol Input Frequency fIN Output Rise Time tOR Output Fall Time tOF Conditions Min. 25 MHz 20% to 80%, Note 1 0.8 ns 80% to 20%, Note 1 0.7 ns Output Clock Duty Cycle at VDD/2, Note 1 40 Absolute Clock Period Jitter Note 1 ±125 ps Clock Jitter, Cycle-to-Cycle 33.333M, 66.666M, Note 1 150 ps Clock Jitter, Long Term 25M, n=1000, Note1 900 ps 0 ppm Frequency Synthesis Error 60 % Output Enable Time tOE PDTS high to output locked to ±1% 350 µs Output Disable Time tOD PDTS low to tri-state 25 ns Note 1: Measured with a 15 pF load. 5 MDS 650-36 D In te grated C ircuit Syste ms ● 525 R ace Street, San Jose, CA 9 5126 Revision 030206 ● tel (40 8) 29 7-120 1 ● w ww.i c s t. c o m ICS650-36 Networking & PCI Clock Source Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units θJA Still air 78 °C/W θJA 1 m/s air flow 70 °C/W θJA 3 m/s air flow 68 °C/W 37 °C/W θJC Marking Diagrams (ICS650G-36) (ICS650G-36LF) 16 16 9 650G-36 ###### YYWW$$ 1 9 650G36LF ###### YYWW 1 8 (ICS650GI-36) 8 (ICS650GI-36LF) 16 9 16 650GI-36 ###### YYWW$$ 1 9 650GI36L ###### YYWW 8 1 8 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. “LF” or “L” designates Pb free packaging. 4. “I” designates industrial temperature range. 5. Bottom marking: (origin). Origin = country of origin if not USA. 6 MDS 650-36 D In te grated C ircuit Syste ms ● 525 R ace Street, San Jose, CA 9 5126 Revision 030206 ● tel (40 8) 29 7-120 1 ● w ww.i c s t. c o m ICS650-36 Networking & PCI Clock Source Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E1 A A1 A2 b C D E E1 e L α aaa E IN D EX AR EA 1 2 D A 2 Min Inches* Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 *For reference only. Controlling dimensions in mm. A A 1 c -C e S E A T IN G P LA N E b L aaa C Ordering Information Part / Order Number ICS650G-36 ICS650G-36T ICS650G-36LF ICS650G-36LFT ICS650GI-36 ICS650GI-36T ICS650GI-36LF ICS650GI-36LFT Marking (see page 6) (see page 6) Shipping Packaging Package Temperature Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 0 to +70 °C 0 to +70 °C 0 to +70 °C 0 to +70 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 7 MDS 650-36 D In te grated C ircuit Syste ms ● 525 R ace Street, San Jose, CA 9 5126 Revision 030206 ● tel (40 8) 29 7-120 1 ● w ww.i c s t. c o m