CS3001
CS3002
Precision Low Voltage Amplifier; DC to 2 kHz
Features
Description
Low Offset: 10 µV Max
Low Drift: 0.05 µV/°C Max
Low Noise
The CS3001 single amplifier and the CS3002 dual amplifier are designed for precision amplification of low
level signals and are ideally suited to applications that
require very high closed loop gains. These amplifiers
achieve excellent offset stability, super high open loop
gain, and low noise over time and temperature. The devices also exhibit excellent CMRR and PSRR. The
common mode input range includes the negative supply
rail. The amplifiers operate with any total supply voltage
from 2.7 V to 6.7 V (±1.35 V to ±3.35 V).
– 6 nV/√Hz @ 0.5 Hz
– 0.1 to 10 Hz = 125 nVp-p
– 1/f corner @ 0.08 Hz
Open-Loop Voltage Gain
– 1000 Trillion Typ
– 10 Billion Min
Pin Configurations
Rail-to-Rail Output Swing
1.8 mA Supply Current
Slew rate: 5 V/µs
CS3001
Applications
Thermocouple/Thermopile Amplifiers
Load Cell and Bridge Transducer Amplifiers
Precision Instrumentation
Battery-Powered Systems
PWDN
1
-In
2
+In
3
V-
4
CS3002
8 NC
Out A 1
-
7 V+
-In A 2
+
6 Output
+In A 3
5 NC
A
- +
7 Out B
B
+ -
V- 4
8-lead SOIC
Noise vs. Frequency (Measured)
8 V+
6 -In B
5 +In B
8-lead SOIC
CS3001
Dexter Research
Thermopile 1M
100
nV/√Hz
R2
64.9k
10
R1
100
1
0.001
0.01
0.1
1
10
Frequency (Hz)
Preliminary Product Information
Cirrus Logic, Inc.
http://www.cirrus.com
C1
0.015µ F
Thermopile Amplifier with a Gain of 650 V/V
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
OCT ‘02
DS490PP1
1
CS3001
CS3002
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ................................................... 3
1.1 Electrical Characteristics ...................................................................................... 3
1.2 Absolute Maximum Ratings ................................................................................. 4
2. PERFORMANCE PLOTS ......................................................................................... 4
3. CS3001/CS3002 OVERVIEW ................................................................................... 7
3.1 Open Loop Gain and Phase Response .................................................................. 7
3.2 Open Loop Gain and Stability Compensation ...................................................... 8
3.3 Powerdown (PDWN) ......................................................................................... 10
3.4 Applications ........................................................................................................ 11
4. PACKAGE DRAWING ........................................................................................... 13
5. ORDERING INFORMATION ............................................................................... 14
LIST OF FIGURES
Figure 1. Noise vs Frequency (Measured) .........................................................................4
Figure 2. 0.01 Hz to 10 Hz Noise .......................................................................................4
Figure 3. Noise vs Frequency ............................................................................................4
Figure 4. Offset Voltage Stability (DC to 3.2 Hz) ...............................................................4
Figure 5. Open Loop Gain and Phase vs Frequency .........................................................5
Figure 6. Open Loop Gain and Phase vs Frequency (Expanded) .....................................5
Figure 7. Input Bias Current vs Supply Voltage (CS3002) .................................................6
Figure 8. Input Bias Current vs Common Mode Voltage ...................................................6
Figure 9. CS3001/CS3002 Open Loop Gain and Phase Response ..................................7
Figure 10. Non-Inverting Gain Configuration .....................................................................8
Figure 11. Non-Inverting Gain Configuration with Compensation ......................................9
Figure 12. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation ......................10
Figure 13. Thermopile Amplifier with a Gain of 650 V/V ..................................................11
Figure 14. Load Cell Bridge Amplifier and A/D Converter ...............................................12
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to <http://www.cirrus.com/corporate/contacts/sales.cfm>
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this
information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus
and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only
for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
2
CS3001
CS3002
1. CHARACTERISTICS AND SPECIFICATIONS
1.1
Electrical Characteristics
V+ = +5 V, V- = 0V, VCM = 2.5 V (Note 1)
CS3001/CS3002
Parameter
Min
Typ
Max
Unit
Input Offset Voltage
(Note 2)
•
-
-
±10
µV
Average Input Offset Drift
(Note 2)
•
-
±0.01
±0.05
µV/ºC
Long Term Input Offset Voltage Stability
(Note 3)
TA = 25º C
-
±100
±200
±1000
pA
pA
-
±200
±400
±2000
pA
pA
Input Noise Voltage Density RS = 100 Ω, f0 = 1 Hz
RS = 100 Ω, f0 = 1 kHz
-
6
6
nV/ Hz
nV/ Hz
Input Noise Voltage
-
125
nVp-p
Input Noise Current Density f0 = 1 Hz
-
2
pA/ Hz
Input Noise Current
-
40
pAp-p
•
-0.1
-
(V+)-1.25
V
•
115
120
-
dB
•
120
136
-
dB
•
200
300
-
dB
•
+4.7
+4.99
-
V
V
5
-
V/µs
-
100
-
µs
Input Bias Current
•
TA = 25º C
Input Offset Current
•
0.1 to 10 Hz
0.1 to 10 Hz
Input Common Mode Voltage Range
Common Mode Rejection Ratio (dc)
(Note 4)
Power Supply Rejection Ratio
Large Signal Voltage Gain RL = 2 kΩ to V+/2
Output Voltage Swing
RL = 2 kΩ to V+/2
RL = 100 kΩ to V+/2
Slew Rate
(Note 5)
RL = 2 k, 100 pF
Overload Recovery Time
Supply Current per Amplifier
PWDN active (CS3001 Only)
•
•
-
1.8
(Note 6)
2.4
15
mA
µA
PWDN Threshold
(Note 6)
•
(V+) -1.0
-
-
V
Start-up Time
(Note 7)
•
-
9
12
ms
Notes: 1. Symbol “•” denotes specification applies over -40 to +85 ° C.
2. This parameter is guaranteed by design and laboratory characterization. Thermocouple effects prohibit
accurate measurement of these parameters in automatic test systems.
3. 1000-hour life test data @ 125 °C indicates randomly distributed variation approximately equal to
measurement repeatability of 1 µV.
4. Measured within the specified common mode range limits.
5. Guaranteed within the output limits of (V+ -0.3 V) to (V- +0.3 V). Tested with proprietary production test
method.
6. PWDN input has an internal pullup resistor to V+ of approximately 800 kΩ and is the major source of
current consumption when PWDN is active low.
7. The device has a controlled start-up behavior due to its complex open loop gain characteristics. Startup time applies when supply voltage is applied or when PDWN is released.
3
CS3001
CS3002
1.2
Absolute Maximum Ratings
Parameter
Supply Voltage
Min
Typ
Max
Unit
6.8
V
V- -0.3
V+ +0.3
V
-65
+150
ºC
[(V+) - (V-)]
Input Voltage
Storage Temperature Range
2. PERFORMANCE PLOTS
1000
Noise vs. Frequency (Measured)
100
nV/√Hz
nV/√Hz
100
10
10
1
10
1
0.001
0.01
0.1
1
Frequency (Hz)
50
25
nV
50
nV
100
75
0
-50
1
2
3
4
5
6
7
8
9
10
TIME (Sec)
Figure 2. 0.01 Hz to 10 Hz Noise
4
10K
100K
1M
10M
Figure 3. Noise vs Frequency
100
0
1K
Frequency (Hz)
Figure 1. Noise vs Frequency (Measured)
-100
100
10
σ = 13 nV
0
-25
-50
-75
-100
Time (1 Hour)
Figure 4. Offset Voltage Stability (DC to 3.2 Hz)
CS3001
CS3002
500
400
300
200
100
0
-100
-200
-300
-400
-500
Gain
Phase
10
100
1K
10K
100K
1M
10M
Frequency (Hz)
Figure 5. Open Loop Gain and Phase vs Frequency
100
80
Gain (dB)
1
60
40
20
0
-45
Phase (Degrees)
Gain (dB)
Phase (Degrees)
Performance Plots (Cont.)
-90
-135
-180
-225
-270
-315
-360
10K
100K
1M
10M
Figure 6. Open Loop Gain and Phase vs Frequency (Expanded)
5
CS3001
CS3002
Performance Plots (Cont.)
Input Bias Current (pA)
-150
A1A1+
B1A2+
B1+
A2-
-100
-50
0
-50
-100
B2B2+
CM = 0 V
-150
-200
±2.5
±2
±1.35
±3.35
Supply Voltage (±V)
Bias Current
Normalized to CM = 2.5 V
Figure 7. Input Bias Current vs Supply Voltage (CS3002)
3
2
1
0
-1
-2
-3
0
1
2
3
4
Common Mode Voltage (Vs = 5V)
Figure 8. Input Bias Current vs Common Mode Voltage
6
5
CS3001
CS3002
3. CS3001/CS3002 OVERVIEW
The CS3001/CS3002 amplifiers are designed for
precision measurement of signals from DC to
2 kHz when operating from a supply voltage of
+2.7 V to +6.7 V (± 1.35 to ± 3.35 V). The amplifiers are designed with a patented architecture that
utilizes multiple amplifier stages to yield very high
open loop gain at frequencies of 10 kHz and below.
The amplifiers yield low noise and low offset drift
while consuming relatively low supply current. An
increase in noise floor above 2 kHz is the result of
intermediate stages of the amplifier being operated
at very low currents. The amplifiers are intended
for amplifying small signals with large gains in applications where the output of the amplifier can be
band-limited to frequencies below 2 kHz.
3.1
Open Loop Gain and Phase
Response
Figure 9 illustrates the open loop gain and phase response of the CS3001/CS3002. The gain slope of
the amplifier is about –100 dB/decade between
500 Hz and 60 kHz and transitions to –20 dB/decade between 60 kHz and its unity gain crossover
frequency at about 4.8 MHz. Phase margin at unity
gain is about 70 degrees; gain margin is about
20 dB.
100
Gain (dB)
80
-100 dB/ dec
60
40
-20 dB/ dec
20
0
Phase (Degrees)
-45
-90
-135
-180
-225
-270
-315
-360
10K
100K
1M
10M
Figure 9. CS3001/CS3002 Open Loop Gain and Phase Response
7
CS3001
CS3002
3.2
Open Loop Gain and Stability
Compensation
The CS3001 and CS3002 achieve ultra-high open
loop gain. Figure 10 illustrates the amplifier in a
non-inverting gain configuration. The open loop
gain and phase plots indicate that the amplifier is
stable for closed-loop gains less than 50 V/V. For a
gain of 50, the phase margin is between 40° and 60°
depending upon the loading conditions. As shown
in Figure 11 on page 9, the op amp has an input capacitance at the + and – signal inputs of typically
50 pF. This capacitance adds an additional pole in
the loop gain transfer function at a frequency of
f = 1/(2πR*Cin) where R is the parallel combination of R1 and R2 (R1 || R2). A higher value for R
produces a pole at a lower frequency, thus reducing
the phase margin. R1 is recommended to be less
than or equal to 100 ohms, which results in a pole
at 30 MHz or higher. If a higher value of R1 is desired, a compensation capacitor (C2) should be
added in parallel with R2. C2 should be chosen
such that R2*C2 ≥ R1*Cin.
RS
V in
Vo
R2
R1
Figure 10. Non-Inverting Gain Configuration
8
CS3001
CS3002
V in
C in
50 p F
Vo
50 p F
C in
R2
C h o o se C 2 so th at R 2C 2
R1
≥
R 1C in
C2
Figure 11. Non-Inverting Gain Configuration with Compensation
The feedback capacitor C2 is required for closedloop gains greater than 50 V/V. The capacitor introduces a pole and a zero in the loop gain transfer
function,
s
– 1 + -----
z 1
T = ----------------------- A ol
s
1 + -----
p1
1
1
P 1 = ------------------------------------- ≅ ------------------------2π ( R 1 || R 2 )C 2 2π ( R 1 C 2 )
for
1
Z 1 = ----------------------------------2π ( A × R 1 )C 2
R
A = -----2R1
where
This indicates that the separation of the pole and
the zero is governed by the closed loop gain. It is
required that the zero falls on the steep slope
(–100 dB/decade) of the loop gain plot so that there
is some gain higher than 0 dB (typically 20 dB) at
the hand-over frequency (the frequency at which
the slope changes from – 100 dB/decade to
–20 dB/decade).
R2 » R1
9
CS3001
CS3002
Capacitor C2 can be increased in value to limit the
amplifier’s rising noise above 2 kHz.
The loop gain plot shown in Figure 12 illustrates
the unity gain configuration, and indicates how this
is modified when using the amplifier in a higher
gain configuration with compensation. If it is configured for higher gain, for example, 60 dB, the
x–axis will move up by 60 dB (line B). Capacitor
C2 adds a zero and a pole. The modified plot indicates the effects of introducing the pole and zero
due to capacitor C2. The pole can be located at any
frequency higher than the hand-over frequency, the
zero has to be at a frequency lower than the handover frequency so as to provide adequate gain margin. The separation between the pole and the zero
is governed by the closed loop gain. The zero (z1)
occurs at the intersection of the –100 dB/decade
and –80 dB/decade slopes. The point X in the figure should be at closed loop gain plus 20 dB gain
margin. The value for C2 = 1/(2πR1p1). Using
p1 = 1 MHz works very well and is independent of
gain. As the closed loop gain is changed, the zero
location is also modified if R1 remains fixed.
3.3
Powerdown (PDWN)
The CS3001 single amplifier provides a powerdown function on pin 1. If this pin is left open the
amplifier will operate normally. If the powerdown
is asserted low, the amplifier will go into a low
power state. There is a pull-up resistor (approximately 800 k ohm) inside the amplifier from pin
1 to the V+ supply. The current through this pull-up
resistor is the main source of current drain in the
powerdown state.
3.4
Applications
The CS3001 and CS3002 amplifiers are optimum
for applications that require high gain and low drift.
Figure 13 illustrates a thermopile amplifier with a
gain of 650 V/V. The thermopile outputs only a few
millivolts when subjected to infrared radiation. The
amplifier is compensated and bandlimited by C1 in
combination with R2.
|T| (Log gain)
-100 dB/dec
z1
p1
-80 dB/dec
X
Margin
B
Desired Closed
Loop Gain
-20 dB/dec
50kHz
1MHz
5MHz
FREQUENCY
Figure 12. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation
10
CS3001
CS3002
Figure 14 on page 12 illustrates a load cell bridge
amplifier with a gain of 768 V/V. The load cell is
excited with +5 V and has a 1 mV/V sensitivity. Its
full scale output signal is amplified to produce a
fully differential ± 3.8 V into the CS5510/12 A/D
converter. This circuit operates from +5 V.
A similar circuit operating from +3 V can be
constructed using the CS5540/CS5541 A/D converters.
C S 3 00 1
D exter Research
Therm opile 1M
R2
6 4 .9k
R1
10 0
C1
0 .0 1 5 µ F
T h e rm o p ile A m p lifie r w ith a G ain o f 65 0 V /V
Figure 13. Thermopile Amplifier with a Gain of 650 V/V
11
CS3001
CS3002
+5 V
+5 V
VA
+5 V
0 .1 µ F
V+
+
x768
VREF
CS
1 00 Ω
1 m V /V
-
350 Ω
1 4 0 kΩ
0 .2 2 µ F
SC LK
C S 5 5 1 0 /1 2
+
365 Ω
-
1 4 0 kΩ
0 .0 4 7 µ F
C o u n te r /T im e r
0 .2 2 µ F
A IN 1
+
V-
100 Ω
SCL
S C L K = 1 0 k H z to 1 0 0
k H (3 2 .7 6 8
K = 1 0 ik Hl) z t o 1 0
0 kH z
( 3 2 . 7 6 8 n o m i n a l)
Figure 14. Load Cell Bridge Amplifier and A/D Converter
12
µ
SDO
A IN +
CS3001
CS3002
4. PACKAGE DRAWING
8L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1
b
c
D
SEATING
PLANE
∝
A
L
e
A1
INCHES
DIM
A
A1
B
C
D
E
e
H
L
∝
MIN
0.053
0.004
0.013
0.007
0.189
0.150
0.040
0.228
0.016
0°
MAX
0.069
0.010
0.020
0.010
0.197
0.157
0.060
0.244
0.050
8°
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.02
1.52
5.80
6.20
0.40
1.27
0°
8°
JEDEC # : MS-012
13
CS3001
CS3002
5. ORDERING INFORMATION
Part #
Temperature Range
Package Description
CS3001-IS
-40 °C to +85 °C
8-lead SOIC
CS3002-IS
-40 °C to +85 °C
8-lead SOIC
Note: Add the letter R to the Part # to order reels. There are 2000 pieces per reel.
14
• Notes •