AD ADAU1966 16-channel high performance Datasheet

16-Channel High Performance
Differential Output, 192 kHz, 24-Bit DAC
ADAU1966
FEATURES
GENERAL DESCRIPTION
118 dB DAC dynamic range and SNR
−98 dB THD + N
Differential voltage DAC output
2.5 V digital and 3.3 V or 5 V analog and IO supplies
299 mW total (19 mW/channel) quiescent power at AVDD = 3.3 V
PLL generated or direct MCLK master clock
Low EMI design
Linear regulator driver to generate digital supply
Supports 24-bit and 32 kHz to 192 kHz sample rates
Low propagation 192 kHz sample rate mode
Log volume control with autoramp function
Temperature sensor with digital readout ±3°C accuracy
SPI and I2C controllable for flexibility
Software-controllable clickless mute
Software power-down
Right-justified, left-justified, I2S, and TDM modes
Master and slave modes with up to 16-channel input/output
80-lead LQFP package
Qualified for automotive applications
The ADAU1966 is a high performance, single-chip DAC that
provides 16 digital-to-analog converters (DACs) with differential output using the Analog Devices, Inc., patented multibit
sigma-delta (Σ-Δ) architecture. An SPI/I2C port is included,
allowing a microcontroller to adjust volume and many other
parameters. The ADAU1966 operates from 2.5 V digital and
3.3 V or 5 V analog supplies. A linear regulator is included to
generate the digital supply voltage from the analog supply voltage. The ADAU1966 is available in an 80-lead LQFP package.
The ADAU1966 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the internal master clock
from an external LRCLK, the ADAU1966 can eliminate the
need for a separate high frequency master clock and can be
used with or without a bit clock. The DACs are designed using
the latest Analog Devices continuous time architectures to
further minimize EMI. By using 2.5 V digital supplies, power
consumption is minimized, and the digital waveforms are a
smaller amplitude, further reducing emissions.
APPLICATIONS
Automotive audio systems
Home theater systems
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT
ADAU1966
SERIAL DATA PORT
DAC
DAC
DAC
DAC
DIFFERENTIAL
ANALOG
AUDIO
OUTPUTS
DAC
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
SDATA
IN
SDATA
IN
CLOCKS
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
DAC
DAC
DAC
DIFFERENTIAL
ANALOG
AUDIO
OUTPUTS
DAC
DAC
DAC
PRECISION
VOLTAGE
REFERENCE
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
SPI/I2C
CONTROL PORT
CONTROL DATA
INPUT/OUTPUT
INTERNAL
TEMP
SENSOR
09434-001
DAC
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADAU1966
TABLE OF CONTENTS
Features .............................................................................................. 1
Block Power-Down and Thermal Sensor Control 1 Register26
Applications ....................................................................................... 1
Power-Down Control 2 Register .............................................. 27
General Description ......................................................................... 1
Power-Down Control 3 Register .............................................. 28
Functional Block Diagram .............................................................. 1
Thermal Sensor Temperature Readout Register .................... 29
Revision History ............................................................................... 2
DAC Control 0 Register ............................................................ 30
Specifications..................................................................................... 3
DAC Control 1 Register ............................................................ 31
Analog Performance Specifications ........................................... 3
DAC Control 2 Register ............................................................ 32
Crystal Oscillator Specifications................................................. 5
DAC Individual Channel Mutes 1 Register ............................ 33
Digital Input/Output Specifications........................................... 6
DAC Individual Channel Mutes 2 Register ............................ 34
Power Supply Specifications........................................................ 6
Master Volume Control Register.............................................. 35
Digital Filters ................................................................................. 7
DAC 1 Volume Control Register .............................................. 35
Timing Specifications .................................................................. 7
DAC 2 Volume Control Register .............................................. 36
Absolute Maximum Ratings............................................................ 9
DAC 3 Volume Control Register .............................................. 36
Thermal Resistance ...................................................................... 9
DAC 4 Volume Control Register .............................................. 37
ESD Caution .................................................................................. 9
DAC 5 Volume Control Register .............................................. 37
Pin Configuration and Function Descriptions ........................... 10
DAC 6 Volume Control Register .............................................. 38
Typical Performance Characteristics ........................................... 13
DAC 7 Volume Control Register .............................................. 38
Application Circuits ....................................................................... 14
DAC 8 Volume Control Register .............................................. 39
Theory of Operation ...................................................................... 15
DAC 9 Volume Control Register .............................................. 39
Digital-to-Analog Converters (DACs) .................................... 15
DAC 10 Volume Control Register............................................ 40
Clock Signals ............................................................................... 15
DAC 11 Volume Control Register............................................ 40
Power-Up and RST ..................................................................... 16
DAC 12 Volume Control Register............................................ 41
Standalone Mode ........................................................................ 17
DAC 13 Volume Control Register............................................ 41
I2C Control Port .......................................................................... 17
DAC 14 Volume Control Register............................................ 42
Serial Control Port: SPI Control Mode ................................... 19
DAC 15 Volume Control Register............................................ 42
Power Supply and Voltage Reference ....................................... 19
DAC 16 Volume Control Register............................................ 43
Serial Data Ports—Data Format ............................................... 19
Common-Mode and Pad Strength Register ........................... 43
Time-Division Multiplexed (TDM) Modes ............................ 19
DAC Power Adjust 1 Register ................................................... 44
Temperature Sensor ................................................................... 20
DAC Power Adjust 2 Register ................................................... 45
Additional Modes ....................................................................... 22
DAC Power Adjust 3 Register ................................................... 46
Register Summary .......................................................................... 23
DAC Power Adjust 4 Register ................................................... 47
Register Details ............................................................................... 24
Outline Dimensions ....................................................................... 51
PLL and Clock Control 0 Register ........................................... 24
Ordering Guide .......................................................................... 51
PLL and Clock Control 1 Register ........................................... 25
Automotive Products ................................................................. 51
REVISION HISTORY
9/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 52
ADAU1966
SPECIFICATIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word
width = 24 bits, load capacitance (digital output) = 20 pF, load current (digital output) = ±1 mA or 1.5 kΩ to ½ DVDD supply, input
voltage high = 2.0 V, input voltage low = 0.8 V, unless otherwise noted.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at AVDDx = 5 V and an ambient temperature of 25°C. Supply voltages = AVDDx = 5 V, DVDD = 2.5 V,
ambient temperature1 (TA) = 25°C, unless otherwise noted.
Table 1.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Differential Output Voltage
Gain Error
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE VOLTAGES
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
TEMPERATURE SENSOR
Temperature Accuracy
Temperature Readout Range
Temperature Readout Step Size
Temperature Sample Rate
REGULATOR
Input Supply Voltage
Regulated Output Voltage
1
Test Conditions/Comments
Min
Typ
105
108
115.5
118
−90
−98
−98
3.00 (±8.49)
Max
Unit
20 Hz to 20 kHz, −60 dB input
0 dBFS
Two channels running, −1 dBFS
16 channels running, −1 dBFS
AVDDx = 5.0 V
−10
−25
−30
−6
−85
+10
+25
+30
100
0
0.375
95.25
±0.6
100
TS_REF pin, AVDDx = 5.0 V
CM pin, AVDDx = 5.0 V
CM pin, AVDDx = 5.0 V
2.14
1.50
2.25
2.25
−3
−60
2.29
+3
+140
VSUPPLY pin
VSENSE pin
Functionally guaranteed at −40°C to +125°C case temperature.
Rev. 0 | Page 3 of 52
3.0
2.26
5
2.50
V
V
V
6
°C
°C
°C
Hz
5.5
2.59
V
V
1
0.25
dB
dB
dB
dB
dB
V rms (V p-p)
%
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
ADAU1966
Specifications guaranteed at AVDDx = 5 V and an ambient temperature of 105°C. Supply voltages = AVDDx = 5 V, DVDD = 2.5 V,
ambient temperature 1 (TA) = 105°C, unless otherwise noted.
Table 2.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Differential Output Voltage
Gain Error
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
REGULATOR
Input Supply Voltage
Regulated Output Voltage
1
Test Conditions/Comments
Min
Typ
109
110.5
113.5
116
−85
−92.5
−92.5
3.00 (±8.49)
Max
Unit
20 Hz to 20 kHz, −60 dB input
0 dBFS
Two channels running
Eight channels running
AVDDx = 5.0 V
−10
−25
−30
−6
−85
+10
+25
+30
100
0
0.375
95.25
±0.6
100
dB
dB
dB
dB
dB
V rms (V p-p)
%
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
TS_REF pin, AVDDx = 5.0 V
CM pin, AVDDx = 5.0 V
CM pin, AVDDx = 5.0 V
2.14
1.50
2.25
2.25
2.29
V
V
V
VSUPPLY pin
VSENSE pin
3.0
2.25
5
2.50
5.5
2.55
V
V
Functionally guaranteed at −40°C to +125°C case temperature.
Specifications guaranteed at AVDDx = 3.3 V and an ambient temperature of 25°C. Supply voltages = AVDDx = 3.3 V, DVDD = 2.5 V,
ambient temperature 1 (TA) = 25°C, unless otherwise noted.
Table 3.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Differential Output Voltage
Gain Error
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-Emphasis Gain Error
Output Resistance at Each Pin
Test Conditions/Comments
Min
Typ
109
111.5
111
113.5
−90
−97
−97
2.00 (±5.66)
Max
Unit
20 Hz to 20 kHz, −60 dB input
0 dBFS
Two channels running
Eight channels running
AVDDx = 3.3 V
−10
−25
−30
−6
−85
+10
+25
+30
100
0
0.375
95.25
±0.6
100
Rev. 0 | Page 4 of 52
dB
dB
dB
dB
dB
V rms (V p-p)
%
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
ADAU1966
Parameter
REFERENCE
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
REGULATOR
Input Supply Voltage
Regulated Output Voltage
1
Test Conditions/Comments
Min
Typ
Max
Unit
TS_REF pin, AVDDx = 3.3 V
CM pin, AVDDx = 3.3 V
CM pin, AVDDx = 3.3 V
1.43
1.50
1.50
1.50
1.56
V
V
V
VSUPPLY pin
VSENSE pin
3.0
2.26
5
2.50
5.5
2.59
V
V
Functionally guaranteed at −40°C to +125°C case temperature.
Specifications guaranteed at AVDDx = 3.3 V and an ambient temperature of 105°C. Supply voltages = AVDDx = 3.3 V, DVDD = 2.5 V,
ambient temperature 1 (TA) = 105°C, unless otherwise noted.
Table 4.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Differential Output Voltage
Gain Error
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
REGULATOR
Input Supply Voltage
Regulated Output Voltage
1
Conditions/Comments
Min
Typ
108
110
109
112
−85
−92
−92
2.00 (5.66)
Max
Unit
20 Hz to 20 kHz, −60 dB input
0 dBFS
Two channels running
Eight channels running
AVDDx = 3.3 V
−10
−25
−30
−6
−83
+10
+25
+30
100
0
0.375
95.25
±0.6
100
dB
dB
dB
dB
dB
V rms (V p-p)
%
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
TS_REF pin, AVDDx = 3.3 V
CM pin, AVDDx = 3.3 V
CM pin, AVDDx = 3.3 V
1.43
1.50
1.50
1.50
1.56
V
V
V
VSUPPLY pin
VSENSE pin
3.0
2.25
5
2.50
5.5
2.55
V
V
Functionally guaranteed at −40°C to +125°C case temperature.
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 5.
Parameter
Transconductance, TA = 25°C
Transconductance, TA = 105°C
Min
6.4
5.2
Typ
7 to 10
7.5 to 8.5
Rev. 0 | Page 5 of 52
Max
14
12
Unit
mmhos
mmhos
ADAU1966
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +105°C, IOVDD = 5.0 V and 3.3 V ± 10%.
Table 6.
Parameter
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Leakage
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Input Capacitance
Test Conditions/Comments
IOVDD = 5.0 V
IOVDD = 3.3 V
IOVDD = 5.0 V
IOVDD = 3.3 V
IIH at VIH = 2.4 V
IIL at VIL = 0.8 V
IOH = 1 mA
IOL = 1 mA
Min
3.7
2.5
Typ
Max
1.3
0.8
10
10
IOVDD − 0.60
0.4
5
Unit
V
V
V
V
μA
μA
V
V
pF
POWER SUPPLY SPECIFICATIONS
Table 7.
Parameter
SUPPLIES
Voltage
Analog Current—AVDD = 5.0 V
Normal Operation
Power-Down
Analog Current—AVDD = 3.3 V
Normal Operation
Power-Down
Digital Current—DVDD = 2.5 V
Normal Operation
Power-Down
PLL Current—PLLVDD = 2.5 V
Normal Operation
Power-Down
IO Current—IOVDD = 3.3 V
Normal Operation
Power-Down
QUIESCENT DISSIPATION—DITHER INPUT
Operation
All Supplies
All Supplies
Analog Supply
Analog Supply
Digital Supply
PLL Supply
I/O Supply
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
Test Conditions/Comments
Min
Typ
Max
Unit
AVDD
DVDD
PLLVDD
IOVDD
VSUPPLY
3.0
2.25
2.25
3.0
3.0
5.0
2.5
2.5
5.0
5.0
5.5
3.6
3.6
5.5
5.5
V
V
V
V
V
82
1
mA
μA
60
1
mA
μA
fS = 48 kHz to 192 kHz
No MCLK or I2S
30
4
mA
μA
fS = 48 kHz to 192 kHz
5
1
mA
μA
4
1
mA
μA
511
299
410
198
75
13
13
0
mW
mW
mW
mW
mW
mW
mW
mW
85
85
dB
dB
MCLK = 256 × fS, 48 kHz
AVDDx = 5.0 V, DVDD/PLLVDD = 2.5 V, IOVDD = 3.3 V
AVDDx = 3.3 V, DVDD/PLLVDD = 2.5 V, IOVDD = 3.3 V
AVDDx = 5.0 V
AVDDx = 3.3 V
DVDD = 2.5 V
PLLVDD= 2.5 V
IOVDD = 3.3 V
1 kHz, 200 mV p-p
20 kHz, 200 mV p-p
Rev. 0 | Page 6 of 52
ADAU1966
DIGITAL FILTERS
Table 8.
Parameter
DAC INTERPOLATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Propagation Delay
Mode
Factor
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
192 kHz low delay mode, typical at 192 kHz
0.4535 × fS
0.3646 × fS
0.3646 × fS
Min
Typ
Max
22
35
70
±0.01
±0.05
±0.1
0.5 × fS
0.5 × fS
0.5 × fS
0.5465 × fS
0.6354 × fS
0.6354 × fS
24
48
96
26
61
122
68
68
68
25/fS
11/fS
8/fS
2/fS
521
115
42
10
Unit
kHz
kHz
kHz
dB
dB
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
μs
μs
μs
μs
TIMING SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 2.5 V ± 10%.
Table 9.
Parameter
INPUT MASTER CLOCK (MCLK) AND RESET
tMH
tMH
fMCLK
fMCLK
fBCLK
tPDR
tPDRR
PLL
Lock Time
Lock Time
256 × fS VCO Clock, Output Duty Cycle, MCLKO Pin
SPI PORT
tCCH
tCCL
fCCLK
tCDS
tCDH
tCLS
tCLH
tCLHIGH
Description
Min
MCLK duty cycle, DAC clock source = PLL clock at
256 × fS, 384 × fS, 512 × fS, and 768 × fS
DAC clock source = direct MCLK at 512 × fS (bypass
on-chip PLL)
MCLKI frequency, PLL mode
Direct MCLK 512 × fS mode
DBCLK frequency, PLL mode
Low
Recovery, reset to active output
Max
Unit
40
60
%
40
60
%
6.9
40.5
27.1
27.0
MHz
MHz
MHz
ns
ms
10
50
60
ms
ms
%
15
300
MCLK input
DLRCLK input
40
See Figure 14
CCLK high
CCLK low
CCLK frequency, fCCLK = 1/tCCP; only tCCP shown in Figure 14
CDATA setup, time to CCLK rising
CDATA hold, time from CCLK rising
CLATCH setup, time to CCLK rising
CLATCH hold, time from CCLK falling
CLATCH high, not shown in Figure 14
Rev. 0 | Page 7 of 52
Typ
35
35
10
10
10
10
10
10
ns
ns
MHz
ns
ns
ns
ns
ns
ADAU1966
Parameter
tCOE
tCOD
tCOH
tCOTS
I2C
fSCL
tSCLL
tSCLH
tSCS
Description
COUT enable from CCLK falling
COUT delay from CCLK falling
COUT hold from CCLK falling, not shown in Figure 14
COUT tristate from CCLK falling
See Figure 2 and Figure 13
SCL clock frequency
SCL low
SCL high
Setup time (start condition), relevant for repeated start
condition
Hold time (start condition), first clock generated after
this period
Setup time (stop condition)
Data setup time
SDA and SCL rise time
SDA and SCL fall time
Bus-free time between stop and start
See Figure 16
DBCLK high, slave mode
DBCLK low, slave mode
DLRCLK setup, time to DBCLK rising, slave mode
DLRCLK hold from DBCLK rising, slave mode
DLRCLK skew from DBCLK falling, master mode
DSDATAx setup to DBCLK rising
DSDATAx hold from DBCLK rising
tSCH
tSSH
tDS
tSR
tSF
tBFT
DAC SERIAL PORT
tDBH
tDBL
tDLS
tDLH
tDLS
tDDS
tDDH
tDS
tSCH
Min
30
400
kHz
μs
μs
μs
0.6
μs
0.6
100
1.3
μs
ns
ns
ns
μs
10
10
10
5
−8
10
5
ns
ns
ns
ns
ns
ns
ns
300
300
tSF
tSCS
Figure 2. I2C Timing Diagram
Rev. 0 | Page 8 of 52
tBFT
09434-002
tSCLH
tSCLL
Unit
ns
ns
ns
ns
1.3
0.6
0.6
tSCH
SCL
Max
30
30
30
SDA
tSR
Typ
+8
ADAU1966
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 10.
Parameter
Analog (AVDD)
I/O (IOVDD)
Digital (DVDD)
PLL (PLLVDD)
VSUPPLY
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Case)
Storage Temperature Range
Rating
−0.3 V to +5.5 V
−0.3 V to +5.5 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +6.0 V
±20 mA
–0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
θJA represents junction-to-ambient thermal resistance; θJC represents the junction-to-case thermal resistance. All characteristics
are for a 4-layer board with a solid ground plane.
Table 11. Thermal Resistance
Package Type
80-Lead LQFP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 9 of 52
θJA
42.3
θJC
10.0
Unit
°C/W
ADAU1966
DAC9P
DAC8N
DAC8P
DAC7N
73
72
71
70
69
68
67
66
65
64
63
62
61
60
DAC_BIAS2
59
DAC_BIAS1
AVDD3 3
58
AVDD2
DAC13P 4
57
DAC4N
DAC13N 5
56
DAC4P
DAC14P 6
55
DAC3N
DAC14N 7
54
DAC3P
DAC15P 8
53
DAC2N
52
DAC2P
51
DAC1N
DAC16N 11
50
DAC1P
AVDD4 12
49
AVDD1
AGND4 13
48
AGND1
PLLGND 14
47
PU/RST
LF 15
46
SA_MODE
PLLVDD 16
45
CLATCH/ADDR0/SA*
MCLKI/XTALI 17
44
CCLK/SCL/SA*
XTALO 18
43
COUT/SDA/SA*
MCLKO 19
42
CDATA/ADDR1/SA*
DVDD 20
41
DVDD
PIN 1
INDICATOR
DAC_BIAS4 2
ADAU1966
DAC15N 9
DBCLK
33
34
35
36
37
38
39
40
DGND
DGND
32
IOVDD
VSUPPLY
31
DSDATA1
VDRIVE
30
DSDATA2
VSENSE
29
DSDATA3
DGND
IOVDD
*SEE TABLE 15 FOR SA_MODE SETTINGS.
28
DSDATA4
27
DSDATA5
26
DSDATA6
25
DSDATA7/SA*
24
DSDATA8/SA*
23
DGND
22
DLRCLK
21
DVDD
TOP VIEW
(Not to Scale)
DAC16P 10
Figure 3. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20, 29, 41
21, 26, 30, 40
Type 1
I
I
PWR
O
O
O
O
O
O
O
O
PWR
GND
GND
O
PWR
I
O
O
PWR
GND
Mnemonic
DAC_BIAS3
DAC_BIAS4
AVDD3
DAC13P
DAC13N
DAC14P
DAC14N
DAC15P
DAC15N
DAC16P
DAC16N
AVDD4
AGND4
PLLGND
LF
PLLVDD
MCLKI/XTALI
XTALO
MCLKO
DVDD
DGND
Description
DAC Bias 3. AC couple with 470 nF to AGND3.
DAC Bias 4. AC couple with 470 nF to AVDD3.
Analog Power.
DAC13 Positive Output.
DAC13 Negative Output.
DAC14 Positive Output.
DAC14 Negative Output.
DAC15 Positive Output.
DAC15 Negative Output.
DAC16 Positive Output.
DAC16 Negative Output.
Analog Power.
Analog Ground.
PLL Ground.
PLL Loop Filter, Reference to PLLVDD.
Apply 2.5 V to power PLL.
Master Clock Input, Input to Crystal Inverter.
Output from Crystal Inverter.
Master Clock Output.
Digital Power, 2.5 V.
Digital Ground.
Rev. 0 | Page 10 of 52
09434-003
DAC_BIAS3 1
AGND2
DAC9N
74
CM
DAC10P
75
TS_REF
DAC10N
76
DAC5P
DAC11P
77
DAC5N
DAC11N
78
DAC6P
DAC12P
79
DAC7P
DAC12N
80
DAC6N
AGND3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADAU1966
Pin No.
22, 39
23
Type 1
PWR
I
Mnemonic
IOVDD
VSENSE
24
25
O
I
VDRIVE
VSUPPLY
27
28
31
I/O
I/O
I
DBCLK
DLRCLK
DSDATA8/SA
32
I
DSDATA7/SA
33
34
35
36
37
38
42
I
I
I
I
I
I
I
DSDATA6
DSDATA5
DSDATA4
DSDATA3
DSDATA2
DSDATA1
CDATA/ADDR1/SA
43
I/O
COUT/SDA/SA
44
I
CCLK/SCL/SA
45
I
CLATCH/ADDR0/SA
46
I
SA_MODE
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
I
GND
PWR
O
O
O
O
O
O
O
O
PWR
I
I
GND
O
PU/RST
AGND1
AVDD1
DAC1P
DAC1N
DAC2P
DAC2N
DAC3P
DAC3N
DAC4P
DAC4N
AVDD2
DAC_BIAS1
DAC_BIAS2
AGND2
CM
63
O
TS_REF
64
65
66
67
68
69
70
O
O
O
O
O
O
O
DAC5P
DAC5N
DAC6P
DAC6N
DAC7P
DAC7N
DAC8P
Description
Power for Digital Input and Output Pins, 3.3 V to 5 V.
2.5 V Output of Regulator, Collector of Pass Transistor. Bypass with 10 μF in parallel
with 100 nF.
Drive for Base of Pass Transistor.
5 V Input to Voltage Regulator, Emitter of Pass Transistor. Bypass with 10 μF in parallel
with 100 nF.
Bit Clock for DACs.
Frame Clock for DACs.
DAC15 and DAC 16 Serial Data Input/SA_MODE TDM State (see the Standalone Mode
section, Table 15, and Table 16).
DAC13 and DAC 14 Serial Data Input/SA_MODE TDM State (see the Standalone Mode
section, Table 15, and Table 16).
DAC11 and DAC 12 Serial Data Input.
DAC9 and DAC 10 Serial Data Input.
DAC7 and DAC 8 Serial Data Input.
DAC5 and DAC 6 Serial Data Input.
DAC3 and DAC 4 Serial Data Input.
DAC1 and DAC 2 Serial Data Input.
Control Data Input (SPI)/Address 1 (I2C)/SA_MODE State (see the Standalone Mode
section and Table 15).
Control Data Output (SPI)/Control Data Input (I2C)/SA_MODE State (see the
Standalone Mode section and Table 15).
Control Clock Input (SPI)/Control Clock Input (I2C)/SA_MODE State (see the Standalone
Mode section and Table 15).
Control Chip Select (SPI) (Low Active)/Address 0 (I2C)/SA_MODE State (see the
Standalone Mode section and Table 15).
Standalone Mode. This pin allows mode control of ADAU1966 using Pin 42 to Pin 45,
Pin 31, and Pin 32 (high active, see Table 15 and Table 16).
Power-Up/Reset (Low Active).
Analog Ground.
Analog Power.
DAC1 Positive Output.
DAC1 Negative Output.
DAC2 Positive Output.
DAC2 Negative Output.
DAC3 Positive Output.
DAC3 Negative Output.
DAC4 Positive Output.
DAC4 Negative Output.
Analog Power.
DAC Bias 1. AC couple with 470 nF to AVDD2.
DAC Bias 2. AC couple with 470 nF to AGND2.
Analog Ground.
Common-Mode Reference Filter Capacitor Connection. Bypass with 10 μF in parallel
with 100 nF to AGND2. This reference can be shut off in the PLL_CLK_CTRL1 register
and the pin can be driven with an outside voltage source.
Voltage Reference Filter Capacitor Connection. Bypass with 10 μF in parallel with
100 nF to AGND2.
DAC5 Positive Output.
DAC5 Negative Output.
DAC6 Positive Output.
DAC6 Negative Output.
DAC7 Positive Output.
DAC7 Negative Output.
DAC8 Positive Output.
Rev. 0 | Page 11 of 52
ADAU1966
Pin No.
71
72
73
74
75
76
77
78
79
80
1
Type 1
O
O
O
O
O
O
O
O
O
GND
Mnemonic
DAC8N
DAC9P
DAC9N
DAC10P
DAC10N
DAC11P
DAC11N
DAC12P
DAC12N
AGND3
Description
DAC8 Negative Output.
DAC9 Positive Output.
DAC9 Negative Output.
DAC10 Positive Output.
DAC10 Negative Output.
DAC11 Positive Output.
DAC11 Negative Output.
DAC12 Positive Output.
DAC12 Negative Output.
Analog Ground.
I = input, O = output, I/O = input/output, PWR = power, GND = ground.
Rev. 0 | Page 12 of 52
ADAU1966
TYPICAL PERFORMANCE CHARACTERISTICS
0.05
0.20
0.04
0.15
0.03
0.10
MAGNITUDE (dB)
MAGNITUDE (dB)
0.02
0.01
0
–0.01
0.05
0
–0.05
–0.02
–0.10
–0.03
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
FREQUENCY (FACTORED TO fS)
–0.20
0
0.15
0.20
0.25
0.30
0.35
0.40
1.0
Figure 6. DAC Pass-Band Filter Response, 96 kHz
0
0
–10
–10
–20
–20
–30
MAGNITUDE (dB)
–30
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–90
–90
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FREQUENCY (FACTORED TO fS)
0.9
1.0
09434-005
MAGNITUDE (dB)
0.10
FREQUENCY (FACTORED TO fS)
Figure 4. DAC Pass-Band Filter Response, 48 kHz
–100
0.05
09434-006
0
09434-004
–0.05
09434-007
–0.15
–0.04
–100
Figure 5. DAC Stop-Band Filter Response, 48 kHz
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FREQUENCY (FACTORED TO fS)
Figure 7. DAC Stop-Band Filter Response, 96 kHz
Rev. 0 | Page 13 of 52
0.9
ADAU1966
APPLICATION CIRCUITS
Typical application circuits are shown in Figure 8 to Figure 11. Recommended loop filters for DLRCLK and MCLKI/XTALI modes of the
PLL reference are shown in Figure 8. Output filters for the DAC outputs are shown in Figure 9 and Figure 10, and an external regulator
circuit is shown in Figure 11.
LF
DLRCLK
MCLKI/XTALI
LF
39nF
5.6nF
2.2nF
390pF
562Ω
PLLVDD
09434-008
3.32kΩ
PLLVDD
Figure 8. Recommended Loop Filters for DLRCLK or MCLKI/XTALI PLL Reference Modes
DACP
10µF
+
237Ω
OUTP
2.7nF
DACN
10µF
+
237Ω
OUTN
49.9kΩ
09434-009
49.9kΩ
Figure 9. Typical DAC Output Passive Filter Circuit (Differential)
1.1nF
AD8672ARZ
DAC1P
1.50kΩ
1.54kΩ
5
100Ω
7
4.7µF
+
OUTPUT1P
6
+12V DC
422Ω
2.49kΩ
100kΩ
8
0.1µF
4.7µF
0.1µF
4.7µF
+
1nF
4.7µF
1nF
4.7µF
+
V+
V–
4
+
+
100kΩ
–12V DC
1.54kΩ
422Ω
100Ω
1
3
4.7µF
+
OUTPUT1N
09434-010
AD8672ARZ
1.1nF
Figure 10. Typical DAC Output Active Filter Circuit (Differential)
100nF
+
10µF
VSUPPLY
5V
1kΩ
B
VDRIVE
E
FZT953
C
VSENSE
2.5V
100nF
+
10µF
09434-011
DAC1N
2
1.50kΩ
2.49kΩ
Figure 11. Recommended 2.5 V Regulator Circuit
Rev. 0 | Page 14 of 52
ADAU1966
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTERS (DACS)
The 16 ADAU1966 digital-to-analog converter (DAC) channels
are differential for improved noise and distortion performance
and are voltage output for simplified connection. The DACs
include on-chip digital interpolation filters with 68 dB stop-band
attenuation and linear phase response, operating at an oversampling ratio of 256× (48 kHz range), 128× (96 kHz range), or
64× (192 kHz range). Each channel has its own independently
programmable attenuator, adjustable in 255 steps in increments
of 0.375 dB. Digital inputs are supplied through eight serial data
input pins (two channels on each pin), a common frame clock
(DLRCLK), and a bit clock (DBCLK). Alternatively, any one of the
TDM modes can be used to access up to 16 channels on a single
TDM data line.
The ADAU1966 has a low propagation delay mode; this mode
is an option for an fS of 192 kHz and is enabled in Register DAC_
CTRL0[2:1]. By setting these bits to b11, the propagation delay
is reduced by the amount shown in Table 8. The shorter delay is
achieved by reducing the amount of digital filtering; the negative impact of selecting this mode is reduced audio frequency
response and increased out-of-band energy.
When AVDD is supplied with 5 V, each analog output pin has a
nominal common-mode (CM) dc level of 2.25 V and swings
±8.49 V p-p (3 V rms differential) from a 0 dBFS digital input
signal. An AVDD of 3.3 V generates a CM dc voltage of 1.5 V
and allows differential audio swings of ±5.66 V p-p (2 V rms)
from a 0 dBFS digital input signal. The differential analog
outputs require only a single-order passive differential RC filter
to provide the specified DNR performance; see Figure 9 for an
example filter. The outputs can easily drive differential inputs
on a separate PCB through cabling as well as differential inputs
on the same PCB.
If more signal level is required or if a more robust filter is needed, a
single op amp gain stage designed as a second-order, low-pass
Bessel filter can be used to remove the high frequency out-ofband noise present on each pin of the differential outputs. The
choice of components and design of this circuit is critical to
yield the full DNR of the DACs (see the recommended passive
and active circuits in Figure 9 and Figure 10). This filter can be
built into an active difference amplifier to provide a single-ended
output with gain, if necessary. Note that the use of op amps with
low slew rate or low bandwidth can cause high frequency noise
and tones to fold down into the audio band; exercise care when
selecting these components.
The ADAU1966 offers control over the analog performance
of the DACs; it is possible to program the registers to reduce
the power consumption with the trade-off of lower SNR and
THD + N. The reduced power consumption is the result of
changing the internal bias current to the analog output
amplifiers.
Register DAC_POWER1 to Register DAC_POWER4 present
four basic settings for the DAC power vs. performance in each
of the 16 channels: best performance, good performance, low
power, and lowest power. Alternatively, in Register PLL_CLK_
CTRL1[7:6], the LOPWR_MODE bits offer global control over
the power and performance for all 16 channels. The default
setting is b00. This setting allows the channels to be controlled
individually using the DAC_POWERx registers. Setting b10
and Setting b11 select the low power and lowest power settings.
The data presented in Table 13 shows the result of setting all
16 channels to each of the four settings. The SNR and THD + N
specifications are shown in relation to the measured performance of a device at the best performance setting.
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
CLOCK SIGNALS
Upon powering the ADAU1966 and asserting the PU/RST pin
high, the part starts in either standalone mode (SA_MODE) or
program mode, depending on the state of SA_MODE (Pin 46).
The clock functionality of SA_MODE is described in the
Standalone Mode section. In program mode, the default for the
ADAU1966 is for the MCLKO pin to feed a buffered output of
the MCLKI signal. The default for the DLRCLK and DBCLK
ports is slave mode; the DAC must be driven with a coherent set
of MCLK, LRCLK, and BCLK signals to function.
The MCLKO pin can be programmed to provide different clock
signals using Register Bits PLL_CLK_CTRL1[5:4]. The default,
b10, provides a buffered copy of the clock signal that is driving
the MCLKI pin. Two modes, b00 and b01, provide low jitter
clock signals. The b00 setting yields a clock rate between 4 MHz
and 6 MHz, and b01 yields a clock rate between 8 MHz and
12 MHz. Both of these clock frequencies are scaled as ratios of
MCLK automatically inside the ADAU1966. As an example, an
MCLK of 8.192 MHz and a setting of b00 yield an MCLKO of
(8.192/2) = 4.096 MHz. Alternatively, an MCLK of 36.864 MHz
and a setting of b01 yield an MCLKO frequency of (36.864/3) =
12.288 MHz. The setting b11 shuts off the MCLKO pin.
Table 13. DAC Power vs. Performance
Register Setting
Total AVDD Current
SNR
THD + N (−1 dbFS signal)
Best Performance
82 mA
Reference
Reference
Good Performance
73 mA
−0.2 dB
−1.8 dB
Rev. 0 | Page 15 of 52
Low Power
64 mA
−1.5 dB
−3.0 dB
Lowest Power
54 mA
−14.2 dB
−5.8 dB
ADAU1966
After the PU/RST pin has been asserted high, the PLL_CLK_
CTRLx registers (0x00 and 0x01) can be programmed. The
on-chip phase-locked loop (PLL) can be selected to use the
clock appearing at the MCLKI/XTALI pin at a frequency of
256, 384, 512, or 768 times the sample rate (fS), referenced to
the 48 kHz mode from the master clock select (MCS) setting,
as described in Table 14. In 96 kHz mode, the master clock frequency stays at the same absolute frequency; therefore, the
actual multiplication rate is divided by 2. In 192 kHz mode,
the actual multiplication rate is divided by 4. For example, if
the ADAU1966 is programmed in 256 × fS mode, the frequency
of the master clock input is 256 × 48 kHz = 12.288 MHz. If the
ADAU1966 is then switched to 96 kHz operation (by writing to
DAC_CTRL0 [2:1]), the frequency of the master clock should
remain at 12.288 MHz, which is 128 × fS in this example. In
192 kHz mode, MCS becomes 64 × fS.
The internal clock for the digital core varies by mode: 512 × fS
(48 kHz mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz
mode). By default, the on-board PLL generates this internal
master clock from an external clock.
The PLL should be powered and stable before the ADAU1966 is
used as a source for quality audio. The PLL is enabled by reset
and does not require writing to the I2C or SPI port for normal
operation.
With the PLL enabled, the performance of the ADAU1966 is
not affected by jitter as high as a 300 ps rms time interval error
(TIE). If the internal PLL is not used, it is best to use an independent crystal oscillator to generate the master clock.
If the ADAU1966 is to be used in direct MCLK mode, the PLL
can be powered down in the PDN_THRMSENS_CTRL_1 register. For direct MCLK mode, a 512 × fS (referenced to 48 kHz
mode) master clock must be used as MCLK, and the CLK_SEL
bit in the PLL_CLK_CTRL1 register must be set to b1.
The ADAU1966 PLL can also be programmed to run from an
external LRCLK. When the PLLIN bits in the PLL_CLK_CTRL0
register are set to 01 and the appropriate loop filter is connected
to the LF pin (see Figure 8), the ADAU1966 PLL generates all
of the necessary internal clocks for operation with no external
MCLK. This mode reduces the number of high frequency
signals in the design, reducing EMI emissions.
It is possible to further reduce EMI emissions of the circuit by
using the internal DBCLK generation setting of the BCLK_GEN
bit in the DAC_CTRL1 register. With the BCLK_GEN bit set to
b1 (internal) and the SAI_MS bit set to b0 (slave), the ADAU1966
generate its own DBCLK; this works with the PLL input set to
either MCLKI/XTALI or DLRCLK. DLRCLK is the only required
clock in DLRCLK PLL mode.
POWER-UP AND RST
Power sequencing for the ADAU1966 should start with AVDD
and IOVDD, followed by DVDD. It is very important that
AVDD be settled at a regulated voltage and that IOVDD be
within 10% of regulated voltage before applying DVDD. When
using the ADAU1966 internal regulator, this timing occurs by
default.
To guarantee proper startup, the PU/RST pin should be pulled
low by an external resistor and then driven high after the power
supplies have stabilized. The PU/RST can also be pulled high
using a simple RC network.
Driving the PU/RST pin low puts the part into a very low power
state (<3 μA). All functionality of the ADAU1966 is disabled
until the PU/RST pin is asserted high. Once this pin is asserted
high, the ADAU1966 requires 300 ms to stabilize. The MMUTE
bit in the DAC_CTRL0 register must be toggled for operation.
The PUP bit in the PLL_CLK_CTRL0 register can be used to
power down the ADAU1966. Engaging the master power-down
puts the ADAU1966 in an idle state while maintaining the settings of all registers. Additionally, the power-down bits in the
PDN_THRMSENS_CTRL1 register (TS_PDN, PLL_PDN, and
VREG_PDN) can be used to power down individual sections of
the ADAU1966.
The SOFT_RST bit in the PLL_CLK_CTRL0 register sets all of
the control registers to their default settings while maintaining
the internal clocks in default mode. The SOFT_RST bit does
not power down the analog outputs; toggling this bit does not
cause audible popping sounds at the differential analog outputs.
Proper startup of the ADAU1966 should proceed as follows:
1.
2.
3.
4.
5.
Rev. 0 | Page 16 of 52
Apply power to the ADAU1966 as described previously.
Assert the PU/RST pin high after power supplies have
stabilized.
Set the PUP bit to b1.
Program all necessary registers for the desired settings.
Set the MMUTE bit to b0 to unmute all channels.
ADAU1966
Table 14. MCS and fS Modes
Master Clock Select (MCS), PLL_CLK_CTRL0[2:1]
Setting 0, b00
Setting 1, b01
Setting 2, b10
Ratio
MCLK (MHz) Ratio
MCLK
Ratio
MCLK
256 × fS
8.192
384 × fS
12.288
512 × fS
16.384
256 × fS
11.2896
384 × fS
16.9344
512 × fS
22.5792
256 × fS
12.288
384 × fS
18.432
512 × fS
24.576
128 × fS
8.192
192 × fS
12.288
256 × fS
16.384
128 × fS
11.2896
192 × fS
16.9344
256 × fS
22.5792
128 × fS
12.288
192 × fS
18.432
256 × fS
24.576
64 × fS
8.192
96 × fS
12.288
128 × fS
16.384
64 × fS
11.2896
96 × fS
16.9344
128 × fS
22.5792
64 × fS
12.288
96 × fS
18.432
128 × fS
24.576
Sample Rate Select (FS)
DAC_CTRL0[2:1]
32 kHz, b00
44.1 kHz, b00
48 kHz, b00
64 kHz, b01
88.2 kHz, b01
96 kHz, b01
128 kHz, b10 or b11
176.4 kHz, b10 or b11
192 kHz, b10 or b11
STANDALONE MODE
2
The ADAU1966 can operate without a typical I C or SPI
connection to a microcontroller. This standalone mode is
made available by setting the SA_MODE (Pin 46) to high
(IOVDD). All registers are set to default except the options
shown in Table 15.
Table 15. SA_MODE Settings
Pin No.
42
43
44
45
Setting
0
1
0
1
0
1
0
1
Function
Master mode serial audio interface (SAI)
Slave mode SAI
MCLK = 256 × fS, PLL on
MCLK = 384 × fS, PLL on
AVDD = 5.0 V (CM = 2.25 V)
AVDD = 3.3 V (CM = 1.50 V)
I2S SAI format
TDM modes, determined by Pin 31 and Pin 32
When both SA_MODE and Pin 45 are set high, TDM mode is
selected. Table 16 shows the available TDM modes; these modes
are set by connecting Pin 31 (DSDATA8) and Pin 32 (DSDATA7)
to GND or IOVDD.
Table 16. TDM Modes
Pin No.
32:31
Setting
00
01
10
11
Function
TDM4—DLRCLK pulse
TDM8—DLRCLK pulse
TDM16—DLRCLK pulse
TDM8—DLRCLK 50% duty cycle
When the ADAU1966 is powered up in SA_MODE and the
PU/RST pin is asserted high, the MCLKO pin provides a buffered version of the MCLKI pin, whether the source is a crystal
or an active oscillator.
2
I C CONTROL PORT
2
The ADAU1966 has an I C-compatible control port that permits programming and reading back of the internal control
registers for the DACs and clock system. The I2C interface of the
ADAU1966 is a 2-wire interface consisting of a clock line, SCL,
Setting 3, b11
Ratio
MCLK
768 × fS
24.576
768 × fS
33.8688
768 × fS
36.864
384 × fS
24.576
384 × fS
33.8688
384 × fS
36.864
192 × fS
24.576
192 × fS
33.8688
192 × fS
36.864
and a data line, SDA. SDA is bidirectional, and the ADAU1966
drives SDA either to acknowledge the master (ACK) or to send
data during a read operation. The SDA pin for the I2C port is an
open-drain collector and requires a 2 kΩ pull-up resistor. A write
or read access occurs when the SDA line is pulled low while the
SCL line is high, indicated by a start in Figure 12 and Figure 13.
SDA is only allowed to change when SCL is low except when a
start or stop condition occurs, as shown in Figure 12 and Figure 13.
The first eight bits of the data-word consist of the device address
and the R/W bit. The device address consists of an internal built-in
address (0x04) and two address pins, ADDR1 and ADDR0. The
two address bits allow four ADAU1966 devices to be used in a
system. Initiating a write operation to the ADAU1966 involves
sending a start condition and then sending the device address
with the R/W bit set low. The ADAU1966 responds by issuing
an acknowledge to indicate that it has been addressed. The user
then sends a second frame telling the ADAU1966 which register
is required to be written. Another acknowledge is issued by the
ADAU1966. Finally, the user can send another frame with the
eight data bits required to be written to the register. A third
acknowledge is issued by the ADAU1966 after which the user
can send a stop condition to complete the data transfer.
A read operation requires that the user first write to the
ADAU1966 to point to the correct register and then read the
data. This is achieved by sending a start condition followed by
the device address frame, with the R/W bit low, and then the
register address frame. Following the acknowledge from the
ADAU1966, the user must issue a repeated start condition. The
next frame is the device address with the R/W bit set high. On
the next frame, the ADAU1966 outputs the register data on the
SDA line. A stop condition completes the read operation.
Table 17. I2C Addresses
ADDR1
0
0
1
1
Rev. 0 | Page 17 of 52
ADDR0
0
1
0
1
Slave Address
0x04
0x24
0x44
0x64
ADAU1966
SCL
SDA
AD1
AD0
0
0
1
0
0
START BY
MASTER (S)
R/W
0
0
0
0
0
1
1
0
ACK. BY
ADAU1966 (AS)
ACK. BY
ADAU1966 (AS)
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY STOP BY
ADAU1966 (AS) MASTER (P)
FRAME 3
DATA BYTE TO ADAU1966
09434-012
SDA
(CONTINUED)
Figure 12. I2C Write Format
SCL
SDA
AD1
AD0
0
0
1
0
0
R/W
START BY
MASTER (S)
0
0
0
0
0
1
1
0
ACK. BY
ADAU1966 (AS)
ACK. BY
ADAU1966 (AS)
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
SCL
(CONTINUED)
0
0
0
REPEATED START
BY MASTER (S)
0
1
AD1
AD0
D7
R/W
D6
D5
ACK. BY
ADAU1966 (AS)
FRAME 3
CHIP ADDRESS BYTE
D4
D3
D2
D1
D0
ACK. BY STOP BY
MASTER (AM) MASTER (P)
FRAME 4
REGISTER DATA
09434-013
SDA
(CONTINUED)
Figure 13. I2C Read Format
Table 18. I2C Abbreviations
Abbreviation
S
P
AM
AS
Condition
Start bit
Stop bit
Acknowledge by master
Acknowledge by slave
Table 19. Single Word I2C Write
S
AS
Chip Address, R = 0
Register Address
AS
Data-Word
AS
P
Table 20. Burst Mode I2C Write
S
Chip Address, R = 0
AS
Register Address
AS
Data-Word 1
AS
Data-Word 2
AS
Data-Word N
AS
P
Table 21. Single Word I2C Read
S
AS
Chip Address, R = 0
Register Address
AS
S
AS
Chip Address, R = 1
Data-Word
AM
P
Table 22. Burst Mode I2C Read
S
Chip Address, R
=0
AS
Register
Address
AS
S
Chip Address, R
=1
AS
Rev. 0 | Page 18 of 52
DataWord 1
AM
DataWord 2
AM
DataWord N
AM
P
ADAU1966
SERIAL CONTROL PORT: SPI CONTROL MODE
The ADAU1966 has an SPI control port that permits programming and reading back of the internal control registers for the
DACs and clock system. A standalone mode is also available for
operation without serial control; it is configured at reset using the
SA_MODE pin. See the Standalone Mode section for details
about SA_MODE.
By default, the ADAU1966 is in I2C mode, but it can be put into
SPI control mode by pulling CLATCH low three times. This
is done by performing three dummy writes to the SPI port (the
ADAU1966 does not acknowledge these three writes). Beginning with the fourth SPI write, data can be written to or read
from the IC. The ADAU1966 can be taken out of SPI control
mode only by a full reset initiated by power cycling the IC.
The SPI control port of the ADAU1966 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
DACs. Figure 14 shows the format of the SPI signal. The first
byte is a global address with a read/write bit. For the ADAU1966,
the address is 0x06, shifted left one bit due to the R/W bit. The
second byte is the ADAU1966 register address, and the third
byte is the data.
POWER SUPPLY AND VOLTAGE REFERENCE
The ADAU1966 is designed for 3.3 V or 5 V analog and 2.5 V
digital supplies. To minimize noise pickup, the power supply
pins should be bypassed with 100 nF ceramic chip capacitors
placed as close to the pins as possible. A bulk aluminum
electrolytic capacitor of at least 22 μF should also be provided
for each rail on the same PC board as the codec. It is important
that the analog supply be as clean as possible.
The ADAU1966 includes a 2.5 V regulator driver that requires
only an external pass transistor and bypass capacitors to make a
2.5 V regulator from a 5 V or 3.3 V supply. The VSUPPLY and
VSENSE pins should be decoupled with no more than 10 μF, in
parallel with 100 nF high frequency bypassing. If the regulator
driver is not used, connect VSUPPLY and VDRIVE to GND
and leave VSENSE unconnected.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V or 5 V IOVDD supply and
are compatible with TTL and 3.3 V CMOS levels.
The temperature sensor internal voltage reference (VTS_REF)
is brought out on the TS_REF pin and should be bypassed as
close as possible to the chip with a parallel combination of
10 μF and 100 nF.
The internal band gap reference can be disabled in the
PLL_CLK_CTRL1 register by setting VREF_EN to 0; the CM
pin can be then be driven from an external source. This can be
used to scale the DAC output to the clipping level of a power
amplifier based on its power supply voltage.
The CM pin is the internal common-mode reference. It should
be bypassed as close as possible to the chip, with a parallel
combination of 10 μF and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the
analog input and output signal pins. The output current should
be limited to less than 0.5 mA source and 2 mA sink.
SERIAL DATA PORTS—DATA FORMAT
The 16 DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The clock signals are all synchronous with the sample
rate. The normal stereo serial modes are shown in Figure 15.
The DAC serial data mode defaults to I2S (1 BCLK delay) upon
power-up and reset. The ports can also be programmed for leftjustified and right-justified (24-bit and 16-bit) operation using
DAC_CTRL0[7:6]. Stereo and TDM modes can be selected using
DAC_CTRL0[5:3]. The polarity of DBCLK and DLRCLK is
programmable according to the DAC_CTRL1[1] and DAC_
CTRL1[5] bits. The serial ports are programmable as the clock
masters according to the DAC_CTRL1[0] bit. By default, the
serial port is in slave mode.
TIME-DIVISION MULTIPLEXED (TDM) MODES
The ADAU1966 serial ports also have several different TDM
serial data modes. The ADAU1966 can support a single data
line TDM16, a dual data line (TDM8), a quad data line
(TDM4), or eight data lines (TDM2). The DLRCLK can be
operated in both single-cycle pulse mode and a 50% duty
cycle mode. Both 16 DBCLKs or 32 DBCLKs per channel are
selectable for each mode.
The I/O pins of the serial ports are defined according to the
serial mode that is selected. For a detailed description of the
function of each pin in TDM and stereo modes, see Table 23.
Rev. 0 | Page 19 of 52
ADAU1966
conversion, placing the resulting temperature data in the
THRM_TEMP_STAT register. In continuous operation
mode, the data conversion takes place at a rate set by Bits[7:6],
THRM_RATE, with a range of 0.5 sec to 4 sec between samples.
Faster rates are possible using the one-shot mode.
TEMPERATURE SENSOR
The ADAU1966 has an on-board temperature sensor that allows
the user to read the temperature of the silicon inside the part.
The temperature sensor readout has a range of −60°C to +140°C
in 1°C steps. The PDN_THRMSENS_CTRL_1 register controls
the settings of the sensor. The temperature sensor is powered on
by default and can be shut off by setting the TS_PDN[2] bit to
b1 in PDN_THRMSENS_CTRL_1. The temperature sensor can
be run in either continuous operation or one-shot mode. The
temperature sensor conversion mode is modified using Bit 5,
THRM_MODE; the default is THRM_MODE = 1, one-shot
mode. In one-shot mode, writing a 0 followed by writing a 1 to
Bit 4, THRM_GO, results in a single reset and temperature
Once a temperature conversion has been placed in the
THRM_TEMP_STAT register, the data can be translated into
degrees Celsius (°C) using the following steps:
1.
2.
Convert the binary or hexadecimal data read from
THRM_TEMP_STAT into decimal form.
Subtract 60 from the converted THRM_TEMP_STAT
data; this is the temperature of the silicon in °C.
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
LSB
MSB
LSB
MSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 0, SDATA_FMT = 1
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
MSB
LSB
MSB
I2S-JUSTIFIED
MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 0, SDATA_FMT = 0
LEFT CHANNEL
LRCLK
LSB
RIGHT CHANNEL
BCLK
SDATA
MSB
MSB
LSB
LSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL: SAI = 0, SDATA_FMT = 2 OR 3
LRCLK
BCLK
MSB
MSB
LSB
TDM MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 1, 2, 3, OR 4
1/fS
Figure 15. Serial Audio Modes
Rev. 0 | Page 20 of 52
LSB
09434-015
SDATA
ADAU1966
tDBH
DBCLK
tDBL
tDLH
tDLS
DLRCLK
DSDATAx
LEFT-JUSTIFIED
MODE
tDDS
MSB
MSB – 1
tDDH
tDDS
DSDATAx
I2S-JUSTIFIED
MODE
MSB
tDDH
tDDS
MSB
LSB
tDDH
tDDH
09434-016
tDDS
DSDATAx
RIGHT-JUSTIFIED
MODE
Figure 16. DAC Serial Timing
Table 23. Pin Function Changes in Different Serial Audio Interface Modes
DLRCLK
Stereo Modes
(SAI = 0 or 1)
Channel 1/Channel 2
data in
Channel 3/Channel 4
data in
Channel 5/Channel 6
data in
Channel 7/Channel 8
data in
Channel 9/Channel 10
data in
Channel 11/Channel 12
data in
Channel 13/Channel 14
data in
Channel 15/Channel 16
data in
DLRCLK in/DLRCLK out
DBCLK
DBCLK in/DBCLK out
Maximum Sample Rate
192 kHz
Signal
DSDATA1
DSDATA2
DSDATA3
DSDATA4
DSDATA5
DSDATA6
DSDATA7
DSDATA8
TDM4 Mode
(SAI = 2)
Channel 1 to Channel 4
data in
Channel 5 to Channel 8
data in
Channel 9 to Channel 12
data in
Channel 13 to Channel 16
data in
Not used
TDM8 Mode
(SAI = 3)
Channel 1 to Channel 8
data in
Channel 9 to Channel 16
data in
Not used
TDM16 Mode
(SAI = 4)
Channel 1 to Channel 16
data in
Not used
Not used
Not used
Not used
Not used
Not used
Not Used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
TDM frame sync in/
TDM frame sync out
TDM DBCLK in/TDM
DBCLK out
192 kHz
TDM frame sync in/
TDM frame sync out
TDM DBCLK in/TDM
DBCLK out
96 kHz
TDM frame sync in/
TDM frame sync out
TDM DBCLK in/
TDM DBCLK out
48 kHz
Rev. 0 | Page 21 of 52
Not used
ADAU1966
ADDITIONAL MODES
The ADAU1966 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit DBCLK. See
Figure 17 for an example of a DAC TDM data transmission mode
that does not require a high speed DBCLK or an external
MCLK. This configuration is applicable when the ADAU1966
master clock is generated by the PLL with the DLRCLK as the
PLL reference frequency.
To relax the requirement for the setup time of the ADAU1966
in cases of high speed TDM data transmission, the ADAU1966
can latch in the data using the falling edge of DBCLK; see the
BCLK_EDGE bit in the DAC_CTRL1 register. This effectively
dedicates the entire BCLK period to the setup time. This mode
is useful in cases where the source has a large delay time in the
serial data driver. Figure 18 shows this inverted DBCLK mode
of data transmission.
DLRCLK
32 BITS
INTERNAL
DBCLK
DSDATAx
DLRCLK
09434-017
INTERNAL
DBCLK
TDM-DSDATAx
Figure 17. Serial DAC Data Transmission in TDM Format Without DBCLK
(Applicable Only If PLL Locks to DLRCLK)
DLRCLK
DATA MUST BE VALID
AT THIS BCLK EDGE
DSDATAx
MSB
Figure 18. Inverted DBCLK Mode in DAC Serial Data Transmission
(Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission)
Rev. 0 | Page 22 of 52
09434-018
DBCLK
ADAU1966
REGISTER SUMMARY
Table 24. ADAU1966 Register Summary
Reg
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
Name
PLL_CLK_CTRL0
PLL_CLK_CTRL1
PDN_THRMSENS_CTRL_1
PDN_CTRL2
PDN_CTRL3
THRM_TEMP_STAT
DAC_CTRL0
DAC_CTRL1
DAC_CTRL2
DAC_MUTE1
DAC_MUTE2
DACMSTR_VOL
DAC01_VOL
DAC02_VOL
DAC03_VOL
DAC04_VOL
DAC05_VOL
DAC06_VOL
DAC07_VOL
DAC08_VOL
DAC09_VOL
DAC10_VOL
DAC11_VOL
DAC12_VOL
DAC13_VOL
DAC14_VOL
DAC15_VOL
DAC16_VOL
CM_SEL_PAD_STRGTH
DAC_POWER1
DAC_POWER2
DAC_POWER3
DAC_POWER4
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit 7
Bit 6
PLLIN
LOPWR_MODE
THRM_RATE
DAC08_PDN DAC07_PDN
DAC16_PDN DAC15_PDN
Bit 5
Bit 4
XTAL_SET
MCLKO_SEL
THRM_MODE THRM_GO
DAC06_PDN DAC05_PDN
DAC14_PDN DAC13_PDN
Bit 3
SOFT_RST
PLL_MUTE
RESERVED
DAC04_PDN
DAC12_PDN
TEMP
Reset
0x00
0x2A
0xA0
0x00
0x00
0x00
SDATA_FMT
SAI
FS
MMUTE
0x01
BCLK_GEN
LRCLK_MODE LRCLK_POL
SAI_MSB
RESERVED
BCLK_RATE
BCLK_EDGE
SAI_MS
0x00
RESERVED
VREG_CTRL
BCLK_TDMC DAC_POL
AUTO_MUTE_EN DAC_OSR
DE_EMP_EN 0x06
DAC08_MUTE DAC07_MUTE DAC06_MUTE DAC05_MUTE DAC04_MUTE DAC03_MUTE
DAC02_MUTE DAC01_MUTE 0x00
DAC16_MUTE DAC15_MUTE DAC14_MUTE DAC13_MUTE DAC12_MUTE DAC11_MUTE
DAC10_MUTE DAC09_MUTE 0x00
DACMSTR_VOL
0x00
DAC01_VOL
0x00
DAC02_VOL
0x00
DAC03_VOL
0x00
DAC04_VOL
0x00
DAC05_VOL
0x00
DAC06_VOL
0x00
DAC07_VOL
0x00
DAC08_VOL
0x00
DAC09_VOL
0x00
DAC10_VOL
0x00
DAC11_VOL
0x00
DAC12_VOL
0x00
DAC13_VOL
0x00
DAC14_VOL
0x00
DAC15_VOL
0x00
DAC16_VOL
0x00
RESERVED
RESERVED
PAD_DRV
RESERVED
RESERVED
RESERVED
CM_SEL
RESERVED
0x02
DAC04_POWER
DAC03_POWER
DAC02_POWER
DAC01_POWER
0xAA
DAC08_POWER
DAC07_POWER
DAC06_POWER
DAC05_POWER
0xAA
DAC12_POWER
DAC11_POWER
DAC10_POWER
DAC09_POWER
0xAA
DAC16_POWER
DAC15_POWER
DAC14_POWER
DAC13_POWER
0xAA
Rev. 0 | Page 23 of 52
Bit 2
Bit 1
MCS
PLL_LOCK
VREF_EN
TS_PDN
PLL_PDN
DAC03_PDN
DAC02_PDN
DAC11_PDN
DAC10_PDN
Bit 0
PUP
CLK_SEL
VREG_PDN
DAC01_PDN
DAC09_PDN
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
ADAU1966
REGISTER DETAILS
PLL AND CLOCK CONTROL 0 REGISTER
Address: 0x00, Reset: 0x00, Name: PLL_CLK_CTRL0
Table 25. Bit Descriptions for PLL_CLK_CTRL0
Bits
[7:6]
Bit Name
PLLIN
Settings
00
01
10
11
[5:4]
XTAL_SET
00
01
10
11
3
SOFT_RST
0
1
[2:1]
MCS
00
01
10
11
0
PUP
0
1
Description
PLL Input Select. Selects between MCLKI/XTALI or DLRCLK as the input to
the PLL.
MCLKI or XTALI
DLRCLK
Reserved
Reserved
XTAL Oscillator Setting. XTALO pin status.
XTAL Oscillator Enabled
Reserved
Reserved
XTALO Off
Software Reset Control. This bit resets all circuitry inside the IC, except
I2C/SPI communications. All control registers are reset to default values,
except 0x00 and 0x01. The PLL_CLK_CTRLx registers do not change state.
Normal Operation
Device in Reset
Master Clock Select. MCLKI/XTALI pin functionality (PLL active), master
clock rate setting. The following values are for the fS rate window from 32
kHz to 48 kHz. See Table 14 for details when using other fS selections.
256 × fS MCLK (44.1 kHz or 48 kHz)
384 × fS MCLK (44.1 kHz or 48 kHz)
512 × fS MCLK (44.1 kHz or 48 kHz)
768 × fS MCLK (44.1 kHz or 48 kHz)
Master Power-Up Control. This bit must be set to 1 as the first register
write to power up the IC.
Master Power-Down
Master Power-Up
Rev. 0 | Page 24 of 52
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
ADAU1966
PLL AND CLOCK CONTROL 1 REGISTER
Address: 0x01, Reset: 0x2A, Name: PLL_CLK_CTRL1
B7
B6
B5
B4
B3
B2
B1
B0
0
0
1
0
1
0
1
0
[7:6] LOPWR_MODE
[0] CLK_SEL
Global Power/Performance Adjust
DAC Clock Select
00: I2C Register Settings
01: Reserved
10: Lower Power
11: Lowest Power
0: MCLK from PLL
1: MCLK from MCLKI or XTALI
[1] VREF_EN
Internal Voltage Reference Enable
0: Disabled
1: Enabled
[5:4] MCLKO_SEL
MCLK Output Frequency
00: MCLKO = 4 MHz to 6 MHz scaled by fs
[2] PLL_LOCK
01: MCLKO = 8 MHz to 12 MHz scaled by fs
10: MCLKO = Buffered MCLKI
PLL Lock Indicator
0: PLL Not Locked
11: MCLKO Pin Disabled
1: PLL Locked
[3] PLL_MUTE
PLL Automute Enable/Lock
0: No DAC Automute
1: DAC Automute on PLL Unlock
Table 26. Bit Descriptions for PLL_CLK_CTRL1
Bits
[7:6]
Bit Name
LOPWR_MODE
Settings
00
01
10
11
[5:4]
MCLKO_SEL
00
01
10
11
3
PLL_MUTE
0
1
2
PLL_LOCK
0
1
1
VREF_EN
0
1
0
CLK_SEL
0
1
Description
Global Power/Performance Adjust. These bits adjust the power
consumption and performance level for all 16 DAC channels at once. See
the Digital-to-Analog Converters (DACs) section for more details.
I2C Register Settings
Reserved
Low Power
Lowest Power
MCLK Output Frequency. Frequency selection for MCLKO pin. See the
Clock Signals section for more details.
MCLKO = 4 MHz to 6 MHz scaled by fS
MCLKO = 8 MHz to 12 MHz scaled by fS
MCLKO = Buffered MCLKI
MCLKO Pin Disabled
PLL Automute Enable/Lock. This bit enables the PLL lock automute
function.
No DAC Automute
DAC Automute on PLL Unlock
PLL Lock Indicator.
PLL Not Locked
PLL Locked
Internal Voltage Reference Enable. The internal voltage reference powers
the common mode for the ADAU1966. Disabling this bit allows the user to
drive the CM pin with an outside voltage source.
Disabled
Enabled
DAC Clock Select. Selects between PLL or Direct MCLK mode.
MCLK from PLL
MCLK from MCLKI or XTALI
Rev. 0 | Page 25 of 52
Reset
0x0
Access
RW
0x2
RW
0x1
RW
0x0
R
0x1
RW
0x0
RW
ADAU1966
BLOCK POWER-DOWN AND THERMAL SENSOR CONTROL 1 REGISTER
Address: 0x02, Reset: 0xA0, Name: PDN_THRMSENS_CTRL_1
Table 27. Bit Descriptions for PDN_THRMSENS_CTRL_1
Bits
[7:6]
Bit Name
THRM_RATE
Settings
00
01
10
11
5
THRM_MODE
0
1
4
THRM_GO
0
1
2
TS_PDN
0
1
1
PLL_PDN
0
1
0
VREG_PDN
0
1
Description
Conversion Time Interval. When THERM_MODE = 0, the THERM_RATE bits
control the time interval between temperature conversions.
4 sec/Conversion
0.5 sec/Conversion
1 sec/Conversion
2 sec/Conversion
Continuous vs. One-Shot. Determines whether the temperature
conversions occur continuously or only when commanded. To perform
one-shot temperature conversions, set this bit to 1.
Continuous Operation
One-Shot Mode
One-Shot Conversion Mode. When in one-shot conversion mode,
THERM_MODE = 1, the THERM_GO bit must be set to 0 followed by a write
of 1. This sequence results in a single temperature conversion. The
temperature data is available 120 ms after writing a 1 to this bit.
Reset
Convert temperature
Temperature Sensor Power-Down.
Temperature Sensor On
Temperature Sensor Power-Down
PLL Power-Down.
PLL Normal Operation
PLL Power-Down
Voltage Regulator Power-Down.
Voltage Regulator Normal Operation
Voltage Regulator Power-Down
Rev. 0 | Page 26 of 52
Reset
0x2
Access
RW
0x1
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
ADAU1966
POWER-DOWN CONTROL 2 REGISTER
Address: 0x03, Reset: 0x00, Name: PDN_CTRL2
Table 28. Bit Descriptions for PDN_CTRL2
Bits
7
Bit Name
DAC08_PDN
Settings
0
1
6
DAC07_PDN
0
1
5
DAC06_PDN
0
1
4
DAC05_PDN
0
1
3
DAC04_PDN
0
1
2
DAC03_PDN
0
1
1
DAC02_PDN
0
1
0
DAC01_PDN
0
1
Description
Channel 8 Power-Down.
Normal Operation
Power-Down Channel 8
Channel 7 Power-Down.
Normal Operation
Power-Down Channel 7
Channel 6 Power-Down.
Normal Operation
Power-Down Channel 6
Channel 5 Power-Down.
Normal Operation
Power-Down Channel 5
Channel 4 Power-Down.
Normal Operation
Power-Down Channel 4
Channel 3 Power-Down.
Normal Operation
Power-Down Channel 2
Channel 2 Power-Down.
Normal Operation
Power-Down Channel 2
Channel 1 Power-Down.
Normal Operation
Power-Down Channel 1
Rev. 0 | Page 27 of 52
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
ADAU1966
POWER-DOWN CONTROL 3 REGISTER
Address: 0x04, Reset: 0x00, Name: PDN_CTRL3
Table 29. Bit Descriptions for PDN_CTRL3
Bits
7
Bit Name
DAC16_PDN
Settings
0
1
6
DAC15_PDN
0
1
5
DAC14_PDN
0
1
4
DAC13_PDN
0
1
3
DAC12_PDN
0
1
2
DAC11_PDN
0
1
1
DAC10_PDN
0
1
0
DAC09_PDN
0
1
Description
Channel 16 Power-Down.
Normal Operation
Power-Down Channel 16
Channel 15 Power-Down.
Normal Operation
Power-Down Channel 15
Channel 14 Power-Down.
Normal Operation
Power-Down Channel 14
Channel 13 Power-Down.
Normal Operation
Power-Down Channel 13
Channel 12 Power-Down.
Normal Operation
Power-Down Channel 12
Channel 11 Power-Down.
Normal Operation
Power-Down Channel 11
Channel 10 Power-Down.
Normal Operation
Power-Down Channel 10
Channel 9 Power-Down.
Normal Operation
Power-Down Channel 9
Rev. 0 | Page 28 of 52
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
ADAU1966
THERMAL SENSOR TEMPERATURE READOUT REGISTER
Address: 0x05, Reset: 0x00, Name: THRM_TEMP_STAT
Thermal Sensor Temperature Readout. −60°C to +140°C range, 1°C step size. Read this register and convert the hexadecimal or binary
TEMP value into decimal form; then subtract 60 from this decimal conversion. The result is the temperature in degrees Celsius.
Table 30. Bit Descriptions for THRM_TEMP_STAT
Bits
[7:0]
Bit Name
TEMP
Settings
Description
Thermal Sensor Temperature Readout. −60°C to +140°C range, 1°C step
size. To convert TEMP code to temperature, use the equation (TEMP − 60).
Rev. 0 | Page 29 of 52
Reset
0x00
Access
R
ADAU1966
DAC CONTROL 0 REGISTER
Address: 0x06, Reset: 0x01, Name: DAC_CTRL0
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
1
[7:6] SDATA_FMT
[0] MMUTE
SDATA Format
DAC Master Mute
00: I2S—1-BCLK Cycle Delay
01: Left-Justified—0-BCLK Cycle Delay
10: Right-Justified 24-bit Data—
8-BCLK Cycle Delay
11: Right-Justified 16-bit Data—
16-BCLK Cycle Delay
0: Normal Operation
1: All Channels Muted
[2:1] FS
Sample Rate Select
00: 32 kHz/44.1kHz/48kHz
[5:3] SAI
01: 64 kHz/88.2kHz/96kHz
Serial Audio Interface
10: 128 kHz/176.4kHz/192kHz
000: Stereo (I 2S, LJ, RJ)
11: 128 kHz/176.4kHz/192kHz Low Propagation Delay
001: TDM2—Octal Line
010: TDM4—Quad Line
011: TDM8—Dual Line
100: TDM16—Single Line (48 kHz)
101: Reserved
110: Reserved
111: Reserved
Table 31. Bit Descriptions for DAC_CTRL0
Bits
[7:6]
Bit Name
SDATA_FMT
Settings
00
01
10
11
[5:3]
SAI
000
001
010
011
100
101
110
111
[2:1]
FS
00
01
10
11
0
MMUTE
0
1
Description
SDATA Format. Only used when SAI = 000.
I2S—1-BCLK Cycle Delay
Left-Justified—0-BCLK Cycle Delay
Right-Justified 24-bit Data—8-BCLK Cycle Delay
Right-Justified 16-bit Data—16-BCLK Cycle Delay
Serial Audio Interface. When SAI = 000, the SDATA_FMT bits control stereo
SDATA format.
Stereo (I2S, LJ, RJ)
TDM2—Octal Line
TDM4—Quad Line
TDM8—Dual Line
TDM16—Single Line (48 kHz)
Reserved
Reserved
Reserved
Sample Rate Select.
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
128 kHz/176.4 kHz/192 kHz Low Propagation Delay
DAC Master Mute.
Normal Operation
All Channels Muted
Rev. 0 | Page 30 of 52
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x1
RW
ADAU1966
DAC CONTROL 1 REGISTER
Address: 0x07, Reset: 0x00, Name: DAC_CTRL1
Table 32. Bit Descriptions for DAC_CTRL1
Bits
7
Bit Name
BCLK_GEN
Settings
0
1
6
LRCLK_MODE
0
1
5
LRCLK_POL
0
1
4
SAI_MSB
0
1
2
BCLK_RATE
0
1
1
BCLK_EDGE
0
1
0
SAI_MS
0
1
Description
DBCLK Generation. When the PLL is locked to DLRCLK, it is possible to run
the ADAU1966 without an external DBCLK.
Normal Operation—DBCLK
Internal DBCLK Generation
DLRCLK Mode Select. Only Valid for TDM modes.
50% Duty Cycle DLRCLK
Pulse Mode
DLRCLK Polarity. Allows the swapping of data between channels.
Left/Odd channels are DLRCLK Low (Normal)
Left/Odd channels are DLRCLK High (Inverted)
MSB Position.
MSB First DSDATA
LSB First DSDATA
DBCLK Rate. Number of DBCLK cycles per DLRCLK Frame. Used only for
generating DBCLK in Master Mode operation (SAI_MS = 1).
32 Cycles per Frame
16 Cycles per Frame
DBCLK Active Edge. Adjust the polarity of the DBCLK leading edge.
Latch in Rising Edge
Latch in Falling Edge
Serial Interface Master. Both DLRCLK and DBCLK become master when
enabled.
DLRCLK/DBCLK Slave
DLRCLK/DBCLK Master
Rev. 0 | Page 31 of 52
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
ADAU1966
DAC CONTROL 2 REGISTER
Address: 0x08, Reset: 0x06, Name: DAC_CTRL2
Table 33. Bit Descriptions for DAC_CTRL2
Bits
[6:5]
Bit Name
VREG_CTRL
Settings
00
01
10
11
4
BCLK_TDMC
0
1
3
DAC_POL
0
1
2
AUTO_MUTE_EN
0
1
1
DAC_OSR
0
1
0
DE_EMP_EN
0
1
Description
Voltage Regulator Control. Select the Regulator Output Voltage.
Regulator Out = 2.5 V
Regulator Out = 2.75 V
Regulator Out = 3.0 V
Regulator Out = 3.3 V
DBCLK Rate in TDM Mode. Number of DBCLK cycles per channel slot when
in TDM mode.
32 BCLK cycles/channel slot
16 BCLK cycles/channel slot
DAC Output Polarity. This is a global switch of DAC polarity.
Noninverted DAC Output
Inverted DAC Output
Automute Enable. Automatically mutes the DACs when 1024 consecutive
zero input samples are received. This is independent per channel.
Auto-Zero Input Mute Disabled
Auto-Zero Input Mute Enabled
DAC Oversampling Rate. OSR Selection.
256 × fS DAC Oversampling
128 × fS DAC Oversampling
De-Emphasis Enable.
No De-Emphasis/Flat
De-Emphasis Enabled
Rev. 0 | Page 32 of 52
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x1
RW
0x1
RW
0x0
RW
ADAU1966
DAC INDIVIDUAL CHANNEL MUTES 1 REGISTER
Address: 0x09, Reset: 0x00, Name: DAC_MUTE1
Table 34. Bit Descriptions for DAC_MUTE1
Bits
7
Bit Name
DAC08_MUTE
Settings
0
1
6
DAC07_MUTE
0
1
5
DAC06_MUTE
0
1
4
DAC05_MUTE
0
1
3
DAC04_MUTE
0
1
2
DAC03_MUTE
0
1
1
DAC02_MUTE
0
1
0
DAC01_MUTE
0
1
Description
DAC8 Soft Mute.
DAC8 Normal Operation
DAC8 Mute
DAC7 Soft Mute.
DAC7 Normal Operation
DAC7 Mute
DAC6 Soft Mute.
DAC6 Normal Operation
DAC6 Mute
DAC5 Soft Mute.
DAC5 Normal Operation
DAC5 Mute
DAC4 Soft Mute.
DAC4 Normal Operation
DAC4 Mute
DAC3 Soft Mute.
DAC3 Normal Operation
DAC3 Mute
DAC2 Soft Mute.
DAC2 Normal Operation
DAC2 Mute
DAC1 Soft Mute.
DAC1 Normal Operation
DAC1 Mute
Rev. 0 | Page 33 of 52
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
ADAU1966
DAC INDIVIDUAL CHANNEL MUTES 2 REGISTER
Address: 0x0A, Reset: 0x00, Name: DAC_MUTE2
Table 35. Bit Descriptions for DAC_MUTE2
Bits
7
Bit Name
DAC16_MUTE
Settings
0
1
6
DAC15_MUTE
0
1
5
DAC14_MUTE
0
1
4
DAC13_MUTE
0
1
3
DAC12_MUTE
0
1
2
DAC11_MUTE
0
1
1
DAC10_MUTE
0
1
0
DAC09_MUTE
0
1
Description
DAC16 Soft Mute.
DAC16 Normal Operation
DAC16 Mute
DAC15 Soft Mute.
DAC15 Normal Operation
DAC15 Mute
DAC14 Soft Mute.
DAC14 Normal Operation
DAC14 Mute
DAC13 Soft Mute.
DAC13 Normal Operation
DAC13 Mute
DAC12 Soft Mute.
DAC12 Normal Operation
DAC12 Mute
DAC11 Soft Mute.
DAC11 Normal Operation
DAC11 Mute
DAC10 Soft Mute.
DAC10 Normal Operation
DAC10 Mute
DAC9 Soft Mute.
DAC9 Normal Operation
DAC9 Mute
Rev. 0 | Page 34 of 52
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
ADAU1966
MASTER VOLUME CONTROL REGISTER
Address: 0x0B, Reset: 0x00, Name: DACMSTR_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 36. Bit Descriptions for DACMSTR_VOL
Bits
[7:0]
Bit Name
DACMSTR_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
Master Volume Control.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Reset
0x00
Access
RW
Reset
0x00
Access
RW
DAC 1 VOLUME CONTROL REGISTER
Address: 0x0C, Reset: 0x00, Name: DAC01_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 37. Bit Descriptions for DAC01_VOL
Bits
[7:0]
Bit Name
DAC01_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 1.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Rev. 0 | Page 35 of 52
ADAU1966
DAC 2 VOLUME CONTROL REGISTER
Address: 0x0D, Reset: 0x00, Name: DAC02_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 38. Bit Descriptions for DAC02_VOL
Bits
[7:0]
Bit Name
DAC02_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 2.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Reset
0x00
Access
RW
Reset
0x00
Access
RW
DAC 3 VOLUME CONTROL REGISTER
Address: 0x0E, Reset: 0x00, Name: DAC03_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 39. Bit Descriptions for DAC03_VOL
Bits
[7:0]
Bit Name
DAC03_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 3.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Rev. 0 | Page 36 of 52
ADAU1966
DAC 4 VOLUME CONTROL REGISTER
Address: 0x0F, Reset: 0x00, Name: DAC04_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 40. Bit Descriptions for DAC04_VOL
Bits
[7:0]
Bit Name
DAC04_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 4.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Reset
0x00
Access
RW
Reset
0x00
Access
RW
DAC 5 VOLUME CONTROL REGISTER
Address: 0x10, Reset: 0x00, Name: DAC05_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 41. Bit Descriptions for DAC05_VOL
Bits
[7:0]
Bit Name
DAC05_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 5.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Rev. 0 | Page 37 of 52
ADAU1966
DAC 6 VOLUME CONTROL REGISTER
Address: 0x11, Reset: 0x00, Name: DAC06_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 42. Bit Descriptions for DAC06_VOL
Bits
[7:0]
Bit Name
DAC06_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 6.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Reset
0x00
Access
RW
Reset
0x00
Access
RW
DAC 7 VOLUME CONTROL REGISTER
Address: 0x12, Reset: 0x00, Name: DAC07_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 43. Bit Descriptions for DAC07_VOL
Bits
[7:0]
Bit Name
DAC07_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 7.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Rev. 0 | Page 38 of 52
ADAU1966
DAC 8 VOLUME CONTROL REGISTER
Address: 0x13, Reset: 0x00, Name: DAC08_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 44. Bit Descriptions for DAC08_VOL
Bits
[7:0]
Bit Name
DAC08_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 8.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Reset
0x00
Access
RW
Reset
0x00
Access
RW
DAC 9 VOLUME CONTROL REGISTER
Address: 0x14, Reset: 0x00, Name: DAC09_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 45. Bit Descriptions for DAC09_VOL
Bits
[7:0]
Bit Name
DAC09_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 9.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Rev. 0 | Page 39 of 52
ADAU1966
DAC 10 VOLUME CONTROL REGISTER
Address: 0x15, Reset: 0x00, Name: DAC10_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 46. Bit Descriptions for DAC10_VOL
Bits
[7:0]
Bit Name
DAC10_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 10.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Reset
0x00
Access
RW
Reset
0x00
Access
RW
DAC 11 VOLUME CONTROL REGISTER
Address: 0x16, Reset: 0x00, Name: DAC11_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 47. Bit Descriptions for DAC11_VOL
Bits
[7:0]
Bit Name
DAC11_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 11.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Rev. 0 | Page 40 of 52
ADAU1966
DAC 12 VOLUME CONTROL REGISTER
Address: 0x17, Reset: 0x00, Name: DAC12_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 48. Bit Descriptions for DAC12_VOL
Bits
[7:0]
Bit Name
DAC12_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 12.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Reset
0x00
Access
RW
Reset
0x00
Access
RW
DAC 13 VOLUME CONTROL REGISTER
Address: 0x18, Reset: 0x00, Name: DAC13_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 49. Bit Descriptions for DAC13_VOL
Bits
[7:0]
Bit Name
DAC13_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 13.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Rev. 0 | Page 41 of 52
ADAU1966
DAC 14 VOLUME CONTROL REGISTER
Address: 0x19, Reset: 0x00, Name: DAC14_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 50. Bit Descriptions for DAC14_VOL
Bits
[7:0]
Bit Name
DAC14_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 14.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Reset
0x00
Access
RW
Reset
0x00
Access
RW
DAC 15 VOLUME CONTROL REGISTER
Address: 0x1A, Reset: 0x00, Name: DAC15_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 51. Bit Descriptions for DAC15_VOL
Bits
[7:0]
Bit Name
DAC15_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 15.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Rev. 0 | Page 42 of 52
ADAU1966
DAC 16 VOLUME CONTROL REGISTER
Address: 0x1B, Reset: 0x00, Name: DAC16_VOL
Each 1-bit step corresponds to a 0.375 dB change in volume. See Table 58 for a complete list of the volume settings.
Table 52. Bit Descriptions for DAC16_VOL
Bits
[7:0]
Bit Name
DAC16_VOL
Settings
00000000
00000001
00000010
11111110
11111111
Description
DAC Volume Control Channel 16.
0 dB (default)
−0.375 dB
−0.750 dB
−95.250 dB
−95.625 dB
Reset
0x00
Access
RW
Reset
0x0
Access
RW
0x1
RW
COMMON-MODE AND PAD STRENGTH REGISTER
Address: 0x1C, Reset: 0x02, Name: CM_SEL_PAD_STRGTH
Table 53. Bit Descriptions for CM_SEL_PAD_STRGTH
Bits
5
Bit Name
PAD_DRV
Settings
0
1
1
CM_SEL
0
1
Description
Output Pad Drive Strength Control. Pad strength is stated for IOVDD = 5 V.
4 mA Drive for All Pads
8 mA Drive for All Pads
Common Mode Generation Selection.
Fixed 3.3 V AVDD CM Generation
Fixed 5 V AVDD CM Generation
Rev. 0 | Page 43 of 52
ADAU1966
DAC POWER ADJUST 1 REGISTER
Address: 0x1D, Reset: 0xAA, Name: DAC_POWER1
Table 54. Bit Descriptions for DAC_POWER1
Bits
[7:6]
Bit Name
DAC04_POWER
Settings
00
01
10
11
[5:4]
DAC03_POWER
00
01
10
11
[3:2]
DAC02_POWER
00
01
10
11
[1:0]
DAC01_POWER
00
01
10
11
Description
DAC Power Control Channel 4.
Low Power
Lowest Power
Best Performance
Good Performance
DAC Power Control Channel 3.
Low Power
Lowest Power
Best Performance
Good Performance
DAC Power Control Channel 2.
Low Power
Lowest Power
Best Performance
Good Performance
DAC Power Control Channel 1.
Low Power
Lowest Power
Best Performance
Good Performance
Rev. 0 | Page 44 of 52
Reset
0x2
Access
RW
0x2
RW
0x2
RW
0x2
RW
ADAU1966
DAC POWER ADJUST 2 REGISTER
Address: 0x1E, Reset: 0xAA, Name: DAC_POWER2
Table 55. Bit Descriptions for DAC_POWER2
Bits
[7:6]
Bit Name
DAC08_POWER
Settings
00
01
10
11
[5:4]
DAC07_POWER
00
01
10
11
[3:2]
DAC06_POWER
00
01
10
11
[1:0]
DAC05_POWER
00
01
10
11
Description
DAC Power Control Channel 8.
Low Power
Lowest Power
Best Performance
Good Performance
DAC Power Control Channel 7.
Low Power
Lowest Power
Best Performance
Good Performance
DAC Power Control Channel 6.
Low Power
Lowest Power
Best Performance
Good Performance
DAC Power Control Channel 5.
Low Power
Lowest Power
Best Performance
Good Performance
Rev. 0 | Page 45 of 52
Reset
0x2
Access
RW
0x2
RW
0x2
RW
0x2
RW
ADAU1966
DAC POWER ADJUST 3 REGISTER
Address: 0x1F, Reset: 0xAA, Name: DAC_POWER3
Table 56. Bit Descriptions for DAC_POWER3
Bits
[7:6]
Bit Name
DAC12_POWER
Settings
00
01
10
11
[5:4]
DAC11_POWER
00
01
10
11
[3:2]
DAC10_POWER
00
01
10
11
[1:0]
DAC09_POWER
00
01
10
11
Description
DAC Power Control Channel 12.
Low Power
Lowest Power
Best Performance
Good Performance
DAC Power Control Channel 11.
Low Power
Lowest Power
Best Performance
Good Performance
DAC Power Control Channel 10.
Low Power
Lowest Power
Best Performance
Good Performance
DAC Power Control Channel 9.
Low Power
Lowest Power
Best Performance
Good Performance
Rev. 0 | Page 46 of 52
Reset
0x2
Access
RW
0x2
RW
0x2
RW
0x2
RW
ADAU1966
DAC POWER ADJUST 4 REGISTER
Address: 0x20, Reset: 0xAA, Name: DAC_POWER4
Table 57. Bit Descriptions for DAC_POWER4
Bits
[7:6]
Bit Name
DAC16_POWER
Settings
00
01
10
11
[5:4]
DAC15_POWER
00
01
10
11
[3:2]
DAC14_POWER
00
01
10
11
[1:0]
DAC13_POWER
00
01
10
11
Description
DAC Power Control Channel 16.
Low Power
Lowest Power
Best Performance
Good Performance
DAC Power Control Channel 15.
Low Power
Lowest Power
Best Performance
Good Performance
DAC Power Control Channel 14.
Low Power
Lowest Power
Best Performance
Good Performance
DAC Power Control Channel 13.
Low Power
Lowest Power
Best Performance
Good Performance
Rev. 0 | Page 47 of 52
Reset
0x2
Access
RW
0x2
RW
0x2
RW
0x2
RW
ADAU1966
Table 58. Volume Table
Binary Value
Volume Attenuation (dB)
Binary Value
Volume Attenuation (dB)
00000000
0
00101110
−17.25
00000001
−0.375
00101111
−17.625
00000010
−0.75
00110000
−18
00000011
−1.125
00110001
−18.375
00000100
−1.5
00110010
−18.75
00000101
−1.875
00110011
−19.125
00000110
−2.25
00110100
−19.5
00000111
−2.625
00110101
−19.875
00001000
−3
00110110
−20.25
00001001
−3.375
00110111
−20.625
00001010
−3.75
00111000
−21
00001011
−4.125
00111001
−21.375
00001100
−4.5
00111010
−21.75
00001101
−4.875
00111011
−22.125
00001110
−5.25
00111100
−22.5
00001111
−5.625
00111101
−22.875
00010000
−6
00111110
−23.25
00010001
−6.375
00111111
−23.625
00010010
−6.75
01000000
−24
00010011
−7.125
01000001
−24.375
00010100
−7.5
01000010
−24.75
00010101
−7.875
01000011
−25.125
00010110
−8.25
01000100
−25.5
00010111
−8.625
01000101
−25.875
00011000
−9
01000110
−26.25
00011001
−9.375
01000111
−26.625
00011010
−9.75
01001000
−27
00011011
−10.125
01001001
−27.375
00011100
−10.5
01001010
−27.75
00011101
−10.875
01001011
−28.125
00011110
−11.25
01001100
−28.5
00011111
−11.625
01001101
−28.875
00100000
−12
01001110
−29.25
00100001
−12.375
01001111
−29.625
00100010
−12.75
01010000
−30
00100011
−13.125
01010001
−30.375
00100100
−13.5
01010010
−30.75
00100101
−13.875
01010011
−31.125
00100110
−14.25
01010100
−31.5
00100111
−14.625
01010101
−31.875
00101000
−15
01010110
−32.25
00101001
−15.375
01010111
−32.625
00101010
−15.75
01011000
−33
00101011
−16.125
01011001
−33.375
00101100
−16.5
01011010
−33.75
00101101
−16.875
01011011
−34.125
Rev. 0 | Page 48 of 52
ADAU1966
Binary Value
Volume Attenuation (dB)
Binary Value
Volume Attenuation (dB)
01011100
−34.5
10001011
−52.125
01011101
−34.875
10001100
−52.5
01011110
−35.25
10001101
−52.875
01011111
−35.625
10001110
−53.25
01100000
−36
10001111
−53.625
01100001
−36.375
10010000
−54
01100010
−36.75
10010001
−54.375
01100011
−37.125
10010010
−54.75
01100100
−37.5
10010011
−55.125
01100101
−37.875
10010100
−55.5
01100110
−38.25
10010101
−55.875
01100111
−38.625
10010110
−56.25
01101000
−39
10010111
−56.625
01101001
−39.375
10011000
−57
01101010
−39.75
10011001
−57.375
01101011
−40.125
10011010
−57.75
01101100
−40.5
10011011
−58.125
01101101
−40.875
10011100
−58.5
01101110
−41.25
10011101
−58.875
01101111
−41.625
10011110
−59.25
01110000
−42
10011111
−59.625
01110001
−42.375
10100000
−60
01110010
−42.75
10100001
−60.375
01110011
−43.125
10100010
−60.75
01110100
−43.5
10100011
−61.125
01110101
−43.875
10100100
−61.5
01110110
−44.25
10100101
−61.875
01110111
−44.625
10100110
−62.25
01111000
−45
10100111
−62.625
01111001
−45.375
10101000
−63
01111010
−45.75
10101001
−63.375
01111011
−46.125
10101010
−63.75
01111100
−46.5
10101011
−64.125
01111101
−46.875
10101100
−64.5
01111110
−47.25
10101101
−64.875
01111111
−47.625
10101110
−65.25
10000000
−48
10101111
−65.625
10000001
−48.375
10110000
−66
10000010
−48.75
10110001
−66.375
10000011
−49.125
10110010
−66.75
10000100
−49.5
10110011
−67.125
10000101
−49.875
10110100
−67.5
10000110
−50.25
10110101
−67.875
10000111
−50.625
10110110
−68.25
10001000
−51
10110111
−68.625
10001001
−51.375
10111000
−69
10001010
−51.75
10111001
−69.375
Rev. 0 | Page 49 of 52
ADAU1966
Binary Value
Volume Attenuation (dB)
Binary Value
Volume Attenuation (dB)
10111010
−69.75
11011101
−82.875
10111011
−70.125
11011110
−83.25
10111100
−70.5
11011111
−83.625
10111101
−70.875
11100000
−84
10111110
−71.25
11100001
−84.375
10111111
−71.625
11100010
−84.75
11000000
−72
11100011
−85.125
11000001
−72.375
11100100
−85.5
11000010
−72.75
11100101
−85.875
11000011
−73.125
11100110
−86.25
11000100
−73.5
11100111
−86.625
11000101
−73.875
11101000
−87
11000110
−74.25
11101001
−87.375
11000111
−74.625
11101010
−87.75
11001000
−75
11101011
−88.125
11001001
−75.375
11101100
−88.5
11001010
−75.75
11101101
−88.875
11001011
−76.125
11101110
−89.25
11001100
−76.5
11101111
−89.625
11001101
−76.875
11110000
−90
11001110
−77.25
11110001
−90.375
11001111
−77.625
11110010
−90.75
11010000
−78
11110011
−91.125
11010001
−78.375
11110100
−91.5
11010010
−78.75
11110101
−91.875
11010011
−79.125
11110110
−92.25
11010100
−79.5
11110111
−92.625
11010101
−79.875
11111000
−93
11010110
−80.25
11111001
−93.375
11010111
−80.625
11111010
−93.75
11011000
−81
11111011
−94.125
11011001
−81.375
11111100
−94.5
11011010
−81.75
11111101
−94.875
11011011
−82.125
11111110
−95.25
11011100
−82.5
11111111
−95.625
Rev. 0 | Page 50 of 52
ADAU1966
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.00
BSC SQ
1.60
MAX
61
80
60
1
SEATING
PLANE
PIN 1
14.00
BSC SQ
TOP VIEW
(PINS DOWN)
10°
6°
2°
1.45
1.40
1.35
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.10 MAX
COPLANARITY
VIEW A
20
41
40
21
0.65
BSC
VIEW A
0.38
0.32
0.22
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 19. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
ADAU1966WBSTZ
ADAU1966WBSTZRL
EVAL-ADAU1966Z
1
2
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
80-Lead LQFP
80-Lead LQFP, 13” Tape and Reel
Evaluation Board
Package Option
ST-80-2
ST-80-2
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADAU1966W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
Rev. 0 | Page 51 of 52
ADAU1966
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09434-0-9/11(0)
Rev. 0 | Page 52 of 52