4.25 Gbps, 8 × 8, Asynchronous Crosspoint Switch ADN4600 FEATURES FUNCTIONAL BLOCK DIAGRAM ADN4600 RECEIVE EQUALIZATION CROSSPOINT ARRAY TRANSMIT PRE-EMPHASIS IP[7:0] OP[7:0] EQ PE ON[7:0] IN[7:0] ADDR[1:0] SCL SDA CONTROL LOGIC RESETB 07061-001 Full 8 × 8 crossbar connectivity Fully buffered signal path supports multicast and broadcast operation Optimized for dc to 4.25 Gbps data Programmable receive equalization Compensates for up to 30 in. of FR4 @ 4.25 Gbps Programmable transmit pre-emphasis/de-emphasis Compensates for up to 30 in. of FR4 @ 4.25 Gbps Flexible 1.8 V to 3.3 V core supply Per lane positive/negative (P/N) pair inversion for routing ease Low power: 125 mW/channel at 4.25 Gbps DC- or ac-coupled differential CML inputs Programmable CML output levels 50 Ω on-chip termination −40°C to +85°C temperature range operation Supports 8b10b, scrambled or uncoded nonreturn-to-zero (NRZ) data I2C control interface Package: 64-lead LFCSP Figure 1. APPLICATIONS 1×, 2×, 4× FibreChannel XAUI Gigabit Ethernet over backplane 10GBase-CX4 InfiniBand® 50 Ω cables GENERAL DESCRIPTION The ADN4600 is an asynchronous, nonblocking crosspoint switch with eight differential PECL-/CML-compatible inputs with programmable equalization and eight differential CML outputs with programmable output levels and pre-emphasis or de-emphasis. The operation of this device is optimized for NRZ data at rates up to 4.25 Gbps. The receive inputs provide programmable equalization with nine settings to compensate for up to 30 in. of FR4 and programmable pre-emphasis with seven settings to compensate for up to 30 in. of FR4 at 4.25 Gbps. The ADN4600 nonblocking switch core implements an 8 × 8 crossbar and supports independent channel switching through the I2C control interface. Every channel implements an asynchronous path supporting NRZ data rates from dc to 4.25 Gbps. Each channel is fully independent of other channels. The ADN4600 has low latency and very low channel-to-channel skew. The main application for the ADN4600 is to support switching on the backplane, line card, or cable interface sides of serial links. The ADN4600 is packaged in a 9 mm × 9 mm, 64-lead LFCSP package and operates from −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. ADN4600 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 13 Functional Block Diagram .............................................................. 1 Introduction ................................................................................ 13 General Description ......................................................................... 1 Receivers ...................................................................................... 13 Revision History ............................................................................... 2 Switch Core ................................................................................. 15 Specifications..................................................................................... 3 Transmitters ................................................................................ 16 Electrical Specifications ............................................................... 3 I2C Control Interface.................................................................. 22 Timing Specifications .................................................................. 5 PCB Design Guidelines ............................................................. 24 Absolute Maximum Ratings............................................................ 6 Control Register Map ..................................................................... 25 ESD Caution .................................................................................. 6 Package Outline Dimensions ........................................................ 28 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 28 REVISION HISTORY 6/08—Revision 0: Initial Version Rev. 0 | Page 2 of 2 ADN4600 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VCC = 1.8 V, VEE = 0 V, VTTI = VTTO = VCC, RL = 50 Ω, differential output swing = 800 mV p-p differential, 4.25 Gbps, PRBS 27 − 1, TA = 25°C, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Maximum Data Rate per Channel Deterministic Jitter Random Jitter Residual Deterministic Jitter with Receive Equalization Residual Deterministic Jitter with Transmit Pre-Emphasis Output Rise/Fall Time Channel-to-Channel Skew Propagation Delay OUTPUT PRE-EMPHASIS Equalization Method Maximum Boost Pre-Emphasis Tap Range INPUT EQUALIZATION Minimum Boost Maximum Boost Number of Equalization Steps Gain Step Size INPUT CHARACTERISTICS Input Voltage Swing Input Voltage Range Input Resistance Input Return Loss OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Range Output Current Output Resistance Output Return Loss Conditions Min In NRZ format Data rate < 4.25 Gbps; BER = 1e − 12 VCC = 1.8 V Data rate < 3.25 Gbps; 0 in. to 30 in. FR4 Data rate < 4.25 Gbps; 0 in. to 30 in. FR4 Data rate < 3.25 Gbps; 0 in. to 30 in. FR4 Data rate < 4.25 Gbps; 0 in. to 30 in. FR4 20% to 80% 4.25 One-tap programmable pre-emphasis 800 mV p-p output swing 200 mV p-p output swing Minimum Maximum EQBY = 1 Maximum boost occurs @ 2.125 GHz Differential, VICM 1 = VCC − 0.6 V; VCC = 3.3 V Single-ended absolute voltage level, VL minimum Single-ended absolute voltage level, VH maximum Single-ended Measured at 2.5 GHz @ dc, differential, PE = 0, default, VCC = 1.8 V @ dc, differential, PE = 0, default, VCC = 3.3 V @ dc, differential, PE = 0, min output level 2 , VCC = 1.8 V @ dc, differential, PE = 0, min output level2, VCC = 3.3 V @ dc, differential, PE = 0, max output level2, VCC = 1.8 V @ dc, differential, PE = 0, max output level2, VCC = 3.3 V Single-ended absolute voltage level, TxHeadroom = 0; VL min Single-ended absolute voltage level, TxHeadroom = 0; VH max Single-ended absolute voltage level, TxHeadroom = 1; VL min Single-ended absolute voltage level, TxHeadroom = 1; VH max Minimum output current per channel Maximum output current per channel, VCC = 1.8 V Single ended Measured at 2.5 GHz Rev. 0 | Page 3 of 3 Typ 635 45 Unit 30 1.5 0.16 0.20 0.13 0.18 75 50 1 Gbps ps p-p ps rms UI UI UI UI ps ps ns 6 12 2 12 dB dB mA mA 1.5 22 8 2.5 dB dB Steps dB 300 45 Max 2000 VEE + 0.4 VCC + 0.5 50 5 740 800 100 100 1300 1800 VCC − 1.1 55 870 mV p-p V p-p V p-p Ω dB mV p-p mV p-p mV p-p mV p-p mV p-p mV p-p V VCC + 0.6 V VCC − 1.2 V VCC + 0.6 V 2 21 50 5 mA 55 Ω dB ADN4600 Parameter POWER SUPPLY Operating Range VCC DVCC VTTI VTTO Supply Current 3 ITTO ICC IEE ITTO ICC IEE LOGIC CHARACTERISTICS Input High (VIH) Input Low (VIL) Output High (VOH) Output Low (VOL) THERMAL CHARACTERISTICS Operating Temperature Range θJA 1 2 3 Conditions Min Typ Max Unit VEE = 0 V VEE = 0 V, DVCC ≤ (VCC + 1.3 V) (VEE + 0.4 V + 0.5 × VID) < VTTI < (VCC + 0.5 V) 1.7 3.0 VEE + 0.4 VCC − 1.1 1.8 3.3 1.8 3.6 3.6 3.6 V V V 1.8 3.6 V 63 460 586 16 173 205 69 565 mA mA mA mA mA mA (VCC − 1.1 V + 0.5 × VOD) < VTTO < (VCC + 0.5 V) All outputs enabled All outputs enabled All outputs enabled Single channel enabled Single channel enabled Single channel enabled DVCC = 3.3 V 18 214 2.5 1.0 2.5 1.0 −40 +85 22 VICM is the input common-mode voltage. Programmable via I2C. Assumes dc-coupled outputs. For ac-coupled outputs, ITTO currents will double. Rev. 0 | Page 4 of 4 V V V V °C °C/W ADN4600 TIMING SPECIFICATIONS Table 2. I2C Timing Parameters Parameter fSCL tHD;STA tSU;STA tLOW tHIGH tHD;DAT tSU;DAT tr tf tSU;STO tBUF CIO Min 0 0.6 0.6 1.3 0.6 0 10 1 1 0.6 1 5 Max 400 N/A N/A N/A N/A N/A N/A 300 300 N/A N/A 7 Unit kHz μs μs μs μs μs ns ns ns μs ns Pf Description SCL clock frequency Hold time for a start condition Setup time for a repeated start condition Low period of the SCL clock High period of the SCL clock Data hold time Data setup time Rise time for both SDA and SCL Fall time for both SDA and SCL Setup time for a stop condition Bus-free time between a stop and a start condition Capacitance for each I/O pin I2C Timing Specifications SDA tSU:DAT tf tLOW tf tHD:STA tf tBUF tf tHD:STA S tHD:DAT tHIGH tSU:STA tSU:STO Sr Figure 2. I2C Timing Diagram Rev. 0 | Page 5 of 5 P S 07061-010 SCL ADN4600 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VCC to VEE VTTI VTTO Internal Power Dissipation Differential Input Voltage Logic Input Voltage Storage Temperature Range Lead Temperature Rating 3.7 V VCC + 0.6 V VCC + 0.6 V 4.26 W 2.0 V VEE − 0.3 V < VIN < VCC + 0.6 V −65°C to +125°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 6 of 6 ADN4600 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VEE VCC VEE OP0 ON0 VCC OP1 ON1 VTTO OP2 ON2 VEE OP3 ON3 ADDR1 ADDR0 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADN4600 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCL SDA VEE IP7 IN7 VCC IP6 IN6 VTTI IP5 IN5 VEE IP4 IN4 VCC VEE VEE VCC ON7 OP7 VCC ON6 OP6 VTTO ON5 OP5 VEE ON4 OP4 VEE VCC VEE NOTES 1. PAD ON BOTTOM OF PACKAGE MUST BE CONNECTED TO VEE. 07061-002 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RESETB VEE IN0 IP0 VCC IN1 IP1 VTTI IN2 IP2 VEE IN3 IP3 DVCC VCC VEE Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2, 11, 16, 17, 27, 30, 32, 33, 37, 46, 53, 62, 64 3, 6, 9, 12, 35, 38, 41, 44 4, 7, 10, 13, 36, 39, 42, 45 5, 15, 18, 21, 31, 34, 43, 59, 63 8, 40 14 19, 22, 25, 28, 51, 54, 57, 60 20, 23, 26, 29, 52, 55, 58, 61 24, 56 47 48 49 50 Mnemonic RESETB VEE Type Control Power Description Reset Input (Active Low) Negative Supply IN0 to IN7 I/O High Speed Inputs IP0 to IP7 I/O High Speed Input Complements VCC Power Positive Supply VTTI DVCC ON7 to ON0 Power Power I/O Input Termination Supply Digital Positive Supply (3.3 V) High Speed Outputs OP7 to ON0 I/O High Speed Output Complements VTTO SDA SCL ADDR0 ADDR1 EPAD Power Control Control Control Control Power Output Termination Supply I2C Control Interface Data Input/Output I2C Control Interface Clock Input I2C Control Interface Address LSB I2C Control Interface Address MSB Connect to VEE Rev. 0 | Page 7 of 7 ADN4600 TYPICAL PERFORMANCE CHARACTERISTICS Figure 5 to Figure 8 were obtained using the standard test circuit shown in Figure 4. 2 50Ω CABLES PATTERN GENERATOR 2 INPUT PIN OUTPUT 2 PIN 50Ω CABLES 2 50Ω ADN4600 AC-COUPLED EVALUATION BOARD TP1 TP2 HIGH SPEED SAMPLING OSCILLOSCOPE 07061-011 DATA OUT 50ps/DIV 50ps/DIV Figure 6. 4.25 Gbps Input Eye (TP1 from Figure 4) Figure 8. 4.25 Gbps Output Eye, No Channel (TP2 from Figure 4) Rev. 0 | Page 8 of 8 07061-015 50ps/DIV 07061-013 200mV/DIV Figure 7. 3.25 Gbps Output Eye, No Channel (TP2 from Figure 4) 200mV/DIV Figure 5. 3.25 Gbps Input Eye (TP1 from Figure 4) 07061-014 200mV/DIV 50ps/DIV 07061-012 200mV/DIV Figure 4. Standard Test Circuit (No Channel) ADN4600 Figure 10 to Figure 13 were obtained using the standard test circuit shown in Figure 9. 2 DATA OUT 50Ω CABLES 2 50Ω CABLES 2 2 DIFFERENTIAL STRIPLINE TRACES TP1 8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT TRACE LENGTHS = 30'' INPUT OUTPUT 2 PIN PIN 50Ω CABLES 2 50Ω ADN4600 TP2 AC-COUPLED EVALUATION BOARD TP3 HIGH SPEED SAMPLING OSCILLOSCOPE 07061-016 PATTERN GENERATOR FR4 TEST BACKPLANE 50ps/DIV 50ps/DIV 07061-020 50ps/DIV Figure 11. 4.25 Gbps Input Eye, 30 Inch FR4 Input Channel (TP2 from Figure 9) 07061-018 200mV/DIV Figure 12. 3.25 Gbps Output Eye, 30 Inch FR4 Input Channel, Best EQ Setting (TP3 from Figure 9) 200mV/DIV Figure 10. 3.25 Gbps Input Eye, 30 Inch FR4 Input Channel (TP2 from Figure 9) 07061-019 200mV/DIV 50ps/DIV 07061-017 200mV/DIV Figure 9. Input Equalization Test Circuit, FR4 (See Figure 5 and Figure 6 for the Reference Eye Diagrams at TP1) Figure 13. 4.25 Gbps Output Eye, 30 Inch FR4 Input Channel, Best EQ Setting (TP3 from Figure 9) Rev. 0 | Page 9 of 9 ADN4600 Figure 15 to Figure 18 were obtained using the standard test circuit shown in Figure 14. 2 DATA OUT 50Ω CABLES 2 ADN4600 TP1 FR4 TEST BACKPLANE 2 50Ω DIFFERENTIAL STRIPLINE TRACES TP2 8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT TRACE LENGTHS = 30'' AC-COUPLED EVALUATION BOARD 50Ω CABLES 2 TP3 HIGH SPEED SAMPLING OSCILLOSCOPE 07061-021 PATTERN GENERATOR 50Ω CABLES 2 INPUT OUTPUT 2 PIN PIN 50ps/DIV 50ps/DIV Figure 16. 4.25 Gbps Output Eye, 30 Inch FR4 Output Channel, PE = 0 (TP3 from Figure 14) 07061-025 50ps/DIV 07061-023 200mV/DIV Figure 17. 3.25 Gbps Output Eye, 30 Inch FR4 Output Channel, PE = Best Setting (TP3 from Figure 14) 200mV/DIV Figure 15. 3.25 Gbps Output Eye, 30 Inch FR4 Output Channel, PE = 0 (TP3 from Figure 14) 07061-024 200mV/DIV 50ps/DIV 07061-022 200mV/DIV Figure 14. Output Pre-Emphasis Test Circuit, FR4 Figure 18. 4.25 Gbps Output Eye, 30 Inch FR4 Output Channel, PE = Best Setting (TP3 from Figure 14) Rev. 0 | Page 10 of 10 ADN4600 Test conditions: VCC = 1.8 V, VEE = 0 V, VTTI = VTTO = VCC, RL = 50 Ω, differential output swing = 800 mV p-p differential, TA = 25°C, unless otherwise noted. 100 80 DETERMINISTIC JITTER (ps) DETERMINISTIC JITTER (ps) 70 60 50 40 30 20 80 60 VCC = 3.3V 40 VCC = 1.8V 20 0 20 60 40 DATA RATE (Hz) 0 1.0 07061-026 0 Figure 19. Deterministic Jitter vs. Data Rate 1.5 2.0 2.5 3.0 INPUT COMMON MODE (V) 3.5 4.0 07061-029 10 Figure 22. Deterministic Jitter vs. Input Common Mode 100 100 80 DETERMINISTIC JITTER (ps) DETERMINISTIC JITTER (ps) 90 70 60 50 40 30 20 80 60 40 20 0.5 1.0 1.5 2.0 DIFFERENTIAL INPUT SWING (V) 2.5 0 1.0 100 80 80 DETERMINISTIC JITTER (ps) 100 60 40 20 0 –60 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 2.0 2.5 VCC (V) 3.0 3.5 4.0 Figure 23. Deterministic Jitter vs. Supply Voltage 100 60 VCC = 1.8V 40 VCC = 3.3V 20 0 1.0 07061-028 DETERMINISTIC JITTER (ps) Figure 20. Deterministic Jitter vs. Input Swing 1.5 Figure 21. Deterministic Jitter vs. Temperature 1.5 2.0 2.5 VTTO (V) 3.0 3.5 4.0 Figure 24. Deterministic Jitter vs. Output Termination Voltage Rev. 0 | Page 11 of 11 07061-031 0 07061-027 0 07061-030 10 ADN4600 450000 100 400000 90 300000 tR/tF (ps) 250000 200000 80 tR/tF 70 150000 100000 60 0 –8 –6 –4 –2 0 2 JITTER (ps) 4 6 8 10 50 –60 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 26. Rise Time/Fall Time vs. Temperature Figure 25. Random Jitter Histogram Rev. 0 | Page 12 of 12 100 07061-033 50000 07061-032 NUMBER OF SAMPLES 350000 ADN4600 THEORY OF OPERATION inversion function, which allows the user to swap the sign of the input signal path to eliminate the need for board-level crossovers in the receiver channel. INTRODUCTION The ADN4600 is an 8 × 8, buffered, asynchronous, 8-channel crosspoint switch that allows fully nonblocking connectivity between its transmitters and receivers. The switch supports multicast and broadcast operation, allowing the ADN4600 to work in redundancy and port-replication applications. Table 5 illustrates some, but not all, possible combinations of input supply voltages. Equalization Settings ADN4600 RECEIVE EQUALIZATION CROSSPOINT ARRAY TRANSMIT PRE-EMPHASIS IP[7:0] OP[7:0] EQ PE ON[7:0] IN[7:0] ADDR[1:0] SCL SDA CONTROL LOGIC 07061-003 RESETB Figure 27. Simplified Functional Block Diagram The ADN4600 offers extensively programmable output levels and pre-emphasis, as well as a squelch function and the ability to fully disable the device. The receivers integrate a programmable, multizero transfer function that has been optimized to compensate either typical backplane or typical cable losses. The ADN4600 provides a balanced, high speed switch core that maintains low channel-to-channel skew and preserves edge rates. The I/O on-chip termination resistors are tied to user-settable supplies to support dc coupling in various logic styles. The ADN4600 supports a wide core supply range; VCC can be set from 1.8 V to 3.3 V. These features together with programmable transmitter output levels allow for several dc- and ac-coupled I/O configurations. RECEIVERS Input Structure and Input Levels VCC SIMPLIFIED RECEIVER INPUT CIRCUIT VTTI RP 52Ω IPx INx RN 52Ω RLN RL R1 750Ω RLP RL Q1 R3 1kΩ Q2 R2 750Ω 07061-004 I1 VEE Figure 28. Simplified Input Structure The ADN4600 receiver inputs incorporate 50 Ω termination resistors, ESD protection, and a multizero transfer function equalizer that can be optimized for backplane and cable operation. Each receive channel also provides a positive/negative (P/N) The ADN4600 receiver incorporates a multizero transfer function with a continuous time equalizer, providing up to 22 dB of high-frequency boost at 2.25 GHz to compensate for up to 30 in. of FR4 at 4.25 Gbps. The ADN4600 also allows independent control of the equalizer transfer function on each channel through the I2C control interface. In the basic mode of operation, the equalizer transfer function allows independent control of the boost in two frequency ranges for optimal matching with the loss shape of the channel (for example, the shape due primarily to skin effect or to dielectric loss). The total equalizer shape space is reduced to two independent frequency response groups—one optimized for cable and the other optimized for FR4 material. The RX EQ bits of the RX[7:0] configuration registers provide eight settings for each frequency response group to ease programming for typical channels. Table 6 summarizes the high-frequency boost for the frequency response grouping optimized for the FR4 material; it lists the basic control settings and the typical length of FR4 trace compensated for by each setting. All eight channels of the ADN4600 use the FR4-optimized frequency response grouping by default. The user can override this default by setting the respective RX LUT select bit high and then selecting the frequency response grouping by setting the RX LUT FR4/CX4 bit high for FR4 and low for cable. Setting the RX EQBY bit of the RX[7:0] configuration registers high sets the equalization to 1.5 dB of boost, which compensates for 0 m to 2 m of CX4 or 0 in. to 10 in. of FR4. In the advanced mode of operation, full control of the equalizer is available through the I2C control interface. The user can specify the boost in the midfrequency range and the boost in the high frequency range independently. This is accomplished by circumventing the frequency response groupings shown in Table 6 by setting the EQ CTL SRC bit (Bit 6 of the RX[7:0] EQ1 control registers) high and writing directly to the equalizer control bits on a per channel basis. Therefore, write values to Bits[5:0] of the RX[7:0] EQ1 control registers and to Bits[5:0] of the RX[7:0] EQ3 control registers for the channel of interest. The bits of these registers are ordered such that Bit 5 is a sign bit, and midlevel boost is centered around 0x00. Setting Bit 5 low and increasing the LSBs decreases the boost, whereas setting Bit 5 high and increasing the LSBs increases the boost. Rev. 0 | Page 13 of 13 ADN4600 Table 5. Common Input Voltage Levels Configuration Low VTTI, AC-Coupled Input Single 1.8 V Supply 3.3 V Core Single 3.3 V Supply VCC (V) 1.8 1.8 3.3 3.3 VTTI (V) 1.6 1.8 1.8 3.3 Table 6. Receive Equalizer Boost vs. Setting RX EQ Bit Settings 0 1 2 3 4 5 6 7 Boost (dB) 3.5 3.9 4.25 4.5 4.75 5.0 5.3 5.5 Typical FR4 Trace Length (Inches) 5 to 10 10 to 15 15 to 20 20 to 25 25 to 30 30 to 35 35 to 40 35 to 40 Table 7. Equalization Control Registers Name RX[7:0] Configuration RX[7:0] EQ1 Control RX[7:0] EQ3 Control RX[7:0] FR4 Control Addr 0xB8, 0xB0, 0xA8, 0xA0, 0x98, 0x90, 0x88, 0x80 0xBB, 0xB3, 0xAB, 0xA3, 0x9B, 0x93, 0x8B, 0x83 0xBC, 0xB4, 0xAC, 0xA4, 0x9C, 0x94, 0x8C, 0x84 0xBD, 0xB5, 0xAD, 0xA5, 0x9D, 0x95, 0x8D, 0x85 Bit 7 Bit 6 RX PNSWAP Bit 5 RX EQBY Bit 4 RX EN Bit 3 Bit 2 RX EQ[2] Bit 1 RX EQ[1] Bit 0 RX EQ[0] Default 0x30 EQ CTL SRC RX EQ1[5] RX EQ1[4] RX EQ1[3] RX EQ1[2] RX EQ1[1] RX EQ1[0] 0x00 RX EQ3[5] RX EQ3[4] RX EQ3[3] RX EQ3[2] RX EQ3[1] RX EQ3[0] 0x00 RX LUT select RX LUT FR4/CX4 0x00 Lane Inversion The receiver P/N inversion feature is a convenience intended to allow the user to implement the equivalent of a board-level crossover in a much smaller area and without additional via impedance discontinuities that degrade the high-frequency integrity of the signal path. The P/N inversion is independent for each of the eight channels and is controlled through the I2C control interface. Warning Using the lane inversion feature to account for signal inversions downstream of the receiver requires additional attention when switching connectivity. Rev. 0 | Page 14 of 14 ADN4600 SWITCH CORE The ADN4600 switch core is a fully nonblocking 8 × 8 array that allows multicast and broadcast configurations. The configuration of the switch core is controlled through the I2C control interface. The control interface receives and stores the desired connection matrix for the eight input and eight output signal pairs. The interface consists of eight rows of double-rank latches, one for each output. The 2-bit data-word stored in these latches indicates to which (if any) of the eight inputs the output will be connected. One output at a time can be preprogrammed by addressing the output and writing the desired connection data into the first rank of latches. This is done by writing to the XPT configuration register (Address 0x40). The output being addressed is written into Bits[2:0], and the input being sent to this output is written into Bits[6:4]. This process can be repeated until each of the desired output changes has been preprogrammed. Bit 3 of the XPT configuration register (Address 0x40) signals whether a broadcast condition is desired. If this bit is set high, the input selected by Bits[6:4] is sent to all outputs. All output connections can then be programmed simultaneously by passing the data from the first rank of latches into the second rank by writing 0x01 to the XPT update register (Address 0x41). This is a selfclearing register and therefore always reads back as 0x00. The output connections always reflect the data programmed into the second rank of latches and do not change until the first rank of data is passed into the second rank by strobing the XPT update register. If necessary for system verification, the data in the first rank of latches can be read back from the control interface. This is done by reading from the XPT Temp[3:0] registers, which show the status of the input data programmed in the first rank of latches for each output. Table 8. Switch Core Control and Status Registers Name XPT Configuration Addr 0x40 XPT Update XPT Status 0 XPT Status 1 XPT Status 2 XPT Status 3 XPT Status 4 XPT Status 5 XPT Status 6 XPT Status 7 0x41 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 Bit 7 Bit 6 IN PORT [2] Bit 5 IN PORT [1] Bit 4 IN PORT [0] Bit 3 Broadcast Bit 2 OUT PORT [2] Bit 1 OUT PORT [1] Default 0x00 OUT0[1] OUT1[1] OUT2[1] OUT3[1] OUT4[1] OUT5[1] OUT6[1] OUT7[1] Bit 0 OUT PORT [0] Update OUT0[0] OUT1[0] OUT2[0] OUT3[0] OUT4[0] OUT5[0] OUT6[0] OUT7[0] OUT0[2] OUT1[2] OUT2[2] OUT3[2] OUT4[2] OUT5[2] OUT6[2] OUT7[2] Bit 2 OUT0[2] OUT2[2] OUT4[2] OUT6[2] Bit 1 OUT0[1] OUT2[1] OUT4[1] OUT6[1] Bit 0 OUT0[0] OUT2[0] OUT4[0] OUT6[0] Default N/A N/A N/A N/A 0x00 N/A N/A N/A N/A N/A N/A N/A N/A Table 9. Switch Core Temporary Registers Name XPT Temp 0 XPT Temp 1 XPT Temp 2 XPT Temp 3 Addr 0x58 0x59 0x5A 0x5B Bit 7 Bit 6 OUT1[2] OUT3[2] OUT5[2] OUT7[2] Bit 5 OUT1[1] OUT3[1] OUT5[1] OUT7[1] Bit 4 OUT1[0] OUT3[0] OUT5[0] OUT7[0] Bit 3 Rev. 0 | Page 15 of 15 ADN4600 Output Structure and Output Levels The ADN4600 transmitter outputs incorporate 50 Ω termination resistors, ESD protection, and output current switch. Each channel provides independent control of both the absolute output level and the pre-emphasis output level. It should be noted that the choice of output level affects the output commonmode level. A 600 mV p-p differential output level with full pre-emphasis range requires an output termination voltage of 2.5 V or greater; therefore, for the VTTO pin, VCC must be equal to or greater than 2.5 V. Pre-Emphasis The output equalization is optimized for less than 2.5 Gbps operation, but can be optimized for higher speed applications up to 4.25 Gbps through the I2C control interface by writing to the TX DATA RATE bit (Bit 4) of the TX[7:0] configuration register, with high representing 4.25 Gbps and low representing 2.5 Gbps. The TX[7:0] CTL SRC bit (Bit 7) in the TX[7:0] Output Level Control 1 register determines whether the preemphasis and output current controls for the channel of interest are selected from the optimized map or directly from the TX[7:0] Output Level Control[1:0] registers (per channel). Setting this bit high selects pre-emphasis control directly from the TX[7:0] Output Level Control[1:0] registers, and setting it low selects pre-emphasis control from the optimized map. TX SIMPLIFIED DIAGRAM The total output amplitude and pre-emphasis setting space is reduced to a single map of basic settings that provides seven settings of output equalization to ease programming for typical channels. The full resolution of seven settings is available through the I2C interface by writing to Bits[2:0] (the TX PE[2:0] bits) of the TX[7:0] configuration registers. Table 10 summarizes the absolute output level, pre-emphasis level, and high frequency boost for each of the control settings and the typical length of FR4 trace compensated for by each setting. VCC ON-CHIP TERMINATION V3 VC RP 52Ω V2 VP ESD VTTO RN 52Ω OPx V1 VN ONx Q1 Q2 Full control of the transmit output levels is available through the I2C control interface. This full control is achieved by writing to the TX[7:0] Output Level Control[1:0] registers for the channel of interest. The supported output levels are shown in Table 12. The TX[7:0] Output Level Control[1:0] registers must be programmed to one of the supported settings listed in this table; other settings are not supported. IDC + TPE IT VEE 07061-006 TRANSMITTERS Figure 29. Simplified Output Structure Table 10. Transmit Pre-Emphasis Boost and Overshoot vs. Setting TX PE 0 1 2 3 4 5 6 Boost (dB) 0 2 3.5 4.9 6 7.4 9.5 Overshoot 0% 25% 50% 75% 100% 133% 200% DC Swing (mV p-p Differential) 800 800 800 800 800 600 400 Typical FR4 Trace Length (Inches) 0 to 5 0 to 5 10 to 15 15 to 20 25 to 30 30 to 35 35 to 40 Table 11. Transmitters Control Registers Name TX[7:0] Configuration TX[7:0] Output Level Control 1 TX[7:0] Output Level Control 0 Addr 0xE0, 0xE8, 0xF0, 0xF8, 0xD8, 0xD0, 0xC8, 0xC0 0xE1, 0xE9, 0xF1, 0xF9, 0xD9, 0xD1, 0xC9, 0xC1 0xE2, 0xEA, 0xF2, 0xFA, 0xDA, 0xD2, 0xCA, 0xC2 Bit 7 Bit 6 Bit 5 TX EN Bit 4 TX data rate TX[7:0] CTL SRC Rev. 0 | Page 16 of 16 Bit 3 Bit 2 TX PE[2] Bit 1 TX PE[1] Bit 0 TX PE[0] Def. 0x20 TX[7:0]_OLEV1[6:0] 0x40 TX[7:0]_OLEV0[6:0] 0x40 ADN4600 Table 12. Output Level Programming VOD (mV) 50 50 50 50 50 50 50 100 100 100 100 100 100 100 150 150 150 150 150 150 150 200 200 200 200 200 200 200 250 250 250 250 250 250 250 300 300 300 300 300 300 300 350 350 350 350 350 350 350 400 400 400 VD Peak (mV) 50 150 250 350 450 550 650 100 200 300 400 500 600 700 150 250 350 450 550 650 750 200 300 400 500 600 700 800 250 350 450 550 650 750 850 300 400 500 600 700 800 900 350 450 550 650 750 850 950 400 500 600 PE (dB) 0.00 9.54 13.98 16.90 19.08 20.83 22.28 0.00 6.02 9.54 12.04 13.98 15.56 16.90 0.00 4.44 7.36 9.54 11.29 12.74 13.98 0.00 3.52 6.02 7.96 9.54 10.88 12.04 0.00 2.92 5.11 6.85 8.30 9.54 10.63 0.00 2.50 4.44 6.02 7.36 8.52 9.54 0.00 2.18 3.93 5.38 6.62 7.71 8.67 0.00 1.94 3.52 ITOT (mA) 2 6 10 14 18 22 26 4 8 12 16 20 24 28 6 10 14 18 22 26 30 8 12 16 20 24 28 32 10 14 18 22 26 30 34 12 16 20 24 28 32 36 14 18 22 26 30 34 38 16 20 24 Tx[7:0] Output Level Control 0 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 Rev. 0 | Page 17 of 17 Tx[7:0] Output Level Control 1 0x81 0x81 0x81 0x81 0x81 0x81 0x81 0x91 0x91 0x91 0x91 0x91 0x91 0x91 0x92 0x92 0x92 0x92 0x92 0x92 0x92 0xA2 0xA2 0xA2 0xA2 0xA2 0xA2 0xA2 0xA3 0xA3 0xA3 0xA3 0xA3 0xA3 0xA3 0xB3 0xB3 0xB3 0xB3 0xB3 0xB3 0xB3 0xB4 0xB4 0xB4 0xB4 0xB4 0xB4 0xB4 0xC4 0xC4 0xC4 ADN4600 VOD (mV) 400 400 400 400 450 450 450 450 450 450 450 500 500 500 500 500 500 500 550 550 550 550 550 550 550 600 600 600 600 600 600 600 650 650 650 650 650 650 700 700 700 700 700 750 750 750 750 800 800 800 850 850 900 VD Peak (mV) 700 800 900 1000 450 550 650 750 850 950 1050 500 600 700 800 900 1000 1100 550 650 750 850 950 1050 1150 600 700 800 900 1000 1100 1200 650 750 850 950 1050 1150 700 800 900 1000 1100 750 850 950 1050 800 900 1000 850 950 900 PE (dB) 4.86 6.02 7.04 7.96 0.00 1.74 3.19 4.44 5.52 6.49 7.36 0.00 1.58 2.92 4.08 5.11 6.02 6.85 0.00 1.45 2.69 3.78 4.75 5.62 6.41 0.00 1.34 2.50 3.52 4.44 5.26 6.02 0.00 1.24 2.33 3.30 4.17 4.96 0.00 1.16 2.18 3.10 3.93 0.00 1.09 2.05 2.92 0.00 1.02 1.94 0.00 0.97 0.00 ITOT (mA) 28 32 36 40 18 22 26 30 34 38 42 20 24 28 32 36 40 44 22 26 30 34 38 42 46 24 28 32 36 40 44 48 26 30 34 38 42 46 28 32 36 40 44 30 34 38 42 32 36 40 34 38 36 Tx[7:0] Output Level Control 0 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x01 0x12 0x23 0x34 0x45 0x56 0x02 0x13 0x24 0x35 0x46 0x03 0x14 0x25 0x36 0x04 0x15 0x26 0x05 0x16 0x06 Rev. 0 | Page 18 of 18 Tx[7:0] Output Level Control 1 0xC4 0xC4 0xC4 0xC4 0xC5 0xC5 0xC5 0xC5 0xC5 0xC5 0xC5 0xD5 0xD5 0xD5 0xD5 0xD5 0xD5 0xD5 0xD6 0xD6 0xD6 0xD6 0xD6 0xD6 0xD6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 0xE6 ADN4600 VTTO High Current Setting and Output Level Shift In low voltage applications, users must pay careful attention to both the differential and common-mode signal levels (see Figure 30 and Table 13). Failure to understand the implications of signal level and choice of ac or dc coupling will almost certainly lead to transistor saturation and poor transmitter performance. dVOCM VH VOD VOCM VL TxHeadroom There is a TxHeadroom register (I C Register Address 0x23) that allows configuration of the individual transmitters for extra headroom at the output for high current applications. The bits in this register are active high (default). There is one bit for each transmitter of the device (see Table 17). Setting this bit high puts the respective transmitter in a configuration for extra headroom, and setting this bit low does not provide extra headroom. VODPP = 2 × VOD VEE 07061-007 2 Figure 30. Simplified Output Voltage Levels Diagram Signal Levels and Common-Mode Shift for DC- and AC-Coupled Outputs Table 13. Signal Levels and Common-Mode Shift for DC- and AC-Coupled Outputs Output Levels and Output Compliance AC-Coupled Transmitter DC-Coupled Transmitter VL VL Min VD VH VH Peak Peak dVOCM VH Peak Peak VL PE dVOCM VH VOD ITOT Peak PE VL VL (V) (V) (V) (mV) (mA) (mV) Boost (dB) (mV) (V) (V) (V) (mV) (V) (V) (V) TxHeadroom = 0 Max Min Min VCC − VL VCC VL (V) (V) (V) TxHeadroom = 1 Max VCC − VL Min (V) VCC (V) VTTO and VCC = 3.3 V 200 8 200 1.00 200 12 300 1.50 200 16 400 2.00 200 20 500 2.50 200 24 600 3.00 200 28 700 3.50 200 32 800 4.00 300 12 300 1.00 300 16 400 1.33 300 20 500 1.67 300 24 600 2.00 300 28 700 2.33 300 32 800 2.67 300 36 900 3.00 400 16 400 1.00 400 20 500 1.25 400 24 600 1.50 400 28 700 1.75 400 32 800 2.00 400 36 900 2.25 400 40 1000 2.50 600 24 600 1.00 600 28 700 1.17 600 32 800 1.33 600 36 900 1.50 600 40 1000 1.67 600 44 1200 1.83 600 48 1400 2.00 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 0.00 3.52 6.02 7.96 9.54 10.88 12.04 0.00 2.50 4.44 6.02 7.36 8.52 9.54 0.00 1.94 3.52 4.86 6.02 7.04 7.96 0.00 1.34 2.50 3.52 4.44 5.26 6.02 200 300 400 500 600 700 800 300 400 500 600 700 800 900 400 500 600 700 800 900 1000 600 700 800 900 1000 1100 1200 3.2 3.1 3 2.9 2.8 2.7 2.6 3.15 3.05 2.95 2.85 2.75 2.65 2.55 3.1 3 2.9 2.8 2.7 2.6 2.5 3 2.9 2.8 2.7 2.6 2.5 2.4 3 2.9 2.8 2.7 2.6 2.5 2.4 2.85 2.75 2.65 2.55 2.45 2.35 2.25 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.4 2.3 2.2 2.1 2 1.9 1.8 3.2 3.15 3.1 3.05 3 2.95 2.9 3.15 3.1 3.05 3 2.95 2.9 2.85 3.1 3.05 3 2.95 2.9 2.85 2.8 3 2.95 2.9 2.85 2.8 2.75 2.7 3 2.85 2.7 2.55 2.4 2.25 2.1 2.85 2.7 2.55 2.4 2.25 2.1 1.95 2.7 2.55 2.4 2.25 2.1 1.95 1.8 2.4 2.25 2.1 1.95 1.8 1.65 1.5 100 150 200 250 300 350 400 150 200 250 300 350 400 450 200 250 300 350 400 450 500 300 350 400 450 500 550 600 3.3 3.25 3.2 3.15 3.1 3.05 3 3.3 3.25 3.2 3.15 3.1 3.05 3 3.3 3.25 3.2 3.15 3.1 3.05 3 3.3 3.25 3.2 3.15 3.1 3.05 3 3.1 3.05 3 2.95 2.9 2.85 2.8 3 2.95 2.9 2.85 2.8 2.75 2.7 2.9 2.85 2.8 2.75 2.7 2.65 2.6 2.7 2.65 2.6 2.55 2.5 2.45 2.4 Rev. 0 | Page 19 of 19 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.1 3 2.9 2.8 2.7 2.6 2.5 3 2.9 2.8 2.7 2.6 2.5 2.4 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.225 2.1 2.225 2.225 2.225 2.225 2.1 2.1 1.8 1.8 1.8 1.8 1.8 1.9 1.9 1.8 1.8 1.8 1.8 1.8 1.9 1.9 1.8 1.8 1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2.2 2.2 2 2 2 2 2 2.2 2.2 2 2 2 2 2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 ADN4600 Output Levels and Output Compliance AC-Coupled Transmitter DC-Coupled Transmitter VL VL Min VD VH VH Peak Peak dVOCM VH Peak Peak VL PE dVOCM VH VOD ITOT Peak PE VL VL (V) (V) (V) (mV) (mA) (mV) Boost (dB) (mV) (V) (V) (V) (mV) (V) (V) (V) TxHeadroom = 0 Max Min Min VCC − VL VCC VL (V) (V) (V) TxHeadroom = 1 Max VCC − VL Min (V) VCC (V) VTTO and VCC = 1.8 V 1 200 8 200 1.00 200 12 300 1.50 200 16 400 2.00 200 20 500 2.50 200 24 600 3.00 300 12 300 1.00 300 16 400 1.33 300 20 500 1.67 300 24 600 2.00 300 28 700 2.33 400 16 400 1.00 400 20 500 1.25 400 24 600 1.50 400 28 700 1.75 400 32 800 2.00 600 24 600 1.00 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 1 0.00 3.52 6.02 7.96 9.54 0.00 2.50 4.44 6.02 7.36 0.00 1.94 3.52 4.86 6.02 0.00 200 300 400 500 600 300 400 500 600 700 400 500 600 700 800 600 1.7 1.6 1.5 1.4 1.3 1.65 1.55 1.45 1.35 1.25 1.6 1.5 1.4 1.3 1.2 1.5 1.5 1.4 1.3 1.2 1.1 1.35 1.25 1.15 1.05 0.95 1.2 1.1 1 0.9 0.8 0.9 1.7 1.65 1.6 1.55 1.5 1.65 1.6 1.55 1.5 1.45 1.6 1.55 1.5 1.45 1.4 1.5 1.5 1.35 1.2 1.05 0.9 1.35 1.2 1.05 0.9 0.75 1.2 1.05 0.9 0.75 0.6 0.9 100 150 200 250 300 150 200 250 300 350 200 250 300 350 400 300 1.8 1.75 1.7 1.65 1.6 1.8 1.75 1.7 1.65 1.6 1.8 1.75 1.7 1.65 1.6 1.8 1.6 1.55 1.5 1.45 1.4 1.5 1.45 1.4 1.35 1.3 1.4 1.35 1.3 1.25 1.2 1.2 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.6 1.5 1.4 1.3 1.2 1.5 1.4 1.3 1.2 1.1 1.4 1.3 1.2 1.1 1 1.2 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.725 0.6 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.9 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 TxHeadroom = 1 is not an option at VTTO and VCC = 1.8 V. Table 14. Symbol Definitions for Output Levels vs. Setting Symbol VOD VODPP dVOCM_DC-COUPLED dVOCM_AC-COUPLED IDC IPE Formula 25 Ω × IDC 25 Ω × IDC × 2 = 2 × VOD 25 Ω × ITX/2 = VODPP/4 + (IPE/2 × 25) 50 Ω × ITX/2 = VODPP/2 + (IPE/2 × 50) VOD/RTERM – Definition Peak differential output voltage Peak-to-peak differential output voltage Output common-mode shift Output common-mode shift Output current that sets output level Output current used for PE ITX VH VL IDC + IPE VTTO − dVOCM + VOD/2 VTTO − dVOCM − VOD/2 Total transmitter output current Maximum single-ended output voltage Minimum single-ended output voltage Rev. 0 | Page 20 of 20 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA ADN4600 Selective Squelch and Disable Each transmitter is equipped with disable and squelch controls. Disable is a full power-down state: all transmitter current, including output current, is reduced to 0 mA and the output pins are pulled up to VTTO, but there is a delay of approximately 1 μs associated with re-enabling the transmitter. The output disable control is accessed through the TX EN bit (Bit 5) of the TX[7:0] configuration registers through the I2C control interface. Squelch simply reduces the output current to submicroamp levels, allowing both output pins to pull up to VTTO through the output termination resistors. The transmitter recovers from squelch in less than 100 ns. The output squelch and the output disable control can both be accessed through the TX[7:0] squelch control registers, with the top nibble representing the squelch control and the bottom nibble representing the output disable for one channel. The channels are disabled or squelched by writing 0s to the corresponding nibbles. The channels are enabled by writing all 1s, which is the default setting. For example, to squelch channel TX0, Register 0xC3 must be set to 0x0F. The entire nibble must be written to all 0s for this functionality. Table 15. Transmitters Squelch Control Registers Name TX[7:0] Squelch Control Addr 0xE3, 0xEB, 0xF3, 0xFB, 0xDB, 0xD3, 0xCB, 0xC3 Bit 7 Bit 6 Bit 5 SQUELCHb[3:0] Bit 4 Rev. 0 | Page 21 of 21 Bit 3 Bit 2 Bit 1 DISABLEb[3:0] Bit 0 Default 0xFF ADN4600 I2C CONTROL INTERFACE 7. Send the data (eight bits) to be written to the register whose address was set in Step 5. This transfer should be MSB first. 8. Wait for the ADN4600 to acknowledge the request. 9. Send a stop condition (that is, while holding the SCL line high, pull the SDA line high) and release control of the bus. 10. Send a repeated start condition (that is, while holding the SCL line high, pull the SDA line low) and continue with Step 2 in this procedure to perform another write. 11. Send a repeated start condition (that is, while holding the SCL line high, pull the SDA line low) and continue with Step 2 of the read procedure (see the I2C Interface Data Transfers: Data Read section) to perform a read from another address. 12. Send a repeated start condition (that is, while holding the SCL line high, pull the SDA line low) and continue with Step 8 of the read procedure (in the I2C Interface Data Transfers: Data Read section) to perform a read from the same address set in Step 5 of the write procedure. Serial Interface General Functionality The ADN4600 register set is controlled through a 2-wire I2C interface. The ADN4600 acts only as an I2C slave device. Therefore, the I2C bus in the system needs to include an I2C master to configure the ADN4600 and other I2C devices that may be on the bus. Data transfers are controlled by the two I2C wires: the SCL input clock pin and the SDA bidirectional data pin. The ADN4600 I2C interface can be run in the standard (100 kHz) and fast (400 kHz) modes. The SDA line only changes value when the SCL pin is low, with two exceptions: the SDA pin is driven low while the SCL pin is high to indicate the beginning or continuation of a transfer, and the SDA line is driven high while the SCL line is high to indicate the end of a transfer. Therefore, it is important to control the SCL clock to toggle only when the SDA line is stable, unless indicating a start, repeated start, or stop condition. I2C Interface Data Transfers: Data Write To write data to the ADN4600 register set, a microcontroller (or any other I2C master) needs to send the appropriate control signals to the ADN4600 slave device. Use the following steps, where the signals are controlled by the I2C master unless otherwise specified. A diagram of the procedure is shown in Figure 31. 2. 3. 4. 5. 6. Send a start condition (that is, while holding the SCL line high, pull the SDA line low). Send the ADN4600 part address (seven bits), whose upper five bits are the static value b10010 and whose lower two bits are controlled by the ADDR1 and ADDR0 input pins. This transfer should be MSB first. Send the write indicator bit (0). Wait for the ADN4600 to acknowledge the request. Send the register address (eight bits) to which data is to be written. This transfer should be MSB first. Wait for the ADN4600 to acknowledge the request. It is important to note that the SDA line only changes when the SCL line is low, except when a start, stop, or repeated start condition is being sent, as is the case in Step 1 and Step 9. SCL GENERAL CASE SDA START FIXED PART ADDR ADDR [1:0] R/W ACK REGISTER ADDR ACK DATA ACK STOP EXAMPLE SDA 1 2 2 3 4 5 2 Figure 31. I C Write Diagram Rev. 0 | Page 22 of 22 6 7 8 9 07061-008 1. In Figure 31, the ADN4600 write process is shown. The SCL signal is shown, along with a general write operation and a specific example. In the example, Data 0x92 is written to Register Address 0x6D of an ADN4600 part with a slave address of 0x4B. The slave address is seven bits wide. The upper five bits of the slave address are internally set to b10010. The lower two bits are controlled by the ADDR[1:0] pins. In this example, the bits controlled by the ADDR[1:0] pins are set to b11. In the figure, the corresponding step number is visible in the circle under the waveform. The SCL line is driven by the I2C master, not by the ADN4600 slave. As for the SDA line, the data in the shaded polygons of Figure 31 is driven by the ADN4600, whereas the data in the nonshaded polygons is driven by the I2C master. The end phase case shown corresponds with Step 9. ADN4600 I2C Interface Data Transfers: Data Read 14. Send a repeated start condition (that is, while holding the SCL line high, pull the SDA line low) and continue with Step 2 of the write procedure (see the I2C Interface Data Transfers: Data Write section) to perform a write. 15. Send a repeated start condition (that is, while holding the SCL line high, pull the SDA line low) and continue with Step 2 of the read procedure to perform a read from a another address. 16. Send a repeated start condition (that is, while holding the SCL line high, pull the SDA line low) and continue with Step 8 of the read procedure to perform a read from the same address. To read data from the ADN4600 register set, a microcontroller (or any other I2C master) needs to send the appropriate control signals to the ADN4600 slave device. Use the following steps, where the signals are controlled by the I2C master unless otherwise specified. A diagram of the procedure is shown in Figure 32. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Send a start condition (that is, while holding the SCL line high, pull the SDA line low). Send the ADN4600 part address (seven bits), whose upper five bits are the static value b10010 and whose lower two bits are controlled by the ADDR1 and ADDR0 input pins. This transfer should be MSB first. Send the write indicator bit (0). Wait for the ADN4600 to acknowledge the request. Send the register address (eight bits) from which data is to be read. This transfer should be MSB first. The register address is kept in the ADN4600 memory until the part is reset or the register address is written over with the same procedure (Step 1 to Step 6 of the write procedure; see the I2C Interface Data Transfers: Data Write section). Wait for the ADN4600 to acknowledge the request. Send a repeated start condition (that is, while holding the SCL line high, pull the SDA line low). Send the ADN4600 part address (seven bits), whose upper five bits are the static value b10010 and whose lower two bits are controlled by the ADDR1 and ADDR0 input pins. This transfer should be MSB first. Send the read indicator bit (1). Wait for the ADN4600 to acknowledge the request. The ADN4600 then serially transfers the data (eight bits) held in the register indicated by the address set in Step 5. Acknowledge the data. Send a stop condition (that is, while holding the SCL line high, pull the SDA line high) and release control of the bus. In Figure 32, the ADN4600 read process is shown. The SCL signal is shown, along with a general read operation and a specific example. In the example, Data 0x49 is read from Register Address 0x6D of an ADN4600 part with a slave address of 0x4B. The part address is seven bits wide. The upper five bits of the slave address are internally set to b10010. The lower two bits are controlled by the ADDR[1:0] pins. In this example, the bits controlled by the ADDR[1:0] pins are set to b11. In Figure 32, the corresponding step number is visible in the circle under the waveform. The SCL line is driven by the I2C master, not by the ADN4600 slave. As for the SDA line, the data in the shaded polygons of Figure 32 is driven by the ADN4600, whereas the data in the nonshaded polygons is driven by the I2C master. The end phase case shown corresponds with Step 13. It is important to note that the SDA line only changes when the SCL line is low, except when a start, stop, or repeated start condition is being sent, as is the case in Step 1, Step 7, and Step 13. In Figure 32, Sr represents a repeated start where the SDA line is brought high before SCL is raised. SDA is then dropped while SCL is still high. SCL GENERAL CASE SDA START FIXED PART ADDR ADDR R/ [1:0] W A REGISTER ADDR A Sr FIXED PART ADDR ADDR R/ [1:0] W A DATA A 11 12 STOP EXAMPLE SDA 1 2 2 3 4 5 6 7 8 8 9 10 NOTES 1. A = ACK. 2. Sr = A REPEATED START WHERE THE SDA LINE IS BROUGHT HIGH BEFORE SCL IS RAISED. Figure 32. I2C Read Diagram Rev. 0 | Page 23 of 23 13 07061-009 1. ADN4600 PCB DESIGN GUIDELINES Transmission Lines Proper RF PCB design techniques must be used for optimal performance. Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections. It is also necessary for the high speed pairs of differential input traces, as well as the high speed pairs of differential output traces, to be matched in length to avoid skew between the differential traces. Power Supply Connections and Ground Planes Use of one low impedance ground plane is recommended. The VEE pins should be soldered directly to the ground plane to reduce series inductance. If the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance. The exposed pad should be connected to the VEE plane using plugged vias so that solder does not leak through the vias during reflow. Use of a 10 μF electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. It is recommended that 0.1 μF and 1 nF ceramic chip capacitors be placed in parallel at each supply pin for high frequency power supply decoupling. When using 0.1 μF and 1 nF ceramic chip capacitors, they should be placed between the IC power supply pins (VCC, VTTI, VTTO) and VEE, as close as possible to the supply pins. Soldering Guidelines for Chip Scale Package The lands on the LFCSP are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central exposed pad. The pad on the printed circuit board should be at least as large as this exposed pad. The user must connect the exposed pad to VEE using plugged vias so that solder does not leak through the vias during reflow. This ensures a solid connection from the exposed pad to VEE. By using adjacent power supply and GND planes, excellent high frequency decoupling can be attained by using close spacing between the planes. This capacitance is given by CPLANE = 0.88εr A/d (pF) where: εr is the dielectric constant of the PCB material. A is the area of the overlap of power and GND planes (cm2). d is the separation between planes (mm). For FR4, εr = 4.4 and 0.25 mm spacing, C ~15 pF/cm2. Rev. 0 | Page 24 of 24 ADN4600 CONTROL REGISTER MAP Table 16. Basic Mode I2C Register Definitions Addr (Hex) 0x00 0x40 0x41 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x80 0x88 0x90 0x98 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 0xF0 0xF8 Name Reset XPT Configuration XPT Update XPT Status 0 XPT Status 1 XPT Status 2 XPT Status 3 XPT Status 4 XPT Status 5 XPT Status 6 XPT Status 7 XPT Temp 0 XPT Temp 1 XPT Temp 2 XPT Temp 3 RX0 Configuration RX1 Configuration RX2 Configuration RX3 Configuration RX4 Configuration RX5 Configuration RX6 Configuration RX7 Configuration TX0 Configuration TX1 Configuration TX2 Configuration TX3 Configuration TX7 Configuration TX6 Configuration TX5 Configuration TX4 Configuration Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IN PORT[2] IN PORT[1] IN PORT[0] Broadcast OUT PORT[2] OUT PORT[1] Bit 0 Reset OUT PORT[0] OUT0[1] OUT1[1] OUT2[1] OUT3[1] OUT4[1] OUT5[1] OUT6[1] OUT7[1] OUT0[1] OUT2[1] OUT4[1] OUT6[1] RX EQ[1] Update OUT0[0] OUT1[0] OUT2[0] OUT3[0] OUT4[0] OUT5[0] OUT6[0] OUT7[0] OUT0[0] OUT2[0] OUT4[0] OUT6[0] RX EQ[0] 0x30 OUT1[2] OUT3[2] OUT5[2] OUT7[2] RX PNSWAP RX PNSWAP RX PNSWAP RX PNSWAP RX PNSWAP RX PNSWAP RX PNSWAP RX PNSWAP Default 0x00 0x00 OUT1[1] OUT3[1] OUT5[1] OUT7[1] RX EQBY OUT1[0] OUT3[0] OUT5[0] OUT7[0] RX EN OUT0[2] OUT1[2] OUT2[2] OUT3[2] OUT4[2] OUT5[2] OUT6[2] OUT7[2] OUT0[2] OUT2[2] OUT4[2] OUT6[2] RX EQ[2] RX EQBY RX EN RX EQ[2] RX EQ[1] RX EQ[0] 0x30 RX EQBY RX EN RX EQ[2] RX EQ[1] RX EQ[0] 0x30 RX EQBY RX EN RX EQ[2] RX EQ[1] RX EQ[0] 0x30 RX EQBY RX EN RX EQ[2] RX EQ[1] RX EQ[0] 0x30 RX EQBY RX EN RX EQ[2] RX EQ[1] RX EQ[0] 0x30 RX EQBY RX EN RX EQ[2] RX EQ[1] RX EQ[0] 0x30 RX EQBY RX EN RX EQ[2] RX EQ[1] RX EQ[0] 0x30 TX EN TX data rate TX PE[2] TX PE[1] TX PE[0] 0x20 TX EN TX data rate TX PE[2] TX PE[1] TX PE[0] 0x20 TX EN TX data rate TX PE[2] TX PE[1] TX PE[0] 0x20 TX EN TX data rate TX PE[2] TX PE[1] TX PE[0] 0x20 TX EN TX data rate TX PE[2] TX PE[1] TX PE[0] 0x20 TX EN TX data rate TX PE[2] TX PE[1] TX PE[0] 0x20 TX EN TX data rate TX PE[2] TX PE[1] TX PE[0] 0x20 TX EN TX data rate TX PE[2] TX PE[1] TX PE[0] 0x20 Rev. 0 | Page 25 of 25 ADN4600 Table 17. Advanced Mode I2C Register Definitions Addr (Hex) 0x23 0x83 0x84 0x85 0x8B 0x8C 0x8D 0x93 0x94 0x95 0x9B 0x9C 0x9D 0xA3 0xA4 0xA5 0xAB 0xAC 0xAD 0xB3 0xB4 0xB5 0xBB 0xBC 0xBD 0xC1 0xC2 0xC3 0xC9 0xCA 0xCB Name TxHeadroom RX0 EQ1 Control RX0 EQ3 Control RX0 FR4 Control RX1 EQ1 Control RX1 EQ3 Control RX1 FR4 Control RX2 EQ1 Control RX2 EQ3 Control RX2 FR4 Control RX3 EQ1 Control RX3 EQ3 Control RX3 FR4 Control RX4 EQ1 Control RX4 EQ3 Control RX4 FR4 Control RX5 EQ1 Control RX5 EQ3 Control RX5 FR4 Control RX6 EQ1 Control RX6 EQ3 Control RX6 FR4 Control RX7 EQ1 Control RX7 EQ3 Control RX7 FR4 Control TX0 Output Level Control 1 TX0 Output Level Control 0 TX0 Squelch Control TX1 Output Level Control 1 TX1 Output Level Control 0 TX1 Squelch Control Bit 7 TxH_B3 Bit 6 TxH_B2 EQ CTL SRC EQ CTL SRC EQ CTL SRC EQ CTL SRC EQ CTL SRC EQ CTL SRC EQ CTL SRC EQ CTL SRC Bit 5 TxH_B1 RX EQ1[5] Bit 4 TxH_B0 RX EQ1[4] Bit 3 TxH_A3 RX EQ1[3] Bit 2 TxH_A2 RX EQ1[2] Bit 1 TxH_A1 RX EQ1[1] Bit 0 TxH_A0 RX EQ1[0] Default 0x00 0x00 RX EQ3[5] RX EQ3[4] RX EQ3[3] RX EQ3[2] RX EQ3[1] RX EQ3[0] 0x00 RX LUT FR4/CX4 RX EQ1[0] 0x00 0x00 RX EQ1[5] RX EQ1[4] RX EQ1[3] RX EQ1[2] RX LUT select RX EQ1[1] RX EQ3[5] RX EQ3[4] RX EQ3[3] RX EQ3[2] RX EQ3[1] RX EQ3[0] 0x00 RX LUT FR4/CX4 RX EQ1[0] 0x00 0x00 RX EQ1[5] RX EQ1[4] RX EQ1[3] RX EQ1[2] RX LUT select RX EQ1[1] RX EQ3[5] RX EQ3[4] RX EQ3[3] RX EQ3[2] RX EQ3[1] RX EQ3[0] 0x00 RX LUT FR4/CX4 RX EQ1[0] 0x00 0x00 RX EQ1[5] RX EQ1[4] RX EQ1[3] RX EQ1[2] RX LUT select RX EQ1[1] RX EQ3[5] RX EQ3[4] RX EQ3[3] RX EQ3[2] RX EQ3[1] RX EQ3[0] 0x00 RX LUT FR4/CX4 RX EQ1[0] 0x00 0x00 RX EQ1[5] RX EQ1[4] RX EQ1[3] RX EQ1[2] RX LUT select RX EQ1[1] RX EQ3[5] RX EQ3[4] RX EQ3[3] RX EQ3[2] RX EQ3[1] RX EQ3[0] 0x00 RX LUT FR4/CX4 RX EQ1[0] 0x00 0x00 RX EQ1[5] RX EQ1[4] RX EQ1[3] RX EQ1[2] RX LUT select RX EQ1[1] RX EQ3[5] RX EQ3[4] RX EQ3[3] RX EQ3[2] RX EQ3[1] RX EQ3[0] 0x00 RX LUT FR4/CX4 RX EQ1[0] 0x00 0x00 RX EQ1[5] RX EQ1[4] RX EQ1[3] RX EQ1[2] RX LUT select RX EQ1[1] RX EQ3[5] RX EQ3[4] RX EQ3[3] RX EQ3[2] RX EQ3[1] RX EQ3[0] 0x00 RX LUT FR4/CX4 RX EQ1[0] 0x00 0x00 RX EQ1[5] RX EQ1[4] RX EQ1[3] RX EQ1[2] RX LUT select RX EQ1[1] RX EQ3[5] RX EQ3[4] RX EQ3[3] RX EQ3[2] RX EQ3[1] RX EQ3[0] 0x00 RX LUT select RX LUT FR4/CX4 0x00 TX0 CTL SRC TX0_OLEV1[6:0] 0x40 TX0_OLEV0[6:0] 0x40 SQUELCHb[3:0] TX1 CTL SRC DISABLEb[3:0] 0xFF TX1_OLEV1[6:0] 0x40 TX1_OLEV0[6:0] 0x40 SQUELCHb[3:0] DISABLEb[3:0] Rev. 0 | Page 26 of 26 0xFF ADN4600 Addr (Hex) 0xD1 0xD2 0xD3 0xD9 0xDA 0xDB 0xE1 0xE2 0xE3 0xE9 0xEA 0xEB 0xF1 0xF2 0xF3 0xF9 0xFA 0xFB Name TX2 Output Level Control 1 TX2 Output Level Control 0 TX2 Squelch Control TX3 Output Level Control 1 TX3 Output Level Control 0 TX3 Squelch Control TX7 Output Level Control 1 TX7 Output Level Control 0 TX7 Squelch Control TX6 Output Level Control 1 TX6 Output Level Control 0 TX6 Squelch Control TX5 Output Level Control 1 TX5 Output Level Control 0 TX5 Squelch Control TX4 Output Level Control 1 TX4 Output Level Control 0 TX4 Squelch Control Bit 7 TX2 CTL SRC Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TX2_OLEV1[6:0] Bit 1 TX2_OLEV0[6:0] SQUELCHb[3:0] TX3 CTL SRC 0x40 TX3_OLEV0[6:0] 0x40 DISABLEb[3:0] 0x40 TX7_OLEV0[6:0] 0x40 DISABLEb[3:0] 0xFF TX6_OLEV1[6:0] 0x40 TX6_OLEV0[6:0] 0x40 DISABLEb[3:0] 0xFF TX5_OLEV1[6:0] 0x40 TX5_OLEV0[6:0] 0x40 SQUELCHb[3:0] TX4 CTL SRC 0xFF TX7_OLEV1[6:0] SQUELCHb[3:0] TX5 CTL SRC 0xFF TX3_OLEV1[6:0] SQUELCHb[3:0] TX6 CTL SRC Default 0x40 0x40 DISABLEb[3:0] SQUELCHb[3:0] TX7 CTL SRC Bit 0 DISABLEb[3:0] 0xFF TX4_OLEV1[6:0] 0x40 TX4_OLEV0[6:0] 0x40 SQUELCHb[3:0] DISABLEb[3:0] Rev. 0 | Page 27 of 27 0xFF ADN4600 PACKAGE OUTLINE DIMENSIONS 9.00 BSC SQ 0.60 MAX 8.75 BSC SQ TOP VIEW (BOTTOM VIEW) 17 16 7.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 EXCEPT FOR EXPOSED PAD DIMENSION 063006-B SEATING PLANE 33 32 PIN 1 INDICATOR *6.15 6.00 SQ 5.85 EXPOSED PAD 0.50 0.40 0.30 12° MAX 64 1 49 48 PIN 1 INDICATOR 1.00 0.85 0.80 0.30 0.25 0.18 0.60 MAX Figure 33. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-2) Dimensions shown in millimeters ORDERING GUIDE Model ADN4600ACPZ 1 AD4600ACPZ-R71 ADN4600-EVALZ1 1 Temperature Range −40°C to +85°C −40oC to +85oC Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07061-0-6/08(0) Rev. 0 | Page 28 of 28 Package Option CP-64-2 CP-64-2