MC74HC589A 8−Bit Serial or Parallel−Input/Serial−Output Shift Register with 3−State Output http://onsemi.com High−Performance Silicon−Gate CMOS The MC74HC589A device consists of an 8−bit storage latch which feeds parallel data to an 8−bit shift register. Data can also be loaded serially (see the Function Table). The shift register output, QH, is a 3−state output, allowing this device to be used in bus−oriented systems. The HC589A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs. MARKING DIAGRAMS 16 PDIP−16 N SUFFIX CASE 648 16 1 1 16 Features • • • • • • • • MC74HC589AN AWLYYWW Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 526 FETs or 131.5 Equivalent Gates Pb−Free Packages are Available* SOIC−16 D SUFFIX CASE 751B 16 1 HC589A AWLYWW 1 16 16 1 TSSOP−16 DT SUFFIX CASE 948F HC 589A ALYW 1 16 SOEIAJ−16 CASE 966 16 74HC589A ALYW 1 1 A L, WL Y, YY W, WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005 February, 2005 − Rev. 3 1 Publication Order Number: MC74HC589A/D MC74HC589A SERIAL DATA INPUT SA A 14 15 B PARALLEL DATA INPUTS C 1 16 VCC 2 C 2 15 A D 3 14 E 4 13 F 5 12 SA SERIAL SHIFT/ PARALLEL LOAD LATCH CLOCK G 6 11 SHIFT CLOCK H 7 10 OUTPUT ENABLE GND 8 9 VCC = PIN 16 GND = PIN 8 4 E DATA LATCH 5 F SHIFT REGISTER 6 G 7 H SHIFT CLOCK B 3 D LATCH CLOCK 1 9 QH 12 SERIAL DATA OUTPUT QH Figure 2. Pin Assignment 11 SERIAL SHIFT/ 13 PARALLEL LOAD 10 OUTPUT ENABLE Figure 1. Logic Diagram ORDERING INFORMATION Package Shipping† MC74HC589AN PDIP−16 2000 / Box MC74HC589ANG PDIP−16 (Pb−Free) 2000 / Box MC74HC589AD SOIC−16 48 Units / Rail MC74HC589ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HC589ADR2 SOIC−16 2500 Tape & Reel MC74HC589ADR2G SOIC−16 (Pb−Free) 2500 Tape & Reel MC74HC589ADTR2 TSSOP−16* 2500 Tape & Reel MC74HC589AFEL SOEIAJ−16 2000 Tape & Reel MC74HC589AFELG SOEIAJ−16 (Pb−Free) 2000 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 MC74HC589A MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) 0.5 to 7.0 V Vin DC Input Voltage (Referenced to GND) 0.5 VCC 0.5 V Vout DC Output Voltage (Referenced to GND) 0.5 VCC 0.5 V Iin DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 35 mA ICC DC Supply Current, VCC and GND Pins 75 mA IGND DC Ground Current per Ground Pin 75 mA TSTG Storage Temperature Range 65 to 150 C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 C TJ Junction Temperature Under Bias 150 C JA Thermal Resistance PDIP SOIC TSSOP 78 112 148 C/W PD Power Dissipation in Still Air at 85C PDIP SOIC TSSOP 750 500 450 mW MSL Moisture Sensitivity FR Flammability Rating VESD ESD Withstand Voltage ILatchup Latchup Performance Level 1 Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) 4000 200 1000 V Above VCC and Below GND at 85C (Note 4) 300 mA Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22−A114−A. 2. Tested to EIA/JESD22−A115−A. 3. Tested to JESD22−C101−A. 4. Tested to EIA/JESD78. 5. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types 55 125 C tr, tf Input Rise and Fall Time 0 0 0 1000 800 500 400 ns VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V (Figure 3) 6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level. http://onsemi.com 3 MC74HC589A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND, Note 7) VCC Guaranteed Limit ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ Symbol Parameter Test Conditions V 55C to 25C 85C 125C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC 0.1 V |Iout| 20 A 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC 0.1 V |Iout| 20 A 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| 20 A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 |Iout| 2.4 mA |Iout| 6.0 mA |Iout| 7.8 mA Vin = VIH or VIL VOL Maximum Low−Level Output Voltage Vin = VIH |Iout| 20 A |Iout| 2.4 mA |Iout| 6.0 mA |Iout| 7.8 mA Vin = VIH or VIL V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 A IOZ Maximum Three−State Leakage Current Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 0.5 5.0 10 A ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 A 6.0 4 40 160 A 7. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D). http://onsemi.com 4 MC74HC589A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns, Notes 8 and 9) VCC Guaranteed Limit ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ Symbol Parameter V 55C to 25C 85C 125C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 4 and10) 2.0 3.0 4.5 6.0 6.0 15 30 35 4.8 10 24 28 4.0 8.0 20 24 MHz tPLH, tPHL Maximum Propagation Delay, Latch Clock to QH (Figures 3 and 10) 2.0 3.0 4.5 6.0 175 100 40 30 225 110 50 40 275 125 60 50 ns tPLH, tPHL Maximum Propagation Delay, Shift Clock to QH (Figures 4 and 10) 2.0 3.0 4.5 6.0 160 90 30 25 200 130 40 30 240 160 48 40 ns tPLH, tPHL Maximum Propagation Delay, Serial Shift/Parallel Load to QH (Figures 6 and 10) 2.0 3.0 4.5 6.0 160 90 30 25 200 130 40 30 240 160 48 40 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to QH (Figures 5 and 11) 2.0 3.0 4.5 6.0 150 80 27 23 170 100 30 25 200 130 40 30 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to QH (Figures 5 and 11) 2.0 3.0 4.5 6.0 150 80 27 23 170 100 30 25 200 130 40 30 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 3 and 10) 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 31 18 15 ns Cin Maximum Input Capacitance − 10 10 10 pF Cout Maximum Three−State Output Capacitance (Output in High−Impedance State) − 15 15 15 pF 8. For propagation delays with loads other than 50 pF, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). 9. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (per Package)* 50 pF *Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). http://onsemi.com 5 MC74HC589A TIMING REQUIREMENTS (Input tr = tf = 6 ns, Note 10) VCC Guaranteed Limit ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎ Symbol Parameter V 55C to 25C 85C 125C Unit tsu Minimum Setup Time, A−H to Latch Clock (Figure 7) 2.0 3.0 4.5 6.0 100 40 20 17 125 50 25 21 150 60 30 26 ns tsu Minimum Setup Time, Serial Data Input SA to Shift Clock (Figure 8) 2.0 3.0 4.5 6.0 100 40 20 17 125 50 25 21 150 60 30 26 ns tsu Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock (Figure 9) 2.0 3.0 4.5 6.0 100 40 20 17 125 50 25 21 150 60 30 26 ns th Minimum Hold Time, Latch Clock to A−H (Figure 7) 2.0 3.0 4.5 6.0 25 10 5 5 30 12 6 6 40 15 8 7 ns th Minimum Hold Time, Shift Clock to Serial Data Input SA (Figure 8) 2.0 3.0 4.5 6.0 5 5 5 5 5 5 5 5 5 5 5 5 ns tw Minimum Pulse Width, Shift Clock (Figure 4) 2.0 3.0 4.5 6.0 75 40 15 13 95 50 19 16 110 60 23 19 ns tw Minimum Pulse Width, Latch Clock (Figure 3) 2.0 3.0 4.5 6.0 80 40 16 14 100 50 20 17 120 60 24 20 ns tw Minimum Pulse Width, Serial Shift/Parallel Load (Figure 6) 2.0 3.0 4.5 6.0 80 40 16 14 100 50 20 17 120 60 24 20 ns tr, tf Maximum Input Rise and Fall Times (Figure 3) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns 10. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D). http://onsemi.com 6 MC74HC589A FUNCTION TABLE Inputs Resulting Function Output Enable Serial Shift/ Parallel Load Latch Clock Shift Clock Serial Input SA Parallel Inputs A−H Data Latch Contents Shift Register Contents Output QH Force Output into High Impedance State H X X X X X X X Z Load Parallel Data into Data Latch L H L, H, X a−h a−h U U Transfer Latch Contents to Shift Register L L L, H, X X X U LRN → SRN LRH Contents of Input Latch and Shift Register are Unchanged L H L, H, L, H, X X U U U Load Parallel Data into Data Latch and Shift Register L L X X a−h a−h a−h h Shift Serial Data into Shift Register L H D X * SRA = D, SRN → SRN+1 SRG → SRH Load Parallel Data in Data Latch and Shift Serial Data into Shift Register L H D a−h a−h SRA = D, SRN → SRN+1 SRG → SRH Operation LR SR a−h D = = = = X latch register contents shift register contents data at parallel data inputs A−H data (L, H) at serial data input SA U = remains unchanged X = don’t care Z = high impedance * = depends on Latch Clock input Switching Waveforms tr LATCH CLOCK tf 1/fmax VCC 90% 50% 10% tw tw GND tPLH SHIFT CLOCK tPLH QH tTLH Figure 4. (Serial Shift/Parallel Load = H) VCC tw GND tPLZ tPHZ 50% SERIAL SHIFT/ PARALLEL LOAD HIGH IMPEDANCE 50% tPZH QH 50% 50% tPZL QH tPHL tTHL Figure 3. (Serial Shift/Parallel Load = L) OUTPUT ENABLE GND tPHL 90% 50% 10% QH VCC 50% 10% VOL 90% VOH VCC 50% 50% GND tPLH QH tPHL 50% HIGH IMPEDANCE Figure 5. Figure 6. http://onsemi.com 7 MC74HC589A Switching Waveforms DATA VALID A−H DATA VALID VCC SA 50% GND tsu LATCH CLOCK VCC 50% GND th tsu SHIFT CLOCK 50% th 50% Figure 7. Figure 8. VCC SERIAL SHIFT/ PARALLEL LOAD 50% GND tsu SHIFT CLOCK 50% Figure 9. TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST 1 k OUTPUT DEVICE UNDER TEST CL * CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 11. Test Circuit Figure 10. Test Circuit Pin Descriptions Data Inputs data in stage H is shifted out QH, being replaced by the data previously stored in stage G. A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7) Latch Clock (Pin 12) Parallel data inputs. Data on these inputs are stored in the data latch on the rising edge of the Latch Clock input. Data latch clock. A low−to−high transition on this input loads the parallel data on inputs A−H into the data latch. SA (Pin 14) Output Enable (Pin 10) Serial data input. Data on this input is shifted into the shift register on the rising edge of the Shift Clock input if Serial Shift/Parallel Load is high. Data on this input is ignored when Serial Shift/Parallel Load is low. Active−low output enable A high level applied to this pin forces the QH output into the high impedance state. A low level enables the output. This control does not affect the state of the input latch or the shift register. Control Inputs Serial Shift/Parallel Load (Pin 13) Output Shift register mode control. When a high level is applied to this pin, the shift register is allowed to serially shift data. When a low level is applied to this pin, the shift register accepts parallel data from the data latch. QH (Pin 9) Serial data output. This pin is the output from the last stage of the shift register. This is a 3−state output. Shift Clock (Pin 11) Serial shift clock. A low−to−high transition on this input shifts data on the serial data input into the shift register and http://onsemi.com 8 MC74HC589A SHIFT CLOCK SERIAL DATA INPUT, SA OUTPUT ENABLE SERIAL SHIFT/ PARALLEL LOAD LATCH CLOCK PARALLEL DATA INPUTS A L H L L B L L L L C L H L L D L L L L E L H L H F L H L H G L L L L H L H H H QH ÉÉÉÉ HIGH IMPEDANCE H SERIAL SHIFT LOAD RESET LATCH LATCH AND SHIFT REGISTER L H H L H L H LOAD LATCH Figure 12. Timing Diagram http://onsemi.com 9 H L L L H SERIAL SHIFT SERIAL SHIFT PARALLEL LOAD SHIFT REGISTER L PARALLEL LOAD SHIFT REGISTER PARALLEL LOAD, LATCH, AND SHIFT REGISTER L H H SERIAL SHIFT MC74HC589A OUTPUT 10 ENABLE 14 SA SHIFT 11 CLOCK SERIAL SHIFT/ 13 PARALLEL LOAD 12 LATCH CLOCK 15 A STAGE A D Q C S D C Q R STAGE B B PARALLEL DATA INPUTS C D E F G 1 D Q C 2 S D C Q R STAGE C* 3 STAGE D* 4 STAGE E* 5 STAGE F* 6 STAGE G* STAGE H H 7 D Q C VCC S D C Q R *Stages C thru G (not shown in detail) are identical to stages A and B above. Figure 13. Logic Detail http://onsemi.com 10 9 QH MC74HC589A PACKAGE DIMENSIONS PDIP−16 N SUFFIX CASE 648−08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. −A− 16 9 1 8 B F C L DIM A B C D F G H J K L M S S SEATING PLANE −T− K H G D M J 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 SOIC−16 D SUFFIX CASE 751B−05 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 1 8 −B− P 8 PL 0.25 (0.010) M B S G R K F X 45 C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 11 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 MC74HC589A PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE A 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÇÇÇ ÉÉ ÇÇÇ ÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A −V− M N F DETAIL E C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G http://onsemi.com 12 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE N−N DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC −W− M 0 8 0 8 MC74HC589A PACKAGE DIMENSIONS SOEIAJ−16 CASE 966−01 ISSUE O 16 LE 9 Q1 M E HE 1 8 L DETAIL P Z D e VIEW P A DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) c M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) http://onsemi.com 13 MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 −−− 0.78 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 −−− 0.031 MC74HC589A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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