LINER LTC6255 280mhz, 2.9ns comparator family with rail-to-rail inputs and cmos output Datasheet

LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
280MHz, 2.9ns Comparator
Family with Rail-to-Rail Inputs
and CMOS Outputs
Description
Features
Very High Toggle Rate: 280MHz
nn Low Propagation Delay: 2.9ns
nn Rail-to-Rail Inputs Extend Beyond Both Rails
nn Output Current Capability: ±22mA
nn Low Quiescent Current: 4.5mA
nn Features within the LTC6752 Family:
nn 2.45V to 5.25V Input Supply and 1.71V to 3.5V
Output Supply (Separate Supply Option)
nn 2.45V to 3.5V Supply (Single Supply Option)
nn Shutdown Pin for Reduced Power
nn Output Latch and Adjustable Hysteresis
nn Complementary Outputs
nn Packages: TSOT-23, SC70, MSOP, 3mm × 3mm QFN
nn Direct Replacement for ADCMP60X Family
nn Fully Specified from –55°C to 125°C
nn
Applications
Clock and Data Recovery
Level Shifting
nn High Speed Data Acquisition Systems
nn Window Comparators
nn High Speed Line Receivers
nn Fast Crystal Oscillators
nn Time of Flight Measurements
nn Time Domain Reflectometry
nn
nn
The LTC®6752 is a family of very high speed comparators
capable of supporting toggle rates up to 280MHz. These
comparators exhibit low propagation delays of 2.9ns, and
fast rise/fall times of 1.2ns. There are a total of 5 members
in the LTC6752 family, with different options for separate
input and output supplies, shutdown, output latch, adjustable hysteresis, complementary outputs, and package.
The LTC6752 comparators have rail-to-rail inputs that
operate from 2.45V, up to 3.5V or 5.25V, depending on
the option. The outputs are CMOS and the separate supply
options can operate down to 1.71V, allowing for directly
interfacing to 1.8V logic devices.
The low propagation delay of only 2.9ns combined with
low dispersion of only 1.8ns (10mV to 125mV overdrive
variation) makes these comparators an excellent choice
for critical timing applications. Similarly, the fast toggle
rate and the low jitter of 4.5ps RMS (100mVP-P, 100MHz
input) make the LTC6752 family ideally suited for high
frequency line driver and clock recovery circuits.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Analog
Devices, Inc. All other trademarks are the property of their respective owners.
Typical Application
High Speed Differential Line Receiver with Excellent
Common Mode Rejection
SMALL DIFFERENTIAL SIGNAL WITH
LARGE COMMON MODE COMPONENT
Q
–IN +IN
500mV/DIV
VCC = 5V
+IN
+
–IN
–
VDD = 2.7V
Q
LTC6752-2
VEE
50ns/DIV
6752 T01a
6752 T01a
6752fc
For more information www.linear.com/LTC6752
1
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Absolute Maximum Ratings
(Note 1)
Total Supply Voltage (VCC to VEE)
(LTC6752-2/LTC6752-3/LTC6752-4).....................5.5V
(LTC6752/LTC6752-1)...........................................3.6V
Total Supply Voltage (VDD to VEE).............................3.6V
Input Current (+IN, –IN, SHDN, LE/HYST)
(Note 2)................................................................. ±10mA
Output Current (Q, Q) (Note 3)............................. ±50mA
Specified Temperature Range (Note 4)
LTC6752I..............................................–40°C to 85°C
LTC6752H........................................... –40°C to 125°C
LTC6752MP........................................ –55°C to 125°C
Storage Temperature Range................... –65°C to 125°C
Maximum Junction Temperature (Note 3)............. 150°C
Lead Temperature Soldering (10s)......................... 300°C
Pin Configuration
LTC6752
LTC6752-1
Q1
Q1
5 VCC
VEE 2
+IN 3
4 –IN
VEE 2
5 LE/HYST
+IN 3
4 –IN
13
VEE
VCC 2
4
5
6
+IN
NC
–IN
VEE 3
VDD
Q
VEE
LE/HYST
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 163°C/W (NOTE 3)
12 11 10
VDD 1
8
7
6
5
1
2
3
4
Q
NC
VCC
+IN
–IN
SHDN
LTC6752-4
TOP VIEW
Q
TOP VIEW
6 VCC
SC6 PACKAGE
6-LEAD PLASTIC SC70
WITH LATCHING/ADJUSTABLE HYSTERESIS
TJMAX = 150°C, θJA = 270°C/W (NOTE 3)
S5 PACKAGE
5-LEAD PLASTIC TSOT-23
TJMAX = 150°C, JA = 215°C/W (NOTE 3)
LTC6752-3
LTC6752-2
TOP VIEW
TOP VIEW
TOP VIEW
9
VEE
Q1
6 VCC
8
LE/HYST
VEE 2
5 VDD
7
SHDN
+IN 3
4 –IN
SC6 PACKAGE
6-LEAD PLASTIC SC70
WITH SEPARATE INPUT/OUTPUT SUPPLIES
TJMAX = 150°C, θJA = 270°C/W (NOTE 3)
UD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC QFN
TJMAX = 150°C, θJA = 68°C/W (NOTE 3)
EXPOSED PAD (PIN 13) IS VEE, MUST BE SOLDERED TO PCB
Table 1. Features and Part Numbers
PART#
LATCHING/ADJUSTABLE
HYSTERESIS
SEPARATE INPUT/
OUTPUT SUPPLIES
SHUTDOWN
COMPLEMENTARY
OUTPUTS
LTC6752
TSOT-23-5
SC70-6
LTC6752-1
l
LTC6752-2
l
l
l
LTC6752-3
l
l
l
LTC6752-4
PACKAGE OFFERING
l
MS8
l
3mm × 3mm QFN
SC70-6
6752fc
2
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Order Information
http://www.linear.com/product/LTC6752#orderinfo
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6752IS5#TRMPBF
LTC6752IS5#TRPBF
LTGKT
–40°C to 85°C
5-Lead Plastic TSOT-23
LTC6752HS5#TRMPBF
LTC6752HS5#TRPBF
LTGKT
5-Lead Plastic TSOT-23
–40°C to 125°C
LTC6752MPS5#TRMPBF
LTC6752MPS5#TRPBF
LTGKT
5-Lead Plastic TSOT-23
–55°C to 125°C
LTC6752ISC6-1#TRMPBF
LTC6752ISC6-1#TRPBF
LGQK
6-Lead Plastic SC-70
–40°C to 85°C
LTC6752HSC6-1#TRMPBF
LTC6752HSC6-1#TRPBF
LGQK
6-Lead Plastic SC-70
–40°C to 125°C
LTC6752ISC6-4#TRMPBF
LTC6752ISC6-4#TRPBF
LGQM
6-Lead Plastic SC-70
–40°C to 85°C
LTC6752HSC6-4#TRMPBF
LTC6752HSC6-4#TRPBF
LGQM
6-Lead Plastic SC-70
–40°C to 125°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
LEAD FREE FINISH
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6752IMS8-2#PBF
LTC6752IMS8-2#TRPBF
LTGKW
8-Lead Plastic MSOP
–40°C to 85°C
LTC6752HMS8-2#PBF
LTC6752HMS8-2#TRPBF
LTGKW
8-Lead Plastic MSOP
–40°C to 125°C
LTC6752IUD-3#PBF
LTC6752IUD-3#TRPBF
LGKV
12-Lead Plastic QFN (3mm × 3mm)
–40°C to 85°C
LTC6752HUD-3#PBF
LTC6752HUD-3#TRPBF
LGKV
12-Lead Plastic QFN (3mm × 3mm)
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Electrical Characteristics
(VCC = 2.5V, VDD = 2.5V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VCC - VEE
Supply Voltage (Note 5)
l
LTC6752/LTC6752-1 (Total Supply)
LTC6752-2/LTC6752-3/LTC6752-4 (Input Stage) l
2.45
2.45
VDD - VEE
Output Stage Supply Voltage (Note 5)
LTC6752-2/LTC6752-3/LTC6752-4
1.71
VCMR
Input Voltage Range (Note 7)
VOS
Input Offset Voltage (Note 6)
l
TYP
l VEE – 0.2
l
–5.5
–8.5
±1.2
MAX
UNITS
3.5
5.25
V
V
3.5
V
VCC + 0.1
V
5.5
8.5
mV
mV
TCVOS
Input Offset Voltage Drift
VHYST
Input Hysteresis Voltage (Note 6)
CIN
Input Capacitance
1.1
pF
RDM
Differential Mode Resistance
57
kΩ
RCM
Common Mode Resistance
6.4
MΩ
IB
Input Bias Current
–1.35
µA
µA
l
LE/HYST Pin Floating
VCM = VEE + 0.3V
l
–3.8
–4
VCM = VCC – 0.3V
18
µV/°C
5
mV
0.3
1.25
2.1
µA
µA
0.75
µA
l
IOS
Input Offset Current
CMRR_
LVCM
Common Mode Input Range, Low VCM
Region
CMRR_FR
Common Mode Rejection Ratio (Measured at VCM = VEE – 0.2V to VCC + 0.1V
Extreme Ends of VCMR)
l
–0.75
±0.1
51
46
69
l
dB
dB
50
45.5
65
l
dB
dB
VCM = VEE – 0.2V to VCC – 1.5V
6752fc
For more information www.linear.com/LTC6752
3
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Electrical Characteristics
(VCC = 2.5V, VDD = 2.5V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
PSRR_VCC
Input Power Supply Rejection Ratio
VCM = 0.3V, VDD = 2.5V, VCC Varied from 2.45V
to 5.25V (LTC6752-2/LTC6752-3/LTC6752-4)
Total Power Supply Rejection Ratio
PSRR_VDD
Output Power Supply Rejection Ratio
MIN
TYP
74
l
59
57
dB
dB
VCM = 0.3V, VCC Varied from 2.45V to 3.5V
(LTC6752/LTC6752-1)
53
51
73
l
dB
dB
VCM = 0.3V, VDD Varied from 1.71V to 3.5V
(LTC6752-2/LTC6752-3/LTC6752-4)
56
51
71
l
dB
dB
6000
V/V
AVOL
Open Loop Gain
LTC6752-1/LTC6752-2/LTC6752-3, Hysteresis
Removed (Note 12)
VOH
Output High Voltage (Amount Below
VDD (LTC6752-2/LTC5752-3/LTC6752-4),
VCC (LTC6752/LTC6752-1))
ISOURCE = 8mA
Output Low Voltage (Referred to VEE)
ISINK = 8mA
VOL
Output Short-Circuit Current
Source
260
340
mV
mV
200
340
400
mV
mV
16
12
30
l
mA
mA
15
9
22
l
mA
mA
Sink
IVCC
VCC Supply Current, Device On
LTC6752/LTC6752-1
4.5
5.0
5.9
mA
mA
1.9
2.25
2.5
mA
mA
2.6
3.2
3.4
mA
mA
4.3
4.75
5.2
mA
mA
4.5
5.0
5.9
mA
mA
6.2
6.65
7.7
mA
mA
l
LTC6752-2/LTC6752-3/LTC6752-4
l
IVDD
VDD Supply Current, Device On
LTC6752-2/LTC6752-4
l
LTC6752-3
l
ITOTAL
Total Supply Current, Device On
LTC6752/LTC6752-1/LTC6752-2/LTC6752-4
l
LTC6752-3
l
tR, tF
Rise/Fall time
10% to 90%
tPD
Propagation Delay (Note 8)
VOVERDRIVE = 50mV
1.2
2.9
l
tSKEW
Propagation Delay Skew, Rising to Falling
Transition (Note 9)
UNITS
130
l
l
ISC
MAX
ns
5
5.5
ns
ns
300
ps
tODD
Overdrive Dispersion (Note 8)
Overdrive Varied from 10mV to 125mV
1.8
ns
tCMD
Common Mode Dispersion
VCM Varied from VEE – 0.2V to VCC + 0.1V
240
ps
TR
Toggle Rate (Note 11)
100mVP-P Input, LTC6752/LTC6752-1/
LTC6752‑2/LTC6752-4
100mVP-P Input, LTC6752-3
280
250
MHz
MHz
tJITTER
RMS Jitter
VIN = 100mVP-P,
fIN = 100MHz, Jitter BW = 10Hz – 50MHz
fIN = 61.44MHz, Jitter BW = 10Hz – 30.72MHz
fIN = 10MHz, Jitter BW = 10Hz – 5MHz
4.5
6.0
30
ps
ps
ps
6752fc
4
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Electrical Characteristics
(VCC = 2.5V, VDD = 2.5V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.25
1.45
V
20
25
Latching/Adjustable Hysteresis Characteristics (LTC6752-1/LTC6752-2/LTC6752-3 Only)
VLE/HYST
LE/HYST Pin Voltage
Open Circuit
l
1.05
l
15
RHYST
Resistance Looking Into LE/HYST
LE/HYST Pin Voltage < Open Circuit Value
VHYST_LARGE
Hysteresis Voltage
VLE/HYST = 800mV
40
kΩ
mV
VIL_LE
Latch Pin Voltage, Latch Guaranteed
VIH_LE
Latch Pin Voltage, Hysteresis Disabled
Output Not Latched
l
0.3
IIH_LE
Latch Pin Current High
VLE/HYST = 1.7V
l
IIL_LE
Latch Pin Current Low
VLE/HYST = 0.3V
l
–47
µA
tSETUP
Latch Setup Time (Note 10)
–2
ns
tHOLD
Latch Hold Time (Note 10)
2
ns
tPL
Latch to Output Delay
7
ns
l
1.7
30
–70
V
V
72
µA
Shutdown Characteristics (LTC6752-2/LTC6752-3 Only)
ISD_VCC
Shutdown Mode Input Stage Supply Current VSHDN = 0.6V
400
585
620
µA
µA
185
340
380
µA
µA
250
650
680
µA
µA
l
ISD_VDD
Shutdown Mode Output Stage Supply
Current
VSHDN = 0.6V, LTC6752-2
l
VSHDN = 0.6V, LTC6752-3
l
tSD
Shutdown Time
Output Hi-Z
VIH_SD
Shutdown Pin Voltage High
Part Guaranteed to Be Powered On
l
VIL_SD
Shutdown Pin Voltage Low
Part Guaranteed to Be Powered Off
l
tWAKEUP
Wake-Up Time from Shutdown
VOD = 100mV, Output Valid
80
ns
1.3
V
0.6
100
V
ns
(VCC = 3.3V, VDD = 3.3V, VEE = 0). The l denotes the specifications which apply over the specified temperature range, otherwise
specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN +
VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VCC - VEE
Supply Voltage (Note 5)
l
LTC6752/LTC6752-1 (Total Supply)
LTC6752-2/LTC6752-3/LTC6752-4 (Input Stage) l
2.45
2.45
VDD - VEE
Output Supply Voltage (Note 5)
LTC6752-2/LTC6752-3/LTC6752-4
1.71
VCMR
Input Voltage Range (Note 7)
VOS
Input Offset Voltage (Note 6)
l
TYP
l VEE – 0.2
l
–5.5
–9
±1.2
MAX
UNITS
3.5
5.25
V
V
3.5
V
VCC + 0.1
V
5.5
9
mV
mV
TCVOS
Input Offset Voltage Drift
VHYST
Input Hysteresis Voltage (Note 6)
CIN
Input Capacitance
1.1
pF
RDM
Differential Mode Resistance
57
kΩ
RCM
Common Mode Resistance
6.4
MΩ
IB
Input Bias Current
–1.4
µA
µA
l
LE/HYST Pin Floating
VCM = VEE + 0.3V
l
–3.8
–4.1
VCM = VCC – 0.3V
18
µV/°C
4.7
mV
0.33
1.5
2.3
µA
µA
±0.1
0.75
µA
l
IOS
Input Offset Current
l
–0.75
6752fc
For more information www.linear.com/LTC6752
5
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Electrical Characteristics
(VCC = 3.3V, VDD = 3.3V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
CMRR_
LVCM
Common Mode Input Range, Low VCM
Region
VCM = VEE – 0.2V to VCC – 1.5V
CMRR_FR
Common Mode Rejection Ratio (Measured at VCM = VEE – 0.2V to VCC + 0.1V
Extreme Ends of VCMR)
PSRR_VCC
Input Power Supply Rejection Ratio
Total Power Supply Rejection Ratio
PSRR_VDD
Output Power Supply Rejection Ratio
MIN
TYP
70
l
52
48
dB
dB
50
46
66
l
dB
dB
VCM = 0.3V, VDD = 3.3V,VCC Varied from 2.45V
to 5.25V (LTC6752-2/LTC6752-3/LTC6752-4)
59
57
75
dB
l
VCM = 0.3V,VCC Varied from 2.45V to 3.5V
(LTC6752/LTC6752-1)
53
51
73
l
dB
dB
VCM = 0.3V, VDD Varied from 1.71V to 3.5V
(LTC6752-2/LTC6752-3/LTC6752-4)
56
51
71
l
dB
dB
7000
V/V
AVOL
Open Loop Gain
LTC6752-1/LTC6752-2/LTC6752-3,Hysteresis
Removed (Note 12)
VOH
Output High Voltage (Amount Below VDD
(LTC6752-2/LTC5752-3/LTC6752-4), VCC
(LTC6752/LTC6752-1))
ISOURCE = 8mA
Output Low Voltage (Referred to VEE)
ISINK = 8mA
VOL
Output Short-Circuit Current
Source
200
300
mV
mV
155
320
350
mV
mV
35
30
70
l
mA
mA
20
15
39
l
mA
mA
Sink
IVCC
VCC Supply Current, Device On
LTC6752/LTC6752-1
4.8
5.8
6.2
mA
mA
1.9
2.35
2.55
mA
mA
2.9
3.45
3.65
mA
mA
4.75
5.35
5.75
mA
mA
4.8
5.8
6.2
mA
mA
6.6
7.7
8.3
mA
mA
l
LTC6752-2/LTC6752-3/LTC6752-4
l
IVDD
VDD Supply Current, Device On
LTC6752-2/LTC6752-4
l
LTC6752-3
l
ITOTAL
Total Supply Current, Device On
LTC6752/LTC6752-1/LTC6752-2/LTC6752-4
l
LTC6752-3
l
tR, tF
Rise/Fall Time
10% to 90%
1.35
tPD
Propagation Delay (Note 8)
VOVERDRIVE = 50mV
3.00
l
tSKEW
Propagation Delay Skew, Rising to Falling
Transition (Note 9)
tODD
Overdrive Dispersion (Note 8)
Overdrive Varied from 10mV to 125mV
UNITS
81
l
l
ISC
MAX
ns
5
5.5
ns
ns
600
ps
1.8
ns
tCMD
Common Mode Dispersion
VCM Varied from VEE—0.2V to VCC + 0.1V
240
ps
TR
Toggle Rate (Note 11)
100mVP-P Input
215
MHz
tJITTER
RMS jitter
VIN = 100mVP-P, fIN = 100MHz,
Jitter BW = 10Hz – 50MHz
fIN = 61.44MHz, Jitter BW = 10Hz – 30.72MHz
fIN = 10MHz, Jitter BW = 10Hz – 5MHz
4.8
ps
5.8
29
ps
ps
6752fc
6
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Electrical Characteristics
(VCC = 3.3V, VDD = 3.3V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Latching/Adjustable Hysteresis Characteristics (LTC6752-1/LTC6752-2/LTC6752-3 Only)
VLE/HYST
LE/HYST Pin Voltage
Open Circuit
l
1.05
1.25
1.45
RHYST
Resistance Looking Into LE/HYST
LE/HYST Pin Voltage < Open Circuit Value
l
15
20
25
VHYST_LARGE
Hysteresis Voltage
VLE/HYST = 800mV
40
V
kΩ
mV
VIL_LE
Latch Pin Voltage, Latch Guaranteed
VIH_LE
Latch Pin Voltage, Hysteresis Disabled
Output Not Latched
l
0.3
IIH_LE
Latch Pin Current High
VLE/HYST = 1.7V
l
IIL_LE
Latch Pin Current Low
VLE/HYST = 0.3V
l
–47
µA
tSETUP
Latch Setup Time (Note 10)
–2
ns
tHOLD
Latch Hold Time (Note 10)
2
ns
tPL
Latch to Output Delay
7
ns
l
V
1.7
V
30
–70
72
µA
Shutdown Characteristics (LTC6752-2/LTC6752-3 Only)
ISD_VCC
Shutdown Mode Input Stage Supply Current VSHDN = 0.6V
430
600
660
µA
µA
200
420
450
µA
µA
300
700
800
µA
µA
l
ISD_VDD
Shutdown Mode Output Stage Supply
Current
VSHDN = 0.6V, LTC6752-2
l
VSHDN = 0.6V, LTC6752-3
l
tSD
Shutdown Time
Output Hi-Z
VIH_SD
Shutdown Pin Voltage High
Part Guaranteed to Be Powered On
l
VIL_SD
Shutdown Pin Voltage Low
Part Guaranteed to Be Powered Off
l
tWAKEUP
Wake-Up Time from Shutdown
VOD = 100mV, Output Valid
80
ns
1.3
V
0.6
V
100
ns
(VCC = 5V, VDD = 1.8V, VEE = 0, LTC6752-2/LTC6752-3/LTC6752-4 only). The l denotes the specifications which apply over the
specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV,
–IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
MAX
UNITS
VCC - VEE
Input Supply Voltage (Note 5)
CONDITIONS
l
2.45
MIN
5.25
V
VDD - VEE
Output Supply Voltage (Note5)
l
1.71
3.5
V
VCMR
Input Voltage Range (Note 7)
l VEE – 0.2
VOS
Input Offset Voltage (Note 6)
l
–5.5
–9
TYP
VCC + 0.1
±1.2
5.5
9
V
mV
mV
TCVOS
Input Offset Voltage Drift
VHYST
Input Hysteresis Voltage (Note 6)
CIN
Input Capacitance
1.1
pF
RDM
Differential Mode Resistance
57
kΩ
RCM
Common Mode Resistance
6.4
MΩ
IB
Input Bias Current
–1.5
µA
µA
l
LE/HYST Pin Floating
VCM = VEE + 0.3V
l
VCM = VCC – 0.3V
–3.9
–4.2
14
µV/°C
5.2
mV
0.36
l
1.6
2.5
µA
µA
6752fc
For more information www.linear.com/LTC6752
7
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Electrical Characteristics
(VCC = 5V, VDD = 1.8V, VEE = 0, LTC6752-2/LTC6752-3/LTC6752-4 only).
The l denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C.
LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless
otherwise noted.
SYMBOL
PARAMETER
IOS
Input Offset Current
CMRR_
LVCM
Common Mode Input Range, Low VCM
Region
CMRR_FR
Common Mode Rejection Ratio (Measured at VCM = VEE – 0.2V to VCC + 0.1V
Extreme Ends of VCMR)
PSRR_VCC
PSRR_VDD
CONDITIONS
MIN
TYP
MAX
l
–0.9
±0.1
0.9
54
51
70
l
dB
dB
53
48
68
l
dB
dB
59
57
75
dB
l
57
51
71
l
dB
dB
3500
V/V
VCM = VEE – 0.2V to VCC – 1.5V
Input Power Supply Rejection Ratio
VCM = 0.3V, VDD = 1.8V,VCC Varied from 2.45V
to 5.25V
Output Power Supply Rejection Ratio
VCM = 0.3V, VDD Varied from 1.71V to 3.5V
AVOL
Open Loop Gain
LTC6752-2/LTC6752-3 Hysteresis Removed
(Note 12)
VOH
Output High Voltage (Amount Below VDD)
ISOURCE = 5.5mA
Output Low Voltage (Referred to VEE)
ISINK = 5.5mA
400
450
mV
mV
200
400
550
mV
mV
l
ISC
Output Short-Circuit Current
Source
9
6.2
17
l
mA
mA
11
6.2
19
l
mA
mA
Sink
IVCC
VCC Supply Current, Device On
2.1
2.65
2.85
mA
mA
2.5
3
3.25
mA
mA
3.4
4.4
4.8
mA
mA
4.5
5.65
6.1
mA
mA
6
7.05
7.65
mA
mA
l
IVDD
VDD Supply Current, Device On
LTC6752-2/LTC6752-4
l
LTC6752-3
l
ITOTAL
Total Supply Current, Device On
LTC6752-2/LTC6752-4
l
LTC6752-3
l
tR, tF
Rise/Fall Time
10% to 90%
tPD
Propagation Delay (Note 8)
VOVERDRIVE = 50mV
1.25
3.4
l
tSKEW
Propagation Delay Skew, Rising to Falling
Transition (Note 9)
µA
200
l
VOL
UNITS
ns
5.3
5.7
ns
ns
400
ps
tODD
Overdrive Dispersion (Note 8)
Overdrive Varied from 10mV to 125mV
1.8
ns
tCMD
Common Mode Dispersion
VCM Varied from VEE – 0.2V to VCC + 0.1V
240
ps
TR
Toggle Rate (Note 11)
100mVP-P Input, LTC6752-2/LTC6752-4
100mVP-P Input, LTC6752-3
230
185
MHz
MHz
tJITTER
RMS Jitter
VIN = 100mVP-P, fIN = 100MHz,
Jitter BW = 10Hz – 50MHz
fIN = 61.44MHz, Jitter BW = 10Hz – 30.72MHz
fIN = 10MHz, Jitter BW = 10Hz – 5MHz
4.3
ps
5.8
28
ps
ps
6752fc
8
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Electrical Characteristics
(VCC = 5V, VDD = 1.8V, VEE = 0, LTC6752-2/LTC6752-3 only).
The l denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C.
LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Latching/Adjustable Hysteresis Characteristics (LTC6752-2/LTC6752-3 Only)
VLE/HYST
LE/HYST Pin Voltage
Open Circuit
l
1.05
1.25
1.45
RHYST
Resistance Looking Into LE/HYST
LE/HYST Pin Voltage < Open Circuit Value
l
15
20
25
VLE/HYST = 800mV
VHYST_LARGE
Modified Input Hysteresis Voltage (Note 2)
VIL_LE
Latch Pin Voltage, Latch Guaranteed
40
l
V
kΩ
mV
0.3
V
72
µA
VIH_LE
Latch Pin Voltage, Hysteresis Disabled
Output Not Latched
l
IIH_LE
Latch Pin Current High
VLE/HYST = 1.7V
l
IIL_LE
Latch Pin Current Low
VLE/HYST = 0.3V
l
–47
µA
tSETUP
Latch Setup Time (Note 10)
–2
ns
tHOLD
Latch Hold Time (Note 10)
2
ns
tPL
Latch To Output Delay
7
ns
1.7
V
30
–70
Shutdown Characteristics (LTC6752-2/LTC6752-3 Only)
ISD_VCC
Shutdown Mode Input Stage Supply Current VSHDN = 0.6V
500
650
750
µA
µA
170
400
450
µA
µA
240
600
650
µA
µA
l
ISD_VDD
Shutdown Mode Output Stage Supply
Current
VSHDN = 0.6V, LTC6752-2
l
VSHDN = 0.6V, LTC6752-3
l
tSD
Shutdown Time
Output Hi-Z
80
VIH_SD
Shutdown Pin Voltage High
Part Guaranteed to Be Powered On
l
VIL_SD
Shutdown Pin Voltage Low
Part Guaranteed to Be Powered Off
l
tWAKEUP
Wake-Up Time from Shutdown
VOD = 100mV, Output Valid
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Reverse biased ESD protection diodes exist on all input,
shutdown, latching/hysteresis and output pins. If the voltage on these
pins goes 300mV beyond either supply rail, the current should be limited
to less than 10mA. This parameter is guaranteed to meet specification
through design and/or characterization. It is not production tested.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating. This parameter is guaranteed to meet
specified performance through design and/or characterization. It is not
production tested.
Note 4: The LTC6752I/LTC6752-1I/LTC6752-2I/LTC6752-3I/LTC6752‑4I
are guaranteed to meet specified performance from –40°C to 85°C. The
LTC6752H/LTC6752-1H/LTC6752-2H/LTC6752-3H/LTC6752-4H are
guaranteed to meet specified performance from –40°C to 125°C.
Note 5: Total output supply voltage range is guaranteed by the PSRR_VDD
test. Total input supply voltage range for the LTC6752-2, LTC6752-3 and
LTC6752-4 is guaranteed by the PSRR_VCC test. For the LTC6752 and
LTC6752-1, the supply voltage range is guaranteed by the PSRR_VCC test.
The LTC6752MP is guaranteed to meet specified performance from –55°C
to 125°C.
ns
1.3
V
0.6
100
V
ns
Note 6: Both hysteresis and offset are measured by determining positive
and negative trip points (input values needed to change the output in the
opposite direction). Hysteresis is defined as the difference of the two trip
points and offset as the average of the two trip points.
Note 7: Guaranteed by CMRR test.
Note 8: Propagation delays are measured with a step size of 150mV.
Note 9: Propagation delay skew is defined as the difference of the
propagation delays for positive and negative steps for the LTC6752,
LTC6752-1, LTC6752-2 and LTC6752-4, and the difference in propagation
delays between the complementary outputs for the LTC6752-3.
Note 10: Latch setup time is defined as the minimum time before the
LE/HYST pin is asserted low for an input signal change to be acquired and
held at the output. Latch hold time is defined as the minimum time before
an input signal change for a high to low transition on the LE/HYST pin to
prevent the output from changing. See Figure 7 for a graphical definition of
these terms.
Note 11: Toggling is defined to be valid if the output swings as follows:
from 10% of VDD - VEE to 90% of VDD - VEE for the LTC6752-2/
LTC6752-3/LTC6752-4, and from 10% of VCC - VEE to 90% of VCC - VEE
for the LTC6752/LTC6752-1. It is tested with a 1kΩ load to VCM
Note 12: The devices have effectively infinite gain when hysteresis is
enabled.
6752fc
For more information www.linear.com/LTC6752
9
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical Performance Characteristics DC
VCC = VDD = 2.5V, CLOAD = 5pF,
VOVERDRIVE = 50mV, VCM = 300mV,TA = 25°C unless otherwise noted. VCC ≠ VDD conditions applicable only to the LTC6752-2/LTC6752-3/
LTC6752-4.
HYSTERESIS
5
OFFSET, HYSTERESIS (mV)
OFFSET/HYSTERESIS (mV)
6
4
2
0
–2
–4
–55 –35 –15
3
2
OFFSET
1
VHYST
VOS
7
0.8
6
0.6
HYSTERESIS
4
3
2
OFFSET
1
0
–1
–2
3
2
OFFSET
3.15
3.85
4.55
VCC VOLTAGE (V)
0
1.6
5.25
2.1
6752 G02
2.6
3.1
VDD VOLTAGE (V)
3.6
6752 G03
Input Bias Current vs Common
Mode Voltage
0.5
0.4
VCM = 2.2V
0.2
0
–0.2
–0.4
–0.6
–0.8
VCM = 300mV
–1.0
VIN = VOS
0
–0.5
–1.0
–1.5
–1.2
–3
–0.2
0.2 0.6 1.0 1.4 1.8 2.2
INPUT COMMON MODE VOLTAGE (V)
2.6
–1.4
–55 –35 –15
–IN
–2.5
LE/HYST PIN CURRENT (µA)
+IN
HYSTERESIS (mV)
–1.5
200
40
VCC = 5V
VDD = 2.5V
VCM = 2.5V
–1.0
–2.0
LE/HYST Pin I-V Characteristics
50
0
30
20
10
–3.0
–3.5
–5.4 –4.2 –3.0 –1.8 –0.6 0.6 1.8 3.0 4.2 5.4
INPUT DIFFERENTIAL VOLTAGE (V)
6752 G07
0
0.75
2.6
6752 G06
Input Hysteresis vs LE/HYST Pin
Voltage
1.0
–0.5
0.2 0.6 1.0 1.4 1.8 2.2
INPUT COMMON MODE VOLTAGE (V)
6752 G05
Input Bias Current vs Differential
Input Voltage
0.5
–2.0
–0.2
5 25 45 65 85 105 125
TEMPERATURE (°C)
6752 G04
BIAS CURRENT (µA)
4
Input Bias Current vs Temperature
INPUT BIAS CURRENT (µA)
OFFSET, HYSTERESIS (mV)
Input Offset Voltage and
Hysteresis vs Input Common Mode
HYSTERESIS
5
1
0
2.45
5 25 45 65 85 105 125
TEMPERATURE (°C)
Input Offset Voltage and
Hysteresis vs VDD Voltage
6
4
6752 G01
5
7
OFFSET, HYSTERESIS (mV)
6
Input Offset Voltage and
Hysteresis vs VCC Voltage
INPUT BIAS CURRENT (µA)
8
Input Offset Voltage and
Hysteresis vs Temperature
1.00
1.25
1.50
LE/HYST VOLTAGE (V)
1.75
6752 G08
150
VCC = 5V
100
VCC = 2.5V
50
0
–50
–100
–0.3
0.5
1.3 2.1 2.9 3.7 4.5
LE/HYST PIN VOLTAGE (V)
5.3
6752 G09
6752fc
10
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical Performance Characteristics DC
VCC = VDD = 2.5V, CLOAD = 5pF,
VOVERDRIVE = 50mV, VCM = 300mV,TA = 25°C unless otherwise noted. VCC ≠ VDD conditions applicable only to the LTC6752-2/ LTC6752-3/
LTC6752-4.
Output Low Voltage vs Load
Current
4.5
SINKING
40
20
0
SOURCING
–20
–40
VCC = 5V, VDD = 1.8V
VCC = VDD = 2.5V
VCC = VDD = 3.3V
–60
–80
–55 –35 –15
0
MEASURED FROM VEE
4.0
60
OUTPUT LOW VOLTAGE (V)
VCC = 3.3V
VDD = 3.3V
3.5
3.0
VCC = 2.5V
VDD = 2.5V
2.5
2.0
VCC = 5V
VDD = 1.8V
1.5
1.0
0.5
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
0
5
10 15 20 25 30 35
SINKING CURRENT (mA)
–3.0
–3.5
–4.0
VOH
MEASURED
FROM VDD
150
100
50
5 25 45 65 85 105 125
TEMPERATURE (°C)
3.5
3.0
2.5
IVDD (LTC6752-2/LTC6752-4)
2.0
SUPPLY CURRENT (mA)
2
IVDD (LTC6752-2/LTC6752-4)
IVCC (LTC6752-2/LTC6752-4)
1
0
2.45
3.65
6752 G16
3
IVCC
1
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
6
ITOTAL
5
4
IVDD
3
2
0
2.45
5 25 45 65 85 105 125
TEMPERATURE (°C)
6752 G15
Supply Current vs Input Common
Mode Voltage (LTC6752/LTC6752-1/
LTC6752-2/LTC6752-4)
4.85
VCC = VDD
IVCC
1
2.75
3.05
3.35
SUPPLY VOLTAGE (V)
IVDD
2
7
5
3
ITOTAL
4
Supply Current vs Supply Voltage
(LTC6752-3)
8
80
5
6752 G14
VCC = VDD
70
Supply Current vs Temperature
(LTC6752-3)
IVCC (LTC6752-2/LTC6752-4)
1.0
–55 –35 –15
Supply Current vs Supply Voltage
(LTC6752/LTC6752-1/LTC6752-2/
LTC6752-4)
ITOTAL (LTC6752-2/LTC6752-4)
ICC (LTC6752/LTC6752-1)
20 30 40 50 60
SOURCING CURRENT (mA)
6
ITOTAL (LTC6752-2/LTC6752-4)
ICC (LTC6752/LTC6752-1)
4.0
6752 G13
4
10
7
1.5
0
–55 –35 –15
0
6752 G12
SUPPLY CURRENT (mA)
200
MEASURED
FROM VEE
SUPPLY CURRENT (mA)
OUTPUT HIGH/LOW VOLTAGE (mV)
–2.5
4.5
VOL
VCC = 2.5V
VDD = 2.5V
VCC = 5V
VDD = 1.8V
–2.0
5.0
SOURCE/SINK CURRENT = 8mA
250
SUPPLY CURRENT (mA)
–1.5
Supply Current vs Temperature
(LTC6752/LTC6752-1/LTC6752-2/
LTC6752-4)
Output High/Low Voltage vs
Temperature
6
–1.0
6752 G11
6752 G10
300
VCC = 3.3V
VDD = 3.3V
–0.5
–4.5
45
40
TOTAL SUPPLY CURRENT IVCC + IVDD (mA)
SHORT-CIRCUIT CURRENT (mA)
80
Output High Voltage vs Sourcing
Current
OUTPUT VOLTAGE RELATIVE TO VDD (V)
Output Short-Circuit Current vs
Temperature
2.75
3.05
3.35
SUPPLY VOLTAGE (V)
3.65
6752 G17
4.80
4.75
4.70
4.65
4.60
4.55
4.50
4.45
–0.2
0.5
1.2
1.9
INPUT COMMON MODE VOLTAGE (V)
2.6
6752 G18
6752fc
For more information www.linear.com/LTC6752
11
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical Performance Characteristics DC
VCC = VDD = 2.5V, CLOAD = 5pF,
VOVERDRIVE = 50mV, VCM = 300mV,TA = 25°C unless otherwise noted. VCC ≠ VDD conditions applicable only to the LTC6752-2/LTC6752-3/
LTC6752-4.
0
6.40
6.35
6.30
6.25
6.20
6.15
–2
5.0
–4
–6
–8
VCC = 5V
–10
0.5
1.2
1.9
INPUT COMMON MODE VOLTAGE (V)
–12
6752 G19
3.5
3.0
2.5
2.0
1.5
1.0
0
–0.3
0.2
0.7
1.2
1.7
2.2
SHDN PIN VOLTAGE (V)
6752 G20
Total Supply Current vs SHDN Pin
Voltage (LTC6752-3)
2.7
6752 G21
Supply Current vs Temperature,
Shutdown (LTC6752-3)
Supply Current vs Temperature,
Shutdown (LTC6752-2)
700
SHUTDOWN SUPPLY CURRENT (µA)
6
5
4
3
2
1
0.2
0.7
1.2
1.7
2.2
SHDN PIN VOLTAGE (V)
2.7
6752 G22
600
700
ITOTAL
SHUTDOWN SUPPLY CURRENT (µA)
7
0
–0.3
4.0
0.5
–16
–0.3 0.5 1.3 2.1 2.9 3.7 4.5 5.3
VOLTAGE BETWEEN SHDN PIN AND VEE (V)
2.6
Total Supply Current vs SHDN Pin
Voltage (LTC6752-2)
4.5
VCC = 2.5V
–14
6.10
–0.2
TOTAL SUPPLY CURRENT (mA)
SHDN Pin I-V Characteristics
TOTAL SUPPLY CURRENT (mA)
2
SHDN PIN CURRENT (µA)
TOTAL SUPPLY CURRENT IVCC + IVDD (mA)
6.45
Supply Current vs Input Common
Mode Voltage (LTC6752-3)
500
400
IVDD
300
200
100
–55 –35 –15
IVCC
5 25 45 65 85 105 125
TEMPERATURE (°C)
6752 G23
600
ITOTAL
500
400
IVDD
300
200
100
–55 –35 –15
IVCC
5 25 45 65 85 105 125
TEMPERATURE (°C)
6752 G24
6752fc
12
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical Performance Characteristics AC
VCC = VDD = 2.5V, CLOAD = 5pF,
VOVERDRIVE = 50mV, VCM = 300mV, TA = 25°C, transient input voltage 10MHz, 150mVP-P square wave unless otherwise noted.
VCC ≠ VDD conditions applicable only to the LTC6752-2/LTC6752-3/LTC6752-4.
Propagation Delay vs Input
Overdrive
4.0
VCC = 5V, VDD = 1.8V
3.5
3.0
2.5
tpd, OUTPUT FALLING (tpdHL)
3.0
tpd, OUTPUT RISING(tpdHL)
2.5
–0.2
10 20 30 40 50 60 70 80 90 100 110 120
OVERDRIVE (mV)
tpdHL
2.80
tpdLH
2.60
2.45 2.85 3.25 3.65 4.05 4.45 4.85 5.25
VCC VOLTAGE (V)
3.3
3.1
tpdHL
2.9
tpdLH
3.4
3.2
3.0
2.8
VCM = 1V
RL = 1kΩ
340
3.0
2.4
VCC = 5V, VDD = 1.8V
VCC = 2.5V, VDD = 2.5V
20
6752 G31
5
10
15
LOAD CAPACITANCE (pF)
20
Toggle Rate vs Input Amplitude,
LTC6752-3
300
VCC = 2.5V, VDD = 2.5V
300
280
VCC = 5V, VDD = 1.8V
260
240
220
VCC = 3.3V, VDD = 3.3V
200
VCC = 2.5V, VDD = 2.5V
260
240
VCC = 3.3V, VDD = 3.3V
220
200
VCC = 5V, VDD = 1.8V
180
160
180
160
VCM = 1V
RL = 1kΩ
280
TOGGLE RATE (MHz)
TOGGLE RATE (MHz)
tRISE
tFALL
0
6752 G30
320
1.5
VCC = 2.5V, VDD = 2.5V
2.6
360
2.0
VCC = 5V, VDD = 1.8V
3.6
Toggle Rate vs Input Amplitude,
LTC6752/LTC6752-1/LTC6752-2/
LTC6752-4
3.5
5
10
15
LOAD CAPACITANCE (pF)
3.8
6752 G29
Rise/Fall times vs
Capacitive Load
2.5
5 25 45 65 85 105 125
TEMPERATURE (°C)
tpdHL
tpdLH
4.0
2.5
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VDD VOLTAGE (V)
6752 G28
0
VCC = 2.5V, VDD = 2.5V
4.2
2.7
2.65
0
2.9
Propagation Delay vs
Capacitive Load
PROPAGATION DELAY (ns)
2.90
0.5
3.1
6752 G27
3.5
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
2.95
1.0
3.3
2.5
–55 –35 –15
0.2 0.6 1.0 1.4 1.8 2.2 2.6
INPUT COMMON MODE VOLTAGE (V)
3.7
2.70
VCC = 5V, VDD = 1.8V
3.5
Propagation Delay vs Output
Stage Supply Voltage
3.00
2.75
3.7
6752 G26
Propagation Delay vs Input Stage
Supply Voltage
2.85
tpdHL
tpdLH
2.7
VCC = 2.5V, VDD = 2.5V
6752 G25
RISE/FALL TIME (ns)
4.1
Propagation Delay vs
Temperature
3.9
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
4.5
2.0
3.5
tpdHL
tpdLH
PROPAGATION DELAY (ns)
5.0
Propagation Delay vs Common
Mode Voltage
20
200
INPUT AMPLITUDE (mVP-P)
2000
6752 G32
140
20
200
INPUT AMPLITUDE (mVP-P)
2000
6752 G33
6752fc
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13
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical Performance Characteristics AC
VCC = VDD = 2.5V, CLOAD = 5pF,
VOVERDRIVE = 50mV, VCM = 300mV, TA = 25°C, transient input voltage 10MHz, 150mVP-P square wave unless otherwise noted.
VCC ≠ VDD conditions applicable only to the LTC6752-2/ LTC6752-3/LTC6752-4.
Toggle Rate vs Capacitive Load,
Toggle Rate vs Temperature, (LTC6752/
Toggle Rate vs Temperature,
(LTC6752/LTC6752-1/LTC6752-2/
LTC6752-1/LTC6752-2/LTC6752-4)
LTC6752-3
LTC6752-4)
290
310
290
TOGGLE RATE (MHz)
TOGGLE RATE (MHz)
270
VCC = 2.5V, VDD = 2.5V
270
250
VCC = 5V, VDD = 1.8V
230
210
190
VCC = 3.3V, VDD = 3.3V
RL = 1kΩ
VIN = 100mVP-P
SINUSOID
170
150
–55 –35 –15
210 VCC = 3.3V, VDD = 3.3V
190
VCC = 5V, VDD = 1.8V
150
–55 –35 –15
VCC = 3.3V, VDD = 3.3V
180
5
10
15
LOAD CAPACITANCE (pF)
250
200
VCC = 5V, VDD = 1.8V
0
5
10
15
LOAD CAPACITANCE (pF)
20
20
6752 G36
100MHz SINOSOIDAL INPUT
JITTER BANDWIDTH: 10Hz TO 50MHz
14
VCC = 3.3V, VDD = 3.3V
12
10
VCC = 5V, VDD = 1.8V
8
6
4
2
VCC = 5V, VDD = 1.8V
0
VCC = 3.3V, VDD = 3.3V
Output Jitter vs Input Amplitude
16
RMS OUTPUT JITTER (ps)
TOGGLE RATE (MHz)
280
80
300
6752 G35
VCC = 2.5V, VDD = 2.5V
130
VCC = 2.5V, VDD = 2.5V
350
100
5 25 45 65 85 105 125
TEMPERATURE (°C)
RL = 1kΩ
VIN = 100mVP-P
SINUSOID
230
400
150
Toggle Rate vs Capacitive Load,
LTC6752-3
330
RL = 1kΩ
VIN = 100mVP-P
SINUSOID
450
230
6752 G34
380
500
RL = 1kΩ
VIN = 100mVP-P
SINUSOID
250
170
5 25 45 65 85 105 125
TEMPERATURE (°C)
VCC = 2.5V, VDD = 2.5V
TOGGLE RATE (MHz)
350
330
0
VCC = 2.5V, VDD = 2.5V
0
100
6752 G37
200 300 400 500 600
INPUT AMPLITUDE (mVP-P)
700
6752 G38
Output Toggle Waveform,
LTC6752-2
Output Toggle Waveforms Q and
Q, LTC6752-3
500mV/DIV
500mV/DIV
2ns/DIV
LTC6752-2
VCC = VDD = 2.5V
CL = 5pF
200MHz
6752 G39
2ns/DIV
6752 G40
LTC6752-3
VCC = VDD = 2.5V
CL = 5pF
200MHz
6752fc
14
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Pin Functions
+IN: Positive Input of the Comparator. The voltage range
of this pin can go from VEE to VCC.
–IN: Negative Input of the Comparator. The voltage range
of this pin can go from VEE to VCC.
VCC: Positive Supply Voltage for the LTC6752/LTC6752-1,
Positive Supply Voltage for the Input Stage of the
LTC6752-2/LTC6752-3/LTC6752-4.
VDD: Positive Supply Voltage for the Output Stage of the
LTC6752-2/LTC6752-3/LTC6752-4. Typically the voltage
is from 1.71V to 3.5V. See the section High Speed Board
Design Techniques for proper power supply layout and
bypassing.
VEE: Negative power supply, normally tied to ground. This
can be tied to a voltage other than ground as long as the
constraints for total supply voltage relative to VCC (and
VDD for separate supply operation) are maintained.
SHDN: Active low comparator shutdown, threshold is
0.6V above VEE. The comparator is enabled when this pin
is left unconnected.
LE/HYST: This pin allows the user to adjust the comparator’s hysteresis as well as latch the output state if the pin
voltage is taken within 300mV above VEE. Hysteresis can
be increased or disabled by voltage, current or a resistor
to VEE. Leaving the pin unconnected results in a typical
hysteresis of 5mV.
Q: Comparator Output. Q is driven high when +IN > –IN
and driven low when +IN < –IN.
Q: Comparator Complementary Output (Available on
LTC6752-3 Only). Logical inversion of Q.
6752fc
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15
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Block Diagram
VDD
+
HYSTERESIS STAGE
–
VEE
VCC
VCC
+
+IN
–
–IN
+
INPUT
STAGE
+
VEE
VCC
+
–
+
20k
LE/HYST
+
–
VCC
SHDN
Q
VCC
VEE
350k
OUTPUT
DRIVER
STAGE
GAIN
STAGE
VEE
LE/HYST PIN INTERFACE
1.25V
–
VEE
VEE
6752 BD
VEE
Figure 1. LTC6752/LTC6752-1/LTC6752-2/LTC6752-4 Block Diagram
6752fc
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Applications Information
Circuit Description
Input Voltage Range and Offset
The block diagram is shown in Figure 1. There are differential inputs (+IN, –IN), a negative power supply (VEE),
two positive supply pins: VCC for the input stage and VDD
for the output stage, an output pin (Q), a pin for latching
and adjusting hysteresis (LE/HYST), and a pin to put the
device in a low power mode (SHDN). In the LTC6752
and LTC6752-1, the two positive supply pins are bonded
together and referred to as VCC. The signal path consists
of a rail-to-rail input stage, an intermediate gain stage,
and an output stage driving a pair of complementary FETs
capable of taking the output pin to either supply rail. A
Latching/Hysteresis interface block allows the user to latch
the output state and/or remove or adjust the comparator
input hysteresis. All of the internal signal paths make use
of low voltage swings for high speed at low power.
The LTC6752-3 has an additional inverted output stage
(not shown) for a complementary logic output signal.
The LTC6752 family uses a rail-to-rail input stage that
consists of a pnp pair and an npn pair that are active over
different input common mode ranges. The pnp pair is active for inputs between VEE – 0.2V and approximately VCC
– 1.5V (low common mode region of operation). The npn
pair is active for inputs between approximately VCC – 1V
and VCC + 0.1V (high common mode region of operation).
Partial activation of both pairs occurs when one input is in
the low common mode region of operation and the other
input is in the high common mode region of operation, or
either of the inputs is between approximately VCC – 1.5V
and VCC – 1V (transition region). The device has small,
trimmed offsets as long as both inputs are completely
in the low or high common mode region of operation.
In the transition region, the offset voltage may increase.
Applications that require good DC precision should avoid
the transition region.
Power Supply Configurations
Input Bias Current
The LTC6752-2/LTC6752-3/LTC6752-4 have separate
positive supply pins for the input and output stages that
allow for separate voltage ranges for the analog input,
and the output logic. Figure 2 shows a few possible configurations. For reliable and proper operation, the input
supply pin should be between 2.45V and 5.25V above the
negative supply pin, and the output supply pin should be
between 1.71V and 3.5V above the negative supply pin.
There are no restrictions regarding the sequence in which
the supplies are applied, as long as the absolute-maximum
ratings are not violated.
When both inputs are in the low common mode region,
the input bias current is negative, with current flowing
out of the input pins. When both inputs are in the high
common mode region, the input bias current is positive,
with current flowing into the input pins.
The LTC6752 and LTC6752-1 have only one positive supply pin. The supply voltage should be between 2.45V and
3.5V for proper and reliable operation.
3V
+IN
+
3V
5V
VCC
+IN
VDD
+
–
0V
(a) SINGLE SUPPLY
2.5V 3.5V
+IN
VDD
+
–
0V
(b) OUTPUT SUPPLY < INPUT SUPPLY
+IN
VDD
+
0V
VCC
VDD
Q
–IN
VEE
2.5V
VCC
Q
–IN
VEE
1.8V
VCC
Q
–IN
The input stage has been designed to accommodate
large differential input voltages without large increases
in input bias current. With one input at the positive input
supply rail and the other input at the negative supply rail,
the magnitude of the input bias currents at either pin is
typically less than 3.5μA.
–
Q
–IN
VEE
0V
(c) OUTPUT SUPPLY > INPUT SUPPLY
–
VEE
–2.5V
(d) NEGATIVE OUTPUT LOGIC
6752 F02
Figure 2. Typical Power Supply Configurations (Applicable to the LTC6752-2/LTC6752-3/LTC6752-4)
6752fc
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Applications Information
Input Protection
ESD
The input stage is protected against damage from conditions where the voltage on either pin exceeds the supply
voltage (VCC to VEE) without external protection. External
input protection circuitry is only needed if input currents
can exceed the absolute maximum rating. For example,
if an input is taken beyond 300mV of either the positive
or negative supply, an internal ESD protection diode will
conduct and an external resistor should be used to limit
the current to less than 10mA.
The LTC6752 family members have reverse-biased ESD
protection diodes on pins as shown in Figure 1.
Outputs
Comparators have very high open-loop gain. With slow
input signals that are close to each other, input noise can
cause the output voltage to switch randomly. This can be
addressed by hysteresis which is positive feedback that
increases the trip point in the direction of the input signal
transition when the output switches. This pulls the inputs
away from each other, and prevents continuous switching
back and forth. The addition of positive feedback also has
the effect of making the small signal gain infinite around the
trip points. Hysteresis is designed into most comparators
and the LTC6752 family has adjustable hysteresis with a
default hysteresis of 5mV.
The LTC6752 family has excellent drive capability. The
comparators can deliver typically ±22mA output current
for an output supply of 2.5V, and ±39mA output current
for a 3.3V output supply. Attention must be paid to keep
the junction temperature of the IC below 150°C should the
output have a continuous short-circuit condition.
Logic Drive Capability
The LTC6752 family has been designed to drive CMOS
logic with a supply of 3.3V, 2.5V and 1.8V. For device reliability, the output power supply (VDD) should not be higher
than 3.6V above the negative supply. When VDD is 3V or
higher the CMOS outputs of the LTC6752 family provide
valid TTL logic threshold levels and can easily interface
with TTL logic devices operating with a 5V supply. This is
possible because all of the threshold levels associated with
TTL logic (VIH/VIL/VOH/VOL) are less than or equal to 2.4V
There are additional clamps between the positive and
negative supplies that further protect the device during
ESD strikes. Hot-plugging of the device into a powered
socket is not recommended since this can trigger the clamp
resulting in large currents flowing between the supply pins.
Hysteresis
The input-output transfer characteristic is illustrated in
Figure 3 showing the definitions of VOS and HYST based
upon the two measurable trip points.
In some cases, additional noise immunity is required
above what is provided by the nominal 5mV hysteresis.
VOUT
Capacitive Loads
The LTC6752 family can drive capacitive loads. Transient
performance parameters in the Electrical Characteristics
Tables and Typical Characteristics section are for a load
of 5pF, corresponding to a standard TTL/CMOS load. The
devices are fully functional for larger capacitive loads,
however speed performance will degrade. The graphs titled
Propagation Delay vs Capacitive Load and Toggle Rate vs
Capacitive Load illustrate the impact of changes to the total
capacitive load. For optimal speed performance, output
load capacitance should be reduced as much as possible.
VOH
FOR VTRIP+ = 3mV,
VTRIP– = –2mV,
VOS = 0.5mV,
VHYST = 5mV
VHYST
(= VTRIP+ – VTRIP–)
VOL
∆VIN = VIN+ – VIN–
0
VTRIP–
VOS
VTRIP+
V
VOS = TRIP
++V
2
–
TRIP
6752 F03
Figure 3
6752fc
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Applications Information
Conversely, when processing small or fast differential signals, hysteresis may need to be eliminated. The LTC6752-1/
LTC6752-2/LTC6752-3 provide a hysteresis pin, LE/
HYST, that can be used to increase the internal hysteresis,
completely remove it, or enable the output to latch. For
these 3 options of the LTC6752, the internal hysteresis
is disabled when the LE/HYST pin voltage is above 1.7V.
Although eliminating hysteresis does reduce the voltage
gain of the comparator to a finite value, in many cases it
will be high enough (typically 6000V/V) to process small
input signals. The output will latch when the LE/HYST pin
voltage is below 0.3V. The internal hysteresis will increase
as the voltage of the pin is adjusted from its default open
circuit value of 1.25V to 800mV.
In addition to adjusting hysteresis using the LE/HYST
pin, additional hysteresis can be added using positive
feedback from the output back to the positive input, as
shown in Figure 6.
The LE/HYST pin can be modeled as a 1.25V voltage
source in series with a 20k resistor. The simplest method
to increase the internal hysteresis is to connect a single
resistor as shown in Figure 4 between the LE/HYST pin and
VEE to adjust hysteresis. Figure 5 shows how hysteresis
typically varies with the value of the resistor.
The offset (with respect to the input signal) and hysteresis
become
+IN
–IN
+
VDD
–
HYSTERISIS (mV)
+
VCC
VDD
Q
–
VEE
6752 F06
Figure 6. Additional Hysteresis Using Positive Feedback
( VDD + VEE )
R1
R2
+ VREF
− VOS
2
R1+R2
R1+R2
V
R1
R2
− OH
+ VOL

→(1)
2 R1+R2
R1+R2
VOS _ FB =
VOH
R
VCC = VDD = 2.5V
VCM = 0.3V
TA = 25°C
CONTROL RESISTOR CONNECTED
BETWEEN LE/HYST PIN AND VEE
35
SIGNAL
LE/HYST
Figure 4. Adjusting Hysteresis Using an External
Resistor at the LE/HYST Pin
40
R1
VHYST _ FB = ( VDD − VEE )
Q
6752 F04
45
VREF
VCC
VEE
50
R2
R1
R2
+ VOL
+
R1+R2
R1+R2
R1
+ VHYST  
→(2)
R1+R2
VOS_FB and VHYST_FB denote the values of offset and
hysteresis with positive feedback present. VHYST denotes
the hysteresis of the device without positive feedback.
For light loads, VOH (output swing high) and VOL (output
swing low) are typically a few mV (typically are less than
10mV for a 500µA load).
On a 3.0V total supply with VEE = 0V, an increase in
hysteresis of approximately 300mV can be obtained with
VREF = 1.25V, R2 = 4.53kΩ , R1 = 511Ω, with an induced
offset of approximately 1.275V.
30
25
20
15
10
5
0
30
80 130 180 230 280 330 380 430 480
CONTROL RESISTANCE (kΩ)
6752 F05
Figure 5. Hysteresis vs Control Resistor
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Applications Information
Latching
The internal latch of the LTC6752-1/LTC6752-2/LTC6752-3
retains the output state when the LE/HYST pin is taken to
less than 300mV above the negative supply.
Figures 7a to 7e illustrate the latch timing definitions. The
latch setup time is defined as the time for which the input
should be stable before the latch pin is asserted low to
ensure that the correct state will be held at the output. The
latch hold time is the interval after which the latch pin is
asserted in which the input signal must remain stable for
the output to be the correct state at the time latch was
asserted. The latch to output delay (tPL) is the time taken
for the output to return to input control after the latch
pin is released. Latching is disabled if the LE/HYST pin
is left floating. Both outputs of the LTC6752-3 are latch
controlled simultaneously.
LE/HYST
t < tHOLD
+IN – –IN
tPD
Q
6752 F07c
Figure 7c. Input State Not Held Long Enough.
Wrong Output State Latched
LE/HYST
t > tSETUP
t > tHOLD
+IN – –IN
LE/HYST
tPD
Q
t > tSETUP
6752 F07d
Figure 7d. Short Input Pulse Properly
Captured and Latched
+IN – –IN
Q
tPD
6752 F07a
LE/HYST
Figure 7a. Input State Change Properly Latched
tPL
+IN – –IN
LE/HYST
Q
t < tSETUP
6752 F07e
Figure 7e. Latched Output Disabled
Shutdown
+IN – –IN
Q
6752 F07b
Figure 7b. Input Change Setup Time Too Short
The LTC6752-2 and LTC6752-3 have shutdown pins
(SHDN, active low) that can reduce the total supply current to a typical value of 580μA for the LTC6752-2 and
650µA for the LTC6752-3 (2.5V supply). When the part is
in shutdown, the outputs are placed in a high-impedance
state, since PFET and NFET output transistors whose drains
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LTC6752-2/LTC6752-3/
LTC6752-4
Applications Information
are tied to the output pins are cut off and cannot source/
sink any current. The shutdown pin needs to be taken to
within 600mV of the negative supply for the part to shut
down. When left floating, the shutdown pin is internally
pulled towards the positive supply, and the comparator
remains fully biased on.
Dispersion
Dispersion is defined as the change in propagation delay
for different input conditions. It becomes very crucial in
timing sensitive applications. Overdrive dispersion from
10mV overdrive to 125mV overdrive is typically less than
1.8ns (150mV total step size). The graph titled Propagation
Delay vs Common Mode Voltage shows the dispersion
due to shifts in input common mode voltage.
Jitter
The LTC6752 family has been designed for low phase
noise and jitter. This allows it to be used in applications
where high frequency low amplitude sine waves need to
be converted to full-logic level square waves with minimal additive jitter. The graph titled Output Jitter vs Input
Amplitude demonstrates the additive jitter of the LTC6752
family for different amplitudes of a sinusoidal input. Refer
to the Electrical Characteristics table to see how jitter varies
with signal frequency.
High Speed Board Design Techniques
Being very high speed devices, members of the LTC6752
family are prone to output oscillations if certain guidelines
are not followed at the board level. Low impedance supply
planes, especially for the VDD and VEE pins, help to reduce
supply bounce related oscillations. Supply bounce tends to
worsen at higher output supply voltages due to larger swings
and higher output current drive capability. Parasitic feedback
between the output and input pins should be minimized. The
pinouts of the LTC6752 family members have been arranged
to minimize parasitic feedback. Input and output traces on
the board should be placed away from each other. If that is
not possible a ground or supply trace should be used as a
guard to isolate them. If possible, a supply/ground trace that
is not directly connected to the supply pins of the device,
but rather directly connected to the supply terminal of the
board, should be used for such a purpose.
The positive supply pins should be adequately bypassed
to the VEE pin to minimize transients on the supply. Low
ESR and ESL capacitors are required due to the high speed
nature of the device. Even a few nanohenries of parasitic
trace inductance in series with the supply bypassing can
cause several hundred millivolts of disturbance on the supply
pins during output transitions. A 2.2µF capacitor in parallel
with multiple low ESL, low ESR 100nF capacitors connected
as close to the supply pins as possible to minimize trace
impedance is recommended. In many applications the VEE
pin will be connected to ground. In applications where the
VEE pin is not connected to ground, the positive supplies
should still be bypassed to VEE. The VEE pin should also then
be bypassed to a ground plane with a 2.2µF capacitor in
parallel with low ESL, low ESR 100nF capacitors if possible.
For devices with separate positive input and output supplies, capacitors should not be placed between the two
positive supplies; otherwise disturbances due to output
switching can couple back to the inputs.
To minimize supply bounce, the board layout must be made
with careful consideration of the supply current return
paths. The output current will return back to the supply
via the lowest impedance path available. If the terminating
connection of the load is easily available on the board, VEE
should be bypassed to the terminating connection using
2.2µF and 100nF capacitors as described previously.
Due to the fast rise and fall times of the LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/LTC6752-4, output traces should be
shielded with a low impedance ground plane to minimize
electromagnetic interference. Due to the complementary
nature of its outputs, the LTC6752-3 can provide a first
order cancellation of EMI effects.
When the input slew rate is small, sustained oscillations
can occur at the output pin while the input is transitioning
due to even one millivolt of ground bounce. For applications where the input slew rate is low, internal hysteresis
should not be removed by taking the LE/HYST pin high,
as the addition of hysteresis makes the comparators more
immune to disturbances such as ground bounce. Increasing hysteresis by adjusting the LE/HYST pin voltage or by
adding positive feedback as discussed in the section on
hysteresis can further improve noise immunity.
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6752fc
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical Applications
High Speed Clock Restoration/Level Translation
Circuit
Figure 9 shows the input and output waveforms of the
LTC6752-2, used to recover a distorted 150mVP-P 200MHz
signal at a common mode of 2.5V with respect to its negative supply, into a full scale 1.8V output signal. AC-coupling
could have been used at the input of the comparator, however to preserve input duty cycle information DC-coupling
may be preferable, and that is where having a wide input
common mode range is an advantage.
High speed comparators are often used in digital systems
to recover distorted clock waveforms. The separate input/
output supplies feature of the LTC6752-2 allows it to be
used in applications where signals need to be shifted from
one voltage domain to another. Figure 8 shows a circuit that
can perform both recovery and level translation functions.
In this application, the input clock signal comes from a
source operating from 5V, and the signal is required to
drive a receiver operating on 1.8V. The 5V input supply/1.8V
output supply feature of this part is ideal for such a situation.
If the input signal gets distorted and its amplitude severely
reduced due to stray capacitance, stray inductance or due
to reflections on the transmission line, the LTC6752-2 can
be used to convert it into a full scale digital output signal
that can drive the receiver.
200MHz
CLOCK
SIGNAL
VEE + 5V
LONG
TRACE
+
ATTENUATED
150mVP-P
200MHz,
VCM = 2.5V
6752 F09
Figure 9
VDD
~1.8VP-P
200MHz,
CLOCK
SIGNAL
–
VREF = VEE + 2.5V
VREF
2ns/DIV
Optical Receiver Circuit
VEE + 1.8V
LTC6752-2
VEE
VIN, 50mV/DIV
VEE + 1.8V
VCC
CLOCK/DATA
SOURCE
VOUT, 500mV/DIV
The LTC6752, along with a high speed high performance
FET input operational amplifier like the LTC6268, can be
used to implement an optical receiver as shown in Figure 10.
CLOCK/DATA
RECEIVER
Figure 11 shows the output of the LTC6268 driving the –IN
pin of the LTC6752-2, the +IN pin of the LTC6752-2, and
the LTC6752-2 output. The photodiode is being driven by
a light source of sinusoidally varying intensity.
VEE
VEE
6752 F08
Figure 8. High Speed Clock Restoration/Level
Translation/Level Shifting Circuit
3.3V
3.3V
20k
5.49k
3.3V
47.6k
–
LTC6268
–
1k
VCC
VDD
LTC6752-2
+
FCI-125
0.1µF
+
1k
3.3V
LE/HYST
VEE
Q
0V TO 3.3VOUT
SHDN
0.1µF
4.53k
6752 F10
Figure 10. Optical Receiver Circuit
6752fc
22
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical Applications
a threshold of 11mV to overcome comparator and system
offsets, and establish a low output in the absence of an
input signal. An input pulse causes the output of U1 to go
high, which then causes the output of U2 to go high. The
output of U2 is fed back to the input of the 1st comparator, Timing Capacitor C now begins charging through R.
After 100ns, U2 goes low, allowing U1 also to go low. A
new pulse at the input of U2 can now restart the process.
Timing capacitor C can be increased without limit for
longer output pulses.
5.0
4.5
4.0
3.5
3.0
500mV/DIV 2.5
OUT
2.0
IN–
1.5
IN+
1.0
0.5
0
0
10
20
30
40
50
10ns/DIV
60
70
80
Figure 13 shows input and output waveforms for the pulse
stretcher circuit.
90
6752 F11
Figure 11
Pulse Stretcher Circuit/Monostable Multivibrator
OUTPUT, 2V/DIV
For detecting short pulses from a single sensor, a pulse
stretcher is often required. The circuit of Figure 12 acts as
a one-shot, stretching the width of an incoming pulse to a
consistent ~100ns. The circuit works as follows: Comparator U1 functions as a threshold detector, and Comparator
U2 functions as a one-shot. Comparator U1 is biased with
INPUT, 20mV/DIV
20ns/DIV
6752 F13
Figure 13
3.3V
ZOUT = 50Ω
INPUT 15mV TO 3.3V PULSE
MINIMUM PULSE WIDTH 5ns
+
49.9Ω
1k
3.3V
COMPARATOR U1
VDD
LTC6752-2
15k
49.9Ω
VCC
–
OUT
VEE
OUTPUT 3.3V 100ns PULSE
LE/HYST
SHDN
1000pF
2k
22k
SOD-123
OSA
3.3V
COMPARATOR U2
OUT
VDD
VEE
VCC
+
22k
LTC6752-2
LE/HYST
SHDN
–
TIMING
CAPACITOR C
100pF
6.65k
TIMING
RESISTOR R
Figure 12
6752fc
For more information www.linear.com/LTC6752
23
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical Applications
Common Mode Rejecting Line Receiver
Fast Event Capture
Differential electrical signals being transmitted over long
cables are often attenuated. Electrical noise on the cables
can take the form of common mode signals.
The circuit shown in Figure 16 can be used to capture
small and fast events. The comparator output is used to
signal the latch pin and hold the output in the HIGH state.
The circuit will reset when the RESET line is low. An open
drain 1.5ns NAND gate is used to both invert the output
signal and is used to MUX in the RESET line from the
supervising circuit. One important feature of the NAND is
that it is open drain which allows the comparator to use
either its default 5mV of hysteresis or a user programmed
hysteresis. The latch recovery time of this circuit is roughly
210ns and is dominated by the time constant created by the
capacitance seen at the output of the NAND gate and the
20k series resistance of the LE/HYST pin. The waveforms
are shown in Figure 17.
The LTC6752 comparators can be used to retrieve attenuated differential signals that have been corrupted by high
frequency common mode noise, as shown in Figure 14.
Figure 15 shows an LTC6752-2 retrieving a 200MHz,
200mVP-P differential input signal that has 2.5V of random,
common mode noise superimposed on it. The input supply
(VCC) used was 5V and the output supply used was 2.7V.
A small amount of modulation is seen at the output due
to a small amount of differential modulation at the inputs,
which causes cycle to cycle variations in propagation delay.
3.3V
2.2μF
EVENT IN
50mV, 10ns
SMALL DIFFERENTIAL SIGNAL WITH
LARGE COMMON MODE COMPONENT
VCC = 5V
+IN
–IN
INPUT
+
VCC
REF
+
VDD = 2.7V
Q
LTC6752-2
182k
–
VDD
LTC6752-2
3.3V
200Ω
–
VEE
OUT
SHDN
NXP 74LVC1G38
RESET
6752 F14
Figure 14
Q
LE/HYST
0.1μF
VEE
0.1μF
6752 F16
Figure 16
OUT
Q
–IN +IN
RESET
500mV/DIV
500mV/DIV
INPUT
50ns/DIV
6752 F15
Figure 15
REF
50ns/DIV
6752 F17
Figure 17
6752fc
24
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Package Description
Please refer to http://www.linear.com/product/LTC6752#packaging for the most recent package drawings.
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
0.62
MAX
0.95
REF
2.90 BSC
(NOTE 4)
1.22 REF
1.4 MIN
3.85 MAX 2.62 REF
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
S5 TSOT-23 0302
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
6752fc
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25
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Package Description
Please refer to http://www.linear.com/product/LTC6752#packaging for the most recent package drawings.
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev G)
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.889 ±0.127
(.035 ±.005)
5.10
(.201)
MIN
0.42 ± 0.038
(.0165 ±.0015)
TYP
3.20 – 3.45
(.126 – .136)
0.65
(.0256)
BSC
0.254
(.010)
8
7 6 5
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
DETAIL “A”
0.52
(.0205)
REF
0° – 6° TYP
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
1
1.10
(.043)
MAX
2 3
4
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS8) 0213 REV G
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6752fc
26
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Package Description
Please refer to http://www.linear.com/product/LTC6752#packaging for the most recent package drawings.
SC6 Package
6-Lead Plastic SC70
(Reference LTC DWG # 05-08-1638 Rev B)
0.47
MAX
0.65
REF
1.80 – 2.20
(NOTE 4)
1.00 REF
INDEX AREA
(NOTE 6)
1.80 – 2.40 1.15 – 1.35
(NOTE 4)
2.8 BSC 1.8 REF
PIN 1
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.10 – 0.40
0.65 BSC
0.15 – 0.30
6 PLCS (NOTE 3)
0.80 – 1.00
1.00 MAX
0.00 – 0.10
REF
GAUGE PLANE
0.15 BSC
0.26 – 0.46
0.10 – 0.18
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
SC6 SC70 1205 REV B
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE INDEX AREA
7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70
8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB
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27
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Package Description
Please refer to http://www.linear.com/product/LTC6752#packaging for the most recent package drawings.
UD Package
12-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1855 Rev Ø)
0.70 ±0.05
3.50 ±0.05
1.65 ±0.05
2.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ±0.05
11
12
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
1.65 ±0.10
(4-SIDES)
(UD12) QFN 0709 REV Ø
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
6752fc
28
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Revision History
REV
DATE
DESCRIPTION
A
01/15
Addition of LTC6752-1 and LTC6752-4 options.
PAGE NUMBER
All
SC6 Package added.
2
Fast Event Capture added to Typical Applications.
B
C
06/15
04/17
24
Test condition for CMRR_LVCM updated: VCM = VEE – 0.2V to VCC – 1.5V
3, 6, 8
Electrical Characteristics section updated to show that VLE/HYST, RHYST, IIH_LE, IIL_LE specifications apply over the
specified temperature range.
5, 7, 9
Figure 1 updated to show hysteresis symbol.
16
The latched output disable description and Figure 7 corrected to show the latch to output delay (tPL) instead of latch
propagation delay (tPDL).
20
Addition of extended temperature range under Features
1
Addition of MP, extended temperature part
Addition of extended temperature range on Note 5
Updated web links
2, 3
9
25 to 28
6752fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC6752
29
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical Application
200MHz Clock Restoration/Level shifting
200MHz
CLOCK
SIGNAL
LONG
TRACE
VEE + 5V
CLOCK/DATA
SOURCE
VEE + 1.8V
VCC
+
VEE + 1.8V
VDD
LTC6752-2
VREF = VEE + 2.5V
VEE
ATTENUATED
150mVP-P
200MHz,
VCM = 2.5V
–
~1.8VP-P
200MHz,
CLOCK
SIGNAL
VOUT, 500mV/DIV
CLOCK/DATA
RECEIVER
VEE
VIN, 50mV/DIV
VREF
VEE
6752 TA02a
6752 TA02b
2ns/DIV
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
High Speed Comparators
LT1715
4ns 150MHz Dual Comparators
4.6mA at 3V
LT1711
High Speed Rail-to-Rail Comparators
3V/5V/±5V, 4.5ns at 20mV Overdrive
LT1713/LT1714
Single/Dual Low Power Rail-to-Rail Comparators
2.7V/5V/±5V, 7ns at 20mV Overdrive
LT1719/LT1720
Dual/Quad 4.5ns Rail-to-Rail Output Comparators
4mA/Comparator, 7ns at 5mV Overdrive
LT1394
7ns Single Supply Ground Sensing Comparator
6mA, 800μV Offset
Clock Buffers/Logic Converters
LTC6957-1/LTC6957-2/ Low Phase Noise, Dual Output Buffer/Driver/Logic
LTC6957-3/LTC6957-4 Converter
LVPECL/LVDS/CMOS Outputs, Additive Jitter 45fsRMS (LTC6957-1)
High Speed Operational Amplifiers
LTC6252/LTC6253/
LTC6254
Single/Dual/Quad 3.5mA 720MHz
280V/μs, 2.75nV/√Hz, Rail-to-Rail I/O
LTC6246/LTC6247/
LTC6248
Single/Dual/Quad 1mA, 180MHz
90V/μs, 4.2nV/√Hz,Rail-to-Rail I/O
LTC6255/LTC6256/
LTC6257
Single/Dual/Quad 65µA, 6.5MHz
LTC6240/LTC6241/
LTC6242
18MHz, Low Noise, CMOS
Rail-to-Rail Outputs
LTC6406
3GHz, Differential Amplifier/Driver
Rail-to-Rail Inputs
LTC6409
10GHz Differential Amplifier/ADC Driver
1.1nV/√Hz
6752fc
30
LT 0417 REV C • PRINTED IN USA
For more information www.linear.com/LTC6752
www.linear.com/LTC6752
 LINEAR TECHNOLOGY CORPORATION 2014