TI DRV3204-Q1 Three-phase brushless motor driver Datasheet

DRV3204-Q1
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SLVSBT3B – MARCH 2013 – REVISED JULY 2013
Three-Phase Brushless Motor Driver
Check for Samples: DRV3204-Q1
FEATURES
DESCRIPTION
•
The DRV3204-Q1 device is a field-effect transistor
(FET) pre-driver designed for three-phase motor
control for applications such as an oil pump or a
water pump. The device has three high-side pre-FET
drivers and three low-side drivers which are under the
control of an external MCU. A charge pump supplies
the power for the high side, and there is no
requirement for a bootstrap capacitor. For
commutation, this integrated circuit (IC) sends a
conditional motor signal and output to the MCU.
Diagnostics provide undervoltage, overvoltage,
overcurrent, overtemperature and power-bridge
faults. One can measure the motor current using an
integrated current-sense amplifier and comparator in
a battery common-mode range, which allows the use
of the motor current in a high-side current-sense
application. External resistors set the gain. One can
configure the pre-drivers and other internal settings
through the SPI.
1
•
•
•
•
•
•
•
•
•
•
•
3-Phase Pre-Drivers for N-Channel MOS FieldEffect Transistors (MOSFETs)
Pulse-Width Modulation (PWM) Frequency up
to 20 kHz
Fault Diagnostics
Charge Pump
Phase Comparators
Microcontroller (MCU) Reset Generator
Serial Port I/F (SPI)
Motor-Current Sense
5-V Regulator
Low-Current Sleep Mode
Operation VB Range From 5.3 V to 26.5 V
48-Pin PHP
APPLICATIONS
•
•
•
Oil Pump
Fuel Pump
Water Pump
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
DRV3204-Q1
SLVSBT3B – MARCH 2013 – REVISED JULY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
WH
WHS
VH
VHS
UH
UHS
CPDR4
PDCPV
CPDR3
CPDR1
NGND
CPDR2
48-PIN PHP
(Top View)
48 47 46 45 44 43 42 41 40 39 38 37
VB
1
36
FAULT
TEST
2
35
PRN
CTLUH
3
34
DIN
CTLVH
4
33
SCK
CTLWH
5
32
CS
UL
6
31
VDD
DOUT
DRV3204-Q1
VL
7
30
WL
8
29
GND
CTLUL
9
28
PHTM
CTLVL
10
27
PH1M
CTLWL
11
26
PH2M
VCC
12
25
PH3M
RES
ENABLE
PMV1
PMV2
AREF
PMV3
ALFB
ALP
ALM
ALV
VCCB
VCFB
13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTIONS
PIN
NAME
NO.
TYPE
MAXIMUM
RATING
ALFB
18
O
-0.3 V-40 V
Motor current-sense amplifier feedback
ALM
16
I
-0.3 V-40 V
Motor current-sense amplifier negative input
ALP
17
I
-0.3 V-40 V
Motor current-sense amplifier positive input
ALV
15
O
-0.3 V-6 V
Motor current-sense amplifier output
AREF
19
O
-0.3 V-40 V
Reference output of motor current- sense amplifier
CPDR1
47
O
-0.3 V-40 V
Charge-pump output
CPDR2
46
O
-0.3 V-40 V
Charge-pump output
CPDR3
45
O
-0.3 V-40 V
Charge-pump output
CPDR4
44
O
-0.3 V-40 V
Charge-pump output
CS
32
I
-0.3 V-6 V
SPI chip select
CTLUH
3
I
-0.3 V-6 V
Pre-driver parallel input
CTLUL
9
I
-0.3 V-6 V
Pre-driver parallel input
CTLVH
4
I
-0.3 V-6 V
Pre-driver parallel input
CTLVL
10
I
-0.3 V-6 V
Pre-driver parallel input
CTLWH
5
I
-0.3 V-6 V
Pre-driver parallel input
CTLWL
11
I
-0.3 V-6 V
Pre-driver parallel input
2
FUNCTION
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PIN FUNCTIONS (continued)
PIN
NAME
NO.
TYPE
MAXIMUM
RATING
FUNCTION
DIN
34
I
-0.3 V-6 V
SPI data input
DOUT
30
O
-0.3 V-6 V
SPI data output
ENABLE
23
I
-0.3 V-40 V
Enable input
FAULT
36
O
-0.3 V-6 V
Diagnosis output
GND
29
I
-0.3 V-0.3 V
GND
NGND
48
I
-0.3 V-0.3 V
Power GND
PDCPV
43
O
-0.3 V-40 V
Charge pump output
PH1M
27
I
-1 V-40 V
Phase comparator input
PH2M
26
I
-1 V-40 V
Phase comparator input
PH3M
25
I
-1 V-40 V
Phase comparator input
PHTM
28
I
-1 V-40 V
Phase comparator reference input
PMV1
22
O
-0.3 V-6 V
Phase comparator output
PMV2
21
O
-0.3 V-6 V
Phase comparator output
PMV3
20
O
-0.3 V-6 V
Phase comparator output
PRN
35
I
-0.3 V-6 V
Watchdog timer-pulse input
RES
24
O
-0.3 V-6 V
MCU reset output
SCK
33
I
-0.3 V-6 V
SPI clock
TEST
2
I
-0.3 V-20 V
TEST input
UH
42
O
-5 V-40 V
Pre-driver output
UHS
41
O
-5 V-40 V
Pre-driver reference
UL
6
O
-0.3 V-20 V
Pre-driver output
VB
1
I
-0.3 V-40 V
VB input
VCC
12
I
-0.3 V-6 V
VCC supply input
VCCB
13
O
-0.3 V-40 V
VCC regulator base driver of PNP external transistor
VCFB
14
I
-0.3 V-40 V
VCC regulator current-sense input
VDD
31
O
-0.3 V-3.6 V
VDD supply output
VH
40
O
-5 V-40 V
Pre-driver output
VHS
39
O
-5 V-40 V
Pre-driver reference
VL
7
O
-0.3 V-20 V
Pre-driver output
WH
38
O
-5 V-40 V
Pre-driver output
WHS
37
O
-5 V-40 V
Pre-driver reference
WL
8
O
-0.3 V-20 V
Pre-driver output
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BLOCK DIAGRAM
1
Charge Pump
TEST
(OPEN)
2
VHS
WH
WHS
42
41
40
39
38
37
PDCPV
43
VH
44
UHS
45
UH
CPRD4
PDCPV
CPRD3
46
PDCPV
VB
47
PDCPV
48
CPRD2
NGND
CPRD1
VB
36
FAULT
35
PRN
VMS
TEST I/F
VM
VB
Battery
CTLUH
3
CTLVH
4
CTLWH
5
VCP12
VB
Monitor
TSD
34
DIN
33
SCK
32
CS
UH
VH
WH
Control Logic
UL
6
VL
7
VCP12
31
3.3V Reg
VDD
WHS
VHS
30
8
CTLUL
9
M
UHS
OVAD
NGND
WL
DOUT
OSC
VCC
WD
29
GND
UL
COMP
+
28
PHTM
ADTH
CTLWL
11
12
AMP
+
-
PH1M
26
PH2M
25
PH3M
UHS
VHS
SLEEP
21
22
23
24
RES
AREF
ALFB
ALP
20
ENABLE
19
PMV1
18
PMV2
17
27
VL
WL
+
PMV3
16
ALM
15
ALV
WHS
VM
VMS
VCCB
14
VCFB
VCFB
13
VCCB
VB
5V Reg
-
VB
AMP
VCC
VCC
+
COMP
-
COMP
10
COMP
VCC
CTLVL
VCOM
VCC
Figure 1. Top Block Diagram
4
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SLVSBT3B – MARCH 2013 – REVISED JULY 2013
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
ESD
MAX
UNIT
(1)
ESD all pins
ESD performance of all pins to any other
pin
HBM model
-2
2
kV
CDM model
-500
500
V
TEMPERATURE
TA
Operating temperature range
-40
125
ºC
TJ
Junction temperature
-40
150
ºC
Tstg
Storage temperature
-55
175
ºC
(1)
Performance of ESD testing is according to the ACE-Q100 standard.
THERMAL INFORMATION
DRV3204-Q1
THERMAL METRIC (1)
PHP
UNIT
48 PINS
Junction-to-ambient thermal resistance (2)
θJA
(3)
26.1
°C/W
θJCtop
Junction-to-case (top) thermal resistance
11.5
°C/W
θJB
Junction-to-board thermal resistance (4)
7.2
°C/W
ψJT
Junction-to-top characterization parameter (5)
0.2
°C/W
ψJB
Junction-to-board characterization parameter
(6)
7.1
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance (7)
0.4
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
spacer
SUPPLY VOLTAGE AND CURRENT
VB = 12 V, TA = -40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY INPUT
VB1 (1)
VB supply voltage (motor operation)
5.3
12
18
V
VB2 (1)
VB supply voltage (MCU operation)
4.5
12
18
V
VB3 (2)
VB supply voltage
18
26.5
V
Ivb
VB operating current
ENABLE = High, no PWM
-
18
27
mA
Ivbq
VB quiescent current
ENABLE = Low
-
50
100
µA
(1)
(2)
Performance of supply voltage 5.3 V-18 V is according to the ACE-Q100 (Grade 1) standard.
Specified by design.
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DETAILED DESCRIPTION
WATCHDOG
Description:
A watchdog monitors the PRN signal and VCC supply level and generates a reset to the MCU via the RES pin if
the status of PRN is not normal or VCC is lower than the specified threshold level. Detection of a special pattern
on the PRN input during power up can disable the watchdog.
VCC
VDD
3k
VDD Under Voltage
Detection
RES
To MCU
Max 100pF
VCC
VCC Under Voltage
Detection
Reset
Logic
OSC1
Clock
Monitor
VCC
100k
PRN
Watch Dog Timer
WDT
WDT
Enable
From MCU
Digital Pattern
Detection
Figure 2. Watchdog Block Diagram
6
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VCC
SLVSBT3B – MARCH 2013 – REVISED JULY 2013
VCCUV
VSTN
tRES
VDDUV
VDD
tRH
tRES
RES
tON
tON
tON
tRL
PRN
Pwth
tOFF
Rising edge of PRN is
detected to reset
watchdog timer.
NOTE: VCC undervoltage condition sets RES = Low.
Figure 3. Watchdog Timing Chart
WATCHDOG ELECTRICAL CHARACTERISTICS (3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
-
0.8
1.3
V
VB = 12 V, TA = -40°C to 125℃
℃ (unless otherwise specified)
WATCHDOG
VSTN (1)
(1)
tON
tOFF
(1)
Function start VCC voltage RES
Power-on time RES
2.5
3
3.5
ms
Clock-off reset time RES
64
80
96
ms
16
20
24
ms
tRL
(1)
Reset-pulse low time RES
tRH
(1)
See Figure 3
Reset-pulse high time RES
64
80
96
ms
tRES
(1)
Reset delay time RES
30
71.5
90
µs
Pwth
(1)
Pulse duration PRN
2
-
-
µs
(3)
(1)
The timing parameters are invalid if watch dog timer is disabled.
Specified by design
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SERIAL PORT I/F
Description:
Seting device configuration and reading out diagnostic information is via SPI. SPI operates in slave mode. SPI
uses four signals according to the timing chart of Figure 5.
Status
CS
SPI Control Logic and
8-Bit Shift Register
Enable
8-Bit Shift Register
DOUT
DIN
SCK
Address
Write Data
Register Map
Read Data
System Clock
Figure 4. Block Diagram of SPI
CS - Chip Select
The MCU uses CS to select this IC. CS is normally high, and communication is possible only when it is forced
low. When CS falls, communication between this IC and the MCU starts. The transmitted data are latched and
the DOUT output pin comes out of high impedance. When CS rises, communication stops. The DOUT output pin
goes into high impedance. The next falling edge starts another communication. There is a minimum waiting time
between two communications (twait). The pin has an internal pullup.
SCK - Synchronization Serial Clock
The MCU uses SCK to synchronize communication. SCK is normally low, and the valid clock-pulse number is 16.
At each falling edge, the MCU writes a new bit on the DIN input, and this IC writes a new bit on the DOUT output
pin. At each rising edge, this IC reads the new bit on DIN, and the MCU reads the new bit on DOUT. The
maximum clock frequency is 4 MHz. The pin has an internal pulldown.
DIN - Serial Input Data
DIN receives 16-bit data. The order of received bits is from the MSB (first) to the LSB (last). The pin has an
internal pulldown. Update of the internal register with the received bits occurs only if the number of clock pulses
is 16 while CS is low.
DOUT - Serial Output Data
DOUT transmits 16-bit data. It is a three-state output, and it is in the high-impedance state when CS is high. The
order of serial data-bit transmission is from the MSB (first) to the LSB (last).
8
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SPI ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VB = 12 V, TA = -40°C to 125℃
℃ (unless otherwise specified)
SPI
fop
SPI clock frequency
tlead
(1)
Enable lead time
twait
(1)
Wait time between two successive communications
-
4
200
-
-
MHz
ns
5
-
-
µs
tlag
(1)
Enable lag time
100
-
-
ns
tpw
(1)
SCLK pulse duration
100
-
-
ns
tsu
(1)
Data setup time
100
-
-
ns
Data hold time
100
-
-
ns
(1)
th
tdis
(1)
Data-output disable time
-
-
200
ns
ten
(1)
Data-output enable time
-
-
100
ns
0
-
100
ns
(1)
tv
(1)
Data delay time, SCK to DOUT
CL = 50 pF, see Figure 6.
Specified by design
tlead
tpw
ttwaitt
tlag
tpw
CS
SCK
DIN
MSB
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
th
tsu
MSB
DOUT
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
HiZ
HiZ
tdel
ten
tdis
Figure 5. SPI Timing Diagram
Table 1. SPI Serial Input Format
MSB
D14
D13
D12
D11
D10
D9
D8
DIN
RW[1]
RW[0]
Addr[5]
Addr[4]
Addr[3]
Addr[2]
Addr[1]
Addr[0]
D7
D6
D5
D4
D3
D2
D1
LSB
DIN
Data[7]
Data[6]
Data[5]
Data[4]
Data[3]
Data[2]
Data[1]
Data[0]
D8
Table 2. SPI Serial Output Data Format
DOUT
DOUT
MSB
D14
D13
D12
D11
D10
D9
0
Frame fault
0
0
0
0
0
1
D7
D6
D5
D4
D3
D2
D1
LSB
Data[7]
Data[6]
Data[5]
Data[4]
Data[3]
Data[2]
Data[1]
Data[0]
SPI serial input and output format
RW[1:0]
: 01: write mode; 00: read mode
Addr[5:0]
: Address of SPI access
Data[7:0]
: Input data to write or output data to read
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: 0: No error exists in the previous SPI frame.
: 1: Error exists in the previous SPI frame.
Table 3. SPI Register Map
Register
Name
Addr
(Hex)
Reserved
00
CFGUNLK
01
FLTCFG
02
Reserved
03
FLTEN0
04
FLTEN1
05
SDNEN0
06
SDNEN1
07
FLTFLG0
08
FLTFLG1
09
CSCFG
0A
PDCFG
0B
DIAG
0C
SPARE
0D
Reserved
b7
b6
b5
b4
b3
b2
b1
b0
RSVD
00
RSVD
CFGUNLK
FLGLATCH_EN
MTOCTH
00
RSVD
VCCUVTH
VBUVTH
00
FE_CPOV
FE_CPUV
FE_VBOV
FE_VBUV
FE_TSD
01
SE_CPOV
SE_CPUV
SE_VBOV
SE_VBUV
FF
SE_TSD
01
CPOV
CPUV
VBOV
VBUV
00
TSD
00
RSVD
FE_MTOC
FE_VCCOC
FE_VCCOV
FE_VDDOV
SE_MTOC
SE_VCCOC
SE_VCCOV
SE_VDDOV
MTOC
VCCOC
VCCOV
00
RSVD
RSVD
VDDOV
RSVD
RSVD
CSOFFSET
RSVD
VCCUVRST
SPARE
WDTRST
00
CMRST
SEL_COMP_HYS
RSVD
FF
00
DEADT
RSVD
0E-3F
Reset
(Hex)
00
00
00
REGISTER DESCRIPTIONS
Access type: R = Read and W = Write.
Reserved register: Read of reserved bits return 0 and write has no effect.
CFGUNLK (address 0x01): Configuration Unlock Register
Bit
Name
Type
Reset
Description
3:0
CFGUNLK
RW
0000
DRV3204 SPI register map has lock and unlock mode, and it is in lock mode by default. MCU
can write values of the following registers in unlock mode;
● FLTCFG
● FLTEN0 and FLTEN1
● SDNEN0 and SDNEN1
● CSCFG
● PDCFG
● WDCFG
In lock mode, read returns the values, but writing the registers have no effect.
Device enters unlock mode by writing 0x5, 0x8, 0x7 to CFGUNLK register in series. Device exits
from unlock mode by writing 0x0.
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FLTCFG (address 0x02): Fault Detection Configuration Register
Bit
Name
Type
Reset
Description
7
FLGLATCH_EN
RW
0
Fault-flag (FLTFLG*) latch enable
0: Fault events do not latch fault-flag register bits.
1: Latching of fault-flag register bits by the fault events occurs. The flag bits remain asserted until
cleared.
6:4
MTOCTH
RW
000
Motor overcurrent detection threshold
000: 2 V
001: 2.5 V
010: 3 V
011: 3.5 V
100: 4 V
Others: 2 V
3
RSVD
R
0
Reserved
2
VCCUVTH
RW
0
VCC undervoltage detection threshold
0: 4 V
1: 4.2 V
1:0
VBUVTH
RW
00
VB undervoltage detection threshold
00: 4 V
01: 4.5 V
10: 5 V
11: 5.5 V
FLTEN0 (address 0x04): FAULT Pin Enable Register 0
Bit
Name
Type
Reset
Description
7
FE_MTOC
RW
1
6
FE_VCCOC
RW
1
5
FE_VCCOV
RW
1
FAULT pin enable of FLTFLG0 register bits.
0: Assertion of the FAULT pin does not occur when the fault flag bit is 1
1: Assertion of the FAULT pin to low level occurs when the fault flag bit is 1. See Figure 6
4
FE_VDDOV
RW
1
3
FE_CPOV
RW
1
2
FE_CPUV
RW
1
1
FE_VBOV
RW
1
0
FE_VBUV
RW
1
FLTEN1 (address 0x05): FAULT Pin Enable Register 1
Bit
Name
Type
Reset
Description
7:1
RSVD
R
0000 000 Reserved
0
FE_TSD
RW
1
FAULT pin enable of TSD flag bit
0: Assertion of the FAULT pin does not occur when the fault flag bit is 1
1: Assertion of the FAULT pin to low level occurs when the TSD flag bit is 1. See Figure 6
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FE_MTOC
MTOC
FE_VCCOC
VCCOC
FE_VCCOV
VCCOV
FE_VDDOV
VDDOV
FE_CPOV
CPOV
FAULT
FE_CPUV
CPUV
FE_VBOV
VBOV
FE_VBUV
VBUV
FE_TSD
TSD
Figure 6. FAULT Pin Enable Logic
SDNEN0 (address 0x06): Pre-Driver Shutdown Enable Register 0
Bit
Name
Type
Reset
Description
7
SE_MTOC
RW
1
6
SE_VCCOC
RW
1
5
SE_VCCOV
RW
1
4
SE_VDDOV
RW
1
Pre-driver shutdown enable of FLTFLG0 register bits
0: Disabling of the pre-driver outputs does not occur when the fault flag bit is 1.
1: Disabling of the pre-driver outputs occurs when the fault flag bit is 1. Both the high-side
and low-side FETs turn off.
See Figure 7.
3
SE_CPOV
RW
1
2
SE_CPUV
RW
1
1
SE_VBOV
RW
1
0
SE_VBUV
RW
1
SDNEN1 (address 0x07): Pre-Driver Shutdown Enable Register 1
Bit
Name
Type
Reset
Description
7:1
RSVD
R
0000 000
Reserved
0
SE_TSD
RW
1
Pre-driver shutdown enable of TSD flag bits
0: Disabling of the pre-driver outputs does not occur when the TSD flag bit is 1.
1: Disabling of the pre-driver outputs occurs when the TSD flag bit is 1. Both the high-side and
low-side FETs turn off.
See Figure 7.
12
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SE_MTOC
MTOC
SE_VCCOC
VCCOC
SE_VCCOV
Pre-driver
control
VCCOV
SE_VDDOV
VDDOV
SE_CPOV
enable
CPOV
SE_CPUV
CPUV
SE_VBOV
VBOV
SE_VBUV
VBUV
SE_TSD
TSD
Figure 7. Pre-Driver Shutdown Logic
FLTFLG0 (address 0x08): Fault Flag Register 0
Bit
Name
Type (1)
Reset
Description
Fault flag bits of the following conditions; (2)
7
MTOC
RW
0
MTOC: Motor overcurrent. (OVAD)
6
VCCOC
RW
0
VCCOC: VCC overcurrent
5
VCCOV
RW
0
VCCOV: VCC overvoltage
4
VDDOV
RW
0
VDDOV: VDD overvoltage
3
CPOV
RW
0
CPOV: Charge-pump overvoltage
2
CPUV
RW
0
CPUV: Charge-pump undervoltage
1
VBOV
RW
0
VBOV: VB overvoltage
0
VBUV
RW
0
VBUV: VB undervoltage
If FLTCFG.FLGLATCH_EN = 1
0: Read = No fault condition exists since last cleared.
Write = No effect
1: Read = Fault condition exists.
Write = Clear the flag.
If FLTCFG.FLGLATCH_EN = 0
0: Read = No fault condition
Write = No effect
1: Read = Fault condition
Write = No effect
(1)
(2)
R: Read, W: Write
Assertion of the fault flags may occur during power up.
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FLGFLT1 (address 0x09): Fault Flag Register 1
Bit
Name
Type (1)
Reset
Description
7:1
RSVD
R
0000
000
Reserved
0
VBUV
RW
1
Fault flag bit of thermal shutdown condition. (2)
If FLTCFG.FLGLATCH_EN = 1
0: Read = No fault condition exists since last cleared.
Write = No effect
1: Read = Fault condition exists.
Write = Clear the flag
If FLTCFG.FLGLATCH_EN = 0
0: Read = No fault condition
Write = No effect
1: Read = Fault condition
Write = No effect
(1)
(2)
R: Read, W: Write
Assertion of the fault flags may occur during power up.
CS
SCK
Fault Event
Status N
Status N+1
Status N
SPI Read Buffer
Status N+1
FLTFLG*
Status N
SPI DOUT
Serial Output Format
FLTFLG*
Status N+1
Serial Output Format
Figure 8. SPI Data-Out Timing Chart of Fault Flag Registers
14
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0
FLGLATCH_EN
1
Fault
Status
0
FLTFLG
Fault
1
SPI Access
to FLTFLG
Read
Write 1
to cClear
(1)
FAULT
H
L
Pre-Driver(2)
Enable
Disable
(1)
Assertion of FAULT occurs if FLTEN = 1.
(2)
Disabling of pre-driveroccurs if SDNEN = 1.
Figure 9. FLGFLG and FLGLATCH_EN
CSCFG (address 0x0A): Current Sense Configuration Register
Bit
Name
Type (1)
Reset
Description
7:3
RSVD
R
0000 0
Reserved
2:0
CSOFFSET RW
000
Current-sense offset
000: 0.5 V
001: 1 V
010: 1.5 V
011: 2 V
100: 2.5 V
Others: 0.5 V
(1)
R: Read W: Write
PDCFG (address 0x0B): Pre-Driver Configuration Register
Bit
Name
Type (1)
Reset
7:2
RSVD
R
0000 00 Reserved
1:0
DEADT
RW
00
(1)
Description
Dead time (= tdead)
00: 2 µs
01: 1.5 µs
10: 1 µs
11: 0.5 µs
The actual dead time has ±0.2 µs variation from the typical value.
R: Read W: Write
DIAG (address 0x0C): Diagnosis Register
Bit
Name
Type
Reset
Description
7:3
RSVD
R
0000 0
Reserved
2
VCCUVRST
R
0
nRES reset source information
1
WDTRST
R
0
Bit 2 = VCCUVRST - VCC undervoltage
0
CMRST
R
0
Bit 1 = WDTRST - watchdog timer
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Bit
Name
Type
Reset
www.ti.com
Description
Bit 0 = CMRST - clock monitor
0: Read = Reset has not occurred.
Write = No effect
1: Read = A corresponding reset source caused the last reset condition.
Write = No effect
Read access to this register clears the bits.
SPARE (address 0x0D): Spare Register
Bit
Name
Type (1)
Reset
Description
7:2
SPARE
RW
0000
00
Spare registers for future use. Read and write have no effect.
1:0
SEL_COMP_HY RW
S
00
Select phase comparator hysteresis voltage. The following show the typical values.
MM 00: 0 V
MM 01: 25 mV
MM 10: 50 mV
MM 11: 100 mV
(1)
R: Read W: Write
CHARGE PUMP
Description:
The charge-pump block generates a supply for the high-side and low-side pre-drivers to maintain the gate
voltage on the external FETs. Use of an external storage capacitor (CCP) and bucket capacitors (C1, C2)
supports pre-driver slope and switching-frequency requirements. R1 and R2 can reduce switching current if
required. The charge pump has voltage-supervisor functions such as over- and undervoltage, and selectable
stop conditions for pre-drivers.
16
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VB
CP Supervisor
CP Logic
CP12
S2
CPCLK
PDCPV
VF
MAX
UV
CPDR2
C1
R1
CPDR1
S1
NGND
CCP
PDCPV
S4
VF
VF
CPDR4
C2
R2
CPDR3
S3
NGND
Figure 10. Charge-Pump Block Diagram
Table 4. Charge-Pump Electrical Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VB = 12 V, TA = -40°C to 125℃
℃ (unless otherwise specified)
CHARGE PUMP
Vchv1_0
Output voltage, PDCPV
VB = 5.3 V, Iload = 0 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+7
VB+8
-
V
Vchv1_1
Output voltage, PDCPV
VB = 5.3 V, Ioad = 5 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+5.5
VB+6.5
-
V
Vchv1_2
Output voltage, PDCPV
VB = 5.3 V, Ioad = 8 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+4.5
VB+5.5
-
V
Vchv2_0
Output voltage, PDCPV
VB = 12 V, Ioad = 0 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+10
VB+12
VB+14
V
Vchv2_1
Output voltage, PDCPV
VB = 12 V, Ioad = 11 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+9.5
VB+11.
5
VB+13.5
V
Vchv2_2
Output voltage, PDCPV
VB = 12 V, Ioad = 18 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+9
VB+11
VB+13
V
Vchv3_0
Output voltage, PDCPV
VB = 18 V, Ioad = 0 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+10
VB+12
VB+14
V
Vchv3_1
Output voltage, PDCPV
VB = 18 V, Ioad = 13 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+10
VB+12
VB+14
V
Vchv3_2
Output voltage, PDCPV
VB = 18 V, Ioad = 22 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF, R1 = R2 = 0 Ω
VB+10
VB+12
VB+14
V
VchvOV
Overvoltage detection threshold
35
37.5
40
V
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Table 4. Charge-Pump Electrical Characteristics (continued)
PARAMETER
VchvUV
tchv
(1)
Rise time
Ron
(1)
CONDITIONS
MIN
TYP
MAX
UNITS
VB+4
VB+4.5
VB+5
V
VB = 5.3 V, C1 = C2 = 47 nF, CCP = 2.2 µF,
R1 = R2 = 0 Ω, Vchv, UV released
1
2
See Figure 10
8
Undervoltage detection threshold
On-resistance, S1-S4
ms
Ω
Specified by design
Pre-Driver
Description:
The pre-driver block provides three high-side pre-drivers and three low-side pre-drivers to drive external Nchannel MOSFETs. The turnon side of the high-side pre-drivers supplies the large N-channel transistor current
for quick charge, and PMOS supports output voltages up to PDCPV. The turnoff side of the high-side pre-drivers
supplies the large N-channel transistor current for quick discharge. The low-side pre-drivers supply the large Nchannel transistor current for charge and discharge. VCP12 (created by a charge pump) controls the output
voltage of the low-side pre-driver to output less than 18 V. The pre-driver has a stop condition in some fault
conditions ( Fault Detection ) and SPI set ( Serial Port I/F ).
High Side Pre Driver
PDCPV
CTLxH
H : PU on
L : PD on
PD CTRL
UH/V
H/WH
RL
CL
UHS/
VHS/
WHS
Low Side Pre Driver
VCP12
CTLxL
H : PU on
L : PD on
PD CTRL
PDCPV
LVS
UL/VL
/WL
RL
CL
NGND
Figure 11. Pre-Driver Block Diagram
18
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Table 5. Pre-Driver Electrical Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.35
2.7
V
25
50
mV
135
270
Ω
Ω
VB = 12 V unless otherwise stated, TA = -40ºC to 125℃
℃, unless otherwise specified
HIGH-SIDE PRE-DRIVER
VOH_H
Output voltage, turnon side
Isink = 10 mA, PDCPV - xH
VOL_H
Output voltage, turnoff side
Isource = 10 mA, xH - xHS
RONH_HP
On-resistance, turnon side (Pch)
U(V/W)H = PDCPV - 1 V
RONH_HN
On-resistance, turnon side (Nch)
U(V/W)H = PDCPV - 2.5 V
RONL_H
On-resistance turnoff side
ton_h1
(1)
Turnon time
CL = 12 nF, RL = 0 Ω from 20% to 80%
50
toff_h1
(1)
4
8
2.5
5
Ω
-
200
ns
Turnoff time
CL = 12 nF, RL = 0 Ω from 80% to 20%
50
-
200
ns
th-ondly1
(1)
Output delay time
CL = 12 nF, RL = 0 Ω to 20%, no dead time
-
200
-
ns
th-offdly1
(1)
Output delay time
CL = 12 nF, RL = 0 Ω to 80%, no dead time
-
200
-
ns
Gate-source high -side voltage
difference
xH-xHS
18
V
V
VGS_hs
-0.3
LOW-SIDE PRE-DRIVER
VOH_L1
Output voltage, turnon side
VB = 12 V, Isink = 10 mA, xL -NGND
10
12
14
VOH_L2
Output voltage, turnon side
VB = 5.3 V, Isink = 10 mA, xL - NGND
5.5
7.5
10
V
VOL_L
Output voltage, turnoff side
Isource = 10 mA, xL - NGND
-
25
50
mV
RONH_L
On-resistance, turnon side
-
6
12
Ω
RONL_L
On-resistance, turnoff side
2.5
5
Ω
Turnon time
CL = 18 nF, RL = 0 Ω,
from 20% to 80% of 12 V,
from 20% to 80% of 6 V (VB = 5.3 V)
50
-
200
ns
Turnoff time
CL = 18 nF, RL = 0 Ω,
from 80% to 20% of 12 V,
from 80% to 20% of 6 V (VB = 5.3 V)
50
-
200
ns
tl-ondly
(1)
Output delay time
CL = 18 nF, RL = 0 Ω,
to 20% of 12 V,
to 20% of VOH = 6 V (VB = 5.3 V),
no dead time
-
200
-
ns
tl-offdly
(1)
Output delay time
CL = 18 nF, RL = 0 Ω,
to 80% of 12 V,
to 80% of VOH = 6 V (VB = 5.3 V),
no dead time
-
200
-
ns
(1)
ton_l
toff_h
(1)
tdiff1
(1)
Differential time1
(Th-on) - (Tl-off), no dead time,
See Figure 12
-200
0
200
ns
tdiff2
(1)
Differential time2
(Tl-on) - (Tl-off), no dead time,
See Figure 12
-200
0
200
ns
2.2
1.7
1.2
0.7
µs
tdead
(1)
(1)
Dead time
OSC1 = 10 MHz SPI register PDCFG.DEADT
2
1.5
1
0.5
Specified by design
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CTLUH
CTLVH
CTLWH
CTLUL
CTLVL
CTLWL
th-ondly
UH
VH
WH
th-offdly
80%
80%
20%
20%
th-on(th-ondly + ton)
UL
VL
WL
xHS
th-off(th-offdly + toff)
80%
80%
20%
NGND
20%
tl-offdly
tl-ondly
tl-off(tl-offdly + toff)
tl-on(tl-ondly + ton)
NOTE: This diagram excludes dead time to explain the timing parameters of the pre-driver.
Figure 12. Delay Time From Input to Output
CTLUH
CTLVH
CTLWH
CTLUL
CTLVL
CTLWL
UH
VH
WH
tdead + th-ondly
th-offdly
UL
VL
WL
tl-offdly
tdead + tl-ondly
Figure 13. Dead Time
Phase Comparator
Description:
The three-channel comparator module monitors the external FETs by detecting the drain-source voltage across
the high-side and low-side FETs. PHTM is the threshold level of the comparators usable for sensorless
communication. Figure 14 shows an example of the threshold level.
20
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UHS,
VHS,
WHS
PH1M
PH2M
PH3M
VB
VCC
+
PMV1
PMV2
PMV3
Clamp
PHTM
-
Clamp
Figure 14. Phase Comparator Block Diagram
Table 6. Phase Comparator Electrical Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VB = 12 V, TA = -40°C to 125℃
℃ (unless otherwise specified)
PHASE COMPARTOR
Viofs
Input offset voltage
-15
-
15
mV
Vinm
Input voltage range, PHTM
1.3
-
4.5
V
Vinp
Input voltage range, PHxM
-1
-
VB
V
-
0
-
12.5
25
50
25
50
100
50
100
200
0.9 ×
VCC
-
-
V
Vhys
Threshold hysteresis voltage
SPI register SPARE. SEL_COMP_HYS
mV
VOH
Output high voltage
Isink = 2.5 mA
VOL
Output low voltage
Isource = 2.5 mA
-
-
0.1 ×
VCC
V
tres_tr
(1)
Response time, rising
CL = 100 pF
-
0.7
1.5
µs
tres_tf
(1)
Response time, falling
CL = 100 pF
-
0.7
1.5
µs
(1)
Specified by design
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Motor-Current Sense
Description:
Operational amplifier is operating with an external resistor network for higher flexibility to adjust the current
measurement to application requirements. The first-stage amplifier is operating with the external resistor and the
output voltage up to VB at ALFB. The gain of amplifier is adjustable by external resistors from ×10 to ×30. The
second-stage amplifier is buffer to MCU at ALV. Current sense has comparator for motor overcurrent (OVAD).
ADTH is overcurrent threshold level and set value by SPI. Figure 15 shows the curve of detection level. ALFB is
divided by 2 and compare this value with ADTH. In recommended application, zero-point adjustment is required
as large error offset in initial condition.
OVAD
VCC
+
-
ADTH
1/2ALFB
CLAMP
VCC
CLAMP
+
ALV
-
VB
-
ALFB
+
R22
C1
Battery
R11
ALP
ALM
Imotor
Rshunt
R12
R21
VCC
M
AREF
+
-
DC
C2
CLAMP
*R11, R12, R21, R22 z 0.1%
*VGain
X10: R11 = R12 = 3 k , R21 = R22 = 30 k
X20: R11 = R12 = 1.5 k , R21 = R22 = 30 k
X30: R11 = R12 = 1 k , R21 = R22 = 30 k
*C1 = 0~10 pF
*C2 = 10 nF
*AREF: 0.5/1.0/1.5/2.0/2.5 V (SPI)
*ADTH: 2.0/2.5/3.0/3.5/4.0 V (SPI)
*ALV = VGain * (Rshunt * Imotor) + AREF
*OVADth = (2 * ADTH - AREF) / (Rshunt * VGain)
Figure 15. Motor Current-Sense Block Diagram
22
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Table 7. Motor Current-Sense Electrical Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VB = 12 V, TA = -40°C to 125℃
℃ (unless otherwise specified)
MOTOR CURRENT SENSE
VOfs
Input offset voltage
-5
VO_0
Output voltage, ALV
Imotor = 0 A, SPI register CSCFG. CSOFFSET
VLine
Linearity, ALV
Rshunt = 1 mΩ,
R11 = R12 = 1 kΩ,
R21 = R22 = 30 kΩ
VGain
Gain
5
mV
-
0.5
1
1.5
2
2.5
-
V
29.4
30
30.6
mV/A
10
30
-
V/V
-
1
2.5
µs
Tset_TR1 (1)
Settling time (rise), ALV
±1%
Rshunt = 1 mΩ, VGain = 30, CL = 100 pF,
Imotor = 0 A → 30 A,
(ALV: 1 V → 1.9 V, AREF = 1 V)
Tset_TR2 (1)
Settling time(rise), ALV
±1%
Rshunt = 1 mΩ, VGain = 30, CL = 100 pF,
Imotor = 0 A → 100 A,
(ALV: 1 V → 4 V, AREF = 1 V)
-
1
2.5
µs
Tset_TF1 (1)
Settling time(fall), ALV
±1%
Rshunt = 1 mΩ, VGain = 30, CL = 100 pF,
Imotor = 30 A→0,
(ALV: 1.9 V → 1 V, AREF = 1 V)
-
1
2.5
µs
Tset_TF2 (1)
Settling time(fall), ALV
±1%
Rshunt = 1 mΩ, VGain = 30, CL = 100 pF,
Imotor = 100 A→0,
(ALV: .4 V → 1 V, AREF = 1 V)
-
1
2.5
µs
OVADth
Overcurrent threshold
Rshunt = 1 mΩ, VGain = 30, AREF = 1 V,
ADTH = 2.5 V, SPI register FLTCFG. MTOCTH,
OVADth = (2 × ADTH - AREF) / (Rshunt ×
VGain)
119.7
133
146.3
A
-
-
1.5
µs
0.8
1
1.2
µs
TDEL_OVAD Propagation delay
(1)
(rise or fall)
tfiltMTOC
(1)
filtering time
OSC1 = 9 MHz-11 MHz
Specified by design
ALV
ALFB/2
VCC
ADTH
VLine
=´Y/´X
´Y
´X
VO_0
0A
Imotor
OVAD
0A
Imotor
Figure 16. Motor Current Sense and Overcurrent
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OVADth
OVAD
tfiltMTOC
tfiltMTOC
MTOC SPI Register Flag
SPI Access
read
write 1
to clear
FAULT
Pre-Driver
Enable
Disable
Enable
(1)
MCU must set the FLTCFG.FLGLATCH_EN bit to 1 to get the latch-type operation shown in this figure.
(2)
When MTOC condition is detected, FAULT is asserted to low if FE_MTOC bit is 1.
(3)
When MTOC condition is detected, Pre Driver is disabled if SE_MTOC is 1.
Figure 17. Motor Overcurrent Event
Regulators
Description:
The regulator block offers 5-V LDO and 3.3-V LDO. The VCC LDO regulates VB down to 5 V with an external
PNP controlled by the regulator block. This 5 V is supplied to MCU and other components.
The VDD regulator regulates VB down to 3.3 V with internal FET and controller. The 5 V LDO is protected
against short to GND fault. Overvoltage and under voltage events of both supplies are detected. The under
voltage of the 5-V LDO is set by SPI.
24
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VB
Current
Limit
OC
Rsns
VCFB
BG
+
AMP
-
PNP Tr
VCCB
CVCC
VCC
OV
Superviser
* 0.2VáRsns*VCCOC
UV
Figure 18. VCC Block Diagram (External Driver)
VB
+
BG
AMP
-
CVDD
VDD
OV
Superviser
UV
Figure 19. VDD Block Diagram
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Table 8. VCC and VDD Electrical Characteristics
PARAMETER
CONDITIONS
MIN
TYP MAX
UNITS
VB = 12 V, TA = -40°C to 125℃
℃ (unless otherwise specified)
VCC
VCC1
Output Voltage
VCC2
Output Voltage
IBVCC
Base Current
hfePNP
DC current gain of external PNP
VLRVCC
Load regulation
CVCC
External Capacitance
RVCC
ESR of external Capacitor
4.9
VB = 4.5 V, ILVCC = 5 mA-150 mA
5
4.25
5.1
4.5
1.5
ILVCC = 5 mA-150 mA
V
mA
100
-
-
-20
-
20
mV
100
µF
22
SPI register FLTCFG. VCCUVTH
V
300
mΩ
3.7
3.9
4
4.2
4.3
4.5
V
50
100
200
mV
6
6.5
7
300
400
550
mA
VCCUV
Under voltage detection threshold
VCCUVHYS
Under voltage detection threshold hysteresis
VCCOV
Overvoltage detection threshold
VCCOC
Current Limit
Rsns = 0.51 Ω, 0.2 V ⋍ Rsns (1), VCCOC
Tvcc1 (2)
Rise Time
VCC > VCCUV, CVCC = 22 µF
0.5
ms
Tvcc2 (2)
Rise Time
VCC > VCCUV, CVCC = 100 µF
1.5
ms
V
VDD
VDD
Output Voltage
CVDD
Load Capacitance
VDDUV
Under voltage detection threshold
VDDOV
Overvoltage detection threshold
Tvdd
(2)
Rise Time
(1)
(2)
No variation of the external components
Specified by design
26
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3
3.3
3.6
1
VDD > VDDUV, CVDD = 1 µF
V
µF
2.1
2.3
2.5
V
4
4.3
4.6
V
100
µs
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VB Monitor
Description:
The VB monitoring system has two comparators for under- and overvoltage, and has pre-driver stop controlling
system respectively. Overvoltage provides pre-driver stop condition selectable (SPI control). On the other hand,
under voltage must stop pre-driver operation under detection (no selectable). System should return to normal
operation automatically after undetected level.
+
VB
VB_OV
VB_UV
VREF
-
Figure 20. VB Monitor Block Diagram
Table 9. Electrical Characteristics
PARAMETER
CONDITIONS
MIN
TYP MAX
UNITS
26.5
27.5
28.5
V
0.2
0.5
1.2
V
SPI register FLTCFG. VBUVTH
3.65
4.15
4.65
5.15
4
4.5
5
5.5
4.35
4.85
5.35
5.85
V
SPI register FLTCFG. VBUVTH
0.1
0.2
0.2
0.3
0.25
0.4
0.5
0.65
0.5
0.8
1.0
1.3
V
VB = 12 V, TA = -40°C to 125℃
℃ (unless otherwise specified)
VB MONITOR
VBOV
VB overvoltage detection threshold level
VBOVhys (1)
VB overvoltage detection hysteresis
VBUV
VBUVhys
(1)
VB Undervoltage detection threshold level
(1)
VB Undervoltage detection hysteresis
Specified by design
Thermal Shut Down
Description:
The device has temperature sensors that produce pre-driver stop condition if the chip temperature exceeds 175
degree.
IPTAT
TSD
Figure 21. Thermal Shutdown Block Diagram
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Table 10. Electrical Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
155
175
195
°C
5
10
15
°C
VB = 12 V, TA = -40°C to 125℃
℃ (unless otherwise specified)
THERMAL SHUT DOWN
TSD (1)
Thermal shut down threshold level
TSDhys (1)
Thermal shut down hysteresis
(1)
Specified by design
Oscillator
Description:
Oscillator block generates two 10-MHZ clock signals. OSC1 is the primary clock used for internal logic
synchronization and timing control. OSC2 is the secondary clock used to monitor the status of OSC1.
OSC1(OSC2)
VREF
Figure 22. Oscillator Block Diagram
Table 11. Oscillator Electrical Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
9
10
11
UNITS
VB = 12 V, TA = -40°C to 125℃
℃ (unless otherwise specified)
OSCILLATOR
OSC1
OSC1 frequency
OSC2
OSC2 frequency
28
10
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MHz
MHz
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I/O
VCC
VDD
VCC
VCC
VDD
VDD
DIN
SCK
CTLxx
TEST
VDD
Ru
CS
PRN
Level Shift
Level Shift
Rd
CLAMP
V5INT
V5INT
ENABLE
Rd
* V5INT is the internal power supply.
Figure 23. Input Buffer1 Block Diagram
VDD
VCC
VCC
Level Shift
FAULT
Figure 24. Output Buffer1 Block Diagram
VDD
VCC
VCC
Level Shift
DOUT
EN
Figure 25. Output Buffer2 Block Diagram
VCC
VDD
VCC
R_RES
VCC
RES
Level Shift
Figure 26. Output Buffer3 Block Diagram
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Table 12. Electrical Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
VB = 12 V, TA = -40°C to 125℃
℃ (unless otherwise specified)
Input Buffer1
VIH
Input threshold logic high
VIL
Input threshold logic low
0.7 × VCC
Ru or Rd
Input pullup or pulldown resistance
50
V
100
0.3 × VCC
V
150
kΩ
Output Buffer1(2)
VOH
Output level logic high
Isink = 2.5 mA
VOL
Output level logic low
Isource = 2.5 mA
0.9 × VCC
V
0.1 × VCC
V
4
kΩ
0.1 × VCC
V
Output Buffer3
R_RES
Pullup Resistor
VOL
Output level logic low
2
Isource = 2 mA
3
VB
Enable
VCC
VDD
Band Gap
Charge Pump
VIH
VIL
Device Active
Sleep
Sleep
Figure 27. ENABLE Timing Chart
Table 13. Recommended Pin Termination
PIN NAME
DESCRIPTION
TERMINATION
TEST
Test mode input
OPEN
Fault Detection
Table 14. Fault Detection
SPI FLTFLG
Pre Driver (1)
FAULT (2)
RES
VB - Overvoltage
VBOV
Disable
L
H
VB - Undervoltage
VBUV
Disable
L
H
CP - Overvoltage
CPOV
Disable
L
H
CP - Undervoltage
CPUV
Disable
L
H
VCC - Overvoltage
VCCOV
Disable
L
H
ITEMS
VCC - Under Voltage
H
L
VCCOC
Disable
L
H
Motor - Overcurrent
MTOC
Disable
L
H
VDD - Overvoltage
VDDOV
Disable
L
H
VCC - Overcurrent
-
VDD - Undervoltage
H
L
Disable
L
H
Watch Dog
-
-
H
L
Clock Monitor
-
-
H
L
(1)
(2)
(3)
30
Disable
(3)
TSD
Thermal shutdown
-
Disable
(3)
Others
Pre-driver is disabled if the conditions occur and SDNEN register bits are 1.
FAULT pin is asserted to low if the conditions occur and FLTEN register bits are 1.
Pre-driver is disabled by VCC undervoltage and VDD undervoltage conditions regardless of SPI register setting.
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Table 14. Fault Detection (continued)
ITEMS
SPI FLTFLG
Pre Driver (1)
FAULT (2)
RES
Others
-
-
H
H
SPI serial out error bit
SPI format error
Application Description
0.51Ö
VB
VCFB
VB
1uF
PNP Tr
VB
100nF
1uF
100uF
VCCB
PGND
GND
100uF
PGND
ALP
VCC
AREF
100nF
30KÖ
1KÖ
10nF
TEST
1mÖ
GND
ALM
GND
ALV
ALFB
30KÖ
1KÖ
4.7pF
CTLUH
CTLVH
UH
10Ö
CTLWH
UHS
CTLUL
CTLVL
UL
10Ö
CTLWL
DRV3204-Q1
Controller
PMV3
VH
10Ö
PMV2
PMV1
VHS
RES
VL
BLDC
Motor
10Ö
PRN
FAULT
CS
SCK
WH
10Ö
WHS
DIN
WL
10Ö
DOUT
VDD
1uF
GND
PGND
100nF
GND
PHTM
ENABLE
PH1M
100KÖ
30KÖ
15pF
10KÖ
100KÖ
10KÖ
15pF
10KÖ
100KÖ
10KÖ
15pF
10KÖ
100KÖ
10KÖ
15pF
10KÖ
GND
2.2uF
VB
47nF
0Ö
1uF
PDCPV
CPRD4
PH2M
CPRD3
100nF
47Ö
CPRD2
CPRD1
PH3M
NGND
GND
GND
PGND
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REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
Page
•
Changed Operation VB Range in Features .......................................................................................................................... 1
•
Changed Applications from automotive to include specific pump applications .................................................................... 1
•
Deleted EEPROM going into the Control Logic from the Top Block Diagram ...................................................................... 4
•
Added VB3 parameter to the SUPPLY VOLTAGE AND CURRENT table and added corresponding table note (2) ............ 5
•
Changed ACE-Q100 from Grade 0 to Grade 1 in table note
•
Changed Charge-Pump Block Diagram by moving line to connection by VF .................................................................... 17
•
Added PDCPV to all output voltage parameters in the Charge-Pump Electrical Characteristics table .............................. 17
•
Changed VGain max value to the typ value in the Motor Current-Sense Electrical Characteristics table ......................... 23
•
Added UNIT of VGain in the Motor Current-Sense Electrical Characteristics table ........................................................... 23
•
Changed VDD Block Diagram by removing OC current limit and resistor to VB ............................................................... 25
•
Added VBOVhys parameter to the VB Monitor table and added corresponding table note (1) ........................................... 27
•
Added VBUVhys parameter to the VB Monitor table and added corresponding table note (1) ........................................... 27
•
Changed Application Description image by moving connecting line between UH, UHS, and UL ...................................... 31
32
(1)
of SUPPLY VOLTAGE AND CURRENT ........................... 5
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Jan-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
DRV3204QPHPQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTQFP
PHP
48
1
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 150
DRV3204
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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7-Jan-2014
Addendum-Page 2
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