INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT540 Octal buffer/line driver; 3-state; inverting Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting 74HC/HCT540 The 74HC/HCT540 are octal inverting buffer/line drivers with 3-state outputs. The 3-state outputs are controlled by the output enable inputs OE1 and OE2. A HIGH on OEn causes the outputs to assume a high impedance OFF-state. The “540” is identical to the “541” but has inverting outputs. FEATURES • Inverting outputs • Output capability: bus driver • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT540 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay An to Yn CI CPD CL = 15 pF; VCC = 5 V 9 11 ns input capacitance 3.5 3.5 pF power dissipation capacitance per buffer notes 1 and 2 39 44 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 HCT 2 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting 74HC/HCT540 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 19 OE1, OE2 output enable input (active LOW) 2, 3, 4, 5, 6, 7, 8, 9 A0 to A7 data inputs 10 GND ground (0 V) 18, 17, 16, 15, 14, 13, 12, 11 Y0 to Y7 bus outputs 20 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting 74HC/HCT540 FUNCTION TABLE INPUTS OUTPUT OE1 OE2 An Yn L L X H L L H X L H X X H L Z Z Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care Z = high impedance OFF-state Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting 74HC/HCT540 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. max. −40 to +125 UNIT V CC WAVEFORMS (V) min. max. tPHL/ tPLH propagation delay An to Yn 30 11 9 100 20 17 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.6 tPZH/ tPZL 3-state output enable time OE to Yn 52 19 15 160 32 27 200 40 34 240 48 41 ns 2.0 4.5 6.0 Fig.7 tPHZ/ tPLZ 3-state output disable time OE to Yn 61 22 18 160 32 27 200 40 34 240 48 41 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.6 December 1990 5 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting 74HC/HCT540 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT OE1 OE2 An 1.50 1.00 1.40 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 UNIT V CC WAVEFORMS (V) min. max. tPHL/ tPLH propagation delay An to Yn 13 24 30 36 ns 4.5 Fig.6 tPZH/ tPZL 3-state output enable time OE to Yn 22 35 44 53 ns 4.5 Fig.7 tPHZ/ tPLZ 3-state output disable time OE to Yn 23 35 44 53 ns 4.5 Fig.7 tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.6 December 1990 6 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting 74HC/HCT540 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (An) to output (Yn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 7