NSC OPA2320AIDGKR Precision, 20mhz, 0.9pa, low-noise, rrio, cmos operational amplifier with shutdown Datasheet

OPA
OPA320, OPA2320
OPA320S, OPA2320S
320
OP
A2
OP
A2
320
320S
OP
A2
320
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SBOS513E – AUGUST 2010 – REVISED JUNE 2013
Precision, 20MHz, 0.9pA, Low-Noise, RRIO,
CMOS Operational Amplifier with Shutdown
Check for Samples: OPA320, OPA2320, OPA320S, OPA2320S
FEATURES
DESCRIPTION
•
The OPA320 (single) and OPA2320 (dual) are a new
generation
of
precision,
low-voltage
CMOS
operational amplifiers optimized for very low noise
and wide bandwidth while operating on a low
quiescent current of only 1.45mA.
1
23
•
•
•
•
•
•
•
•
•
Precision with Zero-Crossover Distortion:
– Low Offset Voltage: 150μV (max)
– High CMRR: 114dB
– Rail-to-Rail I/O
Low Input Bias Current: 0.9pA (max)
Low Noise: 7nV/√Hz at 10kHz
Wide Bandwidth: 20MHz
Slew Rate: 10V/μs
Quiescent Current: 1.45mA/ch
Single-Supply Voltage Range: 1.8V to 5.5V
OPA320S, OPA2320S:
– IQ in Shutdown Mode: 0.1μA
Unity-Gain Stable
Small Packages:
– SOT23, MSOP, DFN
APPLICATIONS
•
•
•
•
•
•
•
•
High-Z Sensor Signal Conditioning
Transimpedance Amplifiers
Test and Measurement Equipment
Programmable Logic Controllers (PLCs)
Motor Control Loops
Communications
Input/Output ADC/DAC Buffers
Active Filters
The OPA320 series is ideal for low-power, singlesupply applications. Low-noise (7nV/√Hz) and highspeed operation also make them well-suited for
driving sampling analog-to-digital converters (ADCs).
Other applications include signal conditioning and
sensor amplification.
The OPA320 features a linear input stage with zerocrossover distortion that delivers excellent commonmode rejection ratio (CMRR) of typically 114dB over
the full input range. The input common-mode range
extends 100mV beyond the negative and positive
supply rails. The output voltage typically swings within
10mV of the rails.
In addition, the OPAx320 have a wide supply voltage
range from 1.8V to 5.5V with excellent PSRR (106dB)
over the entire supply range, making them suitable
for precision, low-power applications that run directly
from batteries without regulation.
The OPA320 (single version) is available in a SOT235 package; the OPA320S shut-down single version is
available in an SOT23-6 package. The dual OPA2320
is offered in SO-8, MSOP-8, and DFN-8 packages,
and the OPA2320S (dual with shut-down) in an
MSOP-10 package.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FilterPro is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
OPA320, OPA2320
OPA320S, OPA2320S
SBOS513E – AUGUST 2010 – REVISED JUNE 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
(1)
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or visit
the device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage, VS = (V+) – (V–)
Signal input pins
Voltage (2)
Current
(2)
OPA320, OPA320S, OPA2320, OPA2320S
UNIT
6
V
(V–) – 0.5 to (V+) + 0.5
V
±10
mA
Output short-circuit current (3)
Continuous
mA
Operating temperature, TA
–40 to +150
°C
Storage temperature, TSTG
–65 to +150
°C
Junction temperature, TJ
ESD ratings
(1)
(2)
(3)
2
+150
°C
Human body model (HBM)
4000
V
Charged device model (CDM)
1000
V
Machine model (MM)
200
V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should
be current limited to 10mA or less.
Short-circuit to ground, one amplifier per package.
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SBOS513E – AUGUST 2010 – REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS: VS = +1.8V to +5.5V or ±0.9V to ±2.75V
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and SHDN x = VS+, unless otherwise noted.
OPA320, OPA320S, OPA2320, OPA2320S
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Input offset voltage
VOS
vs Temperature
dVOS/dT
vs Power supply
PSR
VS = +5.5V
Over temperature
Channel separation
40
150
μV
1.5
5
μV/°C
20
μV/V
VS = +1.8V to +5.5V
5
VS = +1.8V to +5.5V
15
μV/V
At 1kHz
130
dB
INPUT VOLTAGE
Common-mode voltage range
VCM
Common-mode rejection ratio
CMRR
(V–) – 0.1
VS = 5.5V, (V–) – 0.1V < VCM < (V+) + 0.1V
Over temperature
100
(V+) + 0.1
V
114
dB
96
dB
INPUT BIAS CURRENT
Input bias current
IB
Over temperature
±0.9
pA
TA = –40°C to +85°C
±0.2
±50
pA
OPA2320, OPA2320S, TA = –40°C to +125°C
±400
pA
±600
pA
OPA320, OPA320S, TA = –40°C to +125°C
Input offset current
IOS
±0.2
Over temperature
±0.9
pA
TA = –40°C to +85°C
±50
pA
TA = –40°C to +125°C
±400
pA
NOISE
f = 0.1Hz to 10Hz
2.8
μVPP
f = 1kHz
8.5
nV/√Hz
f = 10kHz
7
nV/√Hz
f = 1kHz
0.6
fA/√Hz
Differential
5
pF
Common-mode
4
pF
Input voltage noise
Input voltage noise density
en
Input current noise density
in
INPUT CAPACITANCE
OPEN-LOOP GAIN
Open-loop voltage gain
Phase margin
AOL
0.1V < VO < (V+) – 0.1V, RL = 10kΩ
114
132
dB
0.1V < VO < (V+) – 0.1V, RL = 10kΩ
100
130
dB
0.2V < VO < (V+) – 0.2V, RL = 2kΩ
108
123
dB
0.2V < VO < (V+) – 0.2V, RL = 2kΩ
96
130
dB
47
Degrees
20
MHz
PM
VS = 5V, CL = 50pF
FREQUENCY RESPONSE
Gain bandwidth product
Slew rate
Settling time
VS = 5.0V, CL = 50pF
GBP
Unity gain
SR
G = +1
10
V/μs
To 0.1%, 2V step, G = +1
0.25
μs
To 0.01%, 2V step, G = +1
0.32
μs
To 0.0015%, 2V step, G = +1 (1)
0.5
μs
VIN × G > VS
100
ns
VO = 4VPP, G = +1, f = 10kHz, RL = 10kΩ
0.0005
%
VO = 2VPP, G = +1, f = 10kHz, RL = 600Ω
0.0011
%
tS
Overload recovery time
Total harmonic distortion +
noise (2)
(1)
(2)
THD+N
Based on simulation.
Third-order filter; bandwidth = 80kHz at –3dB.
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ELECTRICAL CHARACTERISTICS: VS = +1.8V to +5.5V or ±0.9V to ±2.75V (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and SHDN x = VS+, unless otherwise noted.
OPA320, OPA320S, OPA2320, OPA2320S
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RL = 10kΩ
10
20
mV
RL = 2kΩ
25
35
mV
30
mV
45
mV
OUTPUT
Voltage output swing from
both rails
VO
RL = 10kΩ
Over temperature
RL = 2kΩ
Short-circuit current
ISC
Capacitive load drive
CL
Open-loop output resistance
RO
VS = 5.5V
±65
mA
See Typical Characteristics
IO = 0mA, f = 1MHz
90
All amplifiers disabled, SHDN = V–
0.1
Ω
SHUTDOWN (3)
Quiescent current per amplifier
IQSD OPA2320S only, SHDN A = VS–, SHDN B = VS+
OPA2320S only, SHDN A = VS+, SHDN B = VS–
High-level input voltage
VIH
Amplifier enabled, VS– + 0.7 [(VS+) + |VS–|]
Low-level input voltage
VIL
Amplifier disabled, VS– + 0.3 [(VS+) + |VS–|]
Amplifier enable time (4)
tON
Amplifier disable time (4)
tOFF
SHDN pin input bias current (per pin)
G = 1, VOUT = 0.1 × VS/2, full shutdown
0.5
1.6
1.6
0.7 × VS+
(5)
mA
5.5
V
0.3 × VS+
V
μs
20
OPA2320S only, partial shutdown (5)
μA
mA
6
G = 1, VOUT = 0.1 × VS/2
3
μs
VIH = 5V
0.13
μA
VIL = 0V
0.04
μA
POWER SUPPLY
Specified voltage range
Quiescent current per amplifier
VS
1.8
5.5
V
IQ
OPA320, OPA320S
IO = 0mA, VS = +5.5V
Over temperature
IO = 0mA, VS = +5.5V
OPA2320, OPA2320S
IO = 0mA, VS = +5.5V
Over temperature
IO = 0mA, VS = +5.5V
Power-on time
1.5
1.45
V+ = 0V to 5V, to 90% IQ level
1.75
mA
1.85
mA
1.6
mA
1.7
mA
μs
28
TEMPERATURE
Specified range
–40
+125
°C
Operating range
–40
+150
°C
(3)
(4)
(5)
4
Specified by design and characterization; not production tested.
Disable time (tOFF) and enable time (tON) are defined as the time between the 50% point of the signal applied to the SHDN pin and the
point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
Full shutdown refers to the dual OPA2320S having both A and B channels disabled (SHDN A = SHDN B = VS–). For partial shutdown,
only one SHDN pin is exercised; in this mode, the internal biasing and oscillator remain operational and the enable time is shorter.
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SBOS513E – AUGUST 2010 – REVISED JUNE 2013
THERMAL INFORMATION: OPA320, OPA320S
THERMAL METRIC (1)
OPA320
OPA320S
DBV (SOT23)
DBV (SOT23)
5 PINS
6 PINS
θJA
Junction-to-ambient thermal resistance
219.3
177.5
θJC(top)
Junction-to-case(top) thermal resistance
107.5
108.9
θJB
Junction-to-board thermal resistance
57.5
27.4
ψJT
Junction-to-top characterization parameter
7.4
13.3
ψJB
Junction-to-board characterization parameter
56.9
26.9
θJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
N/A
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION: OPA2320, OPA2320S
OPA2320
THERMAL METRIC (1)
OPA2320S
D (SO)
DGK (MSOP)
DRG (DFN)
DGS (MSOP)
8 PINS
8 PINS
8 PINS
10 PINS
θJA
Junction-to-ambient thermal resistance
122.6
174.8
50.6
171.5
θJC(top)
Junction-to-case(top) thermal resistance
67.1
43.9
54.9
43.0
θJB
Junction-to-board thermal resistance
64.0
95.0
25.2
91.4
ψJT
Junction-to-top characterization parameter
13.2
2.0
0.6
1.9
ψJB
Junction-to-board characterization parameter
63.4
93.5
25.3
89.9
θJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
N/A
5.7
N/A
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2010–2013, Texas Instruments Incorporated
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PIN CONFIGURATIONS
DBV PACKAGE
SOT23-5
(TOP VIEW)
OUT
1
V-
2
+IN
3
DRG PACKAGE
DFN-8
(TOP VIEW)
V+
5
4
OUT A
1
-IN A
2
+IN A
3
V-
4
-IN
DBV PACKAGE
SOT23-6
(TOP VIEW)
VOUT
1
6
V+
V-
2
5
SHDN
+IN
3
4
-IN
DGS PACKAGE
MSOP-10
(TOP VIEW)
VOUT A
1
-IN A
2
Exposed
Thermal
Die Pad
on
Underside(2)
8
V+
7
OUT B
6
-IN B
5
+IN B
D, DGK PACKAGES
SO-8, MSOP-8
(TOP VIEW)
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
10 V+
9
VOUT B
8
-IN B
A
+IN A
3
B
6
V-
4
7
+IN B
SHDN A
5
6
SHDN B
(1)
No internal connection.
(2)
Connect thermal pad to V–.
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SBOS513E – AUGUST 2010 – REVISED JUNE 2013
TYPICAL CHARACTERISTICS
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10kΩ, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT DISTRIBUTION
14
25
20
Number of Amplifiers
Number of Amplifiers (%)
12
10
8
6
4
15
10
5
2
0
0
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
0.1
0.5
0.9
1.3
1.7
2.1
2.5
2.9
Offset Drift (mV/°C)
Offset Voltage (mV)
Figure 1.
Figure 2.
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
OPEN-LOOP GAIN/PHASE vs FREQUENCY
0
160
80
140
60
120
40
VS = ±2.5V
CL = 50pF
-40
Gain (dB)
100
20
0
-20
-60
Phase
80
-80
60
-100
-120
40
-40
Gain
20
-60
Representative Units
VS = ±2.75V
-80
-3 -2.5 -2 -1.5 -1 -0.5 0
0.5
1
1.5
2
2.5
-140
-160
0
-100
3
-20
-20
Phase (°)
Offset Voltage (mV)
100
1
10
100
1k
Common-Mode Voltage (V)
10k
100k
1M
10M
-180
100M
Frequency (Hz)
Figure 3.
Figure 4.
OPEN-LOOP GAIN vs TEMPERATURE
QUIESCENT CURRENT vs SUPPLY VOLTAGE
1.5
140
+125°C
135
Quiescent Current (mA/Ch)
Open-Loop Gain (dB)
10kW Load
130
125
2kW Load
120
115
110
1.45
+85°C
1.4
+25°C
1.35
-40°C
1.3
105
100
1.25
-50
-25
0
25
50
75
Temperature (°C)
100
125
150
1.5
2
2.5
3
Figure 5.
Copyright © 2010–2013, Texas Instruments Incorporated
3.5
4
4.5
5
5.5
Supply Voltage (V)
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10kΩ, unless otherwise noted.
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
6
0.8
5
4
0.6
Input Bias Current (pA)
Input Bias Current (pA)
INPUT BIAS CURRENT vs SUPPLY VOLTAGE
1
0.4
0.2
0
-0.2
-0.4
-0.6
-1
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2
1
0
-1
-2
-3
IB+
IBIOS
-4
IBIB+
-0.8
3
-5
-6
2.9
-3 -2.5 -2 -1.5 -1 -0.5 0
Supply Voltage (±V)
Figure 7.
INPUT BIAS CURRENT DISTRIBUTION
Input Bias Current (pA)
30
25
20
15
10
5
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-100
2
3
2.5
IOS
IB+
IB-
IB
-50
0.25
0.2
0.15
0.1
0.05
0
-0.1
-0.05
-0.2
-0.15
-0.3
0
-0.25
1.5
INPUT BIAS CURRENT vs TEMPERATURE
35
-0.35
1
Figure 8.
40
Number of Amplifiers (%)
0.5
Common-Mode Voltage (V)
-25
0
25
50
75
100
IOS
125
150
Temperature (°C)
Input Bias Current (pA)
Figure 9.
Figure 10.
CMRR AND PSRR vs FREQUENCY
CMRR AND PSRR vs TEMPERATURE
130
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
140
120
CMRR
100
80
60
40
PSRR
20
0
VS = 1.8V to 5.5V
125
120
115
110
105
100
PSRR
CMRR
95
90
100
1k
10k
100k
1M
10M
-50
-25
0
Frequency (Hz)
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50
75
100
125
150
Temperature (°C)
Figure 11.
8
25
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10kΩ, unless otherwise noted.
INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
0.1Hz TO 10Hz INPUT VOLTAGE NOISE
6
VS = 1.8V to 5.5V
5
4
3
100
Voltage (mV)
Voltage Noise (nV/ÖHz)
1000
10
2
1
0
-1
-2
-3
1
-4
10
100
1k
10k
1M
100k
0
1
2
3
4
Frequency (Hz)
Figure 13.
CLOSED-LOOP GAIN vs FREQUENCY
8
10
9
CLOSED-LOOP GAIN vs FREQUENCY
20
G = +10V/V
VS = +5.5V
RL = 10kW
CL = 50pF
G = +100V/V
40
Gain (dB)
Gain (dB)
7
60
VS = +1.8V
RL = 10kW
CL = 50pF
G = +100V/V
0
6
Figure 14.
60
40
5
Time (1s/div)
20
G = +10V/V
0
G = +1V/V
-20
G = +1V/V
-20
10k
100k
1M
10M
10k
100M
100k
Frequency (Hz)
1M
100M
10M
Frequency (Hz)
Figure 15.
Figure 16.
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
(MSOP-8)
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
6
3
5.5VS
2
4
Output Voltage (V)
Output Voltage (VPP)
5
3.3VS
3
2
1
-40°C
+25°C
+125°C
0
-1
1.8VS
1
-2
RL = 10kW
CL = 50pF
VS = ±2.75 V
0
-3
10k
100k
1M
Frequency (Hz)
10M
0
10
20
30
Figure 17.
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40
50
60
70
80
Output Current (mA)
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10kΩ, unless otherwise noted.
OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY
SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE
1000
70
G = 1, VS = 1.8V
VS = ±2.75V
G = 1, VS = 5.5V
G = 10, VS = 1.8V
50
Overshoot (%)
Impedance (W)
60
100
G = 10, VS = 5.5V
40
30
20
10
0
10
1
10
100
1k
10k
100k
1M
10M
100M
500
0
1000
Frequency (Hz)
1500
Figure 19.
0.01
Load = 600W
0.001
Frequency = 10kHz
VS = ±2.5V
G = +1V/V
Load = 10kW
0.1
0.1
0.01
Load = 600W
0.001
Load = 10kW
0.0001
10
1
Frequency = 10kHz
VIN = 2VPP
VS = ±2.5V
G = +1V/V
10
100
1k
Figure 21.
CHANNEL SEPARATION vs FREQUENCY (for Dual)
0
Frequency = 10kHz
VIN = 4VPP
VS = ±2.5V
G = +1V/V
VS = ±2.75V
-20
Channel Separation (dB)
Total Harmonic Distortion and Noise (%)
100k
Figure 22.
THD+N vs FREQUENCY
10
10k
Frequency (Hz)
VIN (VPP)
0.01
Load = 600W
0.001
-40
-60
-80
-100
-120
Load = 10kW
0.0001
3000
THD+N vs FREQUENCY
Total Harmonic Distortion and Noise (%)
Total Harmonic Distortion and Noise (%)
THD+N vs AMPLITUDE
0.1
2500
Figure 20.
0.1
0.0001
0.01
2000
Capacitive Load (pF)
-140
10
100
1k
10k
100k
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 23.
Figure 24.
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10M
100M
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10kΩ, unless otherwise noted.
SLEW RATE vs SUPPLY VOLTAGE
SMALL-SIGNAL STEP RESPONSE
12
0.1
CL = 50pF
0.075
11.5
Voltage (V)
Slew Rate (V/ms)
0.05
11
Rise
10.5
Fall
10
Gain = +1
VS = ±2.75V
VIN = 100mVPP
0.025
0
-0.025
-0.05
9.5
VOUT
VIN
-0.075
9
1.6
2
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2
-0.1
-0.8
5.6
0
-0.4
0.4
Supply Voltage (V)
Figure 25.
SMALL-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE vs TIME
1.5
0.075
VIN
Gain = -1
VS = ±2.75V
VIN = 100mVPP
Voltage (V)
Voltage (V)
Gain = +1
VS = ±2.75V
VIN = 2VPP
1
0.05
0
1.6
1.2
Figure 26.
0.1
0.025
0.8
Time (ms)
-0.025
0.5
VOUT
0
-0.5
-0.05
-0.1
-1.6
-1
VOUT
VIN
-0.075
-1.2
-0.8
-0.4
0
0.4
0.8
-1.5
-0.4
0
0.4
Time (ms)
0.8
1.2
1.6
Time (ms)
Figure 28.
ENABLE STARTUP
ENABLE STARTUP
Voltage (1 V/div)
Voltage (500 mV/div)
Figure 27.
G = 1 V/V
VS = 1.8V
VIN = 1.5V
Output Pin
Enable Pin
G = 1 V/V
VS = 5.5V
VIN = 4V
Output Pin
Enable Pin
Time (5 s/div)
Time (2.5 s/div)
C001
C001
Figure 29.
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Figure 30.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCM = VOUT = mid-supply, and RL = 10kΩ, unless otherwise noted.
ENABLE SHUTDOWN
Voltage (1 V/div)
Voltage (500 mV/div)
ENABLE SHUTDOWN
G = 1 V/V
VS = 1.8V
VIN = 1.5V
Output Pin
Enable Pin
G = 1 V/V
VS = 5.5V
VIN = 4V
Output Pin
Enable Pin
Time (5 s/div)
Time (2.5 s/div)
C001
C001
Figure 31.
12
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Figure 32.
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APPLICATION INFORMATION
RAIL-TO-RAIL INPUT
OPERATING VOLTAGE
The OPA320 series op amps are unity-gain stable
and can operate on a single-supply voltage (1.8V to
5.5V), or a split supply voltage (±0.9V to ±2.75V),
making them highly versatile and easy to use. The
power-supply pins should have local bypass ceramic
capacitors (typically 0.001μF to 0.1μF). The OPA320
amplifiers are fully specified from +1.8V to +5.5V and
over the extended temperature range of –40°C to
+125°C. Parameters that can exhibit variance with
regard to operating voltage or temperature are
presented in the Typical Characteristics.
INPUT AND ESD PROTECTION
The OPA320 incorporates internal electrostatic
discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily
consists of current-steering diodes connected
between the input and power-supply pins. These ESD
protection diodes also provide in-circuit input
overdrive protection, provided that the current is
limited to 10mA as stated in the Absolute Maximum
Ratings. Many input signals are inherently currentlimited to less than 10mA; therefore, a limiting resistor
is not required. Figure 33 shows how a series input
resistor (RS) may be added to the driven input to limit
the input current. The added resistor contributes
thermal noise at the amplifier input and the value
should be kept to the minimum in noise-sensitive
applications.
The OPA320 product family features true rail-to-rail
input operation, with supply voltages as low as ±0.9V
(1.8V). The design of the OPA320 amplifiers include
an internal charge-pump that powers the amplifier
input stage with an internal supply rail at
approximately 1.6V above the external supply (VS+).
This internal supply rail allows the single differential
input pair to operate and remain very linear over a
very wide input common-mode range. A unique zerocrossover input topology eliminates the input offset
transition region typical of many rail-to-rail,
complementary input stage operational amplifiers.
This topology allows the OPA320 to provide superior
common-mode performance (CMRR > 110dB,
typical) over the entire common-mode input range,
which extends 100mV beyond both power-supply
rails. When driving analog-to-digital converters
(ADCs), the highly linear VCM range of the OPA320
assures maximum linearity and lowest distortion.
PHASE REVERSAL
The OPA320 op amps are designed to be immune to
phase reversal when the input pins exceed the supply
voltages, therefore providing further in-system
stability and predictability. Figure 34 shows the input
voltage exceeding the supply voltage without any
phase reversal.
4
VIN
VS = ±2.5V
3
IOVERLOAD
10mA, Max
OPA320
VOUT
VIN
Voltage (V)
2
V+
VOUT
1
0
-1
-2
RS
-3
Figure 33. Input Current Protection
-4
-500
-250
0
250
500
750
1000
Time (ms)
Figure 34. No Phase Reversal
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FEEDBACK CAPACITOR IMPROVES
RESPONSE
For optimum settling time and stability with highimpedance feedback networks, it may be necessary
to add a feedback capacitor across the feedback
resistor, RF, as shown in Figure 35. This capacitor
compensates for the zero created by the feedback
network impedance and the OPA320 input
capacitance (and any parasitic layout capacitance).
The effect becomes more significant with higher
impedance networks.
OUTPUT IMPEDANCE
CF
RIN
RF
VIN
V+
CIN
RIN ´ CIN = RF ´ CF
OPA320
VOUT
CL
CIN
NOTE: Where CIN is equal to the OPA320 input capacitance
(approximately 9pF) plus any parasitic layout capacitance.
Figure 35. Feedback Capacitor Improves
Dynamic Performance
It is suggested that a variable capacitor be used for
the feedback capacitor because input capacitance
may vary between op amps and layout capacitance is
difficult to determine. For the circuit shown in
Figure 35, the value of the variable feedback
capacitor should be chosen so that the input
resistance times the input capacitance of the OPA320
(typically 9pF) plus the estimated parasitic layout
capacitance equals the feedback capacitor times the
feedback resistor:
RIN × CIN = RF × CF
Where:
CIN is equal to the OPA320 input capacitance
(sum of differential and common-mode) plus the
layout capacitance.
The capacitor value can be adjusted until
optimum performance is obtained.
EMI SUSCEPTIBILITY AND INPUT FILTERING
Operational amplifiers vary in susceptibility to
electromagnetic interference (EMI). If conducted EMI
enters the operational amplifier, the dc offset
observed at the amplifier output may shift from the
nominal value while EMI is present. This shift is a
14
result of signal rectification associated with the
internal semiconductor junctions. While all operational
amplifier pin functions can be affected by EMI, the
input pins are likely to be the most susceptible. The
OPA320 operational amplifier family incorporates an
internal input low-pass filter that reduces the
amplifiers response to EMI. Both common-mode and
differential mode filtering are provided by the input
filter. The filter is designed for a cut-off frequency of
approximately 580MHz (–3dB), with a roll-off of 20dB
per decade.
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The open-loop output impedance of the OPA320
common-source output stage is approximately 90Ω.
When the op amp is connected with feedback, this
value is reduced significantly by the loop gain. For
example, with 130dB (typ) of open-loop gain, the
output impedance is reduced in unity-gain to less
than 0.03Ω. For each decade rise in the closed-loop
gain, the loop gain is reduced by the same amount,
which results in a ten-fold increase in effective output
impedance. While the OPA320 output impedance
remains very flat over a wide frequency range, at
higher frequencies the output impedance rises as the
open-loop gain of the op amp drops. However, at
these frequencies the output also becomes capacitive
as a result of parasitic capacitance. This in turn
prevents the output impedance from becoming too
high, which can cause stability problems when driving
large capacitive loads. As mentioned previously, the
OPA320 has excellent capacitive load drive capability
for an op amp with its bandwidth.
CAPACITIVE LOAD AND STABILITY
The OPA320 is designed to be used in applications
where driving a capacitive load is required. As with all
op amps, there may be specific instances where the
OPA320 can become unstable. The particular op amp
circuit configuration, layout, gain, and output loading
are some of the factors to consider when establishing
whether an amplifier is stable in operation. An op
amp in the unity-gain (+1V/V) buffer configuration and
driving a capacitive load exhibits a greater tendency
to become unstable than an amplifier operated at a
higher noise gain. The capacitive load, in conjunction
with the op amp output resistance, creates a pole
within the feedback loop that degrades the phase
margin. The degradation of the phase margin
increases as the capacitive loading increases. When
operating in the unity-gain configuration, the OPA320
remains stable with a pure capacitive load up to
approximately 1nF.
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This resistor significantly reduces the overshoot and
ringing associated with large capacitive loads. A
possible problem with this technique is that a voltage
divider is created with the added series resistor and
any resistor connected in parallel with the capacitive
load. The voltage divider introduces a gain error at
the output that reduces the output swing. The error
contributed by the voltage divider may be
insignificant. For instance, with a load resistance, RL
= 10kΩ and RS = 20Ω, the gain error is only about
0.2%. However, when RL is decreased to 600Ω,
which the OPA320 is able to drive, the error
increases to 7.5%.
OVERLOAD RECOVERY TIME
Overload recovery time is the time it takes the output
of the amplifier to come out of saturation and recover
to the linear region. Overload recovery is particularly
important in applications where small signals must be
amplified in the presence of large transients.
Figure 38 and Figure 39 show the positive and
negative overload recovery times of the OPA320,
respectively. In both cases, the time elapsed before
the OPA320 comes out of saturation is less than
100ns. In addition, the symmetry between the positive
and negative recovery times allows excellent signal
rectification without distortion of the output signal.
3
VS = ±2.75V
G = -10
2.5
Output
2
Voltage (V)
The equivalent series resistance (ESR) of some very
large capacitors (CL > 1µF) is sufficient to alter the
phase characteristics in the feedback loop such that
the amplifier remains stable. Increasing the amplifier
closed-loop gain allows the amplifier to drive
increasingly larger capacitance. This increased
capability is evident when observing the overshoot
response of the amplifier at higher voltage gains, as
shown in Figure 37. One technique for increasing the
capacitive load drive capability of the amplifier
operating in unity gain is to insert a small resistor
(RS), typically 10Ω to 20Ω, in series with the output,
as shown in Figure 36.
1.5
1
0.5
0
Input
-0.5
-1
9.75
10
10.25
10.5
10.75
11
Time (250ns/div)
V+
Figure 38. Positive Recovery Time
RS
VOUT
OPA320
VIN
10W to
20W
RL
1
CL
0.5
Input
Figure 36. Improving Capacitive Load Drive
70
G = 1, VS = 1.8V
60
Overshoot (%)
-0.5
-1
-1.5
-2
G = 1, VS = 5.5V
Output
G = 10, VS = 1.8V
50
Voltage (V)
0
G = 10, VS = 5.5V
40
VS = ±2.75V
G = -10
-2.5
-3
9.75
10
10.25
10.5
10.75
11
Time (250ns/div)
30
Figure 39. Negative Recovery Time
20
10
0
0
500
1000
1500
2000
2500
3000
Capacitive Load (pF)
Figure 37. Small-Signal Overshoot versus
Capacitive Load (100mVPPoutput step)
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GENERAL LAYOUT GUIDELINES
The OPA320 is a wideband amplifier. To realize the
full operational performance of the device, good highfrequency printed circuit board (PCB) layout practices
are required. The bypass capacitors must be
connected between each supply pin and ground as
close to the device as possible. The bypass capacitor
traces should be designed for minimum inductance.
LEADLESS DFN PACKAGE
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The key elements to a transimpedance design, as
shown in Figure 40, are the expected diode
capacitance (CD), which should include the parasitic
input common-mode and differential-mode input
capacitance (4pF + 5pF for the OPA320); the desired
transimpedance gain (RF); and the gain-bandwidth
(GBW) for the OPA320 (20MHz). With these three
variables set, the feedback capacitor value (CF) can
be set to control the frequency response. CF includes
the stray capacitance of RF, which is 0.2pF for a
typical surface-mount resistor.
The OPA320 series uses the DFN style package
(also known as SON), which is a QFN with contacts
on only two sides of the package bottom. This
leadless package maximizes PCB space and offers
enhanced thermal and electrical characteristics
through an exposed pad. One of the primary
advantages of the DFN package is its low height
(0.8mm).
DFN packages are physically small, have a smaller
routing area, improved thermal performance, reduced
electrical parasitics, and a pinout scheme that is
consistent with other commonly-used packages (such
as SO and MSOP). Additionally, the absence of
external leads eliminates bent-lead issues.
The DFN package can easily be mounted using
standard PCB assembly techniques. See Application
Report, QFN/SON PCB Attachment (SLUA271) and
Application Report, Quad Flatpack No-Lead Logic
Packages (SCBA017), both available for download at
www.ti.com. The exposed leadframe die pad on the
bottom of the DFN package should be connected
to the most negative potential (V–).
APPLICATION EXAMPLES
TRANSIMPEDANCE AMPLIFIER
Wide gain bandwidth, low input bias current, low input
voltage, and current noise make the OPA320 an ideal
wideband photodiode transimpedance amplifier. Lowvoltage noise is important because photodiode
capacitance causes the effective noise gain of the
circuit to increase at high frequency.
16
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(1)
CF
< 1pF
RF
10MW
V+
l
CD
OPA320
VOUT
V-
(1) CF is optional to prevent gain peaking. It includes the stray
capacitance of RF.
Figure 40. Dual-Supply Transimpedance
Amplifier
To
achieve
a
maximally-flat,
second-order
Butterworth frequency response, the feedback pole
should be set to:
1
=
2pRFCF
GBW
4pRFCD
(1)
Bandwidth is calculated by:
f-3dB =
GBW
2pRFCD
(Hz)
(2)
For even higher transimpedance bandwidth, consider
the high-speed CMOS OPA380 (90MHz GBW),
OPA354 (100MHz GBW), OPA300 (180MHz GBW),
OPA355 (200MHz GBW), or OPA656/57 (400MHz
GBW).
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For single-supply applications, the +IN input can be
biased with a positive dc voltage to allow the output
to reach true zero when the photodiode is not
exposed to any light, and respond without the added
delay that results from coming out of the negative rail;
this configuration is shown in Figure 41. This bias
voltage also appears across the photodiode,
providing a reverse bias for faster operation.
(1)
CF
< 1pF
RF
10MW
photodiode
can
significantly
reduce
its
capacitance. Smaller photodiodes have lower
capacitance. Use optics to concentrate light on a
small photodiode.
3. Noise increases with increased bandwidth. Limit
the circuit bandwidth to only that required. Use a
capacitor across the RF to limit bandwidth, even if
not required for stability.
4. Circuit board leakage can degrade the
performance of an otherwise well-designed
amplifier. Clean the circuit board carefully. A
circuit board guard trace that encircles the
summing junction and is driven at the same
voltage can help control leakage.
For additional information, refer to the Application
Bulletins Noise Analysis of FET Transimpedance
Amplifiers (SBOA060), and Noise Analysis for HighSpeed Op Amps (SBOA066), available for download
at the TI web site.
V+
l
OPA320
VOUT
+VBIAS
(1) CF is optional to prevent gain peaking. It includes the stray
capacitance of RF.
Figure 41. Single-Supply Transimpedance
Amplifier
For additional information, refer to Application Bulletin
(SBOA055), Compensate Transimpedance Amplifiers
Intuitively, available for download at www.ti.com.
OPTIMIZING THE TRANSIMPEDANCE
CIRCUIT
To achieve the best performance, components should
be selected according to the following guidelines:
1. For lowest noise, select RF to create the total
required gain. Using a lower value for RF and
adding gain after the transimpedance amplifier
generally produces poorer noise performance.
The noise produced by RF increases with the
square-root of RF, whereas the signal increases
linearly. Therefore, signal-to-noise ratio improves
when all the required gain is placed in the
transimpedance stage.
2. Minimize photodiode capacitance and stray
capacitance at the summing junction (inverting
input). This capacitance causes the voltage noise
of the op amp to be amplified (increasing
amplification at high frequency). Using a lownoise voltage source to reverse-bias a
Copyright © 2010–2013, Texas Instruments Incorporated
HIGH-IMPEDANCE SENSOR INTERFACE
Many sensors have high source impedances that
may range up to 10MΩ, or even higher. The output
signal of sensors often must be amplified or
otherwise conditioned by means of an amplifier. The
input bias current of this amplifier can load the sensor
output and cause a voltage drop across the source
resistance, as shown in Figure 42, where (VIN+ = VS –
IBIAS × RS). The last term, IBIAS × RS, shows the
voltage drop across RS. To prevent errors introduced
to the system as a result of this voltage, an op amp
with very low input bias current must be used with
high impedance sensors. This low current keeps the
error contribution by IBIAS × RS less than the input
voltage noise of the amplifier, so that it does not
become the dominant noise factor. The OPA320
series of op amps feature very low input bias current
(typically 200fA), and are therefore ideal choices for
such applications.
RS
100kW
IB
VIN+
V+
VOUT
OPA320
V-
RF
RG
Figure 42. Noise as a Result of IBIAS
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DRIVING ADCS
The OPA320 can be used to buffer the ADC switched
input capacitance and resulting charge injection while
providing signal gain. Figure 44 shows the OPA320
configured to drive the ADS8326.
The OPA320 series op amps are well-suited for
driving sampling analog-to-digital converters (ADCs)
with sampling speeds up to 1MSPS. The zerocrossover distortion input stage topology allows the
OPA320 to drive ADCs without degradation of
differential linearity and THD.
+5V
50kW
(2.5V)
8
RG
REF1004-2.5
R1
100kW
4
R2
25kW
+5V
+5V
R4
100kW
R3
25kW
1/2
OPA2320
1/2
OPA2320
G=5+
VOUT
RL
10kW
200kW
RG
Figure 43. Two Op Amp Instrumentation Amplifier with Improved High-Frequency Common-Mode
Rejection
+5V
C1
100nF
+5V
(1)
R1
100W
V+
+IN
OPA320
(1)
C3
1nF
VVIN
0 to 4.096V
-IN
ADS8326
16-Bit
250kSPS
REF IN
Optional
R2
50kW
(2)
+5V
SD1
BAS40
-5V
C2
100nF
REF3240
4.096V
C4
100nF
(1) Suggested value; may require adjustment based on specific application.
(2) Single-supply applications lose a small number of ADC codes near ground as a result of op amp output swing limitation. If a negative
power supply is available, this simple circuit creates a –0.3V supply to allow output swing to true ground potential.
Figure 44. Driving the ADS8326
18
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ACTIVE FILTER
The OPA320 is well-suited for active filter applications
that require a wide bandwidth, fast slew rate, lownoise, single-supply operational amplifier. Figure 45
shows a 500kHz, second-order, low-pass filter using
the multiple−feedback (MFB) topology. The
components have been selected to provide a
maximally-flat Butterworth response. Beyond the
cutoff frequency, roll-off is –40dB/dec. The
Butterworth response is ideal for applications
requiring predictable gain characteristics, such as the
anti-aliasing filter used in front of an ADC.
MFB and Sallen-Key, low-pass and high-pass filter
synthesis is quickly accomplished using TI’s
FilterPro™ program. This software is available as a
free download at www.ti.com.
R3
549W
C2
150pF
R1
549W
One point to observe when considering the MFB filter
is that the output is inverted, relative to the input. If
this inversion is not required, or not desired, a
noninverting output can be achieved through one of
these options:
1. adding an inverting amplifier;
2. adding an additional second-order MFB stage; or
3. using a noninverting filter topology, such as the
Sallen-Key (shown in Figure 46).
V+
R2
1.24kW
VIN
OPA320
C1
1nF
VOUT
V-
Figure 45. Second-Order Butterworth 500kHz
Low-Pass Filter
220pF
V+
1.8kW
19.5kW
150kW
VIN = 1VRMS
3.3nF
47pF
VOUT
OPA320
V-
Figure 46. OPA320 Configured as a Three-Pole, 20kHz, Sallen-Key Filter
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (November 2011) to Revision E
Page
•
Deleted Ordering Information table ....................................................................................................................................... 2
•
Changed Shutdown, VIH and VIL parameters in Electrical Characteristics table .................................................................. 4
•
Added Figure 29 and Figure 30 .......................................................................................................................................... 11
•
Added Figure 31 and Figure 32 .......................................................................................................................................... 11
Changes from Revision C (August 2011) to Revision D
•
Page
Changed status of OPA2320 SO-8 (D) to production data from product preview. ............................................................... 2
Changes from Revision B (March 2010) to Revision C
Page
•
Added SHDN value to Electrical Characteristics condition line ............................................................................................ 3
•
Added new test condition row for Input Bias Current Over Temperature parameter ........................................................... 3
•
Changed test condition for Phase Margin parameter in Electrical Characteristics ............................................................... 3
•
Added test condition to Short-Circuit Current parameter in Electrical Characteristics ......................................................... 4
•
Changed Shutdown subsection of Electrical Characteristics along with associated notes .................................................. 4
•
Changed Power Supply subsection of Electrical Characteristics ......................................................................................... 4
•
Added values to Thermal Information tables, moved to new page, and updated format ..................................................... 5
•
Removed D (SO-8) package pinout drawing from Pin Configurations section ..................................................................... 6
•
Changed names of pins 2 and 6 for DGS (MSOP-10) package .......................................................................................... 6
•
Changed Figure 4 ................................................................................................................................................................. 7
•
Changed Figure 18 ............................................................................................................................................................... 9
•
Changed 100µs to 100ns in first paragraph of Overload Recovery Time section .............................................................. 15
•
Changed Figure 38 ............................................................................................................................................................. 15
•
Changed Figure 39 ............................................................................................................................................................. 15
•
Changed R2 value in Figure 44 from 500Ω to 50kΩ ........................................................................................................... 18
20
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Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: OPA320 OPA2320 OPA320S OPA2320S
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2320AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2320A
OPA2320AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OCLQ
OPA2320AIDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OCLQ
OPA2320AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2320A
OPA2320AIDRGR
ACTIVE
SON
DRG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OCMQ
OPA2320AIDRGT
ACTIVE
SON
DRG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OCMQ
OPA2320SAIDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPAI
OPA2320SAIDGST
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPAI
OPA320AIDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAC
OPA320AIDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAC
OPA320SAIDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAE
OPA320SAIDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAE
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Feb-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2320AIDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2320AIDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2320AIDGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2320AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA2320AIDRGR
SON
DRG
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA2320AIDRGT
SON
DRG
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA2320SAIDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2320SAIDGST
VSSOP
DGS
10
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA320AIDBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Feb-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2320AIDGKR
VSSOP
DGK
8
2500
367.0
367.0
35.0
OPA2320AIDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA2320AIDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
OPA2320AIDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA2320AIDRGR
SON
DRG
8
3000
367.0
367.0
35.0
OPA2320AIDRGT
SON
DRG
8
250
210.0
185.0
35.0
OPA2320SAIDGSR
VSSOP
DGS
10
2500
367.0
367.0
35.0
OPA2320SAIDGST
VSSOP
DGS
10
250
210.0
185.0
35.0
OPA320AIDBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
Pack Materials-Page 2
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