CM1248-08DE Low Capacitance Transient Voltage Suppressors / ESD Protectors Features http://onsemi.com • Low I/O Capacitance at 10 pF at 0 V • In−System ESD Protection to ±15 kV Contact Discharge, • • • per the IEC 61000−4−2 International Standard Compact SMT Package Saves Board Space and Facilitates Layout in Space−Critical Applications Each I/O Pin Can Withstand over 1000 ESD Strikes These Devices are Pb−Free and are RoHS Compliant 8 1 UDFN−8 DE SUFFIX CASE 517BC BLOCK DIAGRAM CM1248−08DE 8 7 6 5 DAP VN 1 2 3 4 Note: DAP (Die Attach Pad) is on back−side of chip. MARKING DIAGRAM 1 L48 MG G L48 = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† CM1248−08DE uDFN−8 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2011 February, 2011 − Rev. 4 1 Publication Order Number: CM1248−08DE/D CM1248−08DE PACKAGE / PINOUT DIAGRAMS Top View CH1 (1) CH8 (8) CH2 (2) CH7 (7) CH3 (3) CH6 (6) CH4 (4) CH5 (5) 8−Lead uDFN CM1248−08DE Table 1. PIN DESCRIPTIONS Pins Name (Refer to package / pinout diagrams) CHx (Refer to package / pinout diagrams) VN Description The cathode of the respective TVS diode, which should be connected to the node requiring transient voltage protection. The anode of the TVS diodes. SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Range Rating Units −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. STANDARD OPERATING CONDITIONS Parameter Operating Temperature Rating Units −40 to +85 °C Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1) Symbol CIN Parameter Conditions Channel Input Capacitance Min TA = 25°C, 0 VDC, 1 MHz 0 VDC, 1 MHz Typ Max 10 7 Unit pF 15 DCIN Differential Channel I/O to GND Capacitance TA = 25°C, 2.5 VDC, 1 MHz VRSO Reverse Stand−off Voltage IR = 10 mA, TA = 25°C 5.5 V IR = 1 mA, TA = 25°C 6.1 V ILEAK Leakage Current VSIG Small Signal Clamp Voltage Positive Clamp Negative Clamp I = 10 mA, TA = 25°C I = −10 mA, TA = 25°C VESD ESD Withstand Voltage Contact Discharge per IEC 61000−4−2 standard TA = 25°C (Notes 2 and 3) Diode Dynamic Resistance Forward Conduction Reverse Conduction TA = 25°C, IPP = 1 A, tP = 8/20 ms RD pF VIN = 5.0 VDC, TA = 25°C 0.25 mA VIN = 5.0 VDC 0.75 mA 1. All parameters specified at TA = −40°C to +85°C unless otherwise noted. 2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VN grounded. 3. These measurements performed with no external capacitor on CHX. http://onsemi.com 2 0.19 pF 6.8 −0.89 V kV ±15 0.57 1.36 W CM1248−08DE PERFORMANCE INFORMATION Diode Capacitance Typical diode capacitance with respect to positive TVS cathode voltage (reverse voltage across the diode) is given in Diode Capacitance vs. Reverse Voltage. Figure 1. Diode Capacitance vs. Reverse Voltage Typical High Current Diode Characteristics Measurements are made in pulsed mode with a nominal pulse width of 0.7 ms. Figure 2. Typical Input VI Characteristics (Pulse−mode Measurements, Pulse Width = 0.7 ms nominal) http://onsemi.com 3 CM1248−08DE PACKAGE DIMENSIONS UDFN8, 1.7x1.35, 0.4P CASE 517BC−01 ISSUE O A B D 2X 0.10 C PIN ONE REFERENCE 2X 0.10 C ÉÉ ÉÉ ÇÇ ÉÉ ÉÉ MOLD CMPD EXPOSED Cu A1 E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A3 DETAIL B ALTERNATE CONSTRUCTIONS TOP VIEW A DETAIL B 0.05 C 8X L L1 DETAIL A 0.05 C NOTE 4 SIDE VIEW DETAIL A 8X L (A3) L A1 C SEATING PLANE ALTERNATE TERMINAL CONSTRUCTIONS D2 1 DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 1.70 BSC 1.10 1.30 1.35 BSC 0.30 0.50 0.40 BSC 0.15 −−− 0.20 0.30 −−− 0.05 RECOMMENDED SOLDERING FOOTPRINT* E2 1.40 8X 8 K e e/2 8X 0.40 8X b PACKAGE OUTLINE 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW 1.55 0.50 8X 1 0.25 0.40 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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