STMicroelectronics M59DR016C 16 mbit 1mb x16, dual bank, page 1.8v supply flash memory Datasheet

M59DR016C
M59DR016D
16 Mbit (1Mb x16, Dual Bank, Page)
1.8V Supply Flash Memory
PRODUCT PREVIEW
■
SUPPLY VOLTAGE
– VDD = VDDQ = 1.65V to 2.2V for Program,
Erase and Read
■
– VPP = 12V for fast Program (optional)
ASYNCHRONOUS PAGE MODE READ
– Page Width: 4 words
BGA
– Page Access: 35ns
– Random Access: 100ns
■
PROGRAMMING TIME
TFBGA48 (ZB)
8 x 6 balls array
– 10µs by Word typical
– Double Word Programming Option
■
MEMORY BLOCKS
– Dual Bank Memory Array: 4 Mbit - 12 Mbit
– Parameter Blocks (Top or Bottom location)
■
Figure 1. Logic Diagram
DUAL BANK OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
■
VDD VDDQ VPP
BLOCK PROTECTION/UNPROTECTION
– All Blocks protected at Power Up
– Any combination of Blocks can be protected
20
16
A0-A19
■
COMMON FLASH INTERFACE (CFI)
■
64 bit SECURITY CODE
W
■
ERASE SUSPEND and RESUME MODES
E
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
G
■
ELECTRONIC SIGNATURE
RP
– Manufacturer Code: 20h
WP
DQ0-DQ15
M59DR016C
M59DR016D
– Top Device Code, M59DR016C: 2293h
– Bottom Device Code, M59DR016D: 2294h
VSS
AI04106
March 2001
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/37
M59DR016C, M59DR016D
Figure 2. TFBGA Connections (Top view through package)
1
2
3
A
A13
A11
A8
B
A14
A10
C
A15
D
4
5
6
7
8
VPP
WP
A19
A7
A4
W
RP
A18
A17
A5
A2
A12
A9
NC
NC
A6
A3
A1
A16
DQ14
DQ5
DQ11
DQ2
DQ8
E
A0
E
VDDQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
F
VSS
DQ7
DQ13
DQ4
VDD
DQ10
DQ1
G
AI04113
Table 1. Signal Names
A0-A19
Address Inputs
DQ0-DQ15
Data Input/Outputs, Command Inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Power Down
WP
Write Protect
VDD
Supply Voltage
VDDQ
Supply Voltage for Input/Output
Buffers
VPP
Optional Supply Voltage for
Fast Program & Erase
VSS
Ground
NC
Not Connected Internally
2/37
DESCRIPTION
The M59DR016 is a 16 Mbit non-volatile Flash
memory that may be erased electrically at block
level and programmed in-system on a Word-byWord basis using a 1.65V to 2.2V V DD supply for
the circuitry. For Program and Erase operations
the necessary high voltages are generated internally. The device supports asynchronous page
mode from all the blocks of the memory array.
The array matrix organization allows each block to
be erased and reprogrammed without affecting
other blocks. All blocks are protected against programming and erase at Power Up. Blocks can be
unprotected to make changes in the application
and then reprotected.
Instructions for Read/Reset, Auto Select, Write
Configuration Register, Programming, Block
Erase, Bank Erase, Erase Suspend, Erase Resume, Block Protect, Block Unprotect, Block Locking, CFI Query, are written to the memory through
a Command Interface using standard microprocessor write timings.
The device is offered in TFBGA48 (0.75 mm pitch)
packages and it is supplied with all the bits erased
(set to ‘1’).
M59DR016C, M59DR016D
Table 2. Absolute Maximum Ratings (1)
Symbol
Value
Unit
Ambient Operating Temperature (2)
–40 to 85
°C
TBIAS
Temperature Under Bias
–40 to 125
°C
TSTG
Storage Temperature
–55 to 155
°C
VIO (3)
Input or Output Voltage
–0.5 to VDDQ+0.5
V
Supply Voltage
–0.5 to 2.7
V
Program Voltage
–0.5 to 13
V
TA
VDD, VDDQ
VPP
Parameter
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Depends on range.
3. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
Organization
The M59DR016 is organized as 1Mb x16 bits. A0A19 are the address lines, DQ0-DQ15 are the
Data Input/Output. Memory control is provided by
Chip Enable E, Output Enable G and Write Enable
W inputs.
Reset RP is used to reset all the memory circuitry
and to set the chip in power down mode if this
function is enabled by a proper setting of the Configuration Register. Erase and Program operations
are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, DQ6 and DQ2
provide Toggle signals and DQ5 provides error bit
to indicate the state of the P/E.C operations.
Memory Blocks
The device features asymmetrically blocked architecture. M59DR016 has an array of 39 blocks and
is divided into two banks A and B, providing Dual
Bank operations. While programming or erasing in
Bank A, read operations are possible into Bank B
or vice versa. The memory also features an erase
suspend allowing to read or program in another
block within the same bank. Once suspended the
erase can be resumed. The Bank Size and Sectorization are summarized in Table 7. Parameter
Blocks are located at the top of the memory address space for the M59DR016C, and at the bottom for the M59DR016D. The memory maps are
shown in Tables 3, 4, 5 and 6.
The Program and Erase operations are managed
automatically by the P/E.C. Block protection
against Program or Erase provides additional data
security. All blocks are protected at Power Up. Instructions are provided to protect or unprotect any
block in the application. A second register locks
the protection status while WP is low (see Block
Locking description). The Reset command does
not affect the configuration of unprotected blocks
and the Configuration Register status.
3/37
M59DR016C, M59DR016D
Table 3. Bank A, Top Boot Block Addresses
M59DR016C
#
Size
(KWord)
14
13
Table 5. Bank B, Bottom Boot Block Addresses
M59DR016D
Address Range
#
Size
(KWord)
Address Range
4
0FF000h-0FFFFFh
23
32
0F8000h-0FFFFFh
4
0FE000h-0FEFFFh
22
32
0F0000h-0F7FFFh
12
4
0FD000h-0FDFFFh
21
32
0E8000h-0EFFFFh
11
4
0FC000h-0FCFFFh
20
32
0E0000h-0E7FFFh
10
4
0FB000h-0FBFFFh
19
32
0D8000h-0DFFFFh
9
4
0FA000h-0FAFFFh
18
32
0D0000h-0D7FFFh
8
4
0F9000h-0F9FFFh
17
32
0C8000h-0CFFFFh
7
4
0F8000h-0F8FFFh
16
32
0C0000h-0C7FFFh
6
32
0F0000h-0F7FFFh
15
32
0B8000h-0BFFFFh
5
32
0E8000h-0EFFFFh
14
32
0B0000h-0B7FFFh
4
32
0E0000h-0E7FFFh
13
32
0A8000h-0AFFFFh
3
32
0D8000h-0DFFFFh
12
32
0A0000h-0A7FFFh
2
32
0D0000h-0D7FFFh
11
32
098000h-09FFFFh
1
32
0C8000h-0CFFFFh
10
32
090000h-097FFFh
0
32
0C0000h-0C7FFFh
9
32
088000h-08FFFFh
8
32
080000h-087FFFh
7
32
078000h-07FFFFh
6
32
070000h-077FFFh
5
32
068000h-06FFFFh
4
32
060000h-067FFFh
3
32
058000h-05FFFFh
2
32
050000h-057FFFh
1
32
048000h-04FFFFh
0
32
040000h-047FFFh
Table 4. Bank B, Top Boot Block Addresses
M59DR016C
Size
(KWord)
Address Range
23
32
0B8000h-0BFFFFh
22
32
0B0000h-0B7FFFh
21
32
0A8000h-0AFFFFh
20
32
0A0000h-0A7FFFh
19
32
098000h-09FFFFh
18
32
090000h-097FFFh
17
32
088000h-08FFFFh
16
32
080000h-087FFFh
15
32
078000h-07FFFFh
14
32
13
32
12
32
11
32
10
32
9
8
#
Table 6. Bank A, Bottom Boot Block Addresses
M59DR016D
#
Size
(KWord)
Address Range
070000h-077FFFh
14
32
038000h-03FFFFh
068000h-06FFFFh
13
32
030000h-037FFFh
060000h-067FFFh
12
32
028000h-02FFFFh
058000h-05FFFFh
11
32
020000h-027FFFh
050000h-057FFFh
10
32
018000h-01FFFFh
32
048000h-04FFFFh
9
32
010000h-017FFFh
32
040000h-047FFFh
8
32
008000h-00FFFFh
7
32
038000h-03FFFFh
7
4
007000h-007FFFh
6
32
030000h-037FFFh
6
4
006000h-006FFFh
5
32
028000h-02FFFFh
5
4
005000h-005FFFh
4
32
020000h-027FFFh
4
4
004000h-004FFFh
3
32
018000h-01FFFFh
3
4
003000h-003FFFh
2
32
010000h-017FFFh
2
4
002000h-002FFFh
1
32
008000h-00FFFFh
1
4
001000h-001FFFh
0
32
000000h-007FFFh
0
4
000000h-000FFFh
4/37
M59DR016C, M59DR016D
Table 7. Bank Size and Sectorization
Bank Size
Parameter Blocks
Main Blocks
Bank A
4 Mbit
8 blocks of 4 KWord
7 blocks of 32 KWord
Bank B
12 Mbit
-
24 blocks of 32 KWord
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A19). The address inputs
for the memory array are latched during a write operation on the falling edge of Chip Enable E or
Write Enable W, whichever occurs last.
Data Input/Output (DQ0-DQ15). The Input is
data to be programmed in the memory array or a
command to be written to the Command Interface
(C.I.) Both input data and commands are latched
on the rising edge of Write Enable W. The Ouput
is data from the Memory Array, the Common Flash
Interface, the Electronic Signature Manufacturer
or Device codes, the Block Protection status, the
Configuration Register status or the Status Register Data Polling bit DQ7, the Toggle Bits DQ6 and
DQ2, the Error bit DQ5. The data bus is high impedance when the chip is deselected, Output Enable G is at VIH, or RP is at V IL.
Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E at VIH deselects
the memory and reduces the power consumption
to the standby level. E can also be used to control
writing to the command register and to the memory array, while W remains at V IL.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read operation. When G is at VIH the outputs are High impedance.
Write Enable (W). This input controls writing to
the Command Register and Data latches. Data are
latched on the rising edge of W.
Write Protect (WP). This input gives an additional hardware protection level against program or
erase when pulled at VIL, as described in the Block
Lock instruction description.
Reset/Power Down Input (RP). The RP input
provides hardware reset of the memory (without
affecting the Configuration Register status), and/
or Power Down functions, depending on the Configuration Register status. Reset/Power Down of
the memory is achieved by pulling RP to V IL for at
least tPLPH. When the reset pulse is given, if the
memory is in Read, Erase Suspend Read or
Standby, it will output new valid data in tPHQ7V1 after the rising edge of RP. If the memory is in Erase
or Program modes, the operation will be aborted
and the reset recovery will take a maximum ot
tPLQ7V. The memory will recover from Power
Down (when enabled) in tPHQ7V2 after the rising
edge of RP. See Tables 25, 26 and Figure 9.
VDD and VDDQ Supply Voltage (1.65V to 2.2V).
The main power supply for all operations (Read,
Program and Erase). V DD and VDDQ must be at
the same voltage.
VPP Programming Voltage (11.4V to 12.6V). Used
to provide high voltage for fast factory programming. High voltage on VPP pin is required to use
the Double Word Program instruction. It is also
possible to perform word program or erase instructions with VPP pin grounded.
VSS Ground. VSS is the reference for all the voltage measurements.
DEVICE OPERATIONS
The following operations can be performed using
the appropriate bus cycles: Read Array (Random,
and Page Modes), Write command, Output Disable, Standby, Reset/Power Down and Block
Locking. See Table 8.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Signature, the Status Register, the CFI, the Block
Protection Status or the Configuration Register
status. Read operation of the memory array is performed in asynchronous page mode, that provides
fast access time. Data is internally read and stored
in a page buffer. The page has a size of 4 words
and is addressed by A0-A1 address inputs. Read
operations of the Electronic Signature, the Status
Register, the CFI, the Block Protection Status, the
Configuration Register status and the Security
Code are performed as single asyncronous read
cycles (Random Read). Both Chip Enable E and
Output Enable G must be at VIL in order to read the
output of the memory.
Write. Write operations are used to give Instruction Commands to the memory or to latch Input
Data to be programmed. A write operation is initiated when Chip Enable E and Write Enable W are
at V IL with Output Enable G at VIH. Addresses are
latched on the falling edge of W or E whichever occurs last. Commands and Input Data are latched
on the rising edge of W or E whichever occurs first.
Noise pulses of less than 5ns typical on E, W and
G signals do not start a write cycle.
5/37
M59DR016C, M59DR016D
Table 8. User Bus Operations (1)
Operation
E
G
W
RP
WP
DQ15-DQ0
Write
VIL
VIH
VIL
VIH
VIH
Data Input
Output Disable
VIL
VIH
VIH
VIH
VIH
Hi-Z
Standby
VIH
X
X
VIH
VIH
Hi-Z
X
X
X
VIL
VIH
Hi-Z
VIL
X
X
VIH
VIL
X
Reset / Power Down
Block Locking
Note: 1. X = Don’t care.
Table 9. Read Electronic Signature (AS and Read CFI instructions)
Other
DQ15-DQ8
Addresses
E
G
W
A0
A1
A7-A2
VIL
VIL
VIH
VIL
VIL
0
Don’t Care
00h
20h
M59DR016C
VIL
VIL
VIH
VIH
VIL
0
Don’t Care
22h
93h
M59DR016D
VIL
VIL
VIH
VIH
VIL
0
Don’t Care
22h
94h
Code
Device
Manufacturer Code
DQ7-DQ0
Device Code
Table 10. Read Block Protection (AS and Read CFI instructions)
E
G
W
A0
A1
A19-A12
A7-A2
Other
Addresses
DQ0
DQ1
DQ15-DQ2
Protected Block
VIL
VIL
VIH
VIL
VIH
Block Address
0
Don’t Care
1
0
0000h
Unprotected Block
VIL
VIL
VIH
VIL
VIH
Block Address
0
Don’t Care
0
0
0000h
Locked Block
VIL
VIL
VIH
VIL
VIH
Block Address
0
Don’t Care
X
1
0000h
Block Status
Table 11. Read Configuration Register (AS and Read CFI instructions)
E
G
W
A0
A1
A7-A2
Other Addresses
DQ10
DQ9-DQ0
DQ15-DQ11
Reset
VIL
VIL
VIH
VIH
VIH
0
Don’t Care
0
Don’t Care
Reset/Power Down
VIL
VIL
VIH
VIH
VIH
0
Don’t Care
1
Don’t Care
RP Function
Dual Bank Operations. The Dual Bank allows to
read data from one bank of memory while a program or erase operation is in progress in the other
bank of the memory. Read and Write cycles can
be initiated for simultaneous operations in different
banks without any delay. Status Register during
Program or Erase must be monitored using an address within the bank being modified.
Output Disable. The data outputs are high impedance when the Output Enable G is at VIH with
Write Enable W at VIH.
Standby. The memory is in standby when Chip
Enable E is at VIH and the P/E.C. is idle. The power consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable G or Write Enable W inputs.
6/37
Automatic Standby. When in Read mode, after
150ns of bus inactivity and when CMOS levels are
driving the addresses, the chip automatically enters a pseudo-standby mode where consumption
is reduced to the CMOS standby value, while outputs still drive the bus.
Power Down. The memory is in Power Down
when the Configuration Register is set for Power
Down and RP is at VIL. The power consumption is
reduced to the Power Down level, and Outputs are
in high impedance, independent of the Chip Enable E, Output Enable G or Write Enable W inputs.
Block Locking. Any combination of blocks can
be temporarily protected against Program or
Erase by setting the lock register and pulling WP
to VIL (see Block Lock instruction).
M59DR016C, M59DR016D
INSTRUCTIONS AND COMMANDS
Seventeen instructions are defined (see Table
14), and the internal P/E.C. automatically handles
all timing and verification of the Program and
Erase operations. The Status Register Data Polling, Toggle, Error bits can be read at any time, during programming or erase, to monitor the progress
of the operation.
Instructions, made up of one or more commands
written in cycles, can be given to the Program/
Erase Controller through a Command Interface
(C.I.). The C.I. latches commands written to the
memory. Commands are made of address and
data sequences. Two Coded Cycles unlock the
Command Interface. They are followed by an input
command or a confirmation command. The Coded
Sequence consists of writing the data AAh at the
address 555h during the first cycle and the data
55h at the address 2AAh during the second cycle.
Instructions are composed of up to six cycles. The
first two cycles input a Coded Sequence to the
Command Interface which is common to all instructions (see Table 14). The third cycle inputs
the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature, Block Protection, Configuration Register
Status or CFI Query for Read operations. In order
to give additional data protection, the instructions
for Block Erase and Bank Erase require further
command inputs. For a Program instruction, the
fourth command cycle inputs the address and data
to be programmed. For a Double Word Programming instruction, the fourth and fifth command cycles input the address and data to be
programmed. For a Block Erase and Bank Erase
instructions, the fourth and fifth cycles input a further Coded Sequence before the Erase confirm
command on the sixth cycle. Any combination of
blocks of the same memory bank can be erased.
Erasure of a memory block may be suspended, in
order to read data from another block or to program data in another block, and then resumed.
When power is first applied the command interface
is reset to Read Array.
Command sequencing must be followed exactly.
Any invalid combination of commands will reset
the device to Read Array. The increased number
of cycles has been chosen to ensure maximum
data security.
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded Cycles. Subsequent read operations will read the memory array addressed and
output the data read.
CFI Query (RCFI) Instruction. Common Flash
Interface Query mode is entered writing 98h at address 55h. The CFI data structure gives information on the device, such as the sectorization, the
command set and some electrical specifications.
Tables 15, 19, 20 and 21 show the addresses
used to retrieve each data. The CFI data structure
contains also a security area; in this section, a 64
bit unique security number is written, starting at
address 80h. This area can be accessed only in
read mode by the final user and there are no ways
of changing the code after it has been written by
ST. Write a read instruction (RD) to return to Read
mode.
Table 12. Commands
Hex Code
Command
00h
Bypass Reset
10h
Bank Erase Confirm
20h
Unlock Bypass
30h
Block Erase Resume/Confirm
40h
Double Word Program
60h
Block Protect, or
Block Unprotect, or
Block Lock, or
Write Configuration Register
80h
Set-up Erase
90h
Read Electronic Signature, or
Block Protection Status, or
Configuration Register Status
98h
CFI Query
A0h
Program
B0h
Erase Suspend
F0h
Read Array/Reset
7/37
M59DR016C, M59DR016D
Auto Select (AS) Instruction. This
instruction
uses two Coded Cycles followed by one write cycle giving the command 90h to address 555h for
command set-up. A subsequent read will output
the Manufacturer or the Device Code (Electronic
Signature), the Block Protection status or the Configuration Register status depending on the levels
of A0 and A1 (see Tables 9, 10 and 11). A7-A2
must be at V IL, while other address input are ignored. The bank address is don’t care for this instruction. The Electronic Signature can be read
from the memory allowing programming equipment or applications to automatically match their
interface to the characteristics of M59DR016. The
Manufacturer Code is output when the address
lines A0 and A1 are at V IL, the Device Code is output when A0 is at VIH with A1 at VIL.
The codes are output on DQ0-DQ7 with DQ8DQ15 at 00h. The AS instruction also allows the
access to the Block Protection Status. After giving
the AS instruction, A0 is set to VIL with A1 at VIH,
while A12-A19 define the address of the block to
be verified. A read in these conditions will output a
01h if the block is protected and a 00h if the block
is not protected.
The AS Instruction finally allows the access to the
Configuration Register status if both A0 and A1
are set to VIH. If DQ10 is '0' only the Reset function
is active as RP is set to VIL (default at power-up).
If DQ10 is '1' both the Reset and the Power Down
functions will be achieved by pulling RP to VIL. The
other bits of the Configuration Register are reserved and must be ignored. A reset command
puts the device in read array mode.
Write Configuration Register (CR) Instruction. This instruction uses two Coded Cycles followed by one write cycle giving the command 60h
to address 555h. A further write cycle giving the
command 03h writes the contents of address bits
A0-A15 to the 16 bits configuration register. Bits
written by inputs A0-A9 and A11-A15 are reserved
for future use. Address input A10 defines the status of the Reset/Power Down functions. It must be
set to V IL to enable only the Reset function and to
VIH to enable also the Power Down function. At
Power Up all the Configuration Register bits are
reset to '0'.
Enter Bypass Mode (EBY) Instruction. This instruction uses the two Coded cycles followed by
one write cycle giving the command 20h to address 555h for mode set-up. Once in Bypass
mode, the device will accept the Exit Bypass
8/37
(XBY) and Program or Double Word Program in
Bypass mode (PGBY, DPGBY) commands. The
Bypass mode allows to reduce the overall programming time when large memory arrays need to
be programmed.
Exit Bypass Mode (XBY) Instruction. This instruction uses two write cycles. The first inputs to
the memory the command 90h and the second inputs the Exit Bypass mode confirm (00h). After the
XBY instruction, the device resets to Read Memory Array mode.
Program in Bypass Mode (PGBY) Instruction. This instruction uses two write cycles. The
Program command A0h is written to any Address
on the first cycle and the second write cycle latches the Address on the falling edge of W or E and
the Data to be written on the rising edge and starts
the P/E.C. Read operations within the same bank
output the Status Register bits after the programming has started. Memory programming is made
only by writing '0' in place of '1'. Status bits DQ6
and DQ7 determine if programming is on-going
and DQ5 allows verification of any possible error.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0h is
written to address 555h on the third cycle after two
Coded Cycles. A fourth write operation latches the
Address and the Data to be written and starts the
P/E.C. Read operations within the same bank output the Status Register bits after the programming
has started. Memory programming is made only
by writing '0' in place of '1'. Status bits DQ6 and
DQ7 determine if programming is on-going and
DQ5 allows verification of any possible error. Programming at an address not in blocks being
erased is also possible during erase suspend.
Double Word Program (DPG) Instruction. This
feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel. High voltage (11.4V to 12.6V) on VPP
pin is required. This instruction uses five write cycles. The double word program command 40h is
written to address 555h on the third cycle after two
Coded Cycles. A fourth write cycle latches the address and data to be written to the first location. A
fifth write cycle latches the new data to be written
to the second location and starts the P/E.C.. Note
that the two locations must have the same address
except for the address bit A0. The Double Word
Program can be executed in Bypass mode (DPGBY) to skip the two coded cycles at the beginning
of each command.
M59DR016C, M59DR016D
Table 13. Protection States (1)
Current State (2)
(WP, DQ1, DQ0)
Program/Erase
Allowed
100
Next State After Event (3)
Protect
Unprotect
Lock
WP transition
yes
101
100
111
000
101
no
101
100
111
001
110
yes
111
110
111
011
111
no
111
110
111
011
000
yes
001
000
011
100
001
no
001
000
011
101
011
no
011
011
011
111 or 110 (4)
Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status.
2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by
DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Autoselect instruction with A1 = VIH and A0 = VIL.
3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed
its logic value.
4. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
Block Protect (BP), Block Unprotect (BU),
Block Lock (BL) Instructions. All blocks are
protected at power-up. Each block of the array has
two levels of protection against program or erase
operation. The first level is set by the Block Protect
instruction; a protected block cannot be programmed or erased until a Block Unprotect instruction is given for that block. A second level of
protection is set by the Block Lock instruction, and
requires the use of the WP pin, according to the
following scheme:
– when WP is at V IH, the Lock status is overridden
and all blocks can be protected or unprotected;
– when WP is at V IL, Lock status is enabled; the
locked blocks are protected, regardless of their
previous protect state, and protection status
cannot be changed. Blocks that are not locked
can still change their protection status, and program or erase accordingly;
– the lock status is cleared for all blocks at power
up; once a block has been locked state can be
cleared only with a reset command. The protection and lock status can be monitored for each
block using the Autoselect (AS) instruction. Protected blocks will output a ‘1’ on DQ0 and locked
blocks will output a ‘1’ on DQ1.
Refer to Table 13 for a list of the protection states.
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 555h
on third cycle after the two Coded cycles. The
Block Erase Confirm command 30h is similarly
written on the sixth cycle after another two Coded
cycles and an address within the block to be
erased is given and latched into the memory.
Additional block Erase Confirm commands and
block addresses can be written subsequently to
erase other blocks in parallel, without further Coded cycles. All blocks must belong to the same
bank of memory; if a new block belonging to the
other bank is given, the operation is aborted. The
erase will start after an erase timeout period of
100µs. Thus, additional Erase Confirm commands
for other blocks must be given within this delay.
The input of a new Erase Confirm command will
restart the timeout period. The status of the internal timer can be monitored through the level of
DQ3, if DQ3 is '0' the Block Erase Command has
been given and the timeout is running, if DQ3 is '1',
the timeout has expired and the P/E.C. is erasing
the Block(s). If the second command given is not
an erase confirm or if the Coded cycles are wrong,
the instruction aborts, and the device is reset to
Read Array. It is not necessary to program the
block with 00h as the P/E.C. will do this automatically before erasing to FFh. Read operations within the same bank, after the sixth rising edge of W
or E, output the status register bits.
During the execution of the erase by the P/E.C.,
the memory accepts only the Erase Suspend ES
instruction; the Read/Reset RD instruction is accepted during the 100µs time-out period. Data
Polling bit DQ7 returns '0' while the erasure is in
progress and '1' when it has completed. The Toggle bit DQ6 toggles during the erase operation,
and stops when erase is completed.
After completion the Status Register bit DQ5 returns '1' if there has been an erase failure. In such
a situation, the Toggle bit DQ2 can be used to determine which block is not correctly erased. In the
case of erase failure, a Read/Reset RD instruction
is necessary in order to reset the P/E.C.
9/37
M59DR016C, M59DR016D
Bank Erase (BKE) Instruction. This instruction
uses six write cycles and is used to erase all the
blocks belonging to the selected bank. The Erase
Set-up command 80h is written to address 555h
on the third cycle after the two Coded cycles. The
Bank Erase Confirm command 10h is similarly
written on the sixth cycle after another two Coded
cycles at an address within the selected bank. If
the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts and the device is reset to Read Array.
It is not necessary to program the array with 00h
first as the P/E.C. will automatically do this before
erasing it to FFh. Read operations within the same
bank after the sixth rising edge of W or E output
the Status Register bits. During the execution of
the erase by the P/E.C., Data Polling bit DQ7 returns ’0’, then ’1’ on completion. The Toggle bit
DQ6 toggles during erase operation and stops
when erase is completed. After completion the
Status Register bit DQ5 returns ’1’ if there has
been an Erase Failure.
Erase Suspend (ES) Instruction. In a dual bank
memory the Erase Suspend instruction is used to
read data within the bank where erase is in
10/37
progress. It is also possible to program data in
blocks not being erased.
The Erase Suspend instruction consists of writing
the command B0h without any specific address.
No Coded Cycles are required. Erase suspend is
accepted only during the Block Erase instruction
execution. The Toggle bit DQ6 stops toggling
when the P/E.C. is suspended within 15µs after
the Erase Suspend (ES) command has been written. The device will then automatically be set to
Read Memory Array mode. When erase is suspended, a Read from blocks being erased will output DQ2 toggling and DQ6 at '1'. A Read from a
block not being erased returns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instructions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in DQ6 toggling when the data
is being programmed.
Erase Resume (ER) Instruction. If an Erase
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at an address within the bank being erased and without any Coded Cycle.
M59DR016C, M59DR016D
Table 14. Instructions (1,2)
Mne.
Instr.
Cyc.
1+
RD (4)
Read/Reset
Memory Array
1st Cyc.
Addr. (3)
2nd Cyc.
3rd Cyc.
AS
(4)
CR
PG
DPG
EBY
XBY
PGBY
CFI Query
Auto Select
Configuration
Register Write
Program
Double Word
Program
F0h
Addr.
555h
2AAh
555h
Data
AAh
55h
F0h
Addr.
55h
Data
98h
Addr.
555h
2AAh
555h
Data
AAh
55h
90h
Addr.
555h
2AAh
555h
Configuration Data
Data
AAh
55h
60h
03h
Addr.
555h
2AAh
555h
Data
AAh
55h
A0h
Addr.
555h
2AAh
555h
BP
BU
4
4
2
Block Protect
Block Unprotect
Read electronic Signature or
Block Protection or Configuration
Register Status until a new cycle
is initiated.
Program
Address Read Data Polling or
Toggle Bit until
Program Program completes.
Data
Program Program
Address 1 Address 2
5
Exit Bypass
Mode
Double Word
DPGBY Program in
Bypass Mode
Read Memory Array until a new
write cycle is initiated.
Read CFI data until a new write cycle is initiated.
3+
3
6th Cyc.
Read Memory Array until a new write cycle is initiated.
Data
1+
Enter Bypass
Mode
Program in
Bypass Mode
5th Cyc.
X
3+
RCFI
4th Cyc.
Note 6, 7
Data
AAh
55h
40h
Addr.
555h
2AAh
555h
Data
AAh
55h
20h
Addr.
X
X
Data
90h
00h
Addr.
X
Data
A0h
Addr.
X
2
Program
Data 1
Program
Data 2
Program
Address Read Data Polling or Toggle Bit until Program
Program completes.
Data
Program Program
Address 1 Address 2
3
Note 6, 7
Data
40h
Program
Data 1
Program
Data 2
Addr.
555h
2AAh
555h
Block
Address
Data
AAh
55h
60h
01h
Addr.
555h
2AAh
555h
Block
Address
Data
AAh
55h
60h
D0h
4
1
11/37
M59DR016C, M59DR016D
Mne.
BL
BE
BKE
ES
ER
Note: 1.
2.
3.
4.
Instr.
Block Lock
Block Erase
Bank Erase
Erase Suspend
Erase Resume
Cyc.
1st Cyc.
2nd Cyc.
3rd Cyc.
4th Cyc.
5th Cyc.
6th Cyc.
Addr.
555h
2AAh
555h
Block
Address
Data
AAh
55h
60h
2Fh
Addr.
555h
2AAh
555h
555h
2AAh
Block
Address
Data
AAh
55h
80h
AAh
55h
30h
Addr.
555h
2AAh
555h
555h
2AAh
Bank
Address
Data
AAh
55h
80h
AAh
55h
10h
4
6+
6
1
Addr. (3)
X
Data
B0h
Addr.
Bank
Address
Data
30h
1
Read until Toggle stops, then read all the data needed
from any Blocks not being erased then Resume Erase.
Read Data Polling or Toggle Bits until Erase completes or
Erase is suspended another time
Commands not interpreted in this table will default to read array mode.
For Coded cycles address inputs A11-A19 are don’t care.
X = Don’t Care.
The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles.
5. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
6. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0.
7. High voltage on VPP (11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction.
12/37
M59DR016C, M59DR016D
Table 15. Status Register Bits (1)
DQ
7
Name
Data
Polling
Logic Level
’1’
Erase Complete or erase block
in Erase Suspend.
’0’
Erase On-going
DQ
Program Complete or data of
non erase block during Erase
Suspend.
DQ
Program On-going (2)
’-1-0-1-0-1-0-1-’
DQ
6
Toggle Bit
’-1-1-1-1-1-1-1-’
5
4
3
2
Definition
Erase or Program On-going
Program Complete
Erase Complete or Erase
Suspend on currently addressed
block
Note
Indicates the P/E.C. status, check
during Program or Erase, and on
completion before checking bits DQ5
for Program or Erase Success.
Successive reads output
complementary data on DQ6 while
Programming or Erase operations are
on-going. DQ6 remains at constant
level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
’1’
Program or Erase Error
’0’
Program or Erase On-going
’1’
Erase Timeout Period Expired
P/E.C. Erase operation has started.
Only possible command entry is Erase
Suspend (ES)
’0’
Erase Timeout Period On-going
An additional block to be erased in
parallel can be entered to the P/E.C:
’-1-0-1-0-1-0-1-’
Erase Suspend read in the
Erase Suspended Block.
Erase Error due to the currently
addressed block (when DQ5 =
’1’).
Error Bit
This bit is set to ’1’ in the case of
Programming or Erase failure.
Reserved
Erase Time
Bit
Toggle Bit
1
Reserved
0
Reserved
1
Program on-going or Erase
Complete.
DQ
Erase Suspend read on non
Erase Suspend block.
Indicates the erase status and allows
to identify the erased block.
Note: 1. Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
2. In case of double word program DQ7 refers to the last word input.
13/37
M59DR016C, M59DR016D
Table 16. Polling and Toggle Bits
Mode
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
N/A
Erase Suspend Read
(in Erase Suspend
block)
1
1
Toggle
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ6
DQ2
Erase Suspend Program
DQ7
Toggle
1
Program
STATUS REGISTER BITS
P/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 bits. Any read attempt within
the Bank being modified and during Program or
Erase command execution will automatically output these five Status Register bits. The P/E.C. automatically sets bits DQ2, DQ5, DQ6 and DQ7.
Other bits (DQ0, DQ1 and DQ4) are reserved for
future use and should be masked (see Tables 15
and 16). Read attemps within the bank not being
modified will output array data.
Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7. In
case of a double word program operation, the
complement is done on DQ7 of the last word written to the command interface, i.e. the data written
in the fifth cycle. During Erase operation, it outputs
a ’0’. After completion of the operation, DQ7 will
output the bit last programmed or a ’1’ after erasing. Data Polling is valid and only effective during
P/E.C. operation, that is after the fourth W pulse
for programming or after the sixth W pulse for
erase. It must be performed at the address being
programmed or at an address within the block being erased. See Figure 12 for the Data Polling
flowchart and Figure 10 for the Data Polling waveforms. DQ7 will also flag the Erase Suspend mode
by switching from ’0’ to ’1’ at the start of the Erase
Suspend. In order to monitor DQ7 in the Erase
Suspend mode an address within a block being
erased must be provided. For a Read Operation in
14/37
Suspend mode, DQ7 will output ’1’ if the read is attempted on a block being erased and the data value on other blocks. During Program operation in
Erase Suspend Mode, DQ7 will have the same behaviour as in the normal program execution outside of the suspend mode.
Toggle Bit (DQ6). When Programming or Erasing operations are in progress, successive attempts to read DQ6 will output complementary
data. DQ6 will toggle following toggling of either G,
or E when G is at VIL. The operation is completed
when two successive reads yield the same output
data. The next read will output the bit last programmed or a ’1’ after erasing. The toggle bit DQ6
is valid only during P/E.C. operations, that is after
the fourth W pulse for programming or after the
sixth W pulse for Erase. DQ6 will be set to ’1’ if a
Read operation is attempted on an Erase Suspend
block. When erase is suspended DQ6 will toggle
during programming operations in a block different
from the block in Erase Suspend. Either E or G
toggling will cause DQ6 to toggle. See Figure 13
for Toggle Bit flowchart and Figure 11 for Toggle
Bit waveforms.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. During Erase Suspend a read from a block being erased will cause
DQ2 to toggle. A read from a block not being
erased will output data. DQ2 will be set to ’1’ during
program operation and to ‘0’ in Erase operation.
After erase completion and if the error bit DQ5 is
set to '1', DQ2 will toggle if the faulty block is addressed.
Error Bit (DQ5). This bit is set to '1' by the P/E.C.
when there is a failure of programming or block
erase, that results in invalid data in the memory
block. In case of an error in block erase or program, the block in which the error occurred or to
which the programmed data belongs, must be discarded. Other Blocks may still be used. The error
bit resets after a Read/Reset (RD) instruction. In
case of success of Program or Erase, the error bit
will be set to '0'.
Erase Timer Bit (DQ3). This bit is set to ‘0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, DQ3 returns to ‘1’, in the range
of 80µs to 120µs.
M59DR016C, M59DR016D
Table 17. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C; VDD = V DDQ = 1.65V to 2.2V, VPP = VDD unless otherwise specified)
M59DR016
Parameter
Max (1)
Typical after
100k W/E Cycles
Unit
Typ
Parameter Block (4 KWord) Erase (Preprogrammed)
2.5
0.15
0.4
s
Main Block (32 KWord) Erase (Preprogrammed)
10
1
3
s
Bank Erase (Preprogrammed, Bank A)
2
6
s
Bank Erase (Preprogrammed, Bank B)
10
30
s
Chip Program (2)
20
25
s
Chip Program (DPG, VPP = 12V) (2)
10
Min
s
Word Program (3)
200
10
10
µs
Double Word Program
200
10
10
µs
Program/Erase Cycles (per Block)
100,000
cycles
Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or
erase should perform significantly better.
2. Excludes the time needed to execute the sequence for program instruction.
3. Same timing value if V PP = 12V.
POWER CONSUMPTION
Power Down
The memory provides Reset/Power Down control
input RP. The Power Down function can be activated only if the relevant Configuration Register bit
is set to ’1’. In this case, when the RP signal is
pulled at V SS the supply current drops to typically
ICC2 (see Table 22), the memory is deselected and
the outputs are in high impedance.If RP is pulled
to VSS during a Program or Erase operation, this
operation is aborted in tPLQ7V and the memory
content is no longer valid (see Reset/Power Down
input description).
Power Up
The memory Command Interface is reset on Power Up to Read Array. Either E or W must be tied to
VIH during Power Up to allow maximum security
and the possibility to write a command on the first
rising edge of W.
Supply Rails
Normal precautions must be taken for supply voltage decoupling; each device in a system should
have the V DD rails decoupled with a 0.1µF capacitor close to the VDD, VDDQ and VSS pins. The PCB
trace widths should be sufficient to carry the required VDD program and erase currents.
15/37
M59DR016C, M59DR016D
COMMON FLASH INTERFACE (CFI)
The Common Flash Interface (CFI) specification is
a JEDEC approved, standardised data structure
that can be read from the Flash memory device.
CFI allows a system software to query the flash
device to determine various electrical and timing
parameters, density information and functions
supported by the device. CFI allows the system to
easily interface to the Flash memory, to learn
about its features and parameters, enabling the
software to configure itself when necessary.
Tables 18, 19, 20 and 21 show the address used
to retrieve each data.
The CFI data structure gives information on the
device, such as the sectorization, the command
set and some electrical specifications. Tables 18,
19, 20 and 21 show the addresses used to retrieve
each data. The CFI data structure contains also a
security area; in this section, a 64 bit unique security number is written, starting at address 81h. This
area can be accessed only in read mode and there
are no ways of changing the code after it has been
written by ST. Write a read instruction to return to
Read mode. Refer to the CFI Query instruction to
understand how the M59DR016 enters the CFI
Query mode.
Table 18. Query Structure Overview
Offset
Sub-section Name
Description
00h
Reserved
Reserved for algorithm-specific information
10h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
System Interface Information
Device timing & voltage information
27h
Device Geometry Definition
Flash device layout
P
Primary Algorithm-specific Extended Query table
Additional information specific to the Primary
Algorithm (optional)
A
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections
detailled in Tables 19, 20 and 21. Query data are always presented on the lowest order data outputs.
Table 19. CFI Query Identification String
Offset
Data
Description
00h
0020h
01h
2293h - top
2294h - bottom
02h-0Fh
reserved
10h
0051h
Query Unique ASCII String "QRY"
11h
0052h
Query Unique ASCII String "QRY"
12h
0059h
Query Unique ASCII String "QRY"
13h
0002h
14h
0000h
Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm
15h
offset = P = 0040h
16h
0000h
17h
0000h
18h
0000h
19h
value = A = 0000h
1Ah
0000h
Manufacturer Code
Device Code
Reserved
Address for Primary Algorithm extended Query table
Alternate Vendor Command Set and Control Interface ID Code second vendor
- specified algorithm supported (note: 0000h means none exists)
Address for Alternate Algorithm extended Query table
note: 0000h means none exists
Note: Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
16/37
M59DR016C, M59DR016D
Table 20. CFI Query System Interface Information
Offset
Data
1Bh
0017h
VDD Logic Supply Minimum Program/Erase or Write voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 millivolts
1Ch
0022h
VDD Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 millivolts
0000h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 millivolts
Note: This value must be 0000h if no VPP pin is present
1Eh
00C0h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 millivolts
Note: This value must be 0000h if no VPP pin is present
1Fh
0004h
Typical timeout per single byte/word program (multi-byte program count = 1), 2n µs
(if supported; 0000h = not supported)
20h
0000h
Typical timeout for maximum-size multi-byte program or page write, 2n µs
(if supported; 0000h = not supported)
21h
000Ah
Typical timeout per individual block erase, 2n ms
(if supported; 0000h = not supported)
22h
0000h
Typical timeout for full chip erase, 2n ms
(if supported; 0000h = not supported)
23h
0004h
Maximum timeout for byte/word program, 2n times typical (offset 1Fh)
(0000h = not supported)
24h
0000h
Maximum timeout for multi-byte program or page write, 2n times typical (offset 20h)
(0000h = not supported)
25h
0004h
Maximum timeout per individual block erase, 2n times typical (offset 21h)
(0000h = not supported)
26h
0000h
Maximum timeout for chip erase, 2n times typical (offset 22h)
(0000h = not supported)
1Dh
Description
17/37
M59DR016C, M59DR016D
Table 21. Device Geometry Definition
Offset Word
Mode
Data
27h
0015h
28h
0001h
29h
0000h
2Ah
0000h
2Bh
0000h
2Ch
0002h
Description
Device Size = 2n in number of bytes
Flash Device Interface Code description: Asynchronous x16
Maximum number of bytes in multi-byte program or page = 2n
Number of Erase Block Regions within device
bit 7 to 0 = x = number of Erase Block Regions
Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk."
2. x specifies the number of regions within the device containing one or more contiguous Erase Blocks of the same size. For example, a 128KB device (1Mb)
having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is considered
to have 5 Erase Block Regions. Even though two regions both contain 16KB
blocks, the fact that they are not contiguous means they are separate Erase
Block Regions.
3. By definition, symmetrically block devices have only one blocking region.
M59DR016C M59DR016C Erase Block Region Information
2Dh
001Eh
2Eh
0000h
2Fh
0000h
30h
0001h
31h
0007h
32h
0000h
33h
0020h
34h
0000h
M59DR016D M59DR016D
2Dh
0007h
2Eh
0000h
2Fh
0020h
30h
0000h
31h
001Eh
32h
0000h
33h
0000h
34h
0001h
18/37
bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in
size. The value z = 0 is used for 128 byte block size.
e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K
bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase
Block Region:
e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number]
y = 0 means no blocking (# blocks = y+1 = "1 block")
Note: y = 0 value must be used with number of block regions of one as indicated
by (x) = 0
M59DR016C, M59DR016D
Table 22. AC Measurement Conditions
Input Rise and Fall Times
Figure 4. AC Testing Load Circuit
≤ 4ns
VDDQ / 2
0 to VDDQ
Input Pulse Voltages
Input and Output Timing Ref. Voltages
VDDQ/2
1N914
3.3kΩ
Figure 3. Testing Input/Output Waveforms
DEVICE
UNDER
TEST
VDDQ
OUT
CL = 30pF
VDDQ/2
0V
CL includes JIG capacitance
AI02315
AI02316
Table 23. Capacitance (1)
(TA = 25 °C, f = 1 MHz)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
19/37
M59DR016C, M59DR016D
Table 24. DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VDD = VDDQ = 1.65V to 2.2V)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
0V ≤ VIN ≤ VDD
±1
µA
0V ≤ VOUT ≤ VDD
±5
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC1
Supply Current
(Read Mode)
E = VIL, G = VIH, f = 6MHz
10
20
mA
ICC2
Supply Current
(Power Down)
RP = VSS ± 0.2V
2
10
µA
ICC3
Supply Current (Standby)
E = VDD ± 0.2V
15
50
µA
ICC4 (1)
Supply Current
(Program or Erase)
Word Program, Block Erase
in progress
10
20
mA
ICC5 (1)
Supply Current
(Dual Bank)
Program/Erase in progress
in one Bank, Read in the
other Bank
20
40
mA
VPP = 12V ± 0.6V
5
10
mA
VPP ≤ VCC
0.2
5
µA
VPP = 12V ± 0.6V
100
400
µA
IPP1
VPP Supply Current
(Program or Erase)
IPP2
VPP Supply Current
(Standby or Read)
VIL
Input Low Voltage
–0.5
0.4
V
VIH
Input High Voltage
VDDQ –0.4
VDDQ + 0.4
V
VOL
Output Low Voltage
IOL = 100µA
0.1
V
VOH
Output High Voltage
CMOS
IOH = –100µA
VPP (2,3)
VPP Supply Voltage
(Program or Erase)
VDDQ –0.1
Double Word Program
Note: 1. Sampled only, not 100% tested.
2. VPP may be connected to 12V power supply for a total of less than 100 hrs.
3. For standard program/erase operation VPP is don’t care.
20/37
V
–0.4
VDD + 0.4
V
11.4
12.6
V
M59DR016C, M59DR016D
Table 25. Read AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VDD = VDDQ = 1.65V to 2.2V)
M59DR016
Symbol
Alt
Parameter
Test Condition
100
Min
120
Max
Min
Unit
Max
tAVAV
tRC
Address Valid to Next
Address Valid
E = VIL, G = VIL
tAVQV
tACC
Address Valid to Output
Valid (Random)
E = VIL, G = VIL
100
120
ns
tAVQV1
tPAGE
Address Valid to Output
Valid (Page)
E = VIL, G = VIL
35
45
ns
tELQX (1)
tLZ
Chip Enable Low to Output
Transition
G = VIL
tELQV (2)
tCE
Chip Enable Low to Output
Valid
G = VIL
tGLQX (1)
tOLZ
Output Enable Low to
Output Transition
E = VIL
tGLQV (2)
tOE
Output Enable Low to
Output Valid
E = VIL
tEHQX
tOH
Chip Enable High to Output
Transition
G = VIL
tEHQZ (1)
tHZ
Chip Enable High to Output
Hi-Z
G = VIL
tGHQX
tOH
Output Enable High to
Output Transition
E = VIL
tGHQZ (1)
tDF
Output Enable High to
Output Hi-Z
E = VIL
tAXQX
tOH
Address Transition to
Output Transition
E = VIL, G = VIL
100
120
0
ns
0
100
0
ns
120
0
25
0
ns
35
0
25
0
0
0
ns
ns
35
25
ns
ns
ns
35
0
ns
ns
tPHQ7V1
RP High to Data Valid
(Read Mode)
150
150
ns
tPHQ7V2
RP High to Data Valid
(Power Down enabled)
50
50
µs
tPLQ7V
RP Low to Reset Complete
During Program/Erase
15
µs
tPLPH
tRP
RP Pulse Width
100
100
ns
Note: 1. Sampled only, not 100% tested.
2. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV .
21/37
22/37
Note: Write Enable (W) = High.
DQ0-DQ15
G
E
A0-A19
tAVQV
tGLQV
tGLQX
tELQX
tELQV
VALID
tAVAV
VALID
tGHQZ
tGHQX
tEHQX
tEHQZ
tAXQX
AI04107
M59DR016C, M59DR016D
Figure 5. Random Read AC Waveforms
DQ0-DQ15
G
E
A0-A1
A2-A19
tAVQV
tELQV
VALID
VALID
tGLQV
VALID
tAVQV1
VALID
VALID
VALID
VALID
tEHQX
VALID
tGHQX
VALID
tEHQZ
tGHQZ
AI04108
M59DR016C, M59DR016D
Figure 6. Page Read AC Waveforms
23/37
M59DR016C, M59DR016D
Table 26. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70 °C or –40 to 85 °C; VDD = VDDQ = 1.65V to 2.2V)
M59DR016
Symbol
Alt
Parameter
100
Min
tAVAV
tWC
Address Valid to Next Address Valid
tELWL
tCS
tWLWH
120
Max
Min
Unit
Max
100
120
ns
Chip Enable Low to Write Enable Low
0
0
ns
tWP
Write Enable Low to Write Enable High
50
50
ns
tDVWH
tDS
Input Valid to Write Enable High
50
50
ns
tWHDX
tDH
Write Enable High to Input Transition
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
30
30
ns
tAVWL
tAS
Address Valid to Write Enable Low
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
50
50
ns
Output Enable High to Write Enable Low
0
0
ns
tGHWL
tVDHEL
tVCS
VDD High to Chip Enable Low
50
50
µs
tWHGL
tOEH
Write Enable High to Output Enable Low
30
30
ns
tPLQ7V
24/37
RP Low to Reset Complete During
Program/Erase
15
15
µs
M59DR016C, M59DR016D
Table 27. Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70 °C or –40 to 85 °C; VDD = VDDQ = 1.65V to 2.2V)
M59DR016
Symbol
Alt
Parameter
100
Min
tAVAV
tWC
Address Valid to Next Address Valid
tWLEL
tWS
tELEH
120
Max
Min
Unit
Max
100
120
ns
Write Enable Low to Chip Enable Low
0
0
ns
tCP
Chip Enable Low to Chip Enable High
50
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
50
50
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
30
30
ns
tAVEL
tAS
Address Valid to Chip Enable Low
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
50
50
ns
0
0
ns
tGHEL
Output Enable High Chip Enable Low
tVDHWL
tVCS
VDD High to Write Enable Low
50
50
µs
tEHGL
tOEH
Chip Enable High to Output Enable Low
30
30
ns
tPLQ7V
RP Low to Reset Complete During
Program/Erase
15
15
µs
25/37
M59DR016C, M59DR016D
Figure 7. Write AC Waveforms, W Controlled
tAVAV
A0-A19
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ15
tWHDX
VALID
VDD
tVDHEL
AI04109
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
26/37
M59DR016C, M59DR016D
Figure 8. Write AC Waveforms, E Controlled
tAVAV
A0-A19
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ15
tEHDX
VALID
VDD
tVDHWL
AI04110
Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.
27/37
M59DR016C, M59DR016D
Table 28. Data Polling and Toggle Bits AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VDD = VDDQ = 1.65V to 2.2V)
M59DR016
Symbol
tWHQ7V
tEHQ7V
tQ7VQV
tWHQV
tEHQV
Parameter
Max
Write Enable High to DQ7 Valid (Program, W Controlled)
10
200
µs
Write Enable High to DQ7 Valid (Block Erase, W Controlled)
1
10
s
Chip Enable High to DQ7 Valid (Program, E Controlled)
10
200
µs
Chip Enable High to DQ7 Valid (Block Erase, E Controlled)
1
10
s
0
ns
Q7 Valid to Output Valid (Data Polling)
Write Enable High to Output Valid (Program)
10
200
µs
Write Enable High to Output Valid (Block Erase)
1
10
s
Chip Enable High to Output Valid (Program)
10
200
µs
Chip Enable High to Output Valid (Block Erase)
1
10
s
Note: 1. All other timings are defined in Read AC Characteristics table.
28/37
Unit
Min
M59DR016C, M59DR016D
tPLQ7V
tPLPH
RP
DQ7
W
tPHQ7V
READ
VALID
DQ7
PROGRAM / ERASE
VALID
AI02619
Figure 9. Read and Write AC Characteristics, RP Related
29/37
30/37
DQ0-DQ6/
DQ8-DQ15
DQ7
W
G
E
A0-A19
LAST WRITE
CYCLE OF
PROGRAM
OR ERASE
INSTRUCTION
DATA POLLING
READ CYCLES
tWHQ7V
tEHQ7V
tELQV
tAVQV
tQ7VQV
IGNORE
DQ7
DATA POLLING (LAST) CYCLE
tGLQV
ADDRESS (WITHIN BLOCKS)
VALID
VALID
AI04111
MEMORY
ARRAY
READ CYCLE
M59DR016C, M59DR016D
Figure 10. Data Polling DQ7 AC Waveforms
DATA
TOGGLE
READ CYCLE
Note: All other timings are as a normal Read cycle.
LAST WRITE
CYCLE OF
PROGRAM
OF ERASE
INSTRUCTION
DQ0-DQ1,DQ3-DQ5,
DQ7-DQ15
DQ6,DQ2
W
G
E
A0-A19
DATA TOGGLE
READ CYCLE
IGNORE
STOP TOGGLE
tWHQV
tEHQV
tAVQV
MEMORY ARRAY
READ CYCLE
VALID
VALID
tGLQV
tELQV
VALID
AI04112
M59DR016C, M59DR016D
Figure 11. Data Toggle DQ6, DQ2 AC Waveforms
31/37
M59DR016C, M59DR016D
Figure 12. Data Polling Flowchart
Figure 13. Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
DQ6
=
TOGGLES
YES
NO
NO
YES
NO
DQ5
=1
DQ5
=1
YES
YES
READ DQ7
READ DQ6
DQ7
=
DATA
YES
DQ6
=
TOGGLES
NO
FAIL
NO
NO
YES
PASS
FAIL
PASS
AI02574
AI02626
32/37
M59DR016C, M59DR016D
Table 29. Ordering Information Scheme
Example:
M59DR016C
100 ZB
6
T
Device Type
M59
Architecture
D = Dual Bank Page Mode
Operating Voltage
R = 1.8V
Device Function
016C = 16 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot
016D = 16 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot
Random Speed
100 = 100 ns
120 = 120 ns
Package
ZB = TFBGA48: 0.75mm pitch
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Option
T = Tape & Reel packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
Table 30. Daisy Chain Ordering Scheme
Example:
M59DR016
-ZB T
Device Type
M59DR016
Daisy Chain
-ZB = TFBGA48: 0.75mm pitch
Option
T = Tape & Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
33/37
M59DR016C, M59DR016D
Table 31. Revision History
Date
Version
March 2001
-01
34/37
Revision Details
First Issue
M59DR016C, M59DR016D
Table 32. TFBGA48 - 8 x 6 balls array, 0.75 mm pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
A
Typ
Min
Max
1.350
A1
0.300
0.200
0.0531
0.350
A2
0.0118
0.0079
0.0138
1.000
b
0.300
0.550
0.0394
0.0118
0.0217
D
7.000
6.900
7.100
0.2756
0.2717
0.2795
D1
5.250
–
–
0.2067
–
–
ddd
0.100
0.0039
E
12.000
11.900
12.100
0.4724
0.4685
0.4764
E1
3.750
–
–
0.1476
–
–
e
0.750
–
–
0.0295
–
–
SD
0.375
–
–
0.0148
–
–
SE
0.375
–
–
0.0148
–
–
FE
4.125
–
–
0.1624
–
–
FD
0.875
–
–
0.0344
–
–
Figure 14. TFBGA48 - 8 x 6 balls array, 0.75 mm pitch, Package Outline
D
D1
FD
SD
FE
SE
E1
E
ddd
BALL "A1"
A
e
b
A2
A1
BGA-Z03
Drawing is not to scale.
35/37
M59DR016C, M59DR016D
Figure 15. TFBGA48 Daisy Chain - Package Connections (Top view through package
1
2
3
4
5
6
7
8
A
B
C
D
E
F
AI03079
Figure 16. TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package)
1
2
3
4
5
6
7
8
START
POINT
A
B
C
D
E
END
POINT
F
AI03080
36/37
M59DR016C, M59DR016D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners.
 2001 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
www.st.com
37/37