Fujitsu MB90523PFF 16-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13702-4E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90520 Series
MB90522/523/F523/V520
■ DESCRIPTION
The MB90520 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process
control applications in consumer products that require high-speed real-time processing.
The instruction set of the F2MC-16LX CPU core inherits AT architecture of the F2MC* family with additional
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division
instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for
processing long word data.
The MB90520 series has peripheral resources of 8/10-bit A/D converter, 8-bit D/A converter, UART (SCI),
extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and 1,
I/O timer (16-bit free-run timers 1 and 2, input captures 0 and 1 (ICU), output compares 0 and 1 (OCU)), and
an LCD controller/driver.
*:F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
■ FEATURES
• Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
The system can be operated by a sub-clock (rated at 32.768 kHz).
Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, four times the oscillation clock, operation
at VCC of 5.0 V)
(Continued)
■ PACKAGES
120-pin Plastic LQFP
120-pin Plastic QFP
(FPT-120P-M05)
(FPT-120P-M13)
MB90520 Series
(Continued)
• Maximum memory space
16 Mbytes
• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed
4-byte instruction queue
• Enhanced interrupt function
8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS): Up to 16 channels
• Embedded ROM size and types
Mask ROM: 64 kbytes/128 kbytes
Flash ROM: 128 kbytes
• Embedded RAM size
Mask ROM: 4 kbytes
Flash ROM: 4 kbytes
Evaluation product: 6 kbytes
• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware stand-by mode
Clock mode (mode in which other than sub-clock and timebase timer are stopped)
• Process
CMOS technology
• I/O port
General-purpose I/O ports (CMOS): 53 ports
General-purpose I/O ports (via pull-up resistors): 24 ports
General-purpose I/O ports (open-drain): 8 ports
Total: 85 ports
• Timer
Timebase timer/watchdog timer: 1 channel
8/16-bit PPG timers 0, 1: 8-bit × 2 channels or 16-bit × 1 channel
• 16-bit re-load timers 0, 1: 2 channels
(Continued)
2
MB90520 Series
(Continued)
• 16-bit I/O timer
16-bit free-run timers 1, 2: 2 channels
Input captures 0, 1 (ICU): Generates an interrupt request by latching a 16-bit free-run timer counter value upon
detection of an edge input to the pin.
Output compares 0, 1 (OCU): Generates an interrupt request and reverses the output level upon detection of a
match between the 16-bit free-run timer counter value and the compare setting
value.
8/16-bit up/down counter/timers 0, 1: 1 channel (8-bit × 2 channels)
• Extended I/O serial interfaces 0, 1: 1 channel
• UART (SCI)
With full-duplex double buffer
Clock asynchronized or clock synchronized transmission can be selectively used.
• DTP/external interrupt circuit (8 channels)
A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered
by an external input.
• Wake-up interrupt
Receives external interrupt requests and generates an interrupt request upon an “L” level input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.
Conversion time: minimum 15.0 µs (at machine clock frequency of 16 MHz, including sampling time)
• 8-bit D/A converter (based on the R-2R system)
8-bit resolution: 2 channels (independent)
Setup time: 12.5 µs
• Clock timer: 1 channel
• LCD controller/driver
A common driver and a segment driver that can directly drive the LCD (liquid crystal display) panel
• Clock output function
Note: Do not set external bus mode for the MB90520 series because it cannot be operated in this mode.
3
MB90520 Series
■ PRODUCT LINEUP
Part number
MB90522
Item
Classification
ROM size
MB90523
Mask ROM product
64 kbytes
RAM size
MB90F523
MB90V520
Flash ROM product Evaluation product
128 kbytes
4 kbytes
None
6 kbytes
Number of instructions: 351
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
CPU functions
Minimum execution time: 62.5 ns
(at machine clock frequency of 16 MHz)
Interrupt processing time: 1.5 µs
(at machine clock frequency of 16 MHz, minimum value)
General-purpose I/O ports (CMOS output): 53
General-purpose I/O ports (via pull-up resistor): 24
General-purpose I/O ports (N-ch open-drain output): 8
Total: 85
Ports
Clock synchronized transmission (62.5 kbps to 1 Mbps)
Clock asynchronized transmission (1202 bps to 9615 bps)
Transmission can be performed by bi-directional serial transmission or by
master/slave connection.
UART (SCI)
8/10-bit A/D converter
Conversion precision: 8/10-bit can be selectively used.
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Scan conversion mode (converts two or more successive channels and can
program up to 8 channels.)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timers 0, 1
Number of channels: 1 (8-bit × 2 channels)
PPG operation of 8-bit or 16-bit
Pulse wave of given intervals and given duty ratios can be output.
Pulse interval: 62.5 ns to 1 µs (at machine clock frequency of 16 MHz)
8/16-bit up/down counter/
timers 0, 1
Number of channels: 1 (8-bit × 2 channels)
Event input: 6 channels
8-bit up/down counter/timer used: 2 channels
8-bit re-load/compare function supported: 1 channel
16-bit
I/O timer
16-bit free-run
timers 1, 2
Number of channels: 2
Overflow interrupts
(Continued)
4
MB90520 Series
(Continued)
Part number
MB90523
MB90523
MB90F523
MB90V520
Item
16-bit
I/O timer
Output
compares 0, 1
(OCU)
Number of channels: 8
Pin input factor: Match signal of compare register
Input captures
0, 1 (ICU)
Number of channels: 2
Rewriting register value upon pin input (rising, falling, or both edges)
DTP/external interrupt circuit
Number of inputs: 8
Started by rising edge, falling edge, “H” level input, or “L” level input.
External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.
Number of inputs: 8
Started by “L” level input.
Wake-up intrrupt
Delayed interrupt generation
module
Extended I/O serial
interfaces 0, 1
Timebase timer
8-bit D/A converter
LCD controller/driver
Watchdog timer
Low-power consumption
(stand-by) mode
Interrupt generation module for switching tasks
Used in real-time operating systems.
Clock synchronized transmission (3125 bps to 1 Mbps)
LSB first/MSB first
18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(at oscillation of 4 MHz)
8-bit resolution
Number of channels: 2 channels
Based on R-2R system
Number of common output pins: 4
Number of segment output pins: 32
Number of power supply pins for LCD drive: 4
RAM for LCD indication: 16 bytes
Booster for LCD drive: Internal
Split resistor for LCD drive: Internal
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by
Process
Power supply voltage for
operation*
CMOS
3.0 V to 5.5 V
4.0 V to 5.5 V
3.0 V to 5.5 V
* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
Assurance for the MB90V520 is given only for operation with a tool at a power voltage of 3.0 V to 5.5 V, an
operating temperature of 0 to 55 degrees centigrade, and an operating frequency of 1 MHz to 16 MHz.
5
MB90520 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB90522
MB90523
MB90F523
FPT-120P-M05
FPT-120P-M13
: Available
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
■ DIFFERENCES AMONG PRODUCTS
Memory Size
In evaluation with an evaluation chip, note the difference between the evaluation chip and the chip actually used.
The following items must be taken into consideration.
• The MB90V520 does not have an internal ROM. However, operations equivalent to those performed by a chip
with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM
size by setting the development tool.
• In the MB90V520, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH are
mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)
• In the MB90522, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank
FF only.
• In the MB90523/F523, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH
to bank FE and bank FF.
6
MB90520 Series
■ PIN ASSIGNMENT
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P30
VSS
P27/ADTG
P26/ZIN0/INT7
P25/BIN0
P24/AIN0
P23/IC11
P22/IC10
P21/IC01
P20/IC00
P17/WI7
P16/WI6
P15/WI5
P14/WI4
P13/WI3
P12/WI2
P11/WI1
P10/WI0
P07
P06/INT6
P05/INT5
P04/INT4
P03/INT3
P02/INT2
P01/INT1
P00/INT0
VCC
X1
X0
VSS
(Top view)
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RST
MD0
MD1
MD2
HST
V3
V2
V1
V0
P97/SEG31
P96/SEG30
P95/SEG29
P94/SEG28
P93/SEG27
P92/SEG26
P91/SEG25
X0A
X1A
P90/SEG24
P87/SEG23
P86/SEG22
P85/SEG21
P84/SEG20
P83/SEG19
P82/SEG18
P81/SEG17
P80/SEG16
VSS
P77/COM3
P76/COM2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PA6/SEG14
PA7/SEG15
VSS
C
P50/SIN2/AIN1
P51/SOT2/BIN1
P52/SCK2/ZIN1
DVCC
DVSS
P53/DA0
P54/DA1
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VCC
P70/TI0/OUT4
P71/TO0/OUT5
P72/TI1/OUT6
P73/TO1/OUT7
P74/COM0
P75/COM1
P31/CKOT
P32/OUT0
P33/OUT1
P34/OUT2
P35/OUT3
P36/PG00
P37/PG01
VCC
P40/PG10
P41/PG11
P42/SIN0
P43/SOT0
P44/SCK0
P45/SIN1
P46/SOT1
P47/SCK1
SEG00
SEG01
SEG02
SEG03
SEG04
SEG05
SEG06
SEG07
PA0/SEG08
PA1/SEG09
PA2/SEG10
PA3/SEG11
PA4/SEG12
PA5/SEG13
(FPT-120P-M05)
(FPT-120P-M13)
7
MB90520 Series
■ PIN DESCRIPTION
Pin no.
Pin name
LQFP-120*1
QFP-120*2
Circuit
type
92,
93
X0,
X1
A
This is a high-speed crystal oscillator pin.
74,
73
X0A,
X1A
B
This is a low-speed crystal oscillator pin.
MD0 to MD2
C
This is an input pin for selecting operation modes.
Connect directly to VCC or VSS.
90
RST
C
This is an external reset request signal input pin.
86
HST
C
This is a hardware stand-by input pin.
P00 to P06
D
This is a general-purpose I/O port.
This function can be set by the port 0 input pull-up resistor setup
register (RDR0) for input. For output, however, this function is
invalid.
89 to 87
95 to 101
INT0 to INT6
102
103 to 110
This is a request input pin of the DTP/external interrupt circuit ch.0
to ch.6.
P07
D
This is a general-purpose I/O port.
This function can be set by the port 0 input pull-up resistor setup
register (RDR0) for input. For output, however, this function is
invalid.
P10 to 17
D
This is a general-purpose I/O port.
This function can be set by the port 1 input pull-up resistor setup
register (RDR1) for input. For output, however, this function is
invalid.
WI0 to WI7
111,
112,
113,
114
P20,
P21,
P22,
P23
This is an I/O pin for wake-up interrupts.
E
IC00,
IC01,
IC10,
IC11
115
P24
116
P25
BIN0
*1: FPT-120P-M05
*2: FPT-120P-M13
This is a general-purpose I/O port.
This is a trigger input pin for input capture (ICU) 0 and 1.
Since this input is used as required for input capture 0 and 1 (ICU)
ch.0, ch.01, ch.10 and ch.11 input operation, output by other
functions must be suspended except for intentional operation.
E
AIN0
8
Function
This is a general-purpose I/O port.
This port can be used as count clock A input for 8/16-bit up/down
counter/timer 0.
E
This is a general-purpose I/O port.
This port can be used as count clock B input for 8/16-bit up/down
counter/timer 0.
(Continued)
MB90520 Series
Pin no.
Pin name
LQFP-120*1
QFP-120*2
117
118
P26
Circuit
type
E
Function
This is a general-purpose I/O port.
ZIN0
This port can be used as count clock Z input for 8/16-bit up/down
counter/timer 0.
INT7
This is a request input pin of the DTP/external interrupt circuit
ch.7.
P27
E
ADTG
This is a general-purpose I/O port.
This is an external trigger input pin of the 8/10-bit A/D converter.
Since this input is used as required for 8/10-bit A/D converter input
operation, output by other functions must be suspended except for
intentional operation.
120
P30
E
This is a general-purpose I/O port.
1
P31
E
This is a general-purpose I/O port.
CKOT
2
P32
This is a clock monitor function output pin.
This function is valid when clock monitor output is enabled.
E
OUT0
3
P33
This is an event output pin for output compare 0 (OCU) ch.0.
This function is valid when output for each channel is enabled.
E
OUT1
4
P34
P35
E
P36
PG00
*1: FPT-120P-M05
*2: FPT-120P-M13
This is a general-purpose I/O port.
This function becomes valid when waveform output from the
OUT2 is disabled.
This is an event output pin for output compare 0 (OCU) ch.2.
This function is valid when output for each channel is enabled.
E
OUT3
6
This is a general-purpose I/O port.
This function becomes valid when waveform output from the
OUT1 is disabled.
This is an event output pin for output compare 0 (OCU) ch.1.
This function is valid when output for each channel is enabled.
OUT2
5
This is a general-purpose I/O port.
This function becomes valid when waveform output from the
OUT0 is disabled.
This is a general-purpose I/O port.
This function becomes valid when waveform output from the
OUT3 is disabled.
This is an event output pin for output compare 0 (OCU) ch.3.
This function is valid when output for each channel is enabled.
E
This is a general-purpose I/O port.
This function becomes valid when waveform output from the PG00
is disabled.
This is an output pin of 8/16-bit PPG timer 0.
This function becomes valid when waveform output from PG00 is
enabled.
(Continued)
9
MB90520 Series
Pin no.
Pin name
LQFP-120*1
QFP-120*2
7
P37
Circuit
type
Function
E
This is a general-purpose I/O port.
This function becomes valid when waveform output from the PG01
is disabled.
PG01
9,
10
P40,
P41
This is an output pin of 8/16-bit PPG timer 0.
This function becomes valid when waveform output from PG01 is
enabled.
D
PG10,
PG11
11
P42
This is an output pin of 8/16-bit PPG timer 1.
This function becomes valid when waveform outputs from PG10
and PG11 are enabled.
D
SIN0
12
P43
P44
D
P45
SIN1
*1: FPT-120P-M05
*2: FPT-120P-M13
10
This is a general-purpose I/O port.
This function can be set by the pull-up resistor setup register
(RDR4) for input. For output, however, this function is invalid.
This is a serial data output pin of UART (SCI).
This function becomes valid when serial data output from UART
(SCI) is enabled.
D
SCK0
14
This is a general-purpose I/O port.
This function can be set by the pull-up resistor setup register
(RDR4) for input. For output, however, this function is invalid.
This is a serial data input pin of UART (SCI).
Because this input is used as required when UART (SCI) is
performing input operations, it is necessary to stop outputs by
other functions unless such outputs are made intentionally.
When using other output functions as well, disable output during
SIN operation.
SOT0
13
This is a general-purpose I/O port.
This function becomes valid when waveform output from the PG10
and PG11 are disabled.
This function can be set by the pull-up resistor setup register
(RDR4) for input. For output, however, this function is invalid.
This is a general-purpose I/O port.
This function can be set by the pull-up resistor setup register
(RDR4) for input. For output, however, this function is invalid.
This is a serial clock I/O pin of UART (SCI).
This function becomes valid when serial clock output from UART
(SCI) is enabled.
D
This is a general-purpose I/O port.
This function can be set by the port 4 input pull-up resistor setup
register (RDR4) for input. For output, however, this function is
invalid.
This is a data input pin for extended I/O serial interface 0.
Since this input is used as required for serial data input operation,
output by other functions must be suspended except for intentional
operation. When using other output functions as well, disable
output during SIN operation.
(Continued)
MB90520 Series
Pin no.
Pin name
LQFP-120*1
QFP-120*2
15
P46
Circuit
type
D
SOT1
16
P47
36
37
40,
41
P50
D
This is a general-purpose I/O port.
This function can be set by the port 4 input pull-up resistor setup
register (RDR4) for input. For output, however, this function is
invalid.
This is a serial clock I/O pin for extended I/O serial interface 0.
This function becomes valid when serial clock output from SCK1 is
enabled.
D
This is a general-purpose I/O port.
SIN2
This is a data input pin for extended I/O serial interface 1.
Since this input is used as required for serial data input operation,
output by other functions must be suspended except for intentional
operation.
AIN1
This port can be used as count clock A input for 8/16-bit up/down
counter/timer 1.
P51
D
This is a general-purpose I/O port.
SOT2
This is a data output pin for extended I/O serial interface 1.
This function becomes valid when serial data output from SOT2 is
enabled.
BIN1
This port can be used as count clock B input for 8/16-bit up/down
counter/timer 1.
P52
D
This is a general-purpose I/O port.
SCK2
This is a serial clock I/O pin for extended I/O serial interface 1.
This function becomes valid when serial clock output from serial
SCK2 is enabled.
ZIN1
This port can be used as control clock Z input for 8/16-bit up/down
counter/timer 1.
P53,
P54
I
DA0,
DA1
46 to 53
This is a general-purpose I/O port.
This function can be set by the port 4 input pull-up resistor setup
register (RDR4) for input. For output, however, this function is
invalid.
This is a data output pin for extended I/O serial interface 0.
This function becomes valid when serial data output from SOT1 is
enabled.
SCK1
35
Function
P60 to P67
AN0 to AN7
*1: FPT-120P-M05
*2: FPT-120P-M13
This is a general-purpose I/O port.
These are analog signal output pins for 8-bit D/A converter ch.0
and ch.1.
K
This is a general-purpose I/O port.
The input function become valid when the analog input enable
register (ADER) is set to select a port.
These are analog input pins of the 8/10-bit A/D converter.
This function is valid when the analog input enable register
(ADER) is enabled.
(Continued)
11
MB90520 Series
Pin no.
Pin name
LQFP-120*1
QFP-120*2
55,
57
56,
58
59 to 62
P70,
P72
Circuit
type
E
These are event input pins for 16-bit re-load timers 0 and 1.
Since this input is used as required for 16-bit re-load timers 0 and
1 operation, output by other functions must be suspended except
for intentional operation.
OUT4,
OUT6
These are event output pins for output compare 1 (OCU) ch.4 and
ch.6.
This function is valid when output for each channel is enabled.
P71,
P73
E
These are output pins for 16-bit re-load timers 0 and 1.
This function is valid when TO0 and TO1 output are enabled.
OUT5,
OUT7
These are event output pins for output compare 1 (OCU) ch.5 and
ch.7.
This function is valid when output for each channel is enabled.
P74 to P77
L
P80 to P87
P90,
P91 to P97
This is a general-purpose I/O port.
This function is valid with port output specified for the LCD
controller/driver control register.
These are common pins for the LCD controller/driver.
This function is valid with common output specified for the LCD
controller/driver control register.
L
This is a general-purpose I/O port.
This function is valid with port output specified for the LCD
controller/driver control register.
These are segment outputs for the LCD controller/driver.
This function is valid with segment output specified for the LCD
controller/driver control register.
M
SEG24,
SEG25 to
SEG31
This is a general-purpose I/O port.
The maximum IOL can be 10mA.
This function is valid with port output specified for the LCD
controller/driver control register.
These are segment outputs for the LCD controller/driver.
This function is valid with port output specified for the LCD
controller/driver control register.
17 to 24
SEG00 to
SEG07
F
These are pins dedicated to LCD segments 00 to 07 for the LCD
controller/driver.
25 to 32
PA0 to PA7
L
This is a general-purpose I/O port.
This function is valid with port output specified for the LCD
controller/driver control register.
SEG08 to
SEG15
*1: FPT-120P-M05
*2: FPT-120P-M13
12
This is a general-purpose I/O port.
This function is valid when TO0 and TO1 output are disabled.
TO0,
TO1
SEG16 to
SEG23
72,
75 to 81
This is a general-purpose I/O port.
TI0,
TI1
COM0 to
COM3
64 to 71
Function
These are pins for LCD segments 08 to 15 for the LCD controller/
driver.
Units of four ports or segments can be selected by the internal
register in the LCD controller.
(Continued)
MB90520 Series
(Continued)
Pin no.
Circuit
type
Function
C
G
This is a capacitance pin for power supply stabilization.
Connect an external ceramic capacitor rated at about 0.1 µF. This
capacitor is not, however, required for the M90F523 (flash
product).
V0 to V3
N
This is a pin for the reference power supply for the LCD controller/
driver.
Pin name
LQFP-120*1
QFP-120*2
34
82 to 85
8,
54,
94
VCC
Power
supply
This is a power supply (5.0 V) input pin to the digital circuit.
33,
63,
91,
119
VSS
Power
supply
This provides the GND level (0.0 V) input pin for the digital circuit.
42
AVCC
H
This is a power supply for the analog circuit.
Make sure to turn on/turn off this power supply with a voltage
exceeding AVCC applied to VCC.
43
AVRH
J
This is a reference voltage input to the analog circuit.
Make sure to turn on/turn off this power supply with a voltage
exceeding AVRH applied to AVCC.
44
AVRL
H
This is a reference voltage input to the analog circuit.
45
AVSS
H
This is a GND level of the analog circuit.
38
DVCC
H
This is the Vref input pin for the D/A converter.
The voltage to be applied must not exceed VCC.
39
DVSS
H
This is the GND level pin for the D/A converter.
The potential must be the same as VSS.
*1: FPT-120P-M05
*2: FPT-120P-M13
13
MB90520 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• High-speed oscillation feedback resistor
approx. 1MΩ
X1
X0
Nch
Pch
Pch
Nch
Standby control signal
B
• Low-speed oscillation feedback resistor
approx. 1MΩ
X1A
X0A
Pch
Nch
Pch
Nch
Standby control signal
C
• Hysteresis input
R
Hysteresis input
D
Selecting signal
with or without a
input pull-up resistor
Pch
Pch
Nch
• Hysteresis input (can be set with the input
pull-up resistor)
CMOS level output
• Pull-up resistor approx. 50 kΩ
• Provided with a standby control function
for input interruption
R
Hysteresis input
IOL = 4 mA
Standby control for
input interruption
(Continued)
14
MB90520 Series
Type
Circuit
E
Remarks
• CMOS hysteresis input/output
• CMOS level output
• Provided with a standby control function
for input interruption
VCC
Pch
Nch
R
Hysteresis input
IOL = 4 mA
Standby control for input interruption
F
• Pins dedicated to segment output
Pch
R
Nch
G
• C pin output
(Pin for capacitor connection)
N.C. pin for the MB90F523
Pch
Nch
H
• Analog power input protector
Pch
AVP
Nch
I
VCC
Pch
Nch
R
Hysteresis input
• CMOS hysteresis input/output
• Pin for analog output/CMOS output
(During analog output, CMOS output is
not produced.)
(Analog output has priority over CMOS
output: DAE = 1)
• Provided with a standby control function
for input interruption
Standby control for input interruption
IOL = 4 mA
DAO
(Continued)
15
MB90520 Series
Type
Circuit
Remarks
J
ANE
Pch
Nch
• Input pin for ref+ power for the A/D
converter
Provided with power protection
Pch
Nch
AVR
ANE
K
• Hysteresis input/analog input
• CMOS output
• Provided with a standby control for input
interruption
Pch
Nch
R
Hysteresis input
Standby control for input interruption
Analog input
IOL = 4 mA
L
• CMOS hysteresis input/output
• Segment input
• Standby control to cut off the input is
available in segment input operation
Pch
Nch
R
Hysteresis input
Standby control for input interruption
SEG
IOL = 4 mA
M
• Hysteresis input
• Nch open-drain output
(High current for LCD drive)
• Standby control to cut off the input is
available in segment input operation
Nch
Nch
R
Hysteresis input
IOL = 10 mA
Standby control for input interruption
N
Pch
Nch
IOL = 10 mA
16
• Reference power supply pin for the LCD
controller
R
MB90520 Series
■ HANDLING DEVICES
1. Ensuring that the Voltage does not exceed the Maximum Rating (to Avoid a Latch-up).
In CMOS ICs, a latch-up phenomenon is caused when a voltage exceeding VCC or below VSS is applied to
input or output pins or if a voltage exceeding the rating is applied across VCC and VSS.
When a latch-up is caused, the power supply current may be dramatically increased, resulting in thermal
breakdown of devices. To avoid the latch-up, make sure that the voltage does not exceed the maximum rating.
In turning on/turning off the analog power supply, make sure the analog power voltages (AVCC, AVRH, DVCC)
and analog input voltages do not exceed the digital voltage (VCC).
And also make sure the voltages applied to the LCD power supply pins (V3 to V0) do not exceed the power
supply voltage (VCC).
2. Handling Unused Pins
• Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused
input pins should be pulled-up or pull-down through at least 2 kΩ resistance.
• Unused input/output pins may be left open in output state, but if such pins are in input state they should be
handled in the same way as input pins.
3. Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
• Using external clock
X0
MB90520 series
Open
X1
4. Unused Sub Clock Mode
If sub clock modes are not used, the oscillator should be connected to the X0A pin and X1A pin.
5. Power Supply Pins
In products with multiple Vcc or Vss pins, pins with the same potential are internally connected in the device to
avoid abnormal operations including latch-ups. However, the pins should be connected to external powers and
ground lines to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating.
Make sure to connect Vcc and Vss pins via lowest impedance to power lines.
It is recommended that a bypass capacitor of around 0.1 µF be placed between the Vcc and Vss pins near the
device.
17
MB90520 Series
• Using power supply pins
VCC
VSS
VCC
VSS
VSS
VCC
MB90520 series
VCC
VSS
VSS
VCC
6. Crystal Oscillator Circuit
Noise around the X0 and X1 pins may cause abnormal operation in this device. In designing printed circuit
boards, the X0 and X1 pins and crystal oscillator (or ceramic oscillator), as well as the bypass capacitor to the
ground, should be placed as close as possible, and the related wiring should have as few crossings with other
wiring as possible.
Circuit board artwork in which the area of the X0 and X1 pins is surrounded by grounding is recommended for
stabilizing the operation.
7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL, DVCC,
DVSS) and analog inputs (AN0 to AN7) after turning on the digital power supply (VCC).
Turn off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that AVRH and DVCC do not exceed AVCC (turning on/off the analog and digital supplies simultaneously is
acceptable).
8. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter and those of D/A converter to AVCC = DVCC = VCC, AVSS = AVRH = AVRL
= VSS.
9. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
10.Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V).
11.Use of SEG/COM Pins for the LCD Controller/Driver as Ports
In MB90520 series, pins SEG08 to SEG31, and COM0 to COM3 can also be used as general-purpose ports.
The electrical standard is such that pins SEG08 to SEG23, and COM0 to COM3 have the same ratings as the
CMOS output port, while pins SEG24 to SEG31 have the same ratings as the open-drain type.
18
MB90520 Series
12.Indeterminate outputs from ports 0 and 1
The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during
a power-on reset) after the power is turned on.
Pay attention to the port output timing shown as follow
• Timming chart of indeterminate outputs from ports o and 1
Oscillation setting time∗2
Step-down circuit
setting time ∗1
Vcc(power-supply pin)
PONR(power-on reset) signal
RST(external asynchronous reset) signal
RST(internal reset) signal
Oscillation clock signal
KA(internal operation clock A) signal
KB(internal operation clock B) signal
PORT(port output)signal
indereterminate period
* : 1:Step-down circuit setting time : 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms)
* : 2:Oscillation setting time: 218/oscillation clock frequency (oscillation cllock frequency of 16 MHz: 16.38 ms)
13.Initialization
The device contains internal registers that can be initialized only by a power-on reset. To initialize the internal
registers, restart the power supply.
14. Interrupt Recovery from Standby
If an external interrupt is used for recovery from standby, use an “H” level input request. An “L” level request
causes abnormal operation.
15.Precautions for Use of “DIV A, Ri”, and “DIVW A, Ri” Instructions
The signed multiplication-division instructions “DIV A, Ri”, and “DIVW A, RWi” should be used when the
corresponding bank registers (DTB, ADB, USB, SSB) are set to value “00h”. If the corresponding bank registers
(DTB, ADB, USB, SSB) are set to a value other than “00h,” then the remainder obtained after the execution of
the instruction will not be placed in the instruction operand register.
16. Precautions for Use of REALOS
Extended intelligent I/O service(EI2OS) cannot be used, when REALOS is used.
19
MB90520 Series
■ BLOCK DIAGRAM
Port 8*5, 9*5, A*5
24
F2MC-16LX
CPU
X0, X1
X0A, X1A
RST
HST
Oscillation clock
Sub clock
4
7
7
Output 4
compare
(OCU)
8/16-bit
up/down
counter/timer
0, 1
16-bit
free-run
timer 2
16-bit
I/O timer 1
2
Input
capture 0
(ICU)
16-bit
free-run
timer 1
P32/OUT0
P33/OUT1
P34/OUT2
P35/OUT3
P31/CKOT
Output
4 compare 0
Input
capture 1
(ICU)
Intrnal data bus
P20/IC00
P21/IC01
P30
P36/PG00
P37/PG01
2
8/16-bit
PPG
timer 0, 1
P42/SIN0
P43/SOT0
P44/SCK0
UART
(SCI)
P45/SIN1
P46/SOT1
P47/SCK1
SIO ch.0
Port 4*2
Port 6*4
8
Other pins
MD0 to MD2,
C, VCC, VSS
8 Wake-up
interrupt
8
P60/AN0 to P67/AN7
AVCC
AVSS
AVRH
AVRL
P27/ADTG
8/10-bit
A/D
converter
Port 2*4
Interrupt controller
Port 5*5
P50/SIN2/AIN1
P51/SOT2/BIN1
P52/SCK2/ZIN1
SIO ch.1
Port 1*2
8
P22/IC10
P23/IC11
Port 2*4
Port 3*4
2
P40/PG10
P41/PG11
P10/WI0 to P17/WI7
2
(OCU)
Clock output
P80/SEG16 to P87/SEG23
P90/SEG24 to P97/SEG31
PA0/SEG08 to PA7/SEG15
SEG00 to SEG07
V0 to V3
P74/COM0 to P77/COM3
P70/TI0/OUT4
P71/TO0/OUT5
P72/TI1/OUT6
P73/TO1/OUT7
16-bit
I/O timer 2
Port 2*4
3
8
4
4
16-bit
re-load
timer 0
16-bit
re-load
timer 1
DTP/
external
interrupt
circuit
P24/AIN0
P25/BIN0
P26/ZIN0/INT7
8
8
Port 7*4
Port 0*2
P07
P00/INT0 to P06/INT6
LCD
controller/
driver
Clock control
block*1
(including
timebase timer)
8
2
8-bit D/A
converter
× 2 ch.
P53/DA0
P54/DA1
DVCC
DVSS
RAM
ROM
Notes: Actually 16-bit free-run timer 1 is supported although two free-run timers are seemingly supported.
*1: The clock control circuit comprises a watchdog timer, a timebase timer, and a power consumption controller.
*2: A register for setting a pull-up resistor is supported.
*3: This is a high-current port for an LCD drive.
*4: A register for setting a pull-up resistor is supported. Signals in the CMOS level are input and output.
*5: Also used for LCD output. With this port used as is, Nch open-drain output develops. A register for setting a pull-up resistor
is supported.
20
MB90520 Series
■ MEMORY MAP
Single chip mode
A mirroring function
is supported.
FFFFFFH
ROM area
Address #1
FE0000H
010000H
ROM area
(image of
bank FF)
Address #2
004000H
002000H
Address #3
RAM Register
000100H
0000C0H
000000H
Part number
Peripheral
Address #1*
Address #2 *
Address #3 *
MB90522
FF0000H
004000H
001100H
MB90523
FE0000H
004000H
001100H
MB90F523
FE0000H
004000H
001100H
: Internal access memory
: Access prohibited
*: Addresses #1, #2 and #3 vary with product type.
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C
compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the
same address, enabling reference of the table on the ROM without stating “far.”
For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are
actually accessed. Since the ROM area of the FF bank exceeds 48k bytes, the whole area cannot be
reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it
were the image for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in
the area of FF4000H to FFFFFFH.
21
MB90520 Series
■ F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
AH
AL
: Accumlator (A)
Dual 16-bit register used for storing results of calculation, etc. The two 16-bit
registers can be combined to be used as a 32-bit register.
USP
: User stack pointer (USP)
16-bit pointer for containing a user stack address.
SSP
: System stack pointer (SSP)
16-bit pointer for displaying the status of the system stack address.
PS
: Processor status (PS)
16-bit register for displaying the system status.
PC
: Program counter (PC)
16-bit register for displaying the storing location of the current instruction code.
DPR
: Direct page register (DPR)
8-bit register for specifying bit 8 through 15 of the operand address in the short
direct addressing mode.
PCB
: Program bank register (PCB)
8-bit register for displaying the program space.
DTB
: Data bank register (DTB)
8-bit register for displaying the data space.
USB
: User stack bank register (USB)
8-bit register for displaying the user stack space.
SSB
: System stack bank register (SSB)
8-bit register for displaying the system stack space.
ADB
: Additional data bank register (ADB)
8-bit register for displaying the additional data space.
8-bit
16-bit
32-bit
22
MB90520 Series
• General-purpose registers
Maximum of 32 banks
R7
R6
RW7
R5
R4
RW6
R3
R2
RW5
R1
R0
RW4
RL3
RL2
RW3
RL1
RW2
RW1
RL0
RW0
000180H + (RP × 10H )
16-bit
• Processor status (PS)
ILM
RP
CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6
PS
ILM2 ILM1 ILM0
Initial value
0
0
0
bit 5 bit 4
bit 3 bit 2
bit 1
bit 0
B4
B3
B2
B1
B0
—
I
S
T
N
Z
V
C
0
0
0
0
0
—
0
1
X
X
X
X
X
— : Unused
X : Indeterminate
23
MB90520 Series
■ I/O MAP
Address
Abbreviated
register
name
000000H
PDR0
000001H
Read/
write
Resource name
Initial value
Port 0 data register
R/W
Port 0
XXXXXXXXB
PDR1
Port 1 data register
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
Port 4
XXXXXXXXB
000005H
PDR5
Port 5 data register
R/W
Port 5
XXXXXXXXB
000006H
PDR6
Port 6 data register
R/W
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
R/W
Port 7
XXXXXXXXB
000008H
PDR8
Port 8 data register
R/W
Port 8
XXXXXXXXB
000009H
PDR9
Port 9 data register
R/W
Port 9
XXXXXXXXB
00000AH
PDRA
Port A data register
R/W
Port A
XXXXXXXX B
00000BH
LCDCMR
Port 7/COM pin selection register
R/W
Port 7,
XXXX0 0 0 0 B
16-bit I/O timer
XXXXXXXXB
OCU compare register ch.4
R/W
(output compare 1
(OCU) section)
XXXXXXXXB
Register name
00000CH
00000DH
OCP4
00000EH
LCD controller/driver
(Disabled)
00000FH
EIFR
Wake-up interrupt flag register
R/W
Wake-up interrupt
XXXXXXX 0 B
000010H
DDR0
Port 0 direction register
R/W
Port 0
00000000B
000011H
DDR1
Port 1 direction register
R/W
Port 1
00000000B
000012H
DDR2
Port 2 direction register
R/W
Port 2
00000000B
000013H
DDR3
Port 3 direction register
R/W
Port 3
00000000B
000014H
DDR4
Port 4 direction register
R/W
Port 4
00000000B
000015H
DDR5
Port 5 direction register
R/W
Port 5
XXX 0 0 0 0 0 B
000016H
DDR6
Port 6 direction register
R/W
Port 6
00000000B
000017H
DDR7
Port 7 direction register
R/W
Port 7
00000000B
000018H
DDR8
Port 8 direction register
R/W
Port 8
00000000B
000019H
DDR9
Port 9 direction register
R/W
Port 9
00000000B
00001AH
DDRA
Port A direction register
R/W
Port A
00000000B
00001BH
ADER
Analog input enable register
R/W
Port 6,
A/Dconverter
11111111B
16-bit I/O timer
XXXXXXXXB
OCP5
OCU compare register ch.5
R/W
(output compare 1
(OCU) section)
XXXXXXXXB
W
Wake-up interrupt
00000000B
00001CH
00001DH
00001EH
00001FH
(Disabled)
EICR
Wake-up interrupt enable register
(Continued)
24
MB90520 Series
Address
Abbreviated
register
name
000020H
SMR
Serial mode register
R/W
000021H
SCR
Serial control register
R/W or
W
Read/
write
Register name
000022H
SIDR/
SODR
Serial input data register/
serial output data register
000023H
SSR
000024H
SMCSL0
Serial mode control lower status register 0
R/W
000025H
SMCSH0
Serial mode control upper status register 0
R/W
000026H
SDR0
Serial data register 0
R/W
000027H
CDCR
Communications prescaler control register
R/W
000028H
SMCSL1
Serial mode control lower status register 1
R/W
000029H
SMCSH1
Serial mode control upper status register 1
R/W
00002AH
SDR1
Serial data register 1
R/W
00002DH
00002EH
00002FH
OCS45
OCS67
OCU control status register ch.45
XXXXXXXXB
00001X00B
Extended I/O
serial
interface 0
Communications prescaler
control register
Extended I/O
serial
interface 1
XXXX0 0 0 0 B
00000010
B
XXXXXXXXB
0 XXX 1 1 1 1 B
XXXX0 0 0 0 B
00000010
B
XXXXXXXXB
0 0 0 0XX0 0 B
R/W
16-bit I/O timer
OCU control status register ch.67
R/W
(output compare 1 (OCU)
section)
ENIR
DTP/interrupt enable register
R/W
000031H
EIRR
DTP/interrupt factor register
R/W
ELVR
Request level setting register
R/W
000033H
00000100B
UART
(SCI)
(Disabled)
000030H
000032H
Initial value
00000000B
R/W or
R
Serial status register
00002BH
00002CH
R
W
Resource
name
XXX 0 0 0 0 0 B
0 0 0 0XX0 0 B
XXX 0 0 0 0 0 B
00000000B
DTP/external
interrupt circuit
XXXXXXXX B
00000000B
00000000B
000034H
16-bit I/O timer
XXXXXXXXB
000035H
(output compare 1 (OCU)
section)
XXXXXXXXB
OCP6
OCU compare register ch.6
R/W
000036H
ADCS1
A/D control status register lower digits
R/W
00000000B
000037H
ADCS2
A/D control status register upper digits
R/W
000038H
ADCR1
A/D data register lower digits
R
000039H
ADCR2
A/D data register upper digits
R or W
0 0 0 0 1 XXXB
00003AH
DADR0
D/A converter data register ch.0
R/W
XXXXXXXXB
00003BH
DADR1
D/A converter data register ch.1
R/W
00003CH
DACR0
D/A control register 0
R/W
00003DH
DACR1
D/A control register 1
R/W
00003EH
CLKR
Clock output enable register
R/W
8/10-bit A/D
converter
8-bit D/A
converter
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXX 0 B
XXXXXXX 0 B
Clock monitor
function
XXXX0 0 0 0 B
(Continued)
25
MB90520 Series
Address
Abbreviated
register
name
Read/ Resource name
write
Register name
00003FH
Initial value
(Disabled)
000040H
PRLL0
PPG0 re-load register L
R/W
XXXXXXXXB
000041H
PRLH0
PPG0 re-load register H
R/W
XXXXXXXXB
000042H
PRLL1
PPG1 re-load register L
R/W
XXXXXXXXB
000043H
PRLH1
PPG1 re-load register H
R/W
000044H
PPGC0
PPG0 operating mode control register
R/W
000045H
PPGC1
PPG1 operating mode control register
R/W
0X000001B
000046H
PPGOE0/
PPGOE1
PPG0 and 1 output control registers
R/W
00000000B
000047H
000048H
000049H
00004AH
00004BH
00004CH
00004DH
00004EH
00004FH
000050H
000051H
000052H
000053H
000054H
000057H
000058H
TMCSR0
TMR0/
TMRLR0
TMCSR1
TMR1/
TMRLR1
IPCP0
Timer control status register lower ch.0
Timer control status register upper ch.0
16-bit timer register upper, lower ch.0/
16-bit re-load register upper, lower ch.0
Timer control status register lower ch.1
Timer control status register upper ch.1
16-bit timer register upper, lower ch.1/
16-bit re-load register upper, lower ch.1
ICU data register ch.0
00005BH
00005CH
00005DH
00005EH
00005FH
000060H
000061H
0X0 0 0XX1 B
00000000B
R/W
16-bit re-load
timer 0
R/W
IPCP1
ICU data register ch.1
ICS01
ICU control status register
XXXXXXXXB
00000000B
R/W
16-bit re-load
timer 1
R/W
XXXX 0 0 0 0 B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R
R
XXXX 0 0 0 0 B
XXXXXXXXB
16-bit I/O timer
(input compare 0,
1 (ICU) section)
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
(Disabled)
TCDT1
Free-run timer data register 1
R/W
TCCS1
Free-run timer control status register 1
R/W
000059H
00005AH
XXXXXXXXB
(Disabled)
000055H
000056H
8/16-bit PPG
timer 0, 1
16-bit I/O timer
(16-bit free-run
timer 1 section)
00000000B
00000000B
00000000B
(Disabled)
OCP0
OCU compare register ch.0
R/W
OCP1
OCU compare register ch.1
R/W
OCP2
OCU compare register ch.2
R/W
OCP3
OCU compare register ch.3
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit I/O timer
(output compare 0
(OCU) section)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
26
MB90520 Series
Address
000062H
000063H
000064H
000065H
000066H
000067H
000068H
Abbreviated
register
name
Read/
write
Register name
OCS01
OCU control status register ch.01
R/W
OCS23
OCU control status register ch.23
R/W
TCDT2
Free-run timer data register 2
R/W
TCCS2
Free-run timer control status register 2
R/W
000069H
LCR0
00006BH
LCR1
LCDC control registers 0 and 1
R/W
R/W
00006CH
OCP7
OCU compare register ch.7
00006EH
R/W
0 0 0 0 XX 0 0 B
16-bit I/O timer
(output compare 0
(OCU) section)
XXX 0 0 0 0 0 B
0 0 0 0 XX 0 0 B
XXX 0 0 0 0 0 B
16-bit I/O timer
(16-bit free-run
timer 2 section)
00000000B
00000000B
00000000B
LCD controller/
driver
00010000B
16-bit I/O timer
(output compare 1
(OCU) section)
XXXXXXXXB
00000000B
XXXXXXXXB
(Disabled)
W
ROM mirroring
function
selection module
XXXXXXX 1 B
R/W
LCD controller/
driver
XXXXXXXXB
00006FH
ROMM
ROM mirroring function selection
register
000070H
to
00007FH
VRAM
RAM for LCD indication
000080H
UDCR0
Up/down count register 0
R
000081H
UDCR1
Up/down count register 1
R
000082H
RCR0
Re-load compare register 0
W
000083H
RCR1
Re-load compare register 1
W
000084H
CSR0
Counter status register 0
000085H
00000000B
8/16-bit up/down
counter/timer
0, 1
R/W
00000000B
00000000B
00000000B
00000000B
(Reserved area)*3
000086H
CCRL0
000087H
CCRH0
000088H
CSR1
Counter control register 0
R/W
Counter status register 1
R/W
000089H
00008AH
Initial value
(Disabled)
00006AH
00006DH
Resource name
8/16-bit up/down
counter/timer
0, 1
X0000000B
00000000B
00000000B
(Reserved area)*3
CCRL1
Counter control register 1
R/W
8/16-bit up/down
counter/timer
0, 1
X0000000B
X0000000B
00008BH
CCRH1
00008CH
RDR0
Port 0 input pull-up resistor setup
register
R/W
Port 0
00000000B
00008DH
RDR1
Port 1 input pull-up resistor setup
register
R/W
Port 1
00000000B
00008EH
RDR4
Port 4 input pull-up resistor setup
register
R/W
Port 4
00000000B
(Continued)
27
MB90520 Series
Address
Abbreviated
register
name
00008FH
to
00009DH
Resource name
Initial value
(Area used by the system)*3
00009EH
PACSR
Program address detection control
status register
R/W
Address match
detection
function
00000000B
00009FH
DIRR
Delayed interrupt factor generation/
cancellation register
R/W
Delayed interrupt generation
module
XXXXXXX 0 B
0000A0H
LPMCR
Low-power consumption mode
control register
R/W or
W
0000A1H
CKSCR
Clock select register
R/W or
R
0000A2H
to
0000A7H
Low-power
consumption
(stand-by) mode
00011000B
11111100B
(Disabled)
0000A8H
WDTC
Watchdog timer control register
R or W
Watchdog timer
XXXXXXXXB
0000A9H
TBTC
Timebase timer control register
R/W
Timebase timer
1 XX 0 0 0 0 0 B
0000AAH
WTC
Clock timer control register
R/W or
R
Clock timer
1X001000B
Flash interface
1 XX 0 0 1 0 0 B
0000ABH
to
0000ADH
0000AEH
(Disabled)
FMCS
Flash control register
0000AFH
28
Read/
write
Register name
R/W
(Disabled)
0000B0H
ICR00
Interrupt control register 00
R/W
00000111B
0000B1H
ICR01
Interrupt control register 01
R/W
00000111B
0000B2H
ICR02
Interrupt control register 02
R/W
00000111B
0000B3H
ICR03
Interrupt control register 03
R/W
00000111B
0000B4H
ICR04
Interrupt control register 04
R/W
00000111B
0000B5H
ICR05
Interrupt control register 05
R/W
00000111B
0000B6H
ICR06
Interrupt control register 06
R/W
0000B7H
ICR07
Interrupt control register 07
R/W
0000B8H
ICR08
Interrupt control register 08
R/W
00000111B
0000B9H
ICR09
Interrupt control register 09
R/W
00000111B
0000BAH
ICR10
Interrupt control register 10
R/W
00000111B
0000BBH
ICR11
Interrupt control register 11
R/W
00000111B
0000BCH
ICR12
Interrupt control register 12
R/W
00000111B
0000BDH
ICR13
Interrupt control register 13
R/W
00000111B
(Continued)
Interrupt
controller
00000111B
00000111B
MB90520 Series
(Continued)
Address
Abbreviated
register
name
0000BEH
ICR14
0000BFH
ICR15
Read/
write
Resource name
Initial value
Interrupt control register 14
R/W
00000111B
Interrupt control register 15
R/W
Interrupt
controller
Register name
0000C0H
to
0000FFH
(External area)*1
000100H
to
00####H
(RAM area)*2
00####H
to
001FEFH
(Reserved area)*3
00000111B
Program address detection register 0
R/W
Program address detection register 1
R/W
001FF2H
Program address detection register 2
R/W
001FF3H
Program address detection register 3
R/W
Program address detection register 4
R/W
XXXXXXXXB
Program address detection register 5
R/W
XXXXXXXXB
001FF0H
001FF1H
001FF4H
001FF5H
PADR0
PADR1
001FF6H
to
001FFFH
XXXXXXXXB
Address match
detection
function
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Reserved area)*3
Descriptions for read/write
R/W: Readable and writable
R: Read only
W: Write only
Descriptions for initial value
0 : The initial value is “0.”
1 : The initial value is “1.”
X : The initial value is indeterminate.
*1: This area is the only external access area having an address of 0000FFH or lower. An access operation to this
area is handled as that to external I/O area.
*2: For details of the “RAM area”, see the memory map.
*3: The “reserved area” is basically disabled because it is used in the system.
*4: “Area used by the system” is the area set by the resistor for evaluating tool.
Notes: • For bits initialized by reset operations, the initial value set by the reset operation is listed as an initial value.
Note that the values are different from reading results.
For LPMCR/CKSCR/WDTC, there are cases in which initialization is performed or not performed,
depending on the types of the reset. The value listed is the initial value in cases where initialization is per
formed.
• The addresses following 0000FFH are reserved. No external bus access signal is generated.
• Boundary ####H between the “RAM area” and the“ reserved area” varies with the product models.
• Channels 0 to 3 of the OCU compare register use 16-bit free-run timer 2, while channels 4 to 7 of the OCU
compare register use 16-bit free-run timer 1. 16-bit free-run timer 1 is also used by input captures (ICU)
0 and 1.
29
MB90520 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTERS
Interrupt vector
Interrupt control register
EI2OS
support
Number
Address
ICR
Address
Reset
×
# 08
FFFFDCH
—
—
INT9 instruction
×
# 09
FFFFD8H
—
—
Exception
×
# 10
FFFFD4H
—
—
# 11
FFFFD0H
ICR00
0000B0H
# 12
FFFFCCH
# 13
FFFFC8H
ICR01
0000B1H
# 14
FFFFC4H
# 15
FFFFC0H
ICR02
0000B2H
# 16
FFFFBCH
Extended I/O serial interface 1
# 17
FFFFB8H
DTP2/DTP3 (external interrupt 2/
external interrupt 3)
ICR03
0000B3H
# 18
FFFFB4H
# 19
FFFFB0H
DTP4/DTP5 (external interrupt 4/
external interrupt 5)
ICR04
0000B4H
# 20
FFFFACH
8/16-bit up/down counter/timer 0
compare match
# 21
FFFFA0H
8/16-bit up/down counter/timer 0
overflow up/down inversion
ICR05
0000B5H
# 22
FFFFA4H
# 23
FFFFA0H
DTP6/DTP7 (external interrupt 6/
external interrupt 7)
ICR06
0000B6H
# 24
FFFF9CH
Output compare 1 (OCU) ch.4/ch.5
match
# 25
FFFF98H
ICR07
0000B7H
# 26
FFFF94H
# 27
FFFF90H
ICR08
0000B8H
# 28
FFFF8CH
8/16-bit up/down counter/timer 1
compare match
# 29
FFFF88H
8/16-bit up/down counter/timer 1
overflow, up/down inversion
ICR09
0000B9H
# 30
FFFF84H
Input capture 0 (ICU) include
# 31
FFFF80H
ICR10
0000BAH
Input capture 1 (ICU) include
# 32
FFFF7CH
Interrupt source
8/10-bit A/D converter
Timebase timer
×
DTP0/DTP1 (external interrupt 0/
external interrupt 1)
16-bit free-run timer 1 overflow
×
Extended I/O serial interface 0
Wake-up interrupt
8/16-bit PPG timer 0 counter
borrow
8/16-bit PPG timer 1 counter
borrow
Clock prescaler
×
×
×
×
Output compare 1 (OCU) ch.6/ch.7
match
16-bit free-run timer 2 overflow
×
Priority
High
Low
(Continued)
30
MB90520 Series
(Continued)
Interrupt source
EI2OS
support
Interrupt vector
Number
Address
Output compare 0 (OCU) ch.0
match
# 33
FFFF78H
Output compare 0 (OCU) ch.1
match
# 34
FFFF74H
Output compare 0 (OCU) ch.2
match
# 35
FFFF70H
Output compare 0 (OCU) ch.3
match
# 36
FFFF6CH
UART (SCI) reception complete
# 37
FFFF68H
16-bit re-load timer 0
# 38
FFFF64H
UART (SCI) transmission complete
# 39
FFFF60H
16-bit re-load timer 1
# 40
FFFF5CH
Reserved
×
# 41
FFFF58H
Delayed interrupt generation
module
×
# 42
FFFF54H
Interrupt control register
ICR
Address
Priority
High
ICR11
0000BBH
ICR12
0000BCH
ICR13
0000BDH
ICR14
0000BEH
ICR15
0000BFH
Low
: Can be used
× : Can not be used
: Can be used with EI2OS stop function
31
MB90520 Series
■ PERIPHERALS
1. I/O Port
(1) Input/Output Port
Port 0 through A are general-purpose I/O ports having a combined function as a resource input. The I/O ports
can be used as general-purpose I/O ports only in the single-chip mode.
• Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR
register.
Note: When a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register,
the destination bit of the operation is set to the specified value, not affecting the bits configured by the
DDR register for output. However, values of bits configured as inputs by the DDR register are changed
because input values to the pins are written into the output latch. To avoid this situation, configure the
pins by the DDR register as output after writing output data to the PDR register when switching the bit
used as input to output.
• Operation as input port
The pin is configured as input by setting the corresponding bit of the DDR register to “0.”
When the pin is configured as an input, the output buffer is turned off and the pin is put into a high-impedance
status.
When data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”).
32
MB90520 Series
(2) Register Configuration
• Port 0 data register (PDR0)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
000000H
P07
P06
P05
P04
P03
P02
P01
P00
XXXXXXXX B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
000001H
R/W
P17
P16
P15
P14
P13
P12
P11
P10
XXXXXXXX B
• Port 1 data register (PDR1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 2 data register (PDR2)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
000002H
P27
P26
P25
P24
P23
P22
P21
P20
XXXXXXXX B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
000003H
P37
P36
P35
P34
P33
P32
P31
P30
XXXXXXXX B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
• Port 3 data register (PDR3)
• Port 4 data register (PDR4)
Address
000004H
P47
P46
P45
P44
P43
P42
P41
P40
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 5 data register (PDR5)
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
—
P54
P53
P52
P51
P50
XXXXXXXX B
—
—
R/W
R/W
R/W
R/W
R/W
bit 6
bit 5
Address
bit 15
bit 14
000005H
—
—
—
bit 7
bit 13
• Port 6 data register (PDR6)
Address
000006H
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
P67
P66
P65
P64
P63
P62
P61
P60
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 7 data register (PDR7)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
000007H
P77
P76
P75
P74
P73
P72
P71
P70
XXXXXXXX B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX B
• Port 8 data register (PDR8)
Address
000008H
P87
P86
P85
P84
P83
P82
P81
P80
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
XXXXXXXX B
• Port 9 data register (PDR9)
Address
000009H
P97
P96
P95
P94
P93
P92
P91
P90
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(Continued)
33
MB90520 Series
• Port A data register (PDRA)
Address
00000AH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
XXXXXXXX B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
• Port 0 direction register (DDR0)
Address
000010H
bit 7
Initial value
D07
D06
D05
D04
D03
D02
D01
D00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
D17
D16
D15
D14
D13
D12
D11
D10
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D27
D26
D25
D24
D23
D22
D21
D20
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 14
bit 13
bit 12
bit 11
bit 10
00000000 B
• Port 1 direction register (DDR1)
Address
000011H
• Port 2 direction register (DDR2)
Address
000012H
• Port 3 direction register (DDR3)
Address
000013H
bit 15
D37
D36
D35
bit 9
bit 8
D34
D33
D32
D31
D30
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
• Port 4 direction register (DDR4)
Address
000014H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D47
D46
D45
D44
D43
D42
D41
D40
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
—
—
—
D54
D53
D52
D51
D50
XXX0 0 0 0 0 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D67
D66
D65
D64
D63
D62
D61
D60
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
D77
D76
D75
D74
D73
D72
D71
D70
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000 B
• Port 5 direction register (DDR5)
Address
000015H
• Port 6 direction register (DDR6)
Address
000016H
• Port 7 direction register (DDR7)
Address
000017H
• Port 8 direction register (DDR8)
Address
000018H
bit 7
D87
R/W
D86
D85
D84
D83
D82
D81
D80
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(Continued)
34
MB90520 Series
(Continued)
• Port 9 direction register (DDR9)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
000019H
D97
D96
D95
D94
D93
D92
D91
D90
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000 B
• Port A direction register (DDRA)
Address
00001AH
bit 7
bit 6
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 0 input pull-up resistor setup register (RDR0)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00008CH
RD07
RD06
RD05
RD04
RD03
RD02
RD01
RD00
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 11
bit 10
bit 9
bit 8
• Port 1 input pull-up resistor setup register (RDR1)
Address
00008DH
bit 15
bit 14
bit 13
bit 12
RD17
RD16
RD15
RD14
RD13
RD12
RD11
RD10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
• Port 4 input pull-up resistor setup register (RDR4)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00008EH
RD47
RD46
RD45
RD44
RD43
RD42
RD41
RD40
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 13
bit 12
bit 11
bit 10
• Analog input enable register (ADER)
Address
00001BH
bit 15
bit 9
bit 8
ADE7
bit 14
ADE6
ADE5
ADE4 ADE3
ADE2
ADE1
ADE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
11111111 B
• Port 7/COM pin selection register (LCDCMR)
Address
bit 15
00000BH
—
—
—
—
COM3 COM2 COM1 COM0
—
—
—
—
R/W
bit 14
bit 13
R/W
R/W
Initial value
XXXX0 0 0 0 B
R/W
R/W : Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
35
MB90520 Series
(3) Block Diagram
• Input/output port
PDR (port data register)
Internal data bus
PDR read
Output latch
Pch
PDR write
Pin
DDR (port direction register)
Nch
Direction latch
DDR write
Standby control (SPL=1)
DDR read
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
• Input pull-up resistor setup register (RDR)
To resource input
PDR (port data register)
Pull-up resistor
About 50 kΩ
(5.0 V)
PDR read
Output latch
Pch
Pch
PDR write
Pin
Internal data bus
DDR (port direction register)
DDR write
Standby control
(SPL=1)
DDR read
RDR latch
RDR write
RDR read
RDR (input pull-up resistor setup register)
Standby control: Stop, timebase timer mode and SPL=1
36
Nch
Direction latch
MB90520 Series
• Analog input enable register (ADER)
ADER (analog input enable register)
ADER read
ADER latch
To analog input
ADER write
Internal data bus
PDR (port data register)
RMW
(read-modify-write
type instruction)
PDR read
Output latch
Pch
PDR write
Pin
DDR (port direction register)
Direction latch
Nch
DDR write
DDR read
Standby control
(SPL=1)
Standby control: Stop, timebase timer mode and SPL=1
37
MB90520 Series
2. Timebase Timer
The timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the
internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from
four types : 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK.
The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation
stabilization time or the watchdog timer, etc.
(1) Register Configuration
• Timebase timer control register (TBTC)
Address
bit 15
bit 14
0000A9H
Reserved
—
R/W
—
bit 13
—
bit 12
bit 11
TBIE
TBOF TBR
—
R/W
R/W
bit 10
R/W
bit 9
bit 8
Initial value
TBC1 TBC0
R/W
1XX0 0 0 0 0 B
R/W
R/W: Readable and writable
— : Undefined bits (read value undefined)
(2) Block Diagram
To watchdog timer
To 8/16-bit PPG timer
Timebase timer counter
Divided-by-2
of HCLK
× 21 × 2 2 × 2 3
...
...
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
OF
OF
OF
OF
To oscillation stabilization
time selector of clock control block
Power-on reset
Start stop-mode
CKSCR : MCS = 1→0*1
Counter
clear circuit
Interval
timer selector
Set TBOF
Clear TBOF
Timebase timer control register
(TBTC)
Reserved
—
—
TBIE TBOF TBR
Timebase timer
interrupt signal
#12*2
*1: Switch machine clock from oscillation clock to PLL clock
*2: Interrupt number
OF : Overflow
HCLK : Oscillation clock frequency
38
TBC1 TBC0
MB90520 Series
3. Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when
the counter is not cleared for a preset period of time.
(1) Register Configuration
• Watchdog timer control register (WDTC)
Address
bit 7
0000A8H
bit 6
bit 5
bit 4
PONR STBR WRST ERST
R
R
R
R
bit 3
bit 2
bit 1
bit 0
SRST
WTE
WT1
WT0
R
W
W
W
Initial value
XXXXXXXX B
R : Read only
W: Write only
X : Indeterminate
(2) Block Diagram
Watchdog timer control register (WDTC)
PONR STBR WRST ERST SRST WTE WT1
WT0
2
Watchdog timer
CLR and start
Overflow
Start sleep-mode
Start hold status
Start stop-mode
Counter clear
control circuit
Count clock
selector
2-bit
counter
CLR
Watchdog timer
reset generation
circuit
To internal reset
generation circuit
CLR
4
Clear
(Timebase timer counter)
Divided-by-2
of HCLK
× 21 × 22
...
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
HCLK : Oscillation clock frequency
39
MB90520 Series
4. 8/16-bit PPG Timer 0, 1
The 8/16-bit PPG timer is a 2-CH re-load timer module for outputting pulse having given frequencies/duty ratios.
The two modules perform the following operation by combining functions.
• 8-bit PPG timer output 2-CH independent output mode
This is a mode for operating independent 2-CH 8-bit PPG timers, in which PG00 and PG10 pins correspond
to outputs from PPG0 and PPG1 respectively.
• 16-bit PPG timer output operation mode
In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer 0 and 1 operating
as a 16-bit timer. Because outputs during 16-bit PPG timer output operation mode are reversed by an underflow
from PPG1, the same output pulses are output from PG10 and PG11 pins.
• 8 + 8-bit PPG timer output operation mode
In this mode, PPG0 is operated as an 8-bit prescaler register, in which an underflow output of PPG0 is used
as a clock source for PPG1.
A prescaler output of PPG0 is output from PG00 and PG01 pins. PPG output of PPG1 is output from PG10 and
PG11 pins.
• PPG output operation
A pulse wave with any period/duty ratio is output. The module can also be used as a D/A converter with an
external add-on circuit.
40
MB90520 Series
(1) Register Configuration
• PPG0 operating mode control register (PPGC0)
Address
000044H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
0X0 0 0XX1 B
PEN0
—
PE00
PIE0
PUF0
—
—
Reserved
R/W
—
R/W
R/W
R/W
—
—
—
bit 8
• PPG1 operating mode control register (PPGC1)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
000045H
PEN1
—
PE10
PIE1
PUF1
MD1
MD0 Reserved
R/W
—
R/W
R/W
R/W
R/W
R/W
bit 4
bit 3
bit 2
Initial value
0X0 0 0 0 0 1 B
R/W
• PPG0 output control register (PPGOE0)
Address
000046H
bit 7
bit 6
PCS2 PCS1
R/W
bit 5
PCS0 PCM2 PCM1 PCM0
R/W
R/W
bit 1
bit 0
Initial value
PE11
PE01
00000000 B
R/W
R/W
R/W
R/W
R/W
bit 4
bit 3
bit 2
• PPG1 output control register (PPGOE1)
Address
bit 7
bit 1
bit 0
Initial value
000046H
PCS2 PCS1
PCS0 PCM2 PCM1 PCM0
PE11
PE01
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 6
bit 5
R/W
• PPG0 re-load register H (PRLH0)
Address
bit 15
bit 14
Initial value
XXXXXXXX B
000041H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
• PPG1 re-load register H (PRLH1)
Address
bit 15
bit 14
Initial value
XXXXXXXX B
000043H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
• PPG0 re-load register L (PRLL0)
Address
bit 7
Initial value
XXXXXXXX B
000040H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
• PPG1 re-load register L (PRLL1)
Address
bit 7
bit 6
Initial value
XXXXXXXX B
000042H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
41
MB90520 Series
(2) Block Diagram
• Block diagram of 8/16-bit PPG timer 0
Data bus for “H” digits
Data bus for “L” digits
PPG0 re-load
register
PPG0 operating mode
control register (PPGC0)
PEN0
PRLL0
PRLH0
—
PE00 PIE0 PUF0
—
—
Reserved
R
Temporary buffer
(PRLBH0)
S
Interrupt
request
#19*
Q
2
Re-load selector
L/H selector
Oprating mode
control signal
Select signal
PPG1 underflow
PPG0 underflow
(to PPG1)
Count value
Re-load
Clear
Pulse selector
Down counter
(PCNT0)
Underflow
CLK
Reverse
PPG0
output latch
Pin
P36/PG00
Timebase timer output (512/HCLK)
Peripheral clock (16/φ)
Peripheral clock (8/φ)
Peripheral clock (4/φ)
Peripheral clock (2/φ)
Peripheral clock (1/φ)
PPG output
control circuit
Count
clock
selector
Pin
P37/PG01
3
Select signal
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01
PPG0, 1 output control register (PPGOE0,1)
* : Interrupt number
HCLK : Oscillation clock frequency
φ : Machine clock frequency
42
MB90520 Series
• Block diagram of 8/16-bit PPG timer 1
Data bus for “H” digits
Data bus for “L” digits
PPG1 operating mode
control register (PPGC1)
PPG1 re-load
register
PRLL0
PRLH0
PEN1
—
Operating
mode
control signal
PEI0
PIE1 PUF1 MD1
Reserved
MD0
2
R
Temporary buffer
(PRLBH1)
S
Re-load selector
(L/H selector)
Interrupt
request
#23*
Q
Select signal
Count value
Re-load
Down counter
(PCNT1)
Clear
Underflow
Reverse
PPG1
output latch
Pin
P40/PG10
PPG1 underflow
(to PPG0)
PPG output control circuit
MD0
CLK
Pin
PPG0 underflow
P41/PG11
Timebase timer output (512/HCLK)
Peripheral clock (16/φ)
Peripheral clock (8/φ)
Peripheral clock (4/φ)
Peripheral clock (2/φ)
Peripheral clock (1/φ)
Count clock selector
3
Select signal
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01
PPG0, 1 Output control register (PPGOE0, 1)
* : Interrupt number
HCLK : Oscillation clock frequency
φ : Machine clock frequency
43
MB90520 Series
5. 16-bit Re-load Timer 0, 1 (With an Event Count Function)
The 16-bit re-load timer has an internal clock mode for counting down in synchronization to three types of internal
clocks and an event count mode for counting down by detecting a given edge of the pulse input to the external
bus pin. Either of the two functions can be selectively used.
For this timer, an “underflow” is defined as the timing of transition from the counter value of “0000H” to “FFFFH.”
According to this definition, an underflow occurs after a counter value of [re-load register setting value + 1] .
In operating the counter, the re-load mode for repeating counting operation after re-loading a counter value after
an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used.
Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent
I/O service (EI2OS).
The MB90520 series has 2 channels of 16-bit re-load timers.
(1) Register Configuration
• Timer control status register upper digits ch.0, ch.1 (TMCSR0, TMCSR1 : H)
Address
TMCSR0 : 000049H
TMCSR1 : 00004DH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
—
—
—
—
CSL1
CSL0 MOD2 MOD1
—
—
—
—
R/W
R/W
bit 9
Initial value
bit 8
R/W
XXXX0 0 0 0 B
R/W
• Timer control status register lower digits ch.0, ch.1 (TMCSR0, TMCSR1 : L)
Address
TMCSR0 : 000048H
TMCSR1 : 00004CH
bit 7
bit 6
bit 4
bit 3
MOD0 OUTE OUTL
RELD
INTE
R/W
R/W
R/W
R/W
bit 5
R/W
bit 2
bit 1
bit 0
UF
CNTE
TRG
R/W
R/W
R/W
Initial value
00000000 B
• 16-bit timer register upper and lower digits ch.0, ch.1 (TMR0, TMR1)
Address
TMR0 : 00004BH
00004AH
TMR1 : 00004EH
00004FH
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial value
XXXXXXXX B
XXXXXXXX B
XXXXXXXX B
XXXXXXXX B
• 16-bit re-load register upper and lower digits ch.0, ch.1 (TMRLR0, TMRLR1)
Address
TMRLR0 : 00004BH
00004AH
TMRLR1 : 00004EH
00004FH
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
W
W
W
W
W
W
R/W : Readable and writable
R : Read only
W : Write only
X : Indeterminate
— : Undefined bits (read value undefined)
44
W
W
W
W
W
W
W
W
W
W
Initial value
XXXXXXXX B
XXXXXXXX B
XXXXXXXX B
XXXXXXXX B
MB90520 Series
(2) Block Diagram
Internal data bus
TMRLR0*1
<TMRLR1>
16-bit re-load register
Re-load
control
circuit
Re-load signal
TMR0*1
<TMR1>
16-bit timer register (down counter) UF
CLK
Count clock generation circuit
φ
Prescaler
3
Gate input
Valid clock
decision
circuit
Clear
To UART*1
<To 8/10-bit
A/D converter>
CLK
Output control circuit
Internal
clock
Input
control
circuit
Pin
Wait signal
Clock
selecter
External
clock
P70/TI0/OUT4*1 3
<P72/TI1/OUT6>
2
Output signal
generation
circuit
Reverse
—
—
P71/TO0/OUT5*1
<P73/TO1/OUT7>
EN
Select
signal
Function select
—
Pin
Operation
control
circuit
— CSL1 CSL0 MOD2MOD1MOD0 OUTE OUTL RELD INTE UF CNTE TRG
Timer control status register (TMCSR0)*1
<TMCSR1>
*1: The timer has ch.0 and ch.1, and figures bracketed by < > are for ch.1
*2: Interrupt number
φ : Machine clock frequency
Clear
EI2CS
Interrupt request signal
#38*1, *2
<#40>
45
MB90520 Series
6. 16-bit I/O Timer
The 16-bit I/O timer module consists of two 16-bit free-run timers, two input capture circuits (ICU), and eight
output comparators (OCU). This module allows two independent waveforms to be output on the basis of the
16-bit free-run timer. Input pulse width and external clock periods can, therefore, be measured.
• Block diagram
Internal data bus
Input capture 0, 1
(ICU)
46
16-bit
Dedicated
Dedicated Output compare 0, 1
free-run timer 1, 2
(OCU)
bus
bus
MB90520 Series
(1) 16-bit Free-run Timer 1, 2
The 16-bit free-run timer consists of a 16-bit up counter, a control register and a communications prescaler
register. The value output from the timer counter is used as basic time (base timer) for input capture (ICU) and
output compare (OCU).
• A counter operation clock can be selected from four internal clocks (φ/4, φ/16, φ/64 and φ/256).
• An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0
and 4. (Compare match requires mode settings.)
• The counter value can be initialized to “0000H” by a reset, software clear or compare match with OCU compare
register 0 and 4.
• Register configuration
• Free-run timer data register 1, 2 (TCDT1, TCDT2)
Address
TCDT1 : 000057H
000056H
TCDT2 : 000067H
000066H
bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
T15 T14 T13 T12 T11 T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000 B
00000000 B
00000000 B
00000000 B
• Free-run timer control status register 1, 2 (TCCS1, TCCS2)
Address
TCCS1 : 000058H
TCCS2 : 000068H
bit 7
bit 6
bit 5
bit 4
Reserved
IVF
IVFE
STOP MODE
R/W
R/W
R/W
R/W
bit 3
R/W
bit 2
bit 1
bit 0
Initial value
CLR
CLK1
CLK0
00000000 B
00000000 B
R/W
R/W
R/W
R/W: Readable and writable
• Block diagram
Count value output
to ICO and OCU
Free-run timer data register (TCDT1)*1 <TCDT2>
OF
16-bit counter
φ
STOP
CLR
Communications
prescaler register
OCU compare register 0
match signal
2
Internal data bus
CLK
Free-run timer
control status register
(TCCS1) *1 <TCCS2>
Reserved
IVF
IVFE STOP MODE CLR CLK1 CLK0
16-bit free-run timer
interrupt request
#14*1, *2
<#28>
*1: The timer has ch.1 and ch.2, and figures bracketed by < > are for ch.2.
*2: Interrupt number
φ : Machine clock frequency
OF : Overflow
47
MB90520 Series
(2) Input Capture 0, 1 (ICU)
The input capture (ICU) generates an interrupt request to the CPU while storing the current counter value of
the 16-bit free-run timer to the ICU data register (IPCP) upon input of a trigger edge from the external pin.
There are two sets (two channels) of input capture external pins and ICU data registers, enabling measurements
of a maximum of four events.
• The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling
measurements of a maximum of four events.
• Trigger edge direction can be selected from rising/falling/both edges.
• The input capture can be set to generate an interrupt request at the storage timing of the counter value of the
16-bit free-run timer to the ICU data register (IPCP).
• The input compare conforms to the extended intelligent I/O service (EI2OS).
• The input capture ( ICU) function is suited for measurements of intervals (frequencies) and pulse-widths.
• Register configuration
• ICU data register ch.0 ch.1 (IPCP0, IPCP1)
Address
IPCP0(upper) : 000051H
IPCP1(upper) : 000053H
bit 15
CP15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
CP14
CP13
CP12
CP11
CP10
CP09
CP08
XXXXXXXXB
R
R
R
R
R
R
R
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
CP04
CP03
CP02
CP01
CP00
XXXXXXXXB
R
R
R
R
Address
IPCP0(lower) : 000050H
IPCP1(lower) : 000052H
bit 7
CP07
CP06
CP05
R
R
R
R
R
Note: This register holds a 16-bit free-run timer value when the valid edge of the corresponding external pin input waveform
is detected. (This register can be word-accessed, but not programmed.)
• ICU control status register (ICS01)
Address
bit 7
bit 6
bit 5
000054H
ICP1
ICP0
R/W
R/W
R/W : Readable and writable
R : Read only
X : Indeterminate
48
bit 4
bit 3
ICE1
ICE0
EG11
R/W
R/W
R/W
bit 2
bit 1
bit 0
Initial value
EG10
EG01
EG00
00000000B
R/W
R/W
R/W
MB90520 Series
• Block diagram
Internal data bus
Latch
signal
P20/IC00
Pin
Output latch
ICU data register (IPCP)
Edge detection circuit
P21/IC01
Pin
P22/IC10
Data latch signal
IPCP0(upper)
Pin
16
2
Pin
P23/IC11
IPCP0(lower)
IPCP1(upper)
IPCP1(lower)
16
16-bit free-run
timer 1, 2
2
ICU control status register (ICS01)
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
Interrupt request
#31*
Interrupt request
#32*
* : Interrupt number
49
MB90520 Series
(3) Output Compare 0, 1 (OCU)
The output compare (OCU) is two sets of compare units each consisting of an eight-channel OCU compare
register, a comparator and a control register.
An interrupt request can be generated for each channel upon a match detection by performing time-division
comparison between the OCU compare data register setting value and the counter value of the 16-bit free-run
timer.
The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a generalpurpose output port for directly outputting the setting value of the CMOD bit.
• Register Configuration
• OCU control status register ch.01, ch.23, ch.45, ch.67 (OCS01, OCS23, OCS45, OCS67)
Address
ch.01 : OCS01 (upper) : 0000063H
ch.23 : OCS23 (upper) : 0000065H
ch.45 : OCS45 (upper) : 000002DH
ch.67 : OCS67 (upper) : 000002FH
Address
ch.01 : OCS01 (lower) : 000062H
ch.23 : OCS23 (lower) : 000064H
ch.45 : OCS45 (lower) : 00002CH
ch.67 : OCS67 (lower) : 00002EH
bit 15
bit 14
bit 13
—
—
—
bit 12
—
—
—
R/W
bit 7
bit 6
bit 5
ICP1
ICP0
ICE1
bit 11
CMOD OTE1
bit 10
bit 9
bit 8
OTE0 OTD1
OTD0
R/W
R/W
R/W
R/W
bit 4
bit 3
bit 2
bit 1
bit 0
ICE0
—
—
CST1
CST0
Initial value
XXX0 0 0 0 0 B
Initial value
0 0 0 0XX0 0 B
R/W
R/W
R/W
R/W
—
—
R/W
R/W
• OCU control status register ch.0 to ch.7 (OCS0 to OCS7)
Address
ch.0 : OCP0 (upper) : 00005BH
ch.1 : OCP1 (upper) : 00005DH
ch.2 : OCP2 (upper) : 00005FH
ch.3 : OCP3 (upper) : 000061H
ch.4 : OCP4 (upper) : 00000DH
ch.5 : OCP5 (upper) : 00001DH
ch.6 : OCP6 (upper) : 000035H
ch.7 : OCP7 (upper) : 00006DH
Address
ch.0 : OCP0 (lower) : 00005AH
ch.1 : OCP1 (lower) : 00005CH
ch.2 : OCP2 (lower) : 00005EH
ch.3 : OCP3 (lower) : 000060H
ch.4 : OCP4 (lower) : 00000CH
ch.5 : OCP5 (lower) : 00001CH
ch.6 : OCP6 (lower) : 000034H
ch.7 : OCP7 (lower) : 00006CH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
C15
C14
C13
C12
C11
C10
C09
C08
XXXXXXXX B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
C07
C06
C05
C04
C03
C02
C01
C00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
50
Initial value
XXXXXXXX B
MB90520 Series
• Block diagram
• Output compare 0 (OCU)
#36*
#35*
Output compare
interrupt request
OCU control status register ch. 23 (OCS23)
—
—
— CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0
—
— CST1 CST0
2
2
16-bit free-run timer 1
Compare control circuit 3
OCP3
OCU compare register ch. 3
Internal data bus
Compare control circuit 2
P35/OUT3
Output
control
circuit 3
OCP2
Pin
OCU compare register ch. 2
P34/OUT2
Output
control
circuit 2
Pin
Compare control circuit 1
P33/OUT1
Output
control
circuit 1
OCP1
OCU compare register ch.1
Pin
P32/OUT0
Output
control
circuit 0
Compare control circuit 0
Pin
OCP0
OCU compare register ch. 0
2
2
—
—
— CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0
OCU control status register ch. 01
(OCS01)
—
— CST1 CST0
#34*
#33*
Output compare
interrupt request
* : Interrupt number
51
MB90520 Series
• Output compare 1(OCU)
Output compare
interrupt request
#27*
OCU control status register ch. 67 (OCS67)
—
—
—
CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0
—
— CST1 CST0
2
2
16-bit free-run timer 2
Compare control circuit 7
OCP7
Internal data bus
OCU compare register ch. 7
P73/TO1/OUT7
Compare control circuit 6
Output control
circuit 7
OCP6
OCU compare register ch. 6
Pin
P72/TI1/OUT6
Output control
circuit 6
Pin
Compare control circuit 5
P71/TO0/OUT5
OCP5
Output control
circuit 5
Pin
OCU compare register ch. 5
P70/TI0/OUT4
Output control
circuit 4
Compare control circuit 4
Pin
OCP4
OCU compare register ch. 4
2
2
—
—
— CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0
—
— CST1 CST0
OCU control status register ch. 45 (OCS45)
#25*
* : Interrupt number
52
Output compare
interrupt request
MB90520 Series
7. 8/16-bit Up/Down Counter/Timer 0, 1
The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit
re-load compare registers, and their controllers.
(1) Register Configuration
• Up/down count register 0 (UDCR0)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
000080H
D07
D06
D05
D04
D03
D02
D01
D00
00000000 B
R
R
R
R
R
R
R
R
bit 9
bit 8
Initial value
00000000 B
• Up/down count register 1 (UDCR1)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
000081H
D17
D16
D15
D14
D13
D12
D11
D10
R
R
R
R
R
R
R
R
• Re-load compare register 0 (RCR0)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
000082H
D07
D06
D05
D04
D03
D02
D01
D00
00000000 B
W
W
W
W
W
W
W
W
• Re-load compare register 1 (RCR1)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
000083H
D17
D16
D15
D14
D13
D12
D11
D10
00000000 B
W
W
W
W
W
W
W
W
bit 3
bit 2
bit 1
• Counter status register 0, 1 (CSR0, CSR1)
Address
CSR0 : 000084H
CSR1 : 000088H
bit 7
bit 6
bit 5
bit 4
CSTR
CITE
UDIE
CMPF
R/W
R/W
R/W
R/W
OVFF UDFF UDF1
bit 0
Initial value
UDF0
00000000 B
R/W
R/W
R
R
bit 3
bit 2
bit 1
bit 0
• Counter control register 0, 1 (CCRL0, CCRL1)
Address
CCRL0 : 000086H
CCRL1 : 00008AH
bit 7
bit 6
— CTUT
R/W
—
• Counter control register 0 (CCRH0)
bit 5
bit 4
UCRE RLDE UDCC CGSC CGE1 CGE0
R/W
R/W
R/W
R/W
bit 11
bit 10
R/W
bit 15
bit 14
bit 13
bit 12
000087H
M16E CDCF
CFIE
CLKS CMS1 CMS0 CES1 CES0
R/W
R/W
R/W
R/W
R/W
bit 14
bit 13
bit 12
bit 11
bit 10
R/W
R/W
X0 0 0 0 0 0 0 B
R/W
Address
bit 9
Initial value
bit 8
Initial value
00000000 B
R/W
• Counter control register 1 (CCRH1)
Address
bit 15
00008BH
—
CDCF
CFIE
CLKS CMS1 CMS0 CES1 CES0
—
R/W
R/W
R/W
R/W
R/W
bit 9
R/W
bit 8
Initial value
X0 0 0 0 0 0 0 B
R/W
R/W : Readable and writable
R : Read only
W : Write only
— : Undefined bits (read value undefined)
53
MB90520 Series
(2) Block Diagram
• Block diagram of 8/16-bit up/down counter/timer 0
Internal data bus
RCR0
Re-load compare register 0
Re-load
control
circuit
UDCR0
CARRY/
Up/down count register 0
BORROW
(to channel 1)
Counter control
register 0 (CCRL0)
Pin
Counter clear
circuit
Edge/level
detection
circuit
φ
Prescaler
P24/AIN0
Pin
Underflow
P26/ZIN0/INT7
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
Overflow
—
Compare
control circuit
Count clock
Counter status
register 0 (CSR0)
UP/down count
clock selector
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Pin
P25/BIN0
Interrupt request
#21*
Interrupt request
#22*
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
Counter control register 0 (CCRH0)
* : Interrupt number
φ: Machine clock frequency
54
M16E
(to channel 1)
MB90520 Series
• Block diagram of 8/16-bit up/down counter/timer 1
Internal data bus
RCR1
Re-load compare register 1
Re-load
control
circuit
UDCR1
Up/down count register 1
Counter control
register 1 (CCRL1)
P52/SCK2/ZIN1
Counter clear
circuit
Edge/level
Pin
detection
circuit
CARRY/BORRW
(from channel 0)
Prescaler
Pin
Compare
control circuit
Count clock
Counter status
(CSR1)
register 1
φ
P50/SIN2/AIN1
Underflow
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
Overflow
—
UP/down count
clock selector
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Pin
P51/SOT2/BIN1
M16E
(from channel 1)
Interrupt request
#29*
Interrupt request
#30*
—
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
Counter control register 1 (CCRH1)
* : Interrupt number
φ: Machine clock frequency
55
MB90520 Series
8. Extended I/O Serial Interface 0, 1
The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel
configuration.
For data transfer, you can select LSB first/MSB first.
(1) Register Configuration
• Serial mode control upper status register 0, 1 (SMCSH0, SMCSH1)
Address
SMCSH0 : 000025H
SMCSH1 : 000029H
bit 15
bit 14
bit 13
SMD2 SMD1 SMD0
R/W
R/W
R/W
bit 12
bit 11
SIE
SIR
R/W
R/W
bit 10
bit 9
bit 8
BUSY STOP STRT
R
R/W
Initial value
00000010 B
R/W
• Serial mode control lower status register 0, 1 (SMCSL0, SMCSL1)
Address
SMCSL0 : 000024H
SMCSL1 : 000028H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
—
—
—
—
MODE
BDS
SOE
SCOE
—
—
—
• Serial data register 0, 1 (SDR0, SDR1)
—
R/W
R/W
R/W
R/W
Address
SDR0 : 000026H
SDR1 : 00002AH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
R : Read only
X : Indeterminate
— : Undefined bits (read value undefined)
56
Initial value
XXXX0 0 0 0 B
MB90520 Series
(2) Block Diagram
Internal data bus
(MSB first) D0 to D7
D7 to D0 (LSB first)
Transfer direction selection
Pin
Read
Write
Serial data register
(SDR)
P45/SIN1
Pin
Pin
P50/SIN2/AIN1
P46/SOT1
Pin
P51/SOT2/BIN1
Pin
P47/SCK1
Control circuit
Shift clock counter
Pin
P52/SCK2/ZIN1
Internal clock
2
1
3
0
SMD2 SMD1 SMD0 SIE
Serial mode control
status register
(SMCSH,L)
SIR BUSY STOP STRT
—
—
—
—
MODE BDS SOE SCOE
Interrupt request
#15 (SMCS0)*
#17 (SMCS1)*
*: Interrupt number
57
MB90520 Series
9. UART (SCI)
UART (SCI) is a general-purpose serial data communication interface for performing synchronous or
asynchronous communication (start-stop synchronization system).
• Data buffer: Full-duplex double buffer
• Transfer mode:Clock synchronized (with start and stop bit)
Clock asynchronized (start-stop synchronization system)
• Baud rate:Embedded dedicated baud rate generator
External clock input possible
Internal clock (a clock supplied from 16-bit re-load timer 0 can be used.)
Internal machine clock
Asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps
For 6 MHz, 8 MHz, 10 MHz,
CLK synchronization 1 Mbps/500 kbps/250 kbps/125 kbps/62.5 kbps
12 MHz and 16 MHz
• Data length:8 bit (without a parity bit)
7 bit (with a parity bit)
• Signal format: NRZ (Non Return to Zero) system
• Reception error detection: Framing error
Overrun error
Parity error (multi-processor mode is supported, enabling setup of any baud rate
by an external clock.)
• Interrupt request: Receive interrupt (reception complete, receive error detection)
Transmit interrupt (transmisson complete)
Transmit/receive conforms to extended intelligent I/O service (EI2OS)
}
58
MB90520 Series
(1) Register Configuration
• Serial control register (SCR)
Address
000021H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
PEN
P
SBL
CL
A/D
REC
RXE
TXE
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MD1
MD0
CS2
CS1
CS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
PE
ORE
FRE
—
RIE
TIE
R
R
R
R
R
—
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
• Serial mode register (SMR)
Address
000020H
Reserved SCKE
SOE
Initial value
00000100 B
Initial value
00000000 B
• Serial status register (SSR)
Address
000023H
RDRF TRDE
Initial value
0 0 0 0 1X0 0 B
• Serial input data register (SIDR)
Address
000022H
Initial value
XXXXXXXX B
• Serial output data register (SODR)
Address
000022H
Initial value
XXXXXXXX B
• Communications prescaler control register (CDCR)
Address
000027H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
MD
—
—
—
DIV3
DIV2
DIV1
DIV0
R/W
—
—
—
R/W
R/W
R/W
R/W
Initial value
0XXX1 1 1 1 B
R/W:Readable and writable
R : Read only
W : Write only
X : Indeterminate
— : Undefined bits (read value undefined)
59
MB90520 Series
(2) Block Diagram
Control bus
Dedicated baud
rate generator
16-bit re-load timer 0
Receive
interrupt signal
#37*
Transmit
interrupt signal
#39*
Transmit
clock
Clock
selector
External clock
Receive
clock
Receive
control circuit
Transmit
control circuit
Pin
P42/SCK0
Start bit
detection circuit
Transmit start
circuit
Receive bit
counter
Transmit bit
counter
Receive parity
counter
Transmit parity
counter
Pin
P43/SOT0
Pin
Shift register for
reception
Shift register for
transmission
SIDR
SODR
P42/SIN0
Start transmission
Reception
complete
Receive condition
decision circuit
To EI2OS reception
error generation
signal (to CPU)
Internal data bus
SMR
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
* : Interrupt number
60
SCR
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
MB90520 Series
10. DTP/External Interrupt Circuit
The DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the
F2MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit*
for transmission to the F2MC-16LX CPU. It is used to activate the intelligent I/O service or interrupt processing.
As with request levels, two types of “H” and “L” can be selected for the intelligent I/O service. Rising and falling
edges as well as “H” and “L” can be selected for an external interrupt request.
* : The external peripheral circuit is connected outside the MB90520 series device.
(1) Register Configuration
• DTP/interrupt factor register (EIRR)
Address
000031H
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXX B
• DTP/interrupt enable register (ENIR)
Address
000030H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000 B
• Request level setting register (ELVR)
Address
bit 7
bit 6
ELVR (lower) : 000032H
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 8
Address
ELVR (upper) : 000033H
Initial value
00000000 B
Initial value
00000000 B
R/W: Readable and writable
X : Indeterminate
61
62
Pin
P00/INT0
Pin
P01/INT1
Pin
P02/INT2
Pin
P03/INT3
*: Interrupt number
Internal data bus
Pin
P04/INT4
P05/INT5
Pin
P06/INT6
Pin
P26/ZIN0/INT7
Level edge
selector 6
Level edge
selector 7
2
EN7
ER7
LB7
EN6
ER6
LA7
EN5
ER5
2
LB6
EN4
ER4
LA6
2
LA5
EN3
ER3
EN2
ER2
Level edge
selector 4
EN1
ER1
LB4
Level edge
selector 5
LB5
Request level setting register (ELVR)
2
LB3
2
LA3
LA2
Level edge
selector 2
Level edge
selector 3
LB2
2
LB1
LB0
Interrupt request signal
#24*
EN0 DTP/interrupt enable register (ENIR)
#13*
#18*
#20*
Level edge
selector 0
Level edge
selector 1
LA0
DTP/external interrupt
input detection circuit
2
LA1
ER0 DTP/interrupt factor register (EIRR)
LA4
2
MB90520 Series
(2) Block Diagram
MB90520 Series
11. Wake-up Interrupt
Wake-up interrupts transmit interrupt request (“L” level) generated by peripheral equipment located between
external peripheral devices and the F2MC-16LX CPU to the CPU and invoke interrupt processing.
The interrupt does not conform to the exterded intelligent I/O service (EI2OS).
(1) Register Configuration
• Wake-up interrupt flag register (EIFR)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
00000FH
—
—
—
—
—
—
—
WIF
—
—
—
—
—
—
—
R/W
Initial value
XXXXXXX0 B
• Wake-up interrupt enable register (EICR)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
00001FH
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
W
W
W
W
W
W
W
W
Initial value
00000000 B
R/W: Readable and writable
W : Write only
— : Undefined bits (read value undefined)
(2) Block Diagram
Internal data bus
Wake-up interrupt
enable register (EICR)
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
Wake-up interrupt flag
register (EIFR)
—
—
—
—
—
—
—
WIF
Interrupt request detection circuit
P10/WI0 Pin
P11/WI1
Pin
P12/WI2 Pin
Wake-up interrupt
request
#16*
P13/WI3 Pin
P14/WI4
Pin
P15/WI5
Pin
P16/WI6
Pin
P17/WI7
Pin
*: Interrupt number
63
MB90520 Series
12. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks. By using this module,
hardware interrupt requests to the CPU can be generated and cancelled using software.
This module does not conform to the extended intelligent I/O service (EI2OS).
(1) Register Configuration
• Delayed interrupt factor generation/cancellation register (DIRR)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
00009FH
—
—
—
—
—
—
—
R0
—
—
—
—
—
—
—
R/W
Initial value
XXXXXXX0 B
Note: Upon a reset, an interrupt is cancelled.
R/W: Readable and writable
— : Undefined bits (read value undefined)
The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this
register with “1” generates a delay interrupt request. Programming this register with “0” cancels a delay interrupt
request. Upon a reset, an interrupt is canceled. The undefined bit area can be programmed with either “0” or
“1.” For future extension, however, it is recommended that bit set and clear instructions be used to access this
register.
(2) Block Diagram
Internal data bus
—
—
—
—
—
Delayed interrupt factor generation/
cancellation register (DIRR)
*: Interrupt number
64
—
—
R0
S factor
R latch
Interrupt request signal
#42*
MB90520 Series
13. 8/10-bit A/D Converter
The 8/10-bit A/D converter converts analog voltage input to the analog input pins (input voltage) to digital values
(A/D conversion) and has the following features:
• Minimum conversion time: minimum 15.0 µs (at machine clock frequency of 16 MHz, including sampling time)
• Minimum sampling period: 4 µs/8 µs (at machine clock frequency of 16 MHz)
• Compare time: 99/176 machine cycles per channel
(99 machine cycles are used for a machine clock frequency below 10 MHz.)
• Conversion method: RC successive approximation method with a sample and hold circuit
• 8/10-bit resolution
• Analog input pins: Selectable from eight channels by software
Single conversion mode: Selects and converts one channel.
Scan conversion mode: Converts two or more successive channels. Up to eight channels can be programmed.
Continuous conversion mode: Repeatedly converts specified channels.
Stop conversion mode: Stops conversion after completing a conversion for one channel and wait for the
next activation (conversion can be started synchronously).
• Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the
end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling
efficient continuous processing.
• When interrupts are enabled, there is no loss of data even in continuous operations because the conversion
data protection function is in effect.
• Starting factors for conversion: Selectable from software activation, external trigger (falling edge) and timer
(rising edge).
65
MB90520 Series
(1) Register Configuration
• A/D control status register upper digits (ADCS2)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
000037H
BUSY
INT
INTE
PAUS
STS1
STS0
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
STRT Reserved
Initial value
00000000 B
• A/D control status register lower digits (ADCS1)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000036H
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
• A/D data register upper digits (ADCR2)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
000039H
SELB
ST1
ST0
CT1
CT0
—
(D9)
(D8)
W
W
W
W
W
—
R
R
Initial value
0 0 0 0 1XXX B
• A/D data register lower digits (ADCR1)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000038H
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
R/W:
R :
W :
X :
— :
66
Readable and writable
Read only
Write only
Indeterminate
Undefined bits (read value undefined)
Initial value
XXXXXXXX B
MB90520 Series
(2) Block Diagram
A/D control status
register (ADCS)
BUSY
INT
Interrupt request #11*
INTE PAUS STS1 STS0 STRT Reserved MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
6
2
Clock selector
Decoder
Internal data bus
P27/ADTG
P73/TO1/OUT7
φ
Comparator
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
Sample hold
circuit
Control circuit
Analog
channel
selector
A/D data register SELB
ST1 ST0 CT1 CT0
(ADCR)
AVRH, AVRL
AVCC
AVSS
—
(D9) (D8) D7
8-bit D/A converter
D6
D5
D4
D3
D2
D1
D0
TO : 16-bit re-load timer channel 1 output
* : Interrupt number
φ : Machine clock frequency
67
MB90520 Series
14. 8-bit D/A Converter
The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two
channels, each of which can be controlled in terms of output by the D/A control register.
(1) Register Configuration
• D/A converter data register ch.0 (DADR0)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00003AH
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXX B
• D/A converter data register ch.1 (DADR1)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
00003BH
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXX B
• D/A control register 0 (DACR0)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00003CH
—
—
—
—
—
—
—
DAE0
—
—
—
—
—
—
—
R/W
Initial value
XXXXXXX0 B
• D/A control register 1 (DACR1)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
00003DH
—
—
—
—
—
—
—
DAE1
—
—
—
—
—
—
—
R/W
R/W: Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
68
bit 8
Initial value
XXXXXXX0 B
MB90520 Series
• Block Diagram
Internal data bus
D/A converter data register ch.1 (DADR1)
D/A converter data register ch.0 (DADR0)
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
D/A converter 1
D/A converter 0
DVRH
DVRL
DA07
DA17
Pin
2R
P54/DA1
R
DA16
2R
DA15
2R
DA14
2R
DA13
2R
DA12
2R
DA11
2R
DA10
Pin
2R
DA06
2R
R
DA05
R
DA04
R
DA03
R
DA02
R
DA01
R
DA00
2R
2R
2R
2R
2R
2R
2R
—
—
R
R
R
R
R
2R
DVSS
DVSS
Standby control
D/A control register 1 (DACR1)
—
R
2R
Standby control
—
P53/DA0
R
—
D/A control register 0 (DACR0)
—
— DAE1
—
—
—
—
—
—
— DAE0
Internal data bus
69
MB90520 Series
15. Clock Timer
The clock timer control register (WTC) controls operation of the clock timer, and time for an interval interrupt.
(1) Register Configuration
• Clock timer control register (WTC)
Address
bit 7
bit 6
bit 5
0000AAH
WDCS
SCE
WTIE WTOF
R/W
R
R/W
bit 4
bit 3
WTR
R/W
R/W
bit 2
bit 1
bit 0
WTC2 WTC1 WTC0
R/W
R/W
Initial value
1X0 0 1 0 0 0 B
R/W
R/W: Readable and writable
R : Read only
X : Indeterminate
(2) Block Diagram
To watchdog timer
Timer counter
LCLK
× 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215
OF
OF
OF
OF
OF
OF
OF
Power-on reset
Shift to a hardware stand-by
Counter
clear circuit
To sub-clock
stabilization time controller
Shift to stop mode
Interval
timer selector
Clock timer interrupt request
#22*
WDCS SCE
WTIE WTOF WTR WTC2 WTC1 WTC0
Clock timer control register (WTC)
* : Interrupt number
OF : Overflow
LCLK : Sub-clock frequency
70
MB90520 Series
16.LCD Controller/Driver
The LCD (liquid crystal display) controller/driver, which contains a 16-byte display data memory, controls LCD
indication using four common output pins and 32 segment output pins. It can select three types of duty output
and directly drive the LCD panel.
(1) Register Configuration
• LCDC control register 0 (LCR0)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00006AH
CSS
LCEN
VSEL
BK
MS1
MS0
FP1
FP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
00010000 B
• LCDC control register 1 (LCR1)
Address
bit 15
00006BH
Reserved SEG5
R/W
R/W
SEG4 Reserved SEG3
SEG2 SEG1 SEG0
R/W
R/W
R/W
R/W
R/W
R/W
bit 11
bit 10
bit 9
bit 8
Initial value
00000000 B
• Port 7/COM pin selection register (LCDCMR)
Address
bit 15
bit 14
bit 13
bit 12
00000BH
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
COM3 COM2 COM1 COM0
Initial value
XXXX0 0 0 0 B
• RAM for LCD indication (VRAM)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
000070H
to
00007FH
b7
b6
b5
b4
b3
b2
b1
b0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXX B
R/W: Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
71
MB90520 Series
(2) Block Diagram
LCDC control
register 0
(LCR0)
Pin
V0
Pin
V1
Pin
V2
Pin
V3
Pin
P74/COM0
Pin
P75/COM1
Pin
P76/COM2
Pin
P77/COM3
Pin
SEG00
Pin
SEG01
Pin
SEG02
Split resistor
CSS LCEN VSEL BK MS1 MS0 FP1 FP0
Timing
controller
Prescaler
generator
LCLK
Common driver
HCLK
32
Reserved SEG5 SEG4 Reserved SEG3 SEG2 SEG1 SEG0
LCDC control register 1
(LCR1)
Controller section
HCLK : Oscillation frequency
LCLK : Sub-clock frequency
72
Segment driver
6
.........
Indication RAM
(16 bytes)
.........
AC
Internal data bus
2
Pin
P95/SEG29
Pin
P96/SEG30
Pin
P97/SEG31
MB90520 Series
17. Communications Prescaler Register
This register controls machine clock division.
Output from the communications prescaler register is used for UART (SCI) and extended I/O serial interface.
The communications prescaler register is so designed that a constant baud rate may be acquired for various
machine clocks.
(1) Register Configuration
• Communications prescaler control register (CDCR)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
000027H
MD
—
—
—
DIV3
DIV2
DIV1
DIV0
R/W
—
—
—
R/W
R/W
R/W
R/W
Initial value
0XXX1 1 1 1 B
R/W: Readable and writable
— : Undefined bits (read value undefined)
73
MB90520 Series
18. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set
instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program
patching function to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value
set in the address detection register matches an address and if the interrupt enable bit is set at “1,” the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register Configuration
• Program address detection register 0 to 2 (PADR0)
Address
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PADR0 (High order address) : 001FF2H
Address
PADR0 (Middle order address) : 001FF1H
Address
PADR0 (Low order address) : 001FF0H
Initial value
XXXXXXXX B
Initial value
XXXXXXXX B
Initial value
XXXXXXXX B
• Program address detection register 3 to 5 (PADR1)
Address
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 3
bit 2
bit 1
bit 0
PADR1 (High order address) : 001FF5H
Address
PADR1 (Middle order address) : 001FF4H
Address
PADR1 (Low order address) : 001FF3H
Initial value
XXXXXXXX B
Initial value
XXXXXXXX B
Initial value
XXXXXXXX B
• Program address detection control status register (PACSR)
Address
bit 7
bit 6
bit 5
bit 4
00009EH Reserved Reserved Reserved Reserved AD1E Reserved AD0E Reserved
R/W
R/W: Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
74
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
MB90520 Series
Internal data bus
Address latch
Address detection register
Enable bit
Compare
(2) Block Diagram
INT9
instruction
F2MC-16LX
CPU core
75
MB90520 Series
19. ROM Mirroring Function Selection Module
The ROM mirror function select module enables the ROM data from the FF bank to be read also from the 00 bank.
(1) Register Configuration
• ROM mirroring function selection register (ROMM)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
00006FH
—
—
—
—
—
—
—
MI
—
—
—
—
—
—
—
W
W : Write only
— : Undefined bits (read value undefined)
Note: Do not access this register during operation at addresses 004000H to 00FFFFH.
(2) Block Diagram
Internal data bus
ROM mirroring function selection
register (ROMM)
Address area
Address
FF bank
00 bank
Data
ROM
76
Initial value
XXXXXXX1 B
MB90520 Series
20. Low-power Consumption (Stand-by) Mode
The F2MC-16LX has the following CPU operating modes configured by selection of an operating clock and clock
operation control.
• Clock mode
PLL clock mode : A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation
clock.
Main clock mode: A mode in which the CPU and peripheral equipment are driven by drivided-by-2 of the
oscillation clock. The PLL multiplication circuits stops in the main clock mode.
• Sub-clock mode
The sub-clock mode causes the CPU to operate only with the sub-clock. This mode uses the sub-clock
frequency divided by four as the operating clock frequency while stopping the main clock and PLL clock.
• CPU intermittent operation mode
The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU
intermittently while external bus and peripheral functions are operated at a high speed.
• Hardware stand-by mode
The hardware standby mode is a mode for reducing power consumption by stopping clock supply to the CPU
by the low-power consumption control circuit (sleep mode), stopping clock supplies to the CPU and peripheral
functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware stand-by mode). Of
these modes, modes other than the PLL clock mode are low power consumption modes.
(1) Register Configuration
• Clock select register (CKSCR)
Address
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
0000A1H
SCM
MCM
WS1
WS0
SCS
MCS
CS1
CS0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
bit 3
bit 2
bit 1
bit 0
TMD
CG1
CG0
SSR
W
R/W
R/W
R/W
Initial value
11111100 B
• Low-power consumption mode control register (LPMCR)
Address
0000A0H
bit 7
bit 6
STP
SLP
W
W
bit 5
SPL
R/W
bit 4
RST
W
Initial value
00011000 B
R/W: Readable and writable
R : Read only
W : Write only
77
MB90520 Series
(2) Block Diagram
Standby control circuit
Low-power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0 SSR
Hardware
standby
CPU clock
control circuit
Peripheral clock
control circuit
S
Q
S
R
Reset
Interrupt
CPU intermittent
operation cycle
selector
2
Clock mode
Sleep signal
Stop signal
Q
R
S
Q
S
R
CPU operation
clock
Peripheral function
operation clock
Machine clock
Q
R
Clock selector
Oscillation
stabilization
time selector
2
2
PLL multiplication
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
X0
X1
Pin
Oscillation
clock
Pin
Dividedby-2
Main
Clock oscillator
Dividedby-2048
Dividedby-4
Dividedby-4
Dividedby-8
clock
Timebase timer
To watchdog timer
X0A Pin
X1A Pin
Sub-clock
Dividedby-1024
Dividedby-8
Clock timer
Sub-clock oscillator
S : Set
R : Reset
Q : Output
78
Dividedby-2
Dividedby-2
MB90520 Series
21.Clock Monitor Function
The clock monitor function outputs the frequency-divided machine clock signal (for monitoring purposes) from
the CKOT pin.
(1) Register configuration
• Clock output enable register
Address
00003EH
bit 7
bit 6
bit 5
bit 4








bit 3
bit 2
CKEN FRQ2
R/W
R/W
bit 1
bit 0
FRQ1 FRQ0
R/W
Initial value
XXXXXXX1B
R/W
R/W:Readable and writable
—:Undefined bits (read value undefined)
Internal data bus
(2) Block Diagram
CKEN
FQR2
FQR1
FQR0
Divider
circuit
φ
P31/CKOT
φ : Machine clock frequency
79
MB90520 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Rating
Unit
Remarks
Min.
Max.
VCC
VSS – 0.3
VSS + 6.0
V
AVCC
VSS – 0.3
VSS + 6.0
V
*1
AVRH,
AVRL
VSS – 0.3
VSS + 6.0
V
*1
DVCC
VSS – 0.3
VSS + 6.0
V
*2
Input voltage
VI
VSS – 0.3
VCC + 6.0
V
*3
Output voltage
VO
VSS – 0.3
VCC + 6.0
V
*3
“L” level maximum output current
IOL

15
mA
*4
“L” level average output current
IOLAV

4
mA
*5
“L” level total maximum output current ΣIOL

100
mA
Power supply voltage
“L” level total average output current
ΣIOLAV

50
mA
*6
“H” level maximum output current
IOH

–15
mA
*4
“H” level average output current
IOHAV

–4
mA
*5
“H” level total maximum output current ΣIOH

–100
mA
“H” level total average output current
ΣIOHAV

–50
mA
Power consumption
PD

300
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
*1:
*2:
*3:
*4:
*5:
*6:
*6
AVCC, AVRH, AVRL, and DVCC shall never exceed VCC. AVRL shall never exceed AVRH.
VCC ≥ AVCC ≥ DVCC ≥ 3.0V
VI and VO shall never exceed VCC + 0.3 V.
The maximum output current is a peak value for a corresponding pin.
Average output current is an average current value observed for a 100 ms period for a corresponding pin.
Total average current is an average current value observed for a 100 ms period for all corresponding pins.
Note: Average output current = operating current × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
80
MB90520 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Unit
Remarks
5.5
V
Normal operation (MB90522, MB90523)
4.0
5.5
V
Normal operation (MB90F523)
Guaranteed frequency = 10 MHz
at 4.0 V to 4.5V
VCC
3.0
5.5
V
Retains status at the time operation
stops
Smoothing capacitor
CS
0.1
1.0
µF
*
Operating temperature
TA
–40
+85
°C
Parameter
Power supply voltage
Symbol
Value
Min.
Max.
VCC
3.0
VCC
* : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be
connected to the VCC pin must have a capacitance value higher than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
• C pin diagram
C
CS
81
MB90520 Series
3. DC Characteristics
Parameter Symbol
Pin name
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit Remarks
Min.
Typ.
Max.
VIHS
P20 to P27,
P30 to P37,
P53, P54,
P70 to P77,
P80 to P87,
PA0 to PA7,
VIHM
MD0 to MD2
VILS
P20 to P27,
P30 to P37,
P53, P54,
P70 to P77,
P80 to P87,
PA0 to PA7,
VILM
MD0 to MD2
“H” level
output
voltage
VOH
Other than P90
to P97
VCC = 4.5 V,
IOH = –2.0 mA
“L” level
output
voltage
VOL
All output pins
VCC = 4.5 V,
IOL = 2.0 mA
“H” level
input
voltage
“L” level
input
voltage
—
VCC + 0.3
V
—
VCC + 0.3
V
VSS – 0.3
—
0.2 VCC
V
VSS – 0.3
—
VSS + 0.3
V
VCC – 0.5
—
—
V
—
—
0.4
V
—
0.1
5
µA
–5
—
5
µA
0.8 VCC
VCC = 3.0 V to 5.5 V
(MB90523)
VCC – 0.3
VCC = 4.0 V to 5.5 V
(MB90F523)
Open-drain
output
Ileak
leakage
current
Output pin
P90 to P97
Input
leakage
current
IIL
Other than P90
to P97
Pull-up
resistance
RUP
P00 to P07, P10
to P17, P40 to
P47, RST, MD0,
MD1
—
15
30
100
kΩ
Pull-down
resistance
RDOWN
MD2
—
15
30
100
kΩ
—
VCC = 5.5 V,
VSS < VI < VCC
(Continued)
82
MB90520 Series
Parameter Symbol
Power
supply
current*
Pin name
ICC
VCC
ICC
VCC
ICC
VCC
ICC
VCC
ICC
VCC
ICC
VCC
ICC
VCC
ICCS
VCC
ICCS
VCC
ICCL
VCC
ICCL
VCC
ICCLS
VCC
ICCLS
VCC
ICCT
VCC
ICCT
VCC
ICCH
VCC
ICCH
VCC
Input
CIN
capacitance
Other than AVCC,
AVSS, C, VCC, VSS
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit Remarks
Min.
Typ.
Max.
Internal operation
at 16 MHz
VCC at 5.0 V
Normal operation
Internal operation
at 16 MHz
VCC at 5.0 V
A/D converter
operation
Internal operation
at 16 MHz
VCC at 5.0 V
D/A converter
operation
When data is
written or erased
in flash mode
Internal operation
at 16 MHz
VCC at 5.0 V
In sleep mode
Internal operation
at 8 kHz
VCC at 5.0 V
TA = +25°C
Subsystem
operation
Internal operation
at 8 kHz
VCC at 5.0 V
TA = +25°C
In subsleep mode
Internal operation
at 8 kHz
VCC at 5.0 V
TA = +25°C
In clock mode
TA = +25°C
In stop mode
—
MB90522,
MB90523
—
30
40
mA
—
85
130
mA MB90F523
—
35
45
mA
—
90
140
mA MB90F523
—
40
50
mA
—
95
145
mA MB90F523
—
95
140
mA MB90F523
—
7
12
mA
—
25
30
mA MB90F523
—
0.1
1.0
mA
—
4
7
mA MB90F523
—
30
50
µA
—
0.1
1
mA MB90F523
—
15
30
µA
MB90522,
MB90523
—
30
50
µA
MB90F523
—
5
20
µA
MB90522,
MB90523
—
0.1
10
µA
MB90F523
—
10
80
pF
MB90522,
MB90523
MB90522,
MB90523
MB90522,
MB90523
MB90522,
MB90523
MB90522,
MB90523
(Continued)
83
MB90520 Series
(Continued)
Parameter Symbol
LCD split
resistor
RLCD
Pin name
V0 to V1,
V1 to V2,
V2 to V3
Output
impedance
RVCOM
for COM0
to COM3
COM0 to COM3
Output
impedance
RVSEG
for SEG00
to SEG31
SEG00 to SEG31
LCDC leak
ILCDC
current
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit Remarks
Min.
Typ.
Max.
—
50
100
200
kΩ
—
—
2.5
kΩ
—
—
15
kΩ
—
—
±5
µA
V1 to V3 = 5.0 V
V0 to V3,
COM1 to COM3,
—
SEG00 to SEG31
* : The current value is preliminary and may be subject to change for enhanced characteristics without previous
notice.The power supply current is measured with an external clock.
84
MB90520 Series
4. AC Characteristics
(1) Reset, Hardware Standby Input Timing
Parameter
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit
Remarks
Min.
Max.
Reset input time
tRSTL
RST
Hardware standby input time
tHSTL
HST
—
4 tCP*
—
ns
4 tCP*
—
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
• Measurement conditions for AC ratings
Pin
CL
CL is a load capacitance connected to a pin under test.
CL of 80 pF must be connected to address data bus (AD15 to AD00).
85
MB90520 Series
(2) Specification for Power-on Reset
Parameter
Symbol Pin name Condition
Power supply rising time
tR
VCC
Power supply cut-off time
tOFF
VCC
—
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Min.
Max.
0.05
30
ms *
Due to repeated
4
—
ms
operations
* : VCC must be kept lower than 0.2 V before power-on.
Notes: • The above ratings are values for causing a power-on reset.
• There are internal registers which can be initialized only by a power-on reset.
Apply power according to this rating to ensure initialization of the registers.
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to raise the voltage
smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage when the PLL clock is not in use. If the voltage drops 1 V or less per
second, however, the PLL clock may be used.
VCC
0.2 V
VSS
86
It is recommended to keep the rising
speed of the supply voltage at 50 mV/ms
or slower.
MB90520 Series
(3) Clock Timings
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit
Remarks
Parameter
Min.
Typ. Max.
FC
X0, X1
—
3
—
16
MHz
4.0 V to
Clock frequency
FC
X0, X1
3
—
10
MHz MB90F523
4.5 V
FCL
X0A, X1A
—
32.768
—
kHz
—
tHCYL
X0, X1
62.5
—
333
ns
4.0 V to
X0, X1
Clock cycle time
tHCYL
100
—
333
ns MB90F523
4.5 V
X0A, X1A
—
—
30.5
—
µs
tLCYL
Recommended
PWH,
X0
—
10
—
—
ns duty ratio of
PWL
30% to 70%
Input clock pulse width
PWLH,
X0A
—
—
15.2
—
µs
PWLL
tCR,
External clock
Input clock rising/falling time
X0, X0A
—
—
—
5
ns
tCF
operation
When the main
—
—
1.5
—
16
MHz
fCP
clock is used
4.0 V to
When the main
fCP
—
Internal operating clock
1.5
—
10
MHz
4.5 V
clock is used
frequency
When the
—
—
—
8.192
—
kHz subclock is
fLCP
used
When the main
—
—
62.5
—
333
ns
tCP
clock is used
4.0 V to
When the main
—
100
—
333
ns
Internal operating clock cycle tCP
4.5 V
clock is used
time
When the
—
—
—
122.1
—
µs subclock is
tLCP
used
Frequency fluctuation rate
∆f
—
—
—
—
5
% *
locked
* : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied
PLL signal is locked.
+
+α
∆f = | α | × 100 (%)
fO
Center frequency fO
–α
–
The PLL frequency deviation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC),”
thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with
long intervals).
87
MB90520 Series
• X0, X1 clock timing
tHCYL
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
• X0A, X1A clock timing
tLCYL
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
X0A
PWLH
0.2 VCC
PWLL
tCR
tCF
• PLL operation guarantee range
Relationship between internal operating clock
frequency and power supply voltage
Power supply voltage VCC
(V)
MB90F523 operation guarantee range
5.5
4.5
4.0
PLL operation
guarantee range
3.3
MB90V520 operation guarantee range
3.0
MB90522,MB90523 operation guarantee range
1
10
8
Internal clock fCP
3
12
16
(MHz)
Relationship between oscillating frequency and internal
operating clock frequency
(MHz)
Multiplied Multiplied Multiplied
-by-3
-by-2
-by-4
Internal clock fCP
16
Multiplied
-by-1
12
8
Not multiplied
4
3
2
1
2
3
4
6
8
Oscillation clock FC
88
12
16
(MHz)
MB90520 Series
The AC ratings are measured for the following measurement reference voltages.
• Input signal waveform
Hystheresis input pin
• Output signal waveform
Hystheresis input pin
0.8 VCC
2.4 VCC
0.2 VCC
0.8 VCC
Pins other than hystheresis input/MD input
0.7 VCC
0.3 VCC
89
MB90520 Series
(4) Recommended Resonator Manufacturers
• Sample application of ceramic resonator
X0
X1
R
*
XTAL
C1
C2
• Mask ROM product (MB90522, MB90523)
Resonator
manufacturer
Murata
Mfg. Co., Ltd.
TDK Corporation
Frequency
(MHz)
C1 (pF)
C2 (pF)
R
CSA2.00MG040
2.00
100
100
Not required
CSA4.00MG040
4.00
100
100
Not required
CSA8.00MTZ
8.00
30
30
Not required
CSA16.00MXZ040
16.00
15
15
Not required
CSA32.00MXZ040
32.00
5
5
Not required
CCR3.52MC3 to
CCR6.96MC3
3.52
to
6.96
Built-in
Built-in
Not required
CCR7.0MC5 to
CCR12.0MC5
7.00
to
12.00
Built-in
Built-in
Not required
CCR20.0MSC6 to
CCR32.0MSC6
20.00
to
32.00
Built-in
Built-in
Not required
Resonator
(Continued)
90
MB90520 Series
(Continued)
• Flash ROM product (MB90F523)
Resonator
Resonator
manufacturer
CSA2.00MG040
CSA4.00MG040
Murata
CSA8.00MTZ
Mfg. Co., Ltd.
CSA16.00MXZ040
CSA32.00MXZ040
CCR3.52MC3 to
CCR6.96MC3
TDK Corporation
CCR7.0MC5 to
CCR12.0MC5
CCR20.0MSC6 to
CCR32.0MSC6
Frequency
(MHz)
2.00
4.00
8.00
16.00
32.00
3.52
to
6.96
7.0
to
12.0
20.0
to
32.0
C1 (pF)
C2 (pF)
R
100
100
30
15
5
100
100
30
15
5
Not required
Not required
Not required
Not required
Not required
Built-in
Built-in
Not required
Built-in
Built-in
Not required
Built-in
Built-in
Not required
Inquiry:Murata Mfg. Co., Ltd..
• Murata Electronics North America, Inc.: TEL 1-404-436-1300
• Murata Europe Management GmbH: TEL 49-911-66870
• Murata Electronics Singapore (Pte.): TEL 65-758-4233
TDK Corporation
• TDK Corporation of America
Chicago Regional Office: TEL 1-708-803-6100
• TDK Electronics Europe GmbH
Components Division: TEL 49-2102-9450
• TDK Singapore (PTE) Ltd.: TEL 65-273-5022
• TDK Hong Kong Co., Ltd.: TEL 852-736-2238
• Korea Branch, TDK Corporation: TEL 82-2-554-6636
91
MB90520 Series
(5)
UART (SCI) Timing
Parameter
Serial clock cycle time
SCK ↓ → SOT delay
time
Valid SIN → SCK ↑
SCK ↑ → valid SIN
hold time
Serial clock “H” pulse
width
Serial clock “L” pulse
width
SCK ↓ → SOT delay
time
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
tSCYC
8 tCP*
SCK0 to SCK2
—
ns
SCK0 to SCK2, Internal shift clock
tSLOV
– 80
80
ns
SOT0 to SOT2 mode
SCK0 to SCK2, CL = 80 pF
100
—
ns
tIVSH
+ 1 TTL for an
SIN0 to SIN2
SCK0 to SCK2, output pin
tSHIX
60
—
ns
SIN0 to SIN2
tSHSL
SCK0 to SCK2
4 tCP*
—
ns
tSLSH
SCK0 to SCK2 External shift
clock mode
SCK0 to SCK2
CL = 80 pF
SOT0 to SOT2
+ 1 TTL for an
SCK0 to SCK2, output pin
SIN0 to SIN2
SCK0 to SCK2,
SIN0 to SIN2
4 tCP*
—
ns
—
150
ns
60
—
ns
60
—
ns
tSLOV
Valid SIN → SCK ↑
tIVSH
SCK ↑ → valid SIN
hold time
tSHIX
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Notes: • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitor value connected to pins while testing.
92
MB90520 Series
• Internal shift clock mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.2 V
tIVSH
SIN
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External shift clock mode
tSLSH
SCK
0.2 VCC
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
SOT
2.4 V
0.8 V
tIVSH
SIN
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
93
MB90520 Series
(6)
Timer Input Timing
Parameter
Input pulse width
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
IC00,IC01,IC10,
tTIWH,
—
4 tCP*
—
ns
tTIWL
IC11,TI0, TI1
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
IN
tTIWH
(7)
tTIWL
Timer Output Timing
Parameter
CLK ↑ → TOUT
transition time
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
OUT0 to OUT3,
PG00,
—
30
—
ns
tTO
PG01,PG10, PG11
2.4 V
CLK
tTO
TOUT
94
2.4 V
0.8 V
MB90520 Series
5. A/D Converter
Parameter
Resolution
Total error
Non-linear error
Differential
linearity error
Zero transition
voltage
Full-scale
transition
voltage
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, 3.0 V ≤ AVRH – AVRL, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit
Min.
Typ.
Max.
—
—
—
8/10
—
bit
—
—
—
—
±5.0
LSB
—
—
—
—
±2.5
LSB
—
—
mV
VFST
AN0 to
AN7
AVRH
–6.5LSB
mV
Sampling time
—
—
VCC = 5.0 V ±10%
at machine clock of 16 MHz
VCC = 5.0 V ±10%
at machine clock of 16 MHz
VAIN
—
AVRH
—
AVRL
—
—
ns
64 tCP*
—
—
ns
—
—
10
µA
AVRL
—
AVRH
V
AVRL
+ 2.7
—
AVCC
V
0
—
—
—
AVCC
IA
IAH
AVCC
IR
AVRH
IRH
AVRH
—
AN0 to
AN7
AVRH
AVRH
–1.5 LSB +1.5 LSB
240 tCP*
AN0 to
AN7
AN0 to
AN7
IAIN
Reference
voltage
Offset between
channels
LSB
AVSS
AVSS
+0.5 LSB
–3.5 LSB
+4.5 LSB
—
Reference
voltage supply
current
±1.9
AN0 to
AN7
—
Power supply
current
—
VOT
Conversion time
Analog port
input current
Analog input
voltage
—
—
5
AVRH
–2.7
—
mA
V
Supply current when CPU
stopped and 8/10-bit A/D
converter not in operation
(VCC = AVCC = AVRH = 5.0 V)
—
Supply current when CPU
stopped and 8/10-bit A/D
converter not in operation
(VCC = AVCC = AVRH = 5.0 V)
—
—
5
µA
—
400
—
µA
—
—
5
µA
—
—
—
4
LSB
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
95
MB90520 Series
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000
0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual
conversion characteristics
Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error: The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error, full-scale transition error and linearity error.
Total error
3FF
3FE
0.5 LSB
Actual conversion
characteristics
Digital output
3FD
{1 LSB × (N – 1) + 0.5 LSB}
004
VNT
(measured value)
003
Actual conversion
characteristics
002
Theoretical
characteristics
001
0.5 LSB
AVRL
1 LSB = (Theoretical value)
AVRH – AVRL
Analog input
[V]
1024
VOT (Theoretical value) = AVRL + 0.5 LSB [V]
AVRH
Total error for digital output N =
VNT – {1 LSB × (N – 1) + 0.5 LSB}
[LSB]
1 LSB
VNT: Voltage at a transition of digital output from (N – 1) to N
VFST (Theoretical value) = AVRH – 1.5 LSB [V]
(Continued)
96
MB90520 Series
(Continued)
Linearity error
Differential linearity error
Theoretical
characteristics
3FF
Actual conversion
characteristics
Digital output
3FD
Actual conversion
characteristics
N+1
{1 LSB × (N – 1)
+ VOT}
VFST
(measured value)
VNT
(measured value)
004
Actual conversion
characteristics
003
Digital output
3FE
N
N–1
V(N + 1)T
(measured value)
N–2
VNT (measured value)
002
Theoretical
characteristics
001
Actual conversion
characteristics
VOT (mesured value)
AVRL
Analog input
AVRH
AVRL
Analog input
AVRH
VNT – {1 LSB × (N – 1) + VOT}
Linearity error of
[LSB]
digital output N =
1 LSB
Differential linearity error
=
of digital N
1 LSB =
V(N + 1)T – VNT
– 1 LSB [LSB]
1 LSB
VFST – VOT
[V]
1022
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST: Voltage at transition of digital output from “3FEH” to “3FFH”
7. Notes for A/D Conversion
Analog inputs should have external circuit impedance of approximately 5 kΩ or less.
External capacitance, if used, should be several thousand times the level of the chip’s internal capacitance in
consideration of the effects of partial potential between the external and internal capacitance.
If the impedance of the external circuit is too high, the analog voltage sampling interval may be insufficient (using
a sampling interval of 4.00 µs and a machine clock frequency of 16 MHz).
• Block diagram of analog input circuit model
Analog input
RON
C
Comparator
MB90522, MB90523
RON: Approx. 1.5 kΩ
C: Approx. 30 pF
MB90F523
RON: Approx. 3.0 kΩ
C: Approx. 65 pF
Note: Listed values must be considered standards.
• Error
The smaller | AVRH – AVRL | is, the greater the error is.
97
MB90520 Series
8. D/A Converter
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, TA = –40°C to +85°C)
Symbol
Pin name
Resolution
—
Differential linearity
error
Parameter
Unit
Remarks
Min.
Typ.
Max.
—
—
8
—
bit
—
—
—
—
±0.9
LSB
Absolute accuracy
—
—
—
—
±1.2
%
Linearity error
—
—
—
—
±1.5
LSB
Conversion time
—
—
—
10
20
Analog reference
voltage
—
DVCC
VSS + 3.0
—
AVCC
V
IDVR
DVCC
—
—
300
µA
IDVRS
DVCC
—
—
10
µA In sleep mode
—
20
—
kΩ
Reference voltage
supply current
Analog output
impedance
98
Value
—
—
µs Load capacitance: 20 pF
MB90520 Series
■ EXAMPLE CHARACTERISTICS
(1) Power Supply Current (MB90523)
ICC – VCC
ICCS – VCC
ICCS (mA)
10
ICC (mA)
35
TA = +25°C
TA = +25°C
9
30
8
25
Fc = 16 MHz
20
Fc = 12.5 MHz
Fc = 10 MHz
15
Fc = 8 MHz
10
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
5
3.0
4.0
5.0
Fc = 16 MHz
7
6
Fc = 12.5 MHz
5
Fc = 10 MHz
Fc = 8 MHz
4
Fc = 5 MHz
Fc = 4 MHz
3
2
Fc = 2 MHz
1
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
ICCS – TA
ICC – TA
ICC (mA)
35
ICCS (mA)
10
VCC = 5.0 V
VCC = 5.0 V
9
30
8
25
Fc = 16 MHz
20
Fc = 12.5 MHz
Fc = 10 MHz
15
Fc = 8 MHz
10
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
5
–20
+10
+40
+70
Fc = 16 MHz
7
6
Fc = 12.5 MHz
5
Fc = 10 MHz
4
Fc = 8 MHz
3
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
2
1
+100
–20
+10
+70
+40
TA (°C)
ICCL – VCC
ICCLS – VCC
ICCLS (mA)
70
ICCL (µA)
160
TA = +25°C
TA = +25°C
60
140
Fc = 8 kHz
120
+100
TA (°C)
100
50
Fc = 8 kHz
40
80
30
60
20
40
10
20
3.0
4.0
5.0
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
99
MB90520 Series
ICCS – Fc
ICC – Fc
ICC (mA)
35
ICCS (mA)
10
TA = +25°C
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
30
25
20
VCC = 3.0 V
15
VCC = 2.5 V
TA = +25°C
7
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
6
VCC = 3.0 V
5
VCC = 2.5 V
9
8
4
3
10
2
5
1
4.0
6.0
8.0
16.0
Fc (MHz)
12.0
4.0
ICCT – VCC
ICCT (µA)
20
12.0
16.0
Fc (MHz)
ICCH – VCC
TA = +25°C
9
16
8
14
Fc = 8 kHz
7
12
6
10
5
8
4
6
3
4
2
2
1
3.0
4.0
5.0
6.0
VCC (V)
3.0
ICCT – TA
4.0
5.0
6.0
VCC (V)
ICCH – TA
ICCT (µA)
10
ICCL (µA)
10
9
9
8
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
7
6
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
5
4
3
8
6
5
4
3
2
1
1
+10
+40
+70
+100
TA (°C)
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
7
2
–20
100
8.0
ICCH (µA)
10
TA = +25°C
18
6.0
–20
+10
+40
+70
+100
TA (°C)
MB90520 Series
ICCLS – TA
ICCL – TA
ICCL (µA)
20
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
18
16
14
12
10
ICCLS (µA)
14
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
12
10
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
8
6
8
6
4
4
2
2
–20
+10
+40
+100
+70
–20
+10
+40
+100
+70
TA (°C)
TA (°C)
(2) Power Supply Current (MB90F523)
ICCS – VCC
ICC – VCC
ICC (mA)
140
ICCS (mA)
40
TA = +25°C
TA = +25°C
35
120
Fc = 16 MHz
30
100
80
60
40
Fc = 12.5 MHz
Fc = 10 MHz
25
Fc = 8 MHz
20
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
15
20
Fc = 16 MHz
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
10
5
3.0
4.0
5.0
3.0
6.0
VCC (V)
ICC – TA
ICC (mA)
120
4.0
5.0
6.0
VCC (V)
ICCS – TA
ICCS (mA)
40
VCC = 5.0 V
VCC = 5.0 V
35
100
80
60
Fc = 16 MHz
30
Fc = 12.5 MHz
25
Fc = 10 MHz
20
Fc = 16 MHz
15
Fc = 12.5 MHz
Fc = 10 MHz
10
Fc = 8 MHz
5
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
Fc = 8 MHz
40
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
20
–20
+10
+40
+70
+100
TA (°C)
–20
+10
+40
+70
+100
TA (°C)
101
MB90520 Series
ICCS – VCC
ICCLS (µA)
200
TA = +25°C
180
160
Fc = 8 MHz
140
120
100
80
60
40
20
3.0
ICC – Fc
ICC (mA)
120
TA = +25°C
4.0
5.0
6.0
VCC (V)
ICCS – Fc
ICCS (mA)
40
TA = +25°C
100
VCC = 6.0 V
35
VCC = 5.5 V
30
VCC = 5.0 V
80
VCC = 6.0 V
VCC = 5.5 V
25
VCC = 5.0 V
VCC = 4.5 V
60
20
VCC = 4.5 V
VCC = 3.5 V
15
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
10
VCC = 2.5 V
5
VCC = 4.0 V
40
20
4.0
8.0
12.0
VCC = 3.0 V
VCC = 2.5 V
16.0
Fc (MHz)
4.0
ICCT – VCC
8.0
12.0
16.0
Fc (MHz)
ICCH – VCC
ICCT (µA)
50
ICCH (µA)
10
TA = +25°C
TA = +25°C
9
40
8
Fc = 8 kHz
30
7
6
5
20
4
3
10
2
1
3.0
102
4.0
5.0
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
MB90520 Series
ICCH – TA
ICCT – TA
ICCH (µA)
10
ICCT (µA)
10
9
9
8
8
7
7
6
6
5
5
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
4
3
2
1
–20
+10
+40
+70
4
3
2
1
+100
–20
+10
+40
+70
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
+100
TA (°C)
TA (°C)
ICCLS – TA
ICCLS (µA)
20
18
16
VCC = 6.0 V
14
VCC = 5.5 V
12
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
10
8
6
4
2
–20
+10
+40
+70
+100
TA (°C)
103
MB90520 Series
■ ORDERING INFORMATION
Part number
104
Package
MB90523PFF
MB90522PFF
MB90F523PFF
120-pin Plastic LQFP
(FPT-120P-M05)
MB90523PFV
MB90522PFV
MB90F523PFV
120-pin Plastic QFP
(FPT-120P-M13)
Remarks
MB90520 Series
■ PACKAGE DIMENSIONS
120-pin Plastic LQFP
(FPT-120P-M05)
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
120
31
"A"
0~8°
LEAD No.
1
30
0.16±0.03
(.006±.001)
0.40(.016)
0.07(.003)
0.145±0.055
(.006±.002)
M
0.50±0.20
(.020±.008)
0.45/0.75
(.018/.030)
C
22.60±0.20(.890±.008)SQ
3.85(.152)MAX
(Mounting height)
20.00±0.10(.787±.004)SQ
90
0.25(.010)
Dimensions in mm (inches)
1998 FUJITSU LIMITED F120006S-3C-4
120-pin Plastic QFP
(FPT-120P-M13)
0.10±0.10
(.004±.004)
(Stand off)
0.05(.002)MIN
(STAND OFF)
61
91
60
14.50
(.571)
REF
21.60
(.850)
NOM
Details of "A" part
0.15(.006)
0.15(.006)
INDEX
0.15(.006)MAX
0.40(.016)MAX
"A"
120
LEAD No.
1
31
Details of "B" part
30
0.50(.0197)
0.20±0.10
(.008±.004)
0.08(.003)
M
0.125±0.05
(.005±.002)
0
10°
0.50±0.20(.020±.008)
0.10(.004)
C
1995 FUJITSU LIMITED F120013S-2C-3
"B"
Dimensions in mm (inches)
105
MB90520 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0012
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.