INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4020B MSI 14-stage binary counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4020B MSI 14-stage binary counter DESCRIPTION The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0, O3 to O13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the HEF4020B is: high speed (typ. 35 MHz at VDD = 15 V). Fig.1 Functional diagram. HEF4020BP(N): 16-lead DIL; plastic (SOT38-1) HEF4020BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4020BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING Fig.2 Pinning diagram. CP clock input (HIGH to LOW edge triggered) MR master reset input (active HIGH) O0, O3 to O13 parallel outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4020B MSI 14-stage binary counter Fig.3 Logic diagram. January 1995 3 Philips Semiconductors Product specification HEF4020B MSI 14-stage binary counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4 VDD V SYMBOL MIN. TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 105 210 ns 78 ns + (0,55 ns/pF) CL 45 90 ns 34 ns + (0,23 ns/pF) CL 30 65 ns 22 ns + (0,16 ns/pF) CL 105 210 ns 78 ns + (0,55 ns/pF) CL 50 95 ns 39 ns + (0,23 ns/pF) CL 35 70 ns 27 ns + (0,16 ns/pF) CL Propagation delays CP → Ο0 HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 On → On + 1 HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 MR → On HIGH to LOW Output transition times HIGH to LOW LOW to HIGH pulse width; HIGH Minimum MR pulse width; HIGH Recovery time for MR Maximum clock pulse frequency ns 53 ns + (0,55 ns/pF) CL 60 ns 19 ns + (0,23 ns/pF) CL 20 40 ns 12 ns + (0,16 ns/pF) CL 70 140 ns 43 ns + (0,55 ns/pF) CL 25 50 ns 14 ns + (0,23 ns/pF) CL 20 40 ns 12 ns + (0,16 ns/pF) CL 360 ns 153 ns + (0,55 ns/pF) CL 90 180 ns 79 ns + (0,23 ns/pF) CL 15 70 140 ns 62 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL tPHL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 10 tTHL tTLH 5 10 tWCPH 30 60 ns 9 ns + (0,42 ns/pF) CL 40 ns 6 ns + (0,28 ns/pF) CL 50 25 ns 25 15 ns 20 10 ns 5 130 65 ns 10 tWMRH 95 50 ns 15 90 45 ns 5 115 60 ns 10 tRMR 65 35 ns 15 55 25 ns 5 5 10 MHz 13 25 MHz 18 35 MHz 10 fmax 4 10 ns + (1,0 ns/pF) CL 20 15 15 January 1995 160 180 5 10 15 Minimum clock 80 30 Philips Semiconductors Product specification HEF4020B MSI 14-stage binary counter VDD V Dynamic power dissipation per package (P) 5 TYPICAL FORMULA FOR P (µW) 600 fi + ∑ (fo CL) × VDD 2 10 2 800 fi + ∑ (fo CL) × VDD 2 15 8 200 fi + ∑ (fo CL) × VDD 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) Fig.4 Waveforms showing propagation delays for MR to On and CP to O0, minimum MR and CP pulse widths. January 1995 5 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors 14-stage binary counter January 1995 6 Product specification HEF4020B MSI Fig.5 Timing diagram.