Actual Size 9mm Square DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 ±3-A HIGH-EFFICIENCY PWM POWER DRIVER Check for Samples: DRV593, DRV594 FEATURES 1 • 2 • • • • • • • • • DESCRIPTION Operation Reduces Output Filter Size and Cost by 50% Compared to DRV591 ±3-A Maximum Output Current Low Supply Voltage Operation: 2.8 V to 5.5 V High Efficiency Generates Less Heat Overcurrent and Thermal Protection Fault Indicators for Overcurrent, Thermal and Undervoltage Conditions Two Selectable Switching Frequencies Internal or External Clock Sync PWM Scheme Optimized for EMI 9×9 mm PowerPAD™ Quad Flatpack Package The DRV593 and DRV594 are high-efficiency, high-current power amplifiers ideal for driving a wide variety of thermoelectric cooler elements in systems powered from 2.8 V to 5.5 V. The operation of the device requires only one inductor and capacitor for the output filter, saving significant printed-circuit board area. Pulse-width modulation (PWM) operation and low output stage on-resistance significantly decrease power dissipation in the amplifier. The DRV593 and DRV594 are internally protected against thermal and current overloads. Logic-level fault indicators signal when the junction temperature has reached approximately 128°C to allow for system-level shutdown before the amplifier's internal thermal shutdown circuitry activates. The fault indicators also signal when an overcurrent event has occurred. If the overcurrent circuitry is tripped, the devices automatically reset (see application information section for more details). APPLICATIONS • • Thermoelectric Cooler (TEC) Driver Laser Diode Biasing The PWM switching frequency may be set to 500 kHz or 100 kHz depending on system requirements. To eliminate external components, the gain is fixed at 2.3 V/V for the DRV593. For the DRV594, the gain is fixed at 14.5 V/V. VDD PWM SHUTDOWN 10 µF H/C FAULT1 FAULT0 PWM PVDD PVDD PVDD FREQ INT/EXT PGND 1 µF H/C Shutdown Control PGND IN− H/C 1 kΩ PGND IN+ H/C 1 kΩ To TEC or Laser Diode Anode PGND DRV593 DRV594 AREF PVDD 1 µF PGND COSC PVDD 220 pF PGND ROSC PVDD DC Control Voltage 10 µH PWM AGND (Connect to PowerPAD) FAULT0 120 kΩ AVDD FAULT1 1 µF PWM 1 µF 10 µF To TEC or Laser Diode Cathode 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2010, Texas Instruments Incorporated DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. ORDERING INFORMATION (1) PowerPAD QUAD FLATPACK (VFP) TA DRV593VFP (2) –40°C to 85°C (1) (2) DRV594VFP (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., DRV593VFPR or DRV594VFPR). ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) DRV593, DRV594 AVDD, PVDD Supply voltage VI Input voltage IO (FAULT0, FAULT1) Output current –0.3 V to 5.5 V –0.3 V to VDD + 0.3 V 1 mA Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature range –40°C to 85°C TJ Operating junction temperature range –40°C to 150°C Tstg Storage temperature range –65°C to 165°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS AVDD, PVDD Supply voltage VIH High-level input voltage FREQ, INT/EXT, SHUTDOWN, COSC VIL Low-level input voltage FREQ, INT/EXT, SHUTDOWN, COSC TA Operating free-air temperature MIN MAX 2.8 5.5 2 –40 UNIT V V 0.8 V 85 °C PACKAGE DISSIPATION RATINGS (1) 2 PACKAGE qJA (1) (°C/W) qJC (°C/W) TA=25°C POWER RATING VFP 29.4 1.2 4.1 W This data was taken using 2 oz trace and copper pad that is soldered directly to a JEDEC standard 4-layer 3 in × 3 in PCB. Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX 14 UNIT |VOO| Output offset voltage (measured differentially) VI = VDD/2, IO = 0 A 100 mV |IIH| High-level input current VDD = 5.5V, VI = VDD 1 mA |IIL| Low-level input current VDD = 5.5V, VI = 0 V 1 mA Vn Integrated output noise voltage f = <1 Hz to 10 kHz VICM Common-mode voltage range Av Closed-loop voltage gain 40 VDD = 5 V 1.2 3.8 VDD = 3.3 V 1.2 2.1 DRV593 2.1 2.3 2.6 DRV594 13.7 14.5 15.3 Full power bandwidth VO rDS(on) 60 Voltage output (measured differentially) IO = ±1 A, rDS(on) = 65 mΩ, VDD = 5 V 4.87 IO = ±3 A, rDS(on) = 65 mΩ, VDD = 5 V 4.61 25 60 95 Low side 25 65 95 VDD = 3.3 V, IO = 4 A, TA = 25°C High side 25 80 140 Low side 25 90 140 3 Status flag output pins (FAULT0, FAULT1) Fault active (open drain output) Sinking 200 mA For 500 kHz operation 225 250 300 For 100 kHz operation 45 50 55 4 12 2.5 8 80 VDD = 5 V, No load or filter Quiescent current Iq(SD) Quiescent current in shutdown mode VDD = 5 V, SHUTDOWN = 0.8 V 0 40 Output resistance in shutdown SHUTDOWN = 0.8 V 1 2 ZI VDD = 3.3 V, No load or filter V/V mΩ mΩ A 0.1 Iq V/V V High side Maximum continuous current output V kHz VDD = 5 V, IO = 4 A, TA = 25°C Drain-source on-state resistance External clock frequency range mV V kHz mA mA kΩ Power-on threshold 1.7 2.8 Power-off threshold 1.6 2.6 V V Thermal trip point FAULT0 active 128 Thermal shutdown Power off 158 °C 100 kΩ Input impedance (IN+, IN-) Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 °C 3 DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com PIN ASSIGNMENTS FREQ INT/EXT PVDD PVDD PVDD PWM PWM PWM VFP PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 AVDD AGND ROSC COSC AREF IN+ IN− SHUTDOWN 1 24 2 23 22 3 4 PowerPAD 5 6 PWM PGND PGND PGND PGND PGND PGND H/C 21 20 19 18 7 17 8 FAULT1 FAULT0 PVDD PVDD PVDD H/C H/C H/C 9 10 11 12 13 14 15 16 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. AGND 2 AREF 5 O Connect 1 mF capacitor to ground for AREF voltage filtering AVDD 1 I Analog power supply COSC 4 I Connect capacitor to ground to set oscillation frequency (220 pF for 500 kHz, 1 nF for 100 kHz) when the internal oscillator is selected; connect clock signal when an external oscillator is used FAULT0 10 O Fault flag 0, low when active open drain output (see application information) FAULT1 9 O Fault flag 1, high when active open drain output (see application information) FREQ 32 I Selects 500 kHz switching frequency when a TTL logic low is applied to this terminal; selects 100 kHz switching frequency when a TTL logic high is applied IN– 7 I Negative differential input IN+ 6 I Positive differential input INT/EXT 31 I Selects the internal oscillator when a TTL logic high is applied to this terminal; selects the use of an external oscillator when a TTL logic low is applied to this terminal H/C 14, 15, 16, 17 O Direction control output for heat and cool modes (4 pins) PWM 24, 25, 26, 27 O PWM output for voltage magnitude (4 pins) PGND 18, 19, 20, 21, 22, 23 PVDD 11, 12, 13, 28, 29, 30 I High-current power supply (6 pins) ROSC 3 I Connect 120-kΩ resistor to AGND to set oscillation frequency (either 500 kHz or 100 kHz). Not needed if an external clock is used. SHUTDOWN 8 I Places the amplifier in shutdown mode when a TTL logic low is applied to this terminal; places the amplifier in normal operation when a TTL logic high is applied 4 Analog ground High-current ground (6 pins) Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 FUNCTIONAL BLOCK DIAGRAM AVDD AGND AVDD R IN− 2.3 x R (DRV593) 14.5 x R (DRV594) _ + PVDD + _ Gate Drive H/C _ + _ + + _ PGND PVDD IN+ R + _ 2.3 x R (DRV593) 14.5 x R (DRV594) PWM Gate Drive PGND SHUTDOWN INT/EXT FREQ TTL Input Buffer Biases and References Start-Up Protection Logic Ramp Generator COSC Thermal ROSC OC Detect VDDok FAULT0 AREF FAULT1 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Efficiency vs Load resistance 2, 3 vs Supply voltage 4 vs Free-air temperature 5 vs Free-air temperature 6 rDS(on) Drain-source on-state resistance Iq Supply current vs Supply voltage PSRR Power supply rejection ratio vs Frequency Closed loop response IO Maximum output current VIO Input offset voltage 7 8, 9 12, 13 vs Output voltage 14 vs Ambient temperature 15 Common-mode input voltage 16, 17 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 5 DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com TEST SETUP FOR GRAPHS The LC output filter used in Figure 2, Figure 3, Figure 8, and Figure 9 is shown below. L1 PWM C1 RL H/C L1 = 10 µH (part number: CDRH104R, manufacturer: Sumida) C1 = 10 µF (part number: ECJ-4YB1C106K, manufacturer: Panasonic) Figure 1. LC Output Filter EFFICIENCY vs LOAD RESISTANCE EFFICIENCY vs LOAD RESISTANCE 100 100 90 90 PO = 2 W 80 80 PO = 0.5 W PO = 1 W 70 PO = 0.5 W Efficiency − % Efficiency − % 70 60 50 40 30 PO = 0.25 W 60 50 40 30 20 20 VDD = 5 V fS = 500 kHz 10 VDD = 3.3 V fS = 500 kHz 10 0 0 1 2 3 4 5 6 7 8 RL − Load Resistance − Ω 9 10 1 2 Figure 2. 6 PO = 1 W 3 4 5 6 7 8 RL − Load Resistance − Ω 9 10 Figure 3. Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 DRAIN-SOURCE ON-STATE RESISTANCE vs SUPPLY VOLTAGE DRAIN-SOURCE ON-STATE RESISTANCE vs FREE-AIR TEMPERATURE 300 rDS(on) − Drain-Source On-State Resistance − mΩ IO = 1 A TA = 25°C 250 Total 200 150 Low Side 100 High Side 50 0 2.7 3.1 3.5 3.9 4.3 4.7 VDD − Supply Voltage − V 5.1 5.5 200 Total 150 Low Side 100 High Side 50 0 −40 −15 10 35 60 TA − Free-Air Temperature − °C Figure 5. DRAIN-SOURCE ON-STATE RESISTANCE vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 85 10 300 250 250 VDD = 5 V IO = 1 A VFP Package Figure 4. VDD = 3.3 V IO = 1 A VFP Package No Load 9 8 Iq − Supply Current − mA rDS(on) − Drain-Source On-State Resistance − mΩ rDS(on) − Drain-Source On-State Resistance − mΩ 300 Total 200 150 Low Side 100 High Side 7 6 5 4 3 2 50 1 0 −40 −15 10 35 60 85 0 2.7 3.1 TA − Free-Air Temperature − °C Figure 6. 3.5 3.9 4.3 4.7 5.1 5.5 VDD − Supply Voltage − V Figure 7. Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 7 DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com POWER SUPPLY REJECTION RATIO vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY −20 −40 −50 −60 −70 −80 10 100 1k 10k f − Frequency − Hz −30 −40 −50 −60 −70 −80 10 100k 100 1k 10k f − Frequency − Hz Figure 8. Figure 9. DRV593 CLOSED LOOP RESPONSE DRV594 CLOSED LOOP RESPONSE 4 Phase 3 10 16 0 14 −10 12 −40 Gain − V/V −30 2 10 0 −10 Phase Phase − ° Gain 100k Gain −20 Gain − V/V VDD = 3.3 V fS = 500 kHz RL = 1 Ω Vripple = 100 mVpp 10 −20 8 −30 6 −40 4 −50 Phase − ° −30 VDD = 5 V fS = 500 kHz RL = 1 Ω Vripple = 100 mVpp PSRR − Power Supply Rejection Ratio − dB PSRR − Power Supply Rejection Ratio − dB −20 −50 1 −60 VDD = 5 V No Load −70 0 10 100 1k 10k f − Frequency − Hz −80 100k 2 0 10 VDD = 5 V No Load 100 1k 10 k −70 100 k f − Frequency − Hz Figure 10. 8 −60 Figure 11. Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 DRV593 CLOSED LOOP RESPONSE DRV594 CLOSED LOOP RESPONSE 16 10 4 0 14 Phase −10 12 Gain − V/V −40 Phase − ° −30 2 −10 Phase −20 Gain 0 10 −20 8 −30 6 −40 4 −50 Phase − ° 3 Gain − V/V 10 Gain −50 1 −60 VDD = 3.3 V No Load 0 10 100 2 −70 −80 100k 1k 10k f − Frequency − Hz 0 10 −60 100 1k 10 k −70 100 k f − Frequency − Hz Figure 12. Figure 13. MAXIMUM OUTPUT CURRENT vs OUTPUT VOLTAGE MAXIMUM OUTPUT CURRENT vs AMBIENT TEMPERATURE 3.5 3.5 I O − Maximum Output Current − A 3 I O − Maximum Output Current − A VDD = 3.3 V No Load TJ = 100°C 2.5 TJ = 85°C 2 TJ = 125°C 1.5 1 VDD = 5 V TA = 25°C VFP Package 0.5 0 0 1 2 3 VO − Output Voltage − V 4 3 2.5 2 1.5 1 0.5 5 TJ ≤ 125°C VFP Package 0 −40 −30 −20 −10 0 Figure 14. 10 20 30 40 50 60 70 80 TA − Ambient Temperature − °C Figure 15. Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 9 DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 20 10 19 8 VIO − Input Offset Voltage − mV VIO − Input Offset Voltage − mV 9 VDD = 5 V No Load 7 6 5 4 3 2 18 17 16 15 14 13 12 11 1 0 1.2 VDD = 3.3 V No Load 1.6 2.0 2.4 2.8 3.2 VIC − Common-Mode Input Voltage − V 3.6 3.8 10 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VIC − Common-Mode Input Voltage − V Figure 16. 10 2.1 Figure 17. Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 APPLICATION INFORMATION PULSE-WIDTH MODULATION SCHEME FOR DRV593 AND DRV594 The pulse-width modulation scheme implemented in the DRV593 and DRV594 eliminates one-half of the full output filter previously required for PWM drivers. The DRV593 and DRV594 require only one inductor and capacitor for the output filter. The H/C outputs determine the direction of the current and do not switch back and forth. The PWM outputs switch to produce a voltage across the load that is proportional to the input control voltage. COOLING MODE Figure 18 shows the DRV593 and DRV594 in cooling mode. The H/C outputs (pins 14-17) are at ground and the PWM outputs (pins 24-27) create a voltage across the load that is proportional to the input voltage. The differential voltage across the load is determined using Equation 1 and the duty cycle using Equation 2. The differential voltage is defined as the voltage measured after the filter on the PWM output relative to the H/C output. V Load + D V DD (1) D+ ǒ Ǔ A v VIN)–V IN– V DD (2) where D duty cycle of the PWM signal Av Gain of DRV593/594 (DRV593: 2.3 V/V, DRV594: 14.5 V/V) VIN+ Positive input terminal of the DRV593/594 VIN– Negative input terminal of the DRV593/594 VDD Power supply voltage For example, a 50% duty cycle, shown in Figure 18, results in 2.5 V across the load for VDD = 5 V. VDD PWM 0 VDD H/C 0 VDD VDD/2 Load Voltage 0 Figure 18. Cooling Mode Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 11 DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com HEATING MODE Figure 19 shows the DRV593 and DRV594 in heating mode. The H/C output is at VDD and the PWM output is proportional to the voltage across the load. The differential voltage across the load is determined using Equation 3. The variables are the same as used previously for Equation 1 and Equation 2. V Load + –(1–D) V DD (3) For example, a 50% duty cycle, shown in Figure 19, results in –2.5 V across the load for VDD = 5 V. The differential voltage across the load is defined as the voltage measured after the filter on the PWM output relative to the H/C output. VDD PWM 0 VDD H/C 0 Load Voltage 0 −VDD/2 −VDD Figure 19. Heating Mode HEAT/COOL TRANSITION As the device transitions from cooling to heating, the duty cycle of the PWM outputs decrease to a small value and the H/C outputs remains at ground. When the device transitions to heating mode, the H/C outputs change from zero volts to VDD and the PWM outputs change to a high duty cycle. The direction of the current flow is reversed, but a low voltage is maintained across the load. The duty cycle decreases as the part is put further into heating mode to drive more current through the load. Figure 20 illustrates the transition from cooling to heating. ZERO-CROSSING REGION When the differential output voltage is near zero, the control logic in the DRV593 and DRV594 causes the outputs to change between heating and cooling modes. There are two possible states for the PWM and H/C outputs to obtain zero volts differentially: both outputs can be at VDD or both outputs can be at ground. Therefore, random noise causes the outputs to change between the two states when the two input voltages are equal. The outputs switch from zero to VDD, although not at a fixed frequency rate. Some of the pulses may be wider than others, but the two outputs (PWM and H/C) track each other to provide zero differential voltage. These uneven pulse widths can increase the switching noise during the zero-crossing condition. 12 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 To avoid this phenomenon, hysteresis should be implemented in the control loop to prevent the device from operating within this region. Although planning for operation during the zero-crossing is important, the normal operating points for the DRV593 and DRV594 are outside of this region. For laser temperature/wavelength regulation, the zero volts output condition is only a concern when the laser temperature or wavelength, relative to the ambient temperature, requires no heating or cooling from the TEC element. VDD IN + IN − 0 VDD PWM 0 VDD H/C 0 Figure 20. Transition From Cooling to Heating VDD PWM PVDD PWM PGND IN+ PGND IN− PGND SHUTDOWN H/C H/C H/C FAULT1 FAULT0 10 µF H/C PVDD Shutdown Control To TEC or Laser Diode Anode PGND DRV593 DRV594 FAULT0 1 µF PVDD PGND COSC AREF 1 kΩ 1 kΩ PGND ROSC PVDD 220 pF AGND (Connect to PowerPAD) FAULT1 DC Control Voltage 10 µH PWM PVDD 120 kΩ PVDD FREQ AVDD INT/EXT 1 µF PWM 1 µF 10 µF 1 µF To TEC or Laser Diode Cathode Figure 21. Typical Application Circuit Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 13 DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com OUTPUT FILTER CONSIDERATIONS TEC element manufacturers provide electrical specifications for maximum dc current and maximum output voltage for each particular element. The maximum ripple current, however, is typically only recommended to be less than 10% with no reference to the frequency components of the current. The maximum temperature differential across the element, which decreases as ripple current increases, may be calculated with the following equation: 1 DT + DT max ǒ1 ) N2Ǔ (4) where ΔT = actual temperature differential Δ Tmax = maximum temperature differential (specified by manufacturer) N = ratio of ripple current to dc current According to this relationship, a 10% ripple current reduces the maximum temperature differential by 1%. An LC network may be used to filter the current flowing to the TEC to reduce the amount of ripple and, more importantly, protect the rest of the system from any electromagnetic interference (EMI). FILTER COMPONENT SELECTION The LC filter, which may be designed from two different perspectives, both described below, helps estimate the overall performance of the system. The filter should be designed for the worst-case conditions during operation, which is typically when the differential output is at 50% duty cycle. The following section serves as a starting point for the design, and any calculations should be confirmed with a prototype circuit in the lab. Any filter should always be placed as close as possible to the DRV593 and DRV594 to reduce EMI. L PWM C TEC R H/C Figure 22. Output Filter LC FILTER IN THE FREQUENCY DOMAIN The transfer function for a second-order low-pass filter (Figure 22) is shown in Equation 5: 1 H (jw) + LP 2 jw – ww ) 1 w )1 Q 0 0 ǒ Ǔ w0 + 1 ǸLC Q + quality factor w + DRV593 or DRV594 switching frequency 14 Submit Documentation Feedback (5) Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 For the DRV593 and DRV594, the differential output switching frequency is typically selected to be 500 kHz. The resonant frequency for the filter is typically chosen to be at least one order of magnitude lower than the switching frequency. Equation 5 may then be simplified to give the following magnitude Equation 6. These equations assume the use of the filter in Figure 22. f H LP dB + –40 log s fo 1 fo + 2p ǸLC f s + 500 kHz (DRV593 or DRV594 switching frequency) (6) Ť ǒǓ Ť If L=10 mH and C=10 mF, the cutoff frequency is 15.9 kHz, which corresponds to –60 dB of attenuation at the 500 kHz switching frequency. For VDD = 5 V, the amount of ripple voltage at the TEC element is approximately 5 mV. The average TEC element has a resistance of 1.5 Ω, so the ripple current through the TEC is approximately 3.4 mA. At the 3-A maximum output current of the DRV593 and DRV594, this 5.4 mA corresponds to 0.11% ripple current, causing less than 0.0001% reduction of the maximum temperature differential of the TEC element (see Equation 4). LC FILTER IN THE TIME DOMAIN The ripple current of an inductor may be calculated using Equation 7: DI L + ǒVO–V TECǓDTs L D + duty cycle (0.5 worst case) T s + 1ńfs + 1ń500 kHz (7) For VO = 5 V, VTEC = 2.5 V, and L = 10 mH, the inductor ripple current is 250 mA. To calculate how much of that ripple current flows through the TEC element, however, the properties of the filter capacitor must be considered. For relatively small capacitors (less than 22 mF) with very low equivalent series resistance (ESR, less than 10 mΩ, such as ceramic capacitors, the following Equation 8 may be used to estimate the ripple voltage on the capacitor due to the change in charge: f 2 DV + p ǒ1–DǓ o C 2 fs ǒǓ 2 V TEC D + duty cycle f s + 500 kHz fo + 1 2p ǸLC (8) For L = 10 mH and C = 10 mF, the cutoff frequency, fo, is 15.9 kHz. For worst case duty cycle of 0.5 and VTEC=2.5 V, the ripple voltage on the capacitors is 6.2 mV. The ripple current may be calculated by dividing the ripple voltage by the TEC resistance of 1.5Ω, resulting in a ripple current through the TEC element of 4.1 mA. Note that this is similar to the value calculated using the frequency domain approach. For larger capacitors (greater than 22 mF) with relatively high ESR (greater than 100 mΩ), such as electrolytic capacitors, the ESR dominates over the charging/discharging of the capacitor. The following simple Equation 9 may be used to estimate the ripple voltage: DV + DIL R C ESR DI + inductor ripple current L R + filter capacitor ESR ESR (9) Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 15 DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 www.ti.com For a 100 mF electrolytic capacitor, an ESR of 0.1 Ω is common. If the 10 µH inductor is used, delivering 250 mA of ripple current to the capacitor (as calculated above), then the ripple voltage is 25 mV. This is over ten times that of the 10 mF ceramic capacitor, as ceramic capacitors typically have negligible ESR. SWITCHING FREQUENCY CONFIGURATION: OSCILLATOR COMPONENTS ROSC and COSC AND FREQ OPERATION The onboard ramp generator requires an external resistor and capacitor to set the oscillation frequency. The frequency may be either 500 kHz or 100 kHz by selecting the proper capacitor value and by holding the FREQ pin either low (500 kHz) or high (100 kHz). Table 2 shows the values required and FREQ pin configuration for each switching frequency. Table 2. Frequency Configuration Options SWITCHING FREQUENCY ROSC COSC FREQ 500 kHz 120 kΩ 220 pF LOW (GND) 100 kHz 120 kΩ 1 nF HIGH (VDD) For proper operation, the resistor ROSC should have 1% tolerance while capacitor COSC should be a ceramic type with 10% tolerance. Both components should be grounded to AGND, which should be connected to PGND at a single point, typically where power and ground are physically connected to the printed-circuit board. EXTERNAL CLOCKING OPERATION To synchronize the switching to an external clock signal, pull the INT/EXT terminal low, and drive the clock signal into the COSC terminal. This clock signal must be from 10% to 90% duty cycle and meet the voltage requirements specified in the electrical specifications table. Since the DRV593 and DRV594 include an internal frequency doubler, the external clock signal must be approximately 250 kHz. Deviations from the 250 kHz clock frequency are allowed and are specified in the electrical characteristic table. The resistor connected from ROSC to ground may be omitted from the circuit in this mode of operation—the source is disconnected internally. INPUT CONFIGURATION: DIFFERENTIAL AND SINGLE-ENDED If a differential input is used, it should be biased around the midrail of the DRV593 or DRV594 and must not exceed the common-mode input range of the input stage (see the operating characteristics at the beginning of the data sheet). The most common configuration employs a single-ended input. The unused input should be tied to VDD/2, which may be simply accomplished with a resistive voltage divider. For the best performance, the resistor values chosen should be at least 100 times lower than the input resistance of the DRV593 or DRV594. This prevents the bias voltage at the unused input from shifting when the signal input is applied. A small ceramic capacitor should also be placed from the input to ground to filter noise and keep the voltage stable. An op amp configured as a buffer may also be used to set the voltage at the unused input. FIXED INTERNAL GAIN The differential output voltage may be calculated using Equation 10: V O +V –V OUT) OUT– ǒ Ǔ + A v V IN)–V IN– (10) AV is the voltage gain, which is fixed internally at 2.3 V/V for DRV593 and 14.5 V/V for DRV594. The maximum and minimum ratings are provided in the electrical specification table at the beginning of the data sheet. POWER SUPPLY DECOUPLING To reduce the effects of high-frequency transients or spikes, a small ceramic capacitor, typically 0.1 mF to 1 mF, should be placed as close to each set of PVDD pins of the DRV593 and DRV594 as possible. For bulk decoupling, a 10 mF to 100 mF tantalum or aluminum electrolytic capacitor should be placed relatively close to the DRV593 and DRV594. 16 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 AREF CAPACITOR The AREF terminal is the output of an internal mid-rail voltage regulator used for the onboard oscillator and ramp generator. The regulator may not be used to provide power to any additional circuitry. A 1 mF ceramic capacitor must be connected from AREF to AGND for stability (see oscillator components above for AGND connection information). SHUTDOWN OPERATION The DRV593 and DRV594 include a shutdown mode that disables the outputs and places the device in a low supply current state. The SHUTDOWN pin may be controlled with a TTL logic signal. When SHUTDOWN is held high, the device operates normally. When SHUTDOWN is held low, the device is placed in shutdown. The SHUTDOWN pin must not be left floating. If the shutdown feature is unused, the pin may be connected to VDD. FAULT REPORTING The DRV593 and DRV594 include circuitry to sense three faults: • Overcurrent • Undervoltage • Overtemperature These three fault conditions are decoded via the FAULT1 and FAULT0 terminals. Internally, these are open-drain outputs, so an external pullup resistor of 5 kΩ or greater is required. Table 3. Fault Indicators FAULT1 FAULT0 0 0 Overcurrent 1 0 Undervoltage 0 1 Overtemperature 1 1 Normal operation The overcurrent fault is reported when the output current exceeds four amps. As soon as the condition is sensed, the overcurrent fault is set and the outputs go into a high-impedance state for approximately 3 ms to 5 ms (500 kHz operation). After 3 ms to 5 ms, the outputs are re-enabled. If the overcurrent condition has ended, the fault is cleared and the device resumes normal operation. If the overcurrent condition still exists, the above sequence repeats. The undervoltage fault is reported when the operating voltage is reduced below 2.8 V. This fault is not latched, so as soon as the power supply recovers, the fault is cleared and normal operation resumes. During the undervoltage condition, the outputs go into a high-impedance state to prevent overdissipation due to increased rDS(on). The overtemperature fault is reported when the junction temperature exceeds 128°C. The device continues operating normally until the junction temperature reaches 158°C, at which point the IC is disabled to prevent permanent damage from occurring. The system's controller must reduce the power demanded from the DRV593 or DRV594 once the overtemperature flag is set, or else the device switches off when it reaches 158°C. This fault is not latched; once the junction temperature drops below 128°C, the fault is cleared, and normal operation resumes. POWER DISSIPATION AND MAXIMUM AMBIENT TEMPERATURE Though the DRV593 and DRV594 are much more efficient than traditional linear solutions, the power drop across the on-resistance of the output transistors does generate some heat in the package, which may be calculated as shown in Equation 11: P DISS ǒ OUTǓ + I 2 r DS(on), total (11) For example, at the maximum output current of 3 A through a total on-resistance of 130 mΩ (at TJ = 25°C), the power dissipated in the package is 1.17 W. Calculate the maximum ambient temperature using Equation 12: Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 17 DRV593 DRV594 SLOS401C – OCTOBER 2002 – REVISED JULY 2010 ǒ T A + TJ * θ JA P DISS www.ti.com Ǔ (12) PRINTED-CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS Since the DRV593 and DRV594 are high-current switching devices, a few guidelines for the layout of the printed-circuit board (PCB) must be considered: 1. Grounding. Analog ground (AGND) and power ground (PGND) must be kept separated, ideally back to where the power supply physically connects to the PCB, minimally back to the bulk decoupling capacitor (10 µF ceramic minimum). Furthermore, the PowerPAD ground connection should be made to AGND, not PGND. Ground planes are not recommended for AGND or PGND, traces should be used to route the currents. Wide traces (100 mils) should be used for PGND while narrow traces (15 mils) should be used for AGND. 2. Power supply decoupling. A small 0.1 mF to 1 mF ceramic capacitor should be placed as close to each set of PVDD pins as possible, connecting from PVDD to PGND. A 0.1 mF to 1 mF ceramic capacitor should also be placed close to the AVDD pin, connecting from AVDD to AGND. A bulk decoupling capacitor of at least 10 mF, preferably ceramic, should be placed close to the DRV593 or DRV594, from PVDD to PGND. If power supply lines are long, additional decoupling may be required. 3. Power and output traces. The power and output traces should be sized to handle the desired maximum output current. The output traces should be kept as short as possible to reduce EMI, i.e., the output filter should be placed as close to the DRV593 or DRV594 outputs as possible. 4. PowerPAD. The DRV593 and DRV594 in the Quad Flatpack package use TI's PowerPAD technology to enhance the thermal performance. The PowerPAD is physically connected to the substrate of the DRV593 and DRV594 silicon, which is connected to AGND. The PowerPAD ground connection should therefore be kept separate from PGND as described above. The pad underneath the AGND pin may be connected underneath the device to the PowerPAD ground connection for ease of routing. For additional information on PowerPAD PCB layout, refer to the PowerPAD Thermally Enhanced Package application note, (SLMA002). 5. Thermal performance. For proper thermal performance, the PowerPAD must be soldered down to a thermal land, as described in the PowerPAD Thermally Enhanced Package application note, (SLMA002). In addition, at high current levels (greater than 2 A) or high ambient temperatures (greater than 25°C), an internal plane may be used for heat sinking. The vias under the PowerPAD should make a solid connection, and the plane should not be tied to ground except through the PowerPAD connection, as described above. 18 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 DRV593 DRV594 www.ti.com SLOS401C – OCTOBER 2002 – REVISED JULY 2010 Changes from Revision A (October 2002) to Revision B Page • Changed Thermal trip point from 115°C to 128°C ................................................................................................................ 3 • Changed Thermal shtudown point from 128°C to 158°C ..................................................................................................... 3 Changes from Revision B (November 2008) to Revision C • Page Changed figure cross reference from "Figure 17 and Figure 18" to "Figure 22" in the "LC FILTER......." section. ............ 14 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): DRV593 DRV594 19 PACKAGE OPTION ADDENDUM www.ti.com 30-May-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty 250 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TBD Call TI Call TI -40 to 85 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TBD Call TI Call TI -40 to 85 Device Marking (4/5) DRV593VFP ACTIVE HLQFP VFP 32 DRV593VFPG4 ACTIVE HLQFP VFP 32 DRV593VFPR ACTIVE HLQFP VFP 32 DRV593VFPRG4 ACTIVE HLQFP VFP 32 DRV594VFP ACTIVE HLQFP VFP 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV594 DRV594VFPR ACTIVE HLQFP VFP 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV594 1000 DRV593 DRV593 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 30-May-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DRV593VFPR HLQFP VFP 32 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 DRV594VFPR HLQFP VFP 32 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV593VFPR HLQFP VFP 32 1000 367.0 367.0 38.0 DRV594VFPR HLQFP VFP 32 1000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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