LMS485E Low Power RS-485 / RS-422 Differential Bus Transceiver General Description Features The LMS485E is a low power differential bus/line transceiver designed for high speed bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines. It meets ANSI Standards TIA/EIA RS422-B, TIA/EIA RS485-A and ITU recommendation and V.11 and X.27. The driver outputs and receiver inputs have ± 15kV ESD protection. The LMS485E combines a TRISTATE™ differential line driver and differential input receiver, both of which operate from a single 5.0V power supply. The driver and receiver have an active high and active low, respectively, that can be externally connected to function as a direction control. The driver outputs and receiver inputs are internally connected to form a differential input/output (I/O) bus port that is designed to offer minimum loading to bus whenever the driver is disabled or when VCC = 0V. These ports feature wide positive and negative common mode voltage ranges, making the device suitable for multipoint applications in noisy environments. The LMS485E is available in 8-Pin SOIC and 8-pin DIP packages. It is a drop-in replacement to Maxim’s MAX485E. n n n n n n n n n n n n Meet ANSI standard RS-485 and RS-422 Data rate 2.5 Mbps Single supply voltage operation, 5V Wide input and output voltage range Thermal shutdown protection Short circuit protection Low quiescent current 800µA (max) Allows up to 32 transceivers on the bus Open circuit fail-safe for receiver Extended operating temperature range −40˚C to 85˚C Drop-in replacement to MAX485E Available in 8-pin SOIC and 8-pin DIP packages Applications n n n n n n n n Low power RS-485 systems Network hubs, bridges, and routers Point of sales equipment (ATM, barcode scanners,…) Local area networks (LAN) Integrated service digital network (ISDN) Industrial programmable logic controllers High speed parallel and serial applications Multipoint applications with noisy environment Typical Application 20086601 A typical multipoint application is shown in the above figure. Terminating resistor, RT are typically required but only located at the two ends of the cable. Pull-up and pull-down resistors maybe required at the end of the bus to provide fail-safe biasing. The biasing resistors provide a bias to the cable when all drivers are in TRI-STATE, See National Application Note, AN-847 for further information. © 2003 National Semiconductor Corporation DS200866 www.national.com LMS485E Low Power RS-485 / RS-422 Differential Bus Transceiver November 2003 LMS485E Connection Diagram 8-Pin SOIC / DIP 20086602 Top View Truth Table DRIVER SECTION RE* DE DI A X H H H L X H L L H X L X Z Z B RECEIVER SECTION RE* DE A-B RO L L ≥ +0.2V H L L ≤ −0.2V L H X X Z L L OPEN * H Note: * = Non Terminated, Open Input only X = Irrelevant Z = TRI-STATE H = High level L = Low level www.national.com 2 Pin # I/O Name Function 1 O RO Receiver Output: If A > B by 200 mV, RO will be high; If A < B by 200 mV, RO will be low. RO will be high also if the inputs (A and B) are open (non-terminated). 2 I RE* Receiver Output Enable: RO is enabled when RE* is low; RO is in TRI-STATEwhen RE* is high 3 I DE Driver Output Enable: The driver outputs (A and B) are enabled when DE is high; they are in TRI-STATETRI-STATE ® when DE is low. Pins A and B also function as the receiver input pins (see below) 4 I DI Driver Input: A low on DI forces A low and B high while a high on DI forces A high and B low when the driver is enabled 5 NA GND Ground 6 I/O A Non-inverting Driver Output and Receiver Input pin. Driver output levels conform to RS-485 signaling levels 7 I/O B Inverting Driver Output and Receiver Input pin. Driver Output levels conform to RS-485 signaling levels 8 NA VCC Power Supply: 4.75V ≤ VCC ≤ 5.25V Ordering Information Package Part Number LMS485ECM 8-Pin SOIC LMS485ECMX LMS485EIM LMS485EIMX 8-Pin DIP Package Marking LMS485ECM LMS485EIM Transport Media 2.5k Units Tape and Reel 95 Units/Rail M08A 2.5k Units Tape and Reel LMS485ECNA LMS485ECNA 40 Units/Rail LMS485EINA LMS485EINA 40 Units/Rail 3 NSC Drawing 95 Units/Rail N08E www.national.com LMS485E Pin Descriptions LMS485E Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Rating (Human Body Model)(Note 4) Supply Voltage, VCC (Note 2) ESD Rating (Machine Model) Input Voltage, VIN (DI, DE, or RE) 15kV Other Pins 6V −0.3V to VCC + 0.3V Voltage Range at Bus Terminals (AB) Receiver Output Bus Pins 2kV All Pins 200V −7V to 12V −0.3V to VCC + 0.3V Operating Ratings Package Thermal Impedance, θJA SOIC Min Nom Max 125˚ C/W DIP Supply Voltage, VCC 92˚ C/W Junction Temperature (Note 3) 150˚C Operating Free-Air Temperature Range, TA Commercial 0˚C to 70˚C Industrial −40˚C to 85˚C Storage Temperature Range −65˚C to 150˚C Soldering Information Infrared or Convection (20 sec.) 235˚C Lead Temperature Range 4.75 Voltage at any Bus Terminal (Separately or Common Mode) −7 High-Level Input Voltage, VIH (Note 5) 2 5.0 5.25 V 12 V V Low-Level Input Voltage, VIL (Note 5) 0.8 V Differential Input Voltage, VID (Note 6) ± 12 V +260˚C Electrical Characteristics Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 5.25 V Driver Section |VOD1| Differential Output Voltage R = ∞ (Figure 1) |VOD2| Differential Output Voltage R = 50Ω (Figure 1) , RS-422 2.0 R = 27Ω (Figure 1) , RS-485 1.5 V 5.0 ∆VOD Change in Magnitude of Driver Differential Output Voltage for Complementary Output States R = 27Ω or 50Ω (Figure 1) , (Note 7) 0.2 VOC Common Mode Output Voltage R = 27Ω or 50Ω (Figure 1) 3.0 ∆VOC Change in Magnitude of R = 27Ω or 50Ω (Figure 1), (Note 7) Driver Common-Mode Output Voltage for Complementary Output States VIH CMOS Input Logic Threshold High DE, DI, RE VIL CMOS Input Logic Threshold Low DE, DI, RE 0.8 IIN1 Logic Input Current DE, DI, RE ±2 µA 0.25 mA 0.2 2.0 V V V V V Receiver Section IIN2 Input Current (A, B) VTH Differential Input Threshold Voltage −7V ≤ VCM ≤ + 12V ∆VTH Input Hysteresis (VTH+− VTH−) VCM = 0 VOH CMOS High-level Output Voltage IOH = 4 mA, VID = −200 mV DE = 0V, VCC = 0V or 5.25V VIN = 12V VIN = − 7V www.national.com −0.2 −0.2 +0.2 95 4 3.5 V mV V (Continued) Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Max Units VOL Symbol CMOS Low-level Output Voltage Parameter IOL = −4 mA, VID = 200 mV Conditions Min Typ 0.4 V IOZR Tristate Output Leakage Current 0.4V ≤ VO ≤ + 2.4V ±1 µA RIN Input Resistance − 7V ≤VCM ≤ +12V 12 kΩ Power Supply Current ICC Supply Current DE = VCC, RE = GND or VCC 400 800 DE = 0V, RE = GND or VCC 360 560 µA IOSD1 Driver Short-circuit Output Current VO = high, −7V ≤ VCM ≤ +12V 250 mA IOSD2 Driver Short-circuit Output Current VO = low, − 7V ≤VCM ≤ +12V 250 mA IOSR Receiver Short-circuit Output Current 0 V ≤ VO ≤ VCC 95 mA 40 80 ns 5 10 ns 10 40 ns Switching Characteristics Driver TPLH, TPHL Propagation Delay Input to Output RL = 54Ω, CL = 100 pF TSKEW Driver Output Skew RL = 54Ω, CL = 100 pF TR, TF Driver Rise and Fall Time RL = 54Ω, CL = 100 pF TZH, TZL Driver Enable to Ouput Valid Time CL = 100 pF 25 70 ns THZ, TLZ Driver Output Disable Time CL = 15 pF 35 70 ns TPLH, TPHL Propagation Delay Input to Output RL = 54Ω, CL = 100 pF 90 200 ns TSKEW Receiver Output Skew RL = 54Ω, CL = 100 pF 5 TZH, TZL Receiver Enable Time CL = 15 pF 20 50 ns THZ, TLZ Receiver Disable Time CL = 15 pF 20 50 ns FMAX Maximum Data Rate 10 3 Receiver 20 2.5 ns Mbps Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. Note 2: All voltage values, except differential I/O bus voltage, are with respect to the network ground terminal. Note 3: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature, TA, is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board. Note 4: ESD rating based upon human body model, 100 pF discharged through 1.5 kΩ. Note 5: Voltage limits apply to DI, DE, RE pins. Note 6: Differential input/output bus voltage is measured at the non-inverting terminal A with respect to the inverting terminal B. Note 7: |∆VOD| and |∆VOC| are changes in magnitude of VOD and VOC, respectively when the input changes from high to low levels. Note 8: Peak current 5 www.national.com LMS485E Electrical Characteristics LMS485E Typical Performance Characteristics Output Current vs. Receiver Output Low Voltage Output Current vs. Receiver Output High Voltage 20086614 20086613 Receiver Output High Voltage vs. Temperature Receiver Output Low-Voltage vs. Temperature 20086616 20086615 Driver Output Current vs. Differential Output Voltage Driver Differential Output Voltage vs. Temperature 20086618 20086617 www.national.com 6 (Continued) Output Current vs. Driver Output Low Voltage Output Current vs. Driver Output High Voltage 20086619 20086620 Supply Current vs. Temperature 20086621 7 www.national.com LMS485E Typical Performance Characteristics LMS485E Parameter Measuring Information 20086603 FIGURE 1. Test Circuit for VOD and VOC 20086604 FIGURE 2. Test Circuit for VOD3 20086605 FIGURE 3. Test Circuit for Driver Propagation Delay 20086606 FIGURE 4. Test Circuit for Driver Enable / Disable www.national.com 8 LMS485E Parameter Measuring Information (Continued) 20086607 FIGURE 5. Test Circuit for Receiver Propagation Delay 20086608 FIGURE 6. Test Circuit for Receiver Enable / Disable 9 www.national.com LMS485E Switching Characteristics 20086611 20086609 FIGURE 9. Receiver Propagation Delay FIGURE 7. Driver Propagation Delay, Rise / Fall Time 20086612 20086610 FIGURE 10. Receiver Enable / Disable Time FIGURE 8. Driver Enable / Disable Time www.national.com 10 POWER LINE NOISE FILTERING A factor to consider in designing power and ground is noise filtering. A noise filtering circuit is designed to prevent noise generated by the integrated circuit (IC) as well as noise entering the IC from other devices. A common filtering method is to place by-pass capacitors (Cbp) between the power and ground lines. Placing a by-pass capacitor (Cbp) with the correct value at the proper location solves many power supply noise problems. Choosing the correct capacitor value is based upon the desired noise filtering range. Since capacitors are not 20086622 FIGURE 11. Placement of by-pass Capacitors, Cbp 11 www.national.com LMS485E ideal, they may act more like inductors or resistors over a specific frequency range. Thus, many times two by-pass capacitors may be used to filter a wider bandwidth of noise. It is highly recommended to place a larger capacitor, such as 10µF, between the power supply pin and ground to filter out low frequencies and a 0.1µF to filter out high frequencies. By-pass capacitors must be mounted as close as possible to the IC to be effective. Longs leads produce higher impedance at higher frequencies due to stray inductance. Thus, this will reduce the by-pass capacitor’s effectiveness. Surface mounted chip capacitors are the best solution because they have lower inductance. Application Information LMS485E Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A 8-Pin DIP NS Package Number N08E www.national.com 12 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. 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