AD ADIS16201CCCZ Programmable dual-axi Datasheet

Programmable Dual-Axis
Inclinometer/Accelerometer
ADIS16201
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AUX
ADC
AUX
DAC VREF
ADIS16201
TEMPERATURE
SENSOR
DUAL-AXIS
ACCELEROMETER
SIGNAL
CONDITIONING
AND
CONVERSION
CALIBRATION
AND
DIGITAL
PROCESSING
CS
SCLK
SPI
PORT
DIN
DIGITAL
CONTROL
SELF-TEST
DOUT
VDD
POWER
MANAGEMENT
ALARMS
AUXILIARY
I/O
COM
RST
DIO0 DIO1
05462-001
Dual-axis inclinometer/accelerometer measurements
12-, 14-bit digital inclination/acceleration sensor outputs
±1.7 g accelerometer measurement range
±90° inclinometer measurement range, linear output
12-bit digital temperature sensor output
Digitally controlled sensitivity and bias calibration
Digitally controlled sample rate
Digitally controlled frequency response
Dual alarm settings with rate/threshold limits
Auxiliary digital I/O
Digitally activated self test
Digitally activated low power mode
SPI®-compatible serial interface
Auxiliary 12-bit ADC input and DAC output
Single-supply operation: 3.0 V to +3.6 V
3500 g powered shock survivability
Figure 1.
APPLICATIONS
Platform control, stabilization, and leveling
Tilt sensing, inclinometers
Motion/position measurement
Monitor/alarm devices (security, medical, safety)
GENERAL DESCRIPTION
The ADIS16201 is a complete, dual-axis acceleration and
inclination angle measurement system available in a single
compact package enabled by the Analog Devices iSensor™
integration. By enhancing the Analog Devices iMEMS® sensor
technology with an embedded signal processing solution, the
ADIS16201 provides factory calibrated and tunable digital
sensor data in a convenient format that can be accessed using a
serial peripheral interface (SPI). The SPI interface provides
access to measurements for dual-axis linear acceleration, dualaxis linear inclination angle, temperature, power supply, and
one auxiliary analog input. Easy access to calibrated digital
sensor data provides developers with a system-ready device,
reducing development time, cost, and program risk.
Unique characteristics of the end system are accommodated
easily through several built-in features, such as a single
command in-system offset calibration, along with convenient
sample rate and bandwidth control.
Rev. C
The ADIS16201 offers the following embedded features, which
eliminate the need for external circuitry and provide a simplified
system interface:
•
Configurable alarm function
•
Auxiliary 12-bit ADC
•
Auxiliary 12-bit DAC
•
Configurable digital I/O port
•
Digital self-test function
The ADIS16201 offers two power management features for
managing system-level power dissipation: low power mode and
a configurable shutdown feature.
The ADIS16201 is available in a 9.2 mm × 9.2 mm × 3.9 mm
laminate-based land grid array (LGA) package with a
temperature range of −40°C to +125°C.
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved.
Technical Support
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ADIS16201
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Calibration Register Definitions .............................................. 19
Applications ....................................................................................... 1
Alarms .......................................................................................... 21
Functional Block Diagram .............................................................. 1
Sample Period Control .............................................................. 23
General Description ......................................................................... 1
Filtering Control ......................................................................... 24
Revision History ............................................................................... 2
Power-Down Control ................................................................ 24
Specifications..................................................................................... 3
Status Feedback........................................................................... 25
Timing Specifications .................................................................. 5
Command Control ..................................................................... 25
Timing Diagrams.......................................................................... 5
Miscellaneous Control Register................................................ 26
Absolute Maximum Ratings ............................................................ 6
Peripherals ....................................................................................... 27
ESD Caution .................................................................................. 6
Auxiliary ADC Function ........................................................... 27
Pin Configuration and Function Descriptions ............................. 7
Auxiliary DAC Function ........................................................... 27
Typical Performance Characteristics ............................................. 8
General Purpose I/O Control ................................................... 28
Theory of Operation ...................................................................... 13
Applications..................................................................................... 29
Accelerometer Operation .......................................................... 13
Serial Peripheral Interface (SPI) ............................................... 29
Inclinometer Operation ............................................................. 13
Hardware Considerations ......................................................... 29
Temperature Sensor ................................................................... 14
Grounding and Board Layout Recomendations .................... 29
Basic Operation............................................................................... 15
Bandgap Reference ..................................................................... 30
Data Output Register Access..................................................... 15
Power-On Reset Operation ....................................................... 30
Programming and Control ............................................................ 17
Second-Level Assembly ............................................................. 30
Control Register Overview........................................................ 17
Example Pad Layout................................................................... 30
Control Register Access ............................................................. 17
Outline Dimensions ....................................................................... 31
Control Register Details................................................................. 19
Ordering Guide .......................................................................... 31
Calibration ................................................................................... 19
REVISION HISTORY
8/13—Rev. B to Rev. C
Changes to Endnote 5 and Added Endnote 6; Table 1 ................ 4
Changed Digital Input/Output Voltage to COM Parameter from
−0.3 V to +5.5 V to −0.3 V to +5.3 V ............................................. 6
Changes to SMPL_PRD Register Definition Section, Table 24,
and AVG_CNT Register Definition Section ............................... 24
Changes to Table 31 ........................................................................ 28
5/06—Rev. 0 to Rev. A
Changes to Figure 3 ...........................................................................5
Changes to Figure 35...................................................................... 18
Changes to Status Feedback Section ............................................ 25
3/06—Revision 0: Initial Version
4/13—Rev. A to Rev. B
Changes to Table 2 ............................................................................ 5
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
Rev. C | Page 2 of 32
Data Sheet
ADIS16201
SPECIFICATIONS
TA = −40oC to +125°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.
Table 1.
Parameter
INCLINOMETER
Input Range
Relative Accuracy
Sensitivity
Sensitivity over Temperature
Offset
Offset over Temperature
ACCELEROMETER
Input Range 1
Nonlinearity1
Alignment Error
Cross Axis Sensitivity
Sensitivity
Sensitivity over Temperature
Offset
Offset over Temperature
ACCELEROMETER NOISE PERFORMANCE
Output Noise
Noise Density
ACCELEROMETER FREQUENCY RESPONSE
Sensor Bandwidth
Sensor Resonant Frequency
ACCELEROMETER SELF-TEST STATE 2
Output Change When Active
TEMPERATURE SENSOR
Output at 25°C
Scale Factor
ADC INPUT
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Input Range
Input Capacitance
ON-CHIP VOLTAGE REFERENCE
Accuracy
Reference Temperature Coefficient
Output Impedance
Conditions
Each axis
Operable to ~±90 degrees
±15 degrees, 25°C, max filter
±30 degrees, 25°C, max filter
±60 degrees, 25°C, max filter
±60 degrees, 25°C
±30 degrees
At 25°C
Each axis
At 25°C
% of full scale
X sensor to Y sensor
Min
9.9
2037
±70
±0.25
±0.5
±1.5
10
±50
2048
±0.082
2.140
At 25°C, 0 g
8151
At 25°C, no averaging
At 25°C, no averaging
372
±0.5
±0.1
±2
2.162
±50
8192
±0.33
2059
±2.5
2.184
8233
Degrees
Degrees
Degrees
Degrees
LSB/degrees
ppm/°C
LSB
LSB/°C
g
%
Degrees
%
LSB/mg
ppm/°C
LSB
LSB/°C
LSB rms
LSB/√Hz rms
2250
5.5
Hz
kHz
708
1040
LSB
1278
−2.13
LSB
LSB/°C
12
±2
±1
±4
±2
Bits
LSB
LSB
LSB
LSB
V
pF
V
mV
ppm/oC
Ω
2.5
20
2.5
−10
+10
±40
70
Rev. C | Page 3 of 32
10.1
Unit
22
0.37
0
During acquisition
At 25°C
Max
±1.7
At 25°C
At 25°C
Typ
ADIS16201
Parameter
DAC OUTPUT
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Output Range
Output Impedance
Output Settling Time
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Logic 1 Input Current, IINH
Logic 0 Input Current, IINL
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
SLEEP TIMER
Timeout Period 3
FLASH MEMORY
Endurance 4
Data Retention 5
CONVERSION RATE
Minimum Conversion Time
Maximum Conversion Time
Maximum Throughput Rate
Minimum Throughput Rate
POWER SUPPLY
Operating Voltage Range VDD
Power Supply Current
Data Sheet
Conditions
5 kΩ/100 pF to GND
Min
Typ
Max
12
4
1
±5
±0.5
0 to 2.5
2
10
For Code 101 to Code 4095
Bits
LSB
LSB
mV
%
V
Ω
µs
2.0
VIH = VDD
VIL = 0 V
±0.2
−40
10
ISOURCE = 1.6 mA
ISINK = 1.6 mA
0.8
±1
−60
2.4
0.5
V
V
128
Seconds
Cycles
Years
244
484
4096
2.066
3.0
Normal mode, SMPL_TIME ≥
0x08 (fs ≤ 910 Hz), at 25°C
Fast mode, SMPL_TIME ≤ 0x07
(fs ≥ 1024 Hz), at 25°C
Sleep mode, at 25°C
Turn-On Time 6
V
V
µA
μA
pF
0.4
20,000
20
TJ = 85°C
Unit
μs
ms
SPS
SPS
3.3
11
3.6
14
36
42
500
130
750
Guaranteed by iMEMs packaged part testing, design, and/or characterization.
Self-test response changes as the square of VDD.
3
Guaranteed by design.
4
Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
V
mA
mA
µA
ms
1
2
5
6
Retention lifetime equivalent at junction temperature (TJ) 85°C as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature.
The start-up time defines the time from VDD > 3.0 V to the first output register update. This parameter does not account for filter settling, which depends on the
SMPL_PRD and AVG_CNT settings.
Rev. C | Page 4 of 32
Data Sheet
ADIS16201
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.
Table 2.
Parameter
fSCLK
Description
Fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz)
Normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz)
Chip select period, fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz)
Chip select period, normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz)
Stall period, fast mode, SMPL_PRD ≤ 0x07 (fs ≥ 1024 Hz)
Stall period, normal mode, SMPL_PRD ≥ 0x08 (fs ≤ 910 Hz)
Chip select to clock edge
Data output valid after SCLK edge
Data input setup time before SCLK rising edge
Data input hold time after SCLK rising edge
Data output fall time
Data output rise time
CS high after SCLK edge
tDATARATE
tDATARATE
tSTALL
tSTALL
tcs
tDAV
tDSU
tDHD
tDF
tDR
tSFS
1
Min1
0.01
0.01
32
42
10
12
48.8
Typ
Max
2.5
1.0
Unit
MHz
MHz
μs
μs
μs
μs
ns
ns
ns
ns
ns min
ns min
ns typ
100
24.4
48.8
5
5
12.5
12.5
5
Guaranteed by design, not tested.
TIMING DIAGRAMS
tDATA RATE
tSTALL
CS
05462-002
SCLK
tSTALL = tDATA RATE – 16/fSCLK
Figure 2. SPI Chip Select Timing
CS
tCS
tSFS
1
2
3
4
5
6
15
16
SCLK
tDAV
MSB
DB14
DB13
tDSU
DIN
W/R
DB12
DB11
A4
A3
DB10
DB2
DB1
LSB
tDHD
A5
A2
D2
Figure 3. SPI Timing
(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
Rev. C | Page 5 of 32
D1
LSB
05462-003
DOUT
ADIS16201
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Acceleration (Any Axis, Unpowered)
Acceleration (Any Axis, Powered)
VDD to COM
Digital Input/Output Voltage to COM
Analog Inputs to COM
Analog Inputs to COM
Operating Temperature Range
Storage Temperature Range
Table 4. Package Characteristics
Rating
3500 g
3500 g
−0.3 V to +7.0 V
−0.3 V to +5.3 V
−0.3 to VDD + 0.3 V
−0.3 to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
Package Type
16-Terminal LGA
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 6 of 32
θJA
250°C/W
θJC
25°C/W
Device Weight
0.6 grams
Data Sheet
ADIS16201
VDD
AUX ADC
VREF
COM
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13
14
15
16
AUX DAC 12
ADIS16201
NC 11
BOTTOM
VIEW
(Not to Scale)
AUX COM 10
OR
1
SCLK
2
DOUT
3
DIN
4
CS
7
6
5
DIO1
DIO0
NC = NO INTERNAL
CONNECTION
8
NC
9 Y SENSOR
AUX COM
RST
05462-004
X SENSOR
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
SCLK
Type 1
I
2
DOUT
O
3
DIN
I
4
5, 6
7, 11
8, 10
9
12
13
14
15
16
CS
DIO0, DIO1
NC
AUX COM
RST
AUX DAC
VDD
AUX ADC
VREF
COM
I
I/O
–
S
I
O
S
I
O
S
1
Description
Serial Clock. SCLK provides the serial clock for accessing data from the part and writing serial data
to the control registers.
Data Out. The data on this pin represents data being read from the control registers and is clocked
out on the falling edge of the SCLK.
Data In. Data written to the control registers is provided on this input and is clocked in on the
rising edge of the SCLK.
Chip Select, Active Low. This input frames the serial data transfer.
Multifunction Digital I/O Pins.
No Connect.
Auxiliary Grounds. Connect to GND for proper operation.
Reset, Active Low. This input resets the embedded microcontroller to a known state.
Auxiliary DAC Analog Voltage Output.
+3.3 V Power Supply.
Auxiliary ADC Analog Input Voltage.
Precision Reference Output.
Common. Reference point for all circuitry in the ADIS16201.
S = Supply; O = Output; I = Input.
Rev. C | Page 7 of 32
ADIS16201
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
2.174
120
2.170
100
QUANTITY
2.165
2.157
80
60
2.153
40
2.148
20
3.0
3.1
3.2
3.3
3.4
3.5
3.7
3.6
0
POWER SUPPLY (V)
–18
–17
–15
–14
–12
–11
–9
–8
–6
–5
–3
–2
0
2
3
5
6
8
9
11
12
14
15
17
18
2.144
2.9
(mg)
Figure 5. Acceleration Sensitivity vs. Power Supply at 25°C
05462-008
2.161
05462-005
ACCELERATION SENSITIVITY (LSB/mg)
140
Figure 8. Acceleration Offset Distribution at 25°C/3.3 V/0 g
25
20
18
20
16
15
QUANTITY
QUANTITY
14
10
12
10
8
6
5
4
–60
–30
0
30
60
90
120
150
(ppm/°C)
0
–200 –160 –120
05462-006
–90
–40
0
40
80
120
160
200
(ppm/°C)
Figure 6. Acceleration Sensitivity Tempco Histogram at 3.3 V
Figure 9. Acceleration Offset Tempco Histogram at 3.3 V
2.192
50
40
ACCELERATION OFFSET (LSB)
2.183
2.175
2.166
2.158
2.149
30
20
10
0
–10
–20
–30
2.141
2.132
–60
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
140
Figure 7. Acceleration Sensitivity vs. Temperature at 3.3 V
–50
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY (V)
Figure 10. Acceleration Offset vs. Supply at 25°C
Rev. C | Page 8 of 32
3.7
05462-010
–40
05462-007
ACCELERATION SENSITIVITY (LSB/mg)
–80
05462-009
2
0
–150 –120
Data Sheet
ADIS16201
140
90
80
120
70
100
QUANTITY
QUANTITY
60
50
40
80
60
30
40
20
20
10
–1.2
–1.1
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
05462-011
0.18
0.19
0.20
0.21
0.22
0.23
0.24
0.25
0.26
0.27
0.28
0.29
0.30
0.31
0.32
0.33
0.34
0.35
0.36
0.37
0.38
0.39
0.40
0.41
0.42
(g)
(Degrees)
Figure 11. X-Axis Self-Test Level at 25°C/3.3 V
05462-014
0
0
Figure 14. Inclination Offset Distribution at 25°C/3.3 V/0 g
80
20
18
70
16
60
QUANTITY
QUANTITY
14
50
40
30
12
10
8
6
20
4
10
05462-012
0.18
0.19
0.20
0.21
0.22
0.23
0.24
0.25
0.26
0.27
0.28
0.29
0.30
0.31
0.32
0.33
0.34
0.35
0.36
0.37
0.38
0.39
0.40
0.41
0.42
(g)
0
–200 –160 –120
–80
–40
0
40
80
120
160
200
(ppm/°C)
05462-015
2
0
Figure 15. Inclination Offset Tempco Histogram at 3.3 V
Figure 12. Y-Axis Self-Test Level at 25°C/3.3 V
10
1200
8
INCLINATION OFFSET (LSB)
800
600
6
4
2
0
–2
–4
–6
400
200
2.9
3.0
3.1
3.2
3.3
3.4
3.5
POWER SUPPLY (V)
3.6
3.7
3.0
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY (V)
Figure 16. Inclination Offset vs. Supply at 25°C
Figure 13. Self-Test Shift vs. Supply at 25°C
Rev. C | Page 9 of 32
3.7
05462-016
–8
–10
2.9
05462-013
SELF-TEST SHIFT (LSB)
1000
–3
1
4096
8191
12286
16381
ADC STATE
2
100
1
50
–1
25
–2
0
–3
1
Figure 17. ADC Gain Distribution at 25°C/3.3 V
80
40
30
10
0
Figure 18. ADC Offset Distribution at 25°C/3.3 V
3
1
–1
Figure 19. Typical ADC Integral Nonlinearity at 25°C/3.3 V
Rev. C | Page 10 of 32
4096
ADC STATE
8191
12286
Figure 22. DAC Offset Distribution at 25°C/3.3 V
(mV)
16381
(µV/LSB)
05462-020
125
05462-021
75
(LSB)
3
05462-022
606.6
606.9
607.2
607.5
607.8
608.1
608.4
608.7
609.0
609.3
609.6
609.9
610.2
610.5
610.8
611.1
611.4
611.7
612.0
612.3
612.6
612.9
613.2
613.5
617.0
50
QUANTITY
05462-017
607.6
607.8
608.0
608.2
608.4
608.6
608.8
609.0
609.2
609.4
609.6
609.8
610.0
610.2
610.4
610.6
610.8
611.0
611.2
611.4
611.6
611.8
612.0
612.2
612.4
QUANTITY
150
–2.7
–2.4
–2.1
–1.8
–1.5
–1.2
–0.9
–0.6
–0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.8
0
QUANTITY
(mV)
05462-018
–2.4
–2.1
–1.8
–1.5
–1.2
–0.9
–0.6
–0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
QUANTITY
(µV/LSB)
05462-019
(LSB)
ADIS16201
Data Sheet
0
Figure 20. Typical ADC Differential Nonlinearity
120
70
60
100
80
60
20
40
20
0
Figure 21. DAC Gain Distribution at 25°C/3.3 V
45
2
40
35
30
25
20
15
–2
10
5
0
Data Sheet
5
140
3.0V/–40°C
3.0V/+25°C
3.0V/+125°C
3.3V /–40°C
3.3V/+25°C
3.3V/+125°C
3.6V/–40°C
3.6V/+25°C
3.6V/+125°C
3
2
1
120
100
QUANTITY
4
NONLINEARITY (LSB)
ADIS16201
0
–1
–2
80
60
40
–3
20
–4
1024
1536
2048
2560
3072
3584
4096
DAC STATE
0
(mA)
Figure 23. Typical DAC Integral Nonlinearity
05462-026
512
9.4
9.6
9.7
9.9
10.0
10.2
10.3
10.5
10.6
10.8
10.9
11.1
11.2
11.4
11.5
11.7
11.8
12.0
12.1
12.3
12.4
12.6
12.7
12.9
13.0
0
05462-023
–5
Figure 26. Normal Mode Power Supply Current Distribution at 25°C/3.3 V
250
140
120
200
QUANTITY
QUANTITY
100
150
100
80
60
40
50
20
0
Figure 24. VREF Distribution at 25°C/3.3 V
29.0
29.6
30.2
30.8
31.4
32.0
32.6
33.2
33.8
34.4
35.0
35.6
36.2
36.8
37.4
38.0
38.6
39.2
39.8
40.4
41.0
41.6
42.2
42.8
43.4
(mA)
05462-027
(V)
05462-024
2.4975
2.4977
2.4979
2.4981
2.4983
2.4985
2.4987
2.4989
2.4991
2.4993
2.4995
2.4997
2.4999
2.5001
2.5003
2.5005
2.5007
2.5009
2.5011
2.5013
2.5015
2.5017
2.5019
2.5021
2.5023
0
Figure 27. Fast Mode Power Supply Current Distribution at 25°C/3.3 V
60
180
160
50
140
QUANTITY
120
30
20
100
80
60
40
10
20
0
370
378
386
394
402
410
418
426
434
442
450
458
466
474
482
490
498
506
514
522
530
538
546
554
562
(µA)
05462-028
(°C)
Figure 25. Temperature Distribution at 25°C/3.3 V
0
05462-025
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
QUANTITY
40
Figure 28. Sleep Mode Power Supply Current Distribution at 25°C/3.3 V
Rev. C | Page 11 of 32
Data Sheet
0.0010
0.0008
0.0008
SLEEP MODE CURRENT (A)
0.0010
0.0006
0.0004
0.0002
0.0004
–30
–10
10
30
50
70
90
110
130
TEMPERATURE (°C)
150
Figure 29. Sleep Mode Current vs. Temperature at 3.3 V
0
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
Figure 30. Sleep Mode Current vs. Supply at 25°C
Rev. C | Page 12 of 32
3.7
05462-030
0
–50
0.0006
0.0002
05462-029
SLEEP MODE CURRENT (A)
ADIS16201
Data Sheet
ADIS16201
THEORY OF OPERATION
The ADIS16201 is a complete dual-axis digital inclinometer/
accelerometer that uses Analog Devices’ surface-micromachining
process and embedded signal processing to make a functionally
complete, low cost dual-axis sensor.
The ADIS16201 offers a fully calibrated, dual–axis
micromachined sensor element that develops independent
analog signals representative of the acceleration levels applied to
the part. An on-board precision ADC samples the acceleration
signals, along with the power supply voltage, an internal
temperature signal, and the auxiliary analog input signal. These
signals are then processed and latched into addressable output
registers. The serial peripheral interface (SPI) provides
convenient, digital access to these registers.
One important behavior to observe when using this approach is
the fact that the relationship between the acceleration
measurements and inclination angle is nonlinear. This nonlinear behavior results in larger quantization error changes as
the inclination angle approaches 90°. Figure 32 provides a closer
look at this behavior by illustrating the increase in step size as
the inclination angle estimate increases. Figure 33 offers a direct
relationship between the quantization error and the overall
inclination angle.
OUTPUT
INCLINATION
ACCELEROMETER OPERATION
0
22.5
45.0
67.5
90.0
TILT (Degrees)
Figure 31. Acceleration and Inclination Angle vs. Actual Tilt Angle
INCLINATION
OUTPUT
The acceleration sensor used in the ADIS16201 is a surfacemachined, polysilicon structure built on top of a silicon wafer.
Polysilicon springs suspend the structure over the surface of the
wafer and provide a resistance against acceleration forces.
Acceleration causes a deflection in the differential capacitor
structure that includes both fixed plates and plates that are
attached to the moving mass. The fixed plates are driven by a set
of square waves that are 180o out-of-phase from one another.
Acceleration deflects the beam and unbalances the differential
capacitor, resulting in an output square wave whose amplitude
is proportional to acceleration. Phase sensitive demodulation
techniques rectify the signal and determine the direction of the
acceleration. The output of the demodulator is amplified,
digitized, and processed to remove any process variations and
sensitivities to supply variations.
05462-031
ACCELERATION
INCLINOMETER OPERATION
ACCELERATION
75
80
85
90
TILT (Degrees)
The ADIS16201 inclinometer output data is linear with respect
to degrees of inclination and is dependent on no forces, other
than gravity, acting on the device. The ADIS16201 leverages a
simple geometrical relationship to convert its calibrated
acceleration measurements into an accurate inclination angle
estimate. Figure 31 displays the acceleration measurements
associated with each incline angle, along with the resulting
inclination angle estimate produced by the ADIS16201.
Rev. C | Page 13 of 32
Figure 32. Acceleration and Inclination Angle vs. Actual Tilt Angle
05462-032
In addition, the acceleration signals are further processed to
produce inclination angle data for both axes. The inclination
angle data represents the tilt away from the ideal plane, which
in this case, is normal to the earth’s gravitational force. This
calculation assumes that no force outside of the earth’s
gravitational force is acting on the device.
ADIS16201
Data Sheet
1.5
TEMPERATURE SENSOR
The TEMP_OUT control register allows the end user to
monitor the internal temperature of the ADIS16201 to an
accuracy of ±5°C. The output data is presented in a straight
binary format with a nominal 25°C die temperature correlating
to a 1278 LSB read through the TEMP_OUT output data
register. The temperature scale factor of −2.129 LSB/°C allows
for a resolution of less than 0.5°C in the temperature reading
within the output data register.
0.5
0
–0.5
–1.0
–1.5
0
15
30
45
60
75
TILT (Degrees)
90
05462-033
ERROR (Degrees)
1.0
Figure 33. Inclination Quantization Error
Rev. C | Page 14 of 32
Data Sheet
ADIS16201
BASIC OPERATION
The data output register configuration is broken down into three
different functions: new data ready bit (ND), alarm indicator
(EA), and data bits (D0 to D13). The ND bit is used to determine
if a particular register has been updated since the last read
command. A Logic Level 1 for ND indicates that unread data is
available. When a register is read, this bit is set to a 0 logic level.
The alarm indicator provides users with a simple method for
passively monitoring a variety of status/alarm conditions and can
be used to simplify system-level processing requirements.
The ADIS16201 is designed for simple integration into industrial system designs, requiring only a 3.3 V power supply and a
4-wire, industry standard, serial peripheral interface (SPI).
Registers that are accessed using the SPI interface facilitate all of
the input/output functions on the ADIS16201. Each of these
registers is assigned a unique address and data format tailored
for its specific function. The SPI port operates in a full duplex
mode; data is clocked out of the DOUT pin at the same time
command/address data is clocked in through the DIN pin. For
more information on basic SPI port operation, see the
Applications section.
The two acceleration output data registers are 14 bits in length
and are formatted as twos complement binary numbers. The
rest of the data output registers are 12 bits in length, leaving D12
and D13 as “don’t care” bits. The output format for each of these
registers, along with their addresses, can be found in Table 7.
Each output data register has two different addresses. The first
address is for the upper byte, which contains the most
significant bits (D8 to D13), ND, and EA data. The second
address is for the lower byte, which contains the eight least
significant bits (D0 to D7). Reading either of these addresses
results in all 16 bits being clocked out on the DOUT line as
defined in Table 6 during the next SPI cycle.
DATA OUTPUT REGISTER ACCESS
For the most basic operation of the ADIS16201, output data
registers require only read commands for accessing calibrated
sensor data, along with the temperature, power supply, and
auxiliary analog input channel data. Each read command
requires two full 16-bit cycles. The first cycle is for transmitting
the register address, and the second cycle is for reading the data.
Table 6 displays the appropriate bit map for the read command.
Bit A0 through Bit A5 contain the address of the register being
accessed. The appropriate sequencing for each SPI signal (CS,
SLCK, DIN, and DOUT) during a read command can be found
in Figure 34.
CS
SCLK
ADDRESS
DIN
IDLE
NEXT COMMAND
DOUT
BASED ON PREVIOUS COMMAND
05462-034
ZERO
READ BIT = 0
16-BIT DATA WORD
Figure 34. Register Read Command Sequence
Table 6. Register Read Command Bit Map
DIN
W/R1
DOUT
ND
EA
Upper Byte
1
0
A5
A4
A3
A2
A1
A0
x
D13
D12
D11
D10
D9
D8
D7
D6
Lower Byte
The W/R bit is always 0 for read commands.
Rev. C | Page 15 of 32
x
x
x
x
x
x
x
D5
D4
D3
D2
D1
D0
ADIS16201
Data Sheet
Table 7. Data Output Register Information
Name
SUPPLY_OUT
XACCL_OUT
YACCL_OUT
AUX_ADC
TEMP_OUT
XINCL_OUT
YINCL_OUT
Function
Power Supply Data
X-Axis Acceleration Data
Y-Axis Acceleration Data
Auxiliary Analog Input Data
Sensor Temperature Data
X-Axis Inclination Data
Y-Axis Inclination Data
Address
0x03, 0x02
0x05, 0x04
0x07, 0x06
0x09, 0x08
0x0B, 0x0A
0x0D, 0x0C
0x0F, 0x0E
Resolution
(Bits)
12
14
14
12
12
12
12
Data
Format
Binary
Twos complement
Twos complement
Binary
Binary
Twos complement
Twos complement
Table 8. Output Coding Example, XACCL_OUT 1, 2
Acceleration Level
+1.7 g
+1 g
+0.4625 g
+0.4625 mg
0g
−0.4625 mg
−0.4265 g
−1 g
−1.7 g
1
2
Binary Output
00 1110 0101 1011
00 1000 0111 0010
00 0011 1110 1000
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1100 0001 1000
11 0111 1000 1110
11 0001 1010 0101
HEX Output
0x0E5B
0x0872
0x03E8
0x0001
0x0000
0x3FFF
0x3C18
0x378E
0x31A5
Two MSBs have been masked off and are not considered in the coding.
Nominal sensitivity (2.162 LSB/mg) and zero offset null performance are assumed.
Rev. C | Page 16 of 32
Decimal
3675
2162
1000
1
0
−1
−1000
−2162
−3675
Scale Factor
(per LSB)
1.22 mV
0.4625 mg
0.4625 mg
0.61 mV
−0.47°C
0.1°
0.1°
Data Sheet
ADIS16201
PROGRAMMING AND CONTROL
CONTROL REGISTER OVERVIEW
CONTROL REGISTER ACCESS
The ADIS16201 offers many programmable features that are
controlled by writing commands to the appropriate control
registers using the SPI. For added system flexibility and
programmability, the following sections describe these controls
and specify the 28 digital control registers that are available
using the SPI interface. A high level listing of these registers is
given within Table 9. The following sections expand upon the
functionality of each of these control registers, providing for the
full clarification of the behavior of each of the control registers.
Available control modes for the device include selectable sample
rates for reading the seven output vectors, configurable output
data, alarm settings, control of the on-board 12-bit auxiliary
DAC, handling of the two general-purpose I/O lines, facilitation
of the sleep mode, enabling the self-test mode, and other
miscellaneous control functions.
The control registers within the ADIS16201 are based upon a
16-bit/2-byte format, and they are accessed via the SPI. The SPI
operates in full duplex mode with the data clocked out of the
DOUT pin at the same time data is clocked in through the DIN
pin. All commands written to the ASIS16201 are categorized as
write commands or read commands. All write commands are
self-contained and take place within a single cycle. Each read
command requires two cycles to complete; the first cycle is for
transmitting the register address, and the second cycle is for
reading the data. During the second cycle, when the data out
line is active, the data in line is used to receive the next
sequential command. This allows for overlapping the commands.
For more information on basic SPI port operation, see the
Applications section.
The conversion process is repeated continually, providing for
continuous update of the seven output registers. The new data
ready bit (ND) flags bits common to all seven output registers,
allowing the completion of the conversion process to be tracked
via the SPI. As an alternative, the digital I/O lines can be configured
through software control to create a data-ready hardware function
that can signal the completion of the conversion process.
Two independent alarms provide the ability to monitor any one
of the seven output registers. They can be configured to report
an alarm condition on either fixed thresholds or rates of change.
The alarm conditions are monitored through the SPI. In addition,
the user can configure the digital I/O lines through software
control to create an alarm function that allows for monitoring
of the alarm conditions through hardware.
The seven output signals noted above are calibrated independently at the factory, delivering a high degree of accuracy. In
addition, the user has access to independent offset and scale
factors for each of the two acceleration and inclination output
vectors. This allows independent scaling and level adjustment
control of any one these four registers prior to the values being
read via the SPI. In turn, field level calibrations can be implemented
within the sensor itself using these offset and scale variables.
System level commands provided within the sensor include
automatic zeroing of the four outputs using a single null command
via the SPI. In addition, the original factory calibration settings
can be recovered at any point, using a simple factory reset
command.
The read and write commands are identified through the most
significant bit (MSB), B15, of the received data. Write a 1 to B15
to indicate a write command. Write a 0 to B15 to indicate a read
command. Bit B13 through Bit B8 contain the address of the
control register that is being accessed. The remaining eight bits of
the write command contain the data that is being written into the
part, whereas the remaining eight bits of the read command
contain don’t care levels. Given that the data within the write
command is eight bits in length, the 8-bit data format is the
default byte size. A write command operates on a single chip
select cycle, as shown in Figure 35. The read command operates
on a 2-chip select cycle basis, as seen in Figure 34. All 64 bytes of
register space are accessed using the 6-bit address. Data written
into the device is one byte at a time with the address of each byte
being explicitly called out in the write command. Conversely, data
being read from the device consists of two, back-to-back, 8-bit
variables being sent out, with the first byte out corresponding to
the upper address (odd number address) and the second byte
relating to the next lower address space (even number address).
For example, a data read of Address 03h results in the data from
Address 03h being fed out followed by data from Address 02h.
Likewise, a data read of Address 02h results in the same data
stream being output from the device.
The ADIS16201 is a flash-based device with the nonvolatile
functional registers implemented as flash registers. Take into
account the endurance limitation of 20,000 writes when
considering the system-level integration of these devices. The
nonvolatile column in Table 9 indicates which registers are
recovered upon power-up. The user must instigate a manual
flash update command (using the command register) in order
to store the nonvolatile data registers, once they are configured
properly. When performing a manual flash update command,
the user needs to ensure that the power supply remains within
limits for a minimum of 50 μs after the write is initiated. This
ensures a successful write of the nonvolatile data.
Rev. C | Page 17 of 32
ADIS16201
Data Sheet
Table 9. Control Register Mapping
Register Name
Type
Nonvolatile
SUPPLY_OUT
XACCL_OUT
YACCL_OUT
AUX_ADC
TEMP_OUT
XINCL_OUT
YINCL_OUT
XACCL_ OFF
YACCL_ OFF
XACCL_ SCALE
YACCL_ SCALE
XINCL_OFF
YINCL_ OFF
XINCL_SCALE
YINCL_ SCALE
ALM_MAG1
ALM_MAG2
ALM_SMPL1
ALM_SMPL2
ALM_CTRL
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
AUX_DAC
GPIO_CTRL
MSC_CTRL
SMPL_PRD
AVG_CNT
PWR_MDE
STATUS
COMMAND
R/W
R/W
R/W
R/W
R/W
R/W
R
W
Address
0x00 to 0x01
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E
0x20
0x22
0x24
0x26
0x28
0x2A to 0x2F
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3E
X
X
Bytes
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
6
2
2
2
2
2
2
2
2
Function
Reserved
Power supply output data
X-axis acceleration output data
Y-axis acceleration output data
Auxiliary ADC data
Temperature output data
X-axis inclination output data
Y-axis inclination output data
X-axis acceleration offset factor
Y-axis acceleration offset factor
X-axis acceleration scale factor
Y-axis acceleration scale factor
X-axis inclination offset factor
Y-axis inclination offset factor
X-axis inclination scale factor
Y-axis inclination scale factor
Alarm 1 amplitude threshold
Alarm 2 amplitude threshold
Alarm 1 sample period
Alarm 2 sample period
Alarm source control register
Reserved
Auxiliary DAC data
Auxiliary digital I/O control register
Miscellaneous control register
ADC sample period control
Defines number of samples used by moving average filter
Counter used to determine length of power-down mode
System status register
System command register
Table 10. Register Write Command Bit Map
W/R 0
Upper Byte
A5
A4
A3
A2
A1
A0
D7
D6
Lower Byte
D5
CS
SCLK
DIN
ADDRESS
ZERO
WRITE BIT = 1
DATA
05462-035
DIN
Figure 35. Control Register Write Command Sequence of SPI Signals
Rev. C | Page 18 of 32
D4
D3
D2
D1
D0
Data Sheet
ADIS16201
CONTROL REGISTER DETAILS
The control registers in the ADIS16201 are 16 bits in length.
Each of them has been assigned an address for their upper byte
and lower byte. The bit map of each control register uses the
numerical assignments that are displayed in the following table.
MSB
LSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
The upper byte consists of Bit 8 to Bit 15, and the lower byte
consists of Bit 0 to Bit 7. Each of the following sections provides
a description of each register that includes purpose, relevant
scaling information, bit maps, addresses, and default values.
CALIBRATION
The ADIS16201 outputs are precalibrated at the factory, providing
a high degree of accuracy and simpler system implementation.
In addition, for system or field updates, the device has eight
control registers associated with calibrating the acceleration and
inclination output data (see the Calibration Register Definitions
section). Each of these registers has read/write capability and is
16 bits (2 bytes) in length. All calibration registers are 12 bits in
length, with the exception of the inclination offset registers, which
are 9 bits in length. All data values are aligned to the LSB. The
OFFSET registers all utilize the twos complement format
allowing for both positive and negative offsets. All scale registers
utilize the straight binary format.
The data within these eight calibration registers is utilized in
offsetting and scaling of the output data registers according to
the following relationship:
Output = A × ( x + C )
where:
x represents the raw data prior to calibration.
C is the offset.
A is the scalar.
Output represents the output data register where the resultant
data is stored.
All four inertial sensor outputs (X and Y acceleration, X and Y
inclination) have their own independent set of calibration
registers.
Simple access to these registers enables field calibration to
correct for in-system error sources. In particular, the offset
control registers allow the user to reset to 0°/0 mg reference
point for the device. This is particularly important when
considering the stack-up of the tolerances in mounting the
ADIS16201 to a printed circuit board (PCB), the PCB to an
enclosure, the enclosure mounted to the chassis of a piece of
equipment, and so on.
The result is that the ADIS16201 mechanical reference can be
offset several degrees from that of the end equipment
mechanical reference, resulting in an accumulation of offset
errors in the inclination and acceleration data output registers.
The offset registers provide a convenient tool for managing
these types of errors.
A global command is implemented within the ADIS16201 to
simplify the loading of the offsets. Once the end piece of
equipment is leveled to its desired reference point, a null
command can be sent to the ADIS16201 via the command
control register, which zeros the two acceleration and the two
inclination output data registers. This command loads all four
offset registers with the inverse of their contents at the time of
the null command. Consequently, on the next reading of the
seven output data registers, the two acceleration and two
inclination output data registers should be reset to mid-scale
(neglecting noise and repeatability limitations). It is suggested
that when the null command is implemented, the AVG_CNT
control register be set to 08h in order to maximize the filtering
and reduce the effects of noise in determining the values to be
loaded into the offset control registers. Optionally, the user can
manually load each of the eight calibration registers via the SPI
in order to calibrate the end system. This is applicable when the
user plans to adjust the scale factors, thus requiring an external
stimulus to excite the ADIS16201.
CALIBRATION REGISTER DEFINITIONS
XACCL_OFF Register Definition
Address
0x11, 0x10
1
Scale1
0.4624 mg
Default
0x0000
Format
Twos
complement
Access
R/W
Scale is the weight of each LSB.
The XACCL_OFF register is the user-controlled register for
calibrating system-level acceleration offset errors. For the X-axis
acceleration, it represents the C variable in the calibration
equation. The maximum calibration range is +0.945 g, or
+2047/−2048 codes, assuming nominal sensor sensitivity. The
contents of this register are nonvolatile.
Table 11. XACCL_OFF Bit Designations
Bit
15:12
11:0
Rev. C | Page 19 of 32
Description
Not used
Data bits
ADIS16201
Data Sheet
XINCL_OFF Register Definition
XACCL_SCALE Register Definition
Address
0x15, 0x14
1
Scale
0.0488%
1
Default
0x0800
Format
Binary
Access
R/W
Scale is the weight of each LSB.
1
The XACCL_SCALE register is the user-controlled register for
calibrating system-level acceleration sensitivity errors. For the
X-axis acceleration, it represents the A variable in the calibration
equation. This register offers a sensitivity calibration range of 0 to
2, or 0 to 4095 codes, assuming nominal sensor sensitivity. The
contents of this register are nonvolatile.
Table 12. XACCL_SCALE Bit Designations
Bit
15:12
11:0
1
Default
0x0000
Format
Twos
complement
Default
0x0000
Format
Twos
complement
Access
R/W
Scale is the weight of each LSB.
The XINCL_OFF register is the user-controlled register for
calibrating system-level inclination offset errors. For the X-axis
inclination, it represents the C variable in the calibration
equation. The maximum calibration range is +25.5° or
+255/−256 codes, assuming nominal sensor sensitivity. The
contents of this register are nonvolatile.
Bit
15:9
8:0
YACCL_OFF Register Definition
Scale1
0.4624 mg
Scale1
0.1°
Table 15. XINCL_OFF Bit Designations
Description
Not used
Data bits
Address
0x13, 0x12
Address
0x19, 0x18
R/W
Both
XINCL_SCALE Register Definition
Address
0x1D, 0x1C
1
Scale is the weight of each LSB.
Description
Not used
Data bits
Scale1
0.0488%
Default
0x0800
Format
Binary
Access
R/W
Scale is the weight of each LSB.
The YACCL_OFF register is the user-controlled register for
calibrating system-level acceleration offset errors. For the Y-axis
acceleration, it represents the C variable in the calibration
equation. The maximum calibration range is +0.945 g, or
+2047/−2048 codes, assuming nominal sensor sensitivity. The
contents of this register are nonvolatile.
The XINCL_SCALE register is the user-controlled register for
calibrating system-level inclination sensitivity errors. For the Xaxis inclination, it represents the A variable in the calibration
equation. The calibration range is from 0 to 2, or 0 to 4095
codes, assuming nominal sensor sensitivity. The contents of this
register are nonvolatile.
Table 13. YACCL_OFF Bit Designations
Table 16. XINCL_SCALE Bit Designations
Bit
15:12
11:0
Bit
15:12
11:0
Description
Not used
Data bits
YINCL_OFF Register Definition
YACCL_SCALE Register Definition
Address
0x17, 0x16
1
Scale1
0.0488%
Default
0x0800
Format
Binary
Access
R/W
Scale is the weight of each LSB.
Table 14. YACCL_SCALE Bit Designations
Description
Not used
Data bits
Address
0x1B, 0x1A
1
The YACCL_SCALE register is the user-controlled register for
calibrating system-level acceleration sensitivity errors. For the
Y-axis acceleration, it represents the A variable in the calibration
equation. This register offers a sensitivity calibration range of 0 to
2, or 0 to 4095 codes, assuming nominal sensor sensitivity. The
contents of this register are nonvolatile.
Bit
15:12
11:0
Description
Not used
Data bits
Scale1
0.1º
Default
0x0000
Format
Twos
complement
Access
R/W
Scale is the weight of each LSB.
The YINCL_OFF register is the user-controlled register for
calibrating system-level inclination offset errors. For the Y-axis
inclination, it represents the C variable in the calibration
equation. The maximum calibration range is +25.5º or +255/
−256 codes, assuming nominal sensor sensitivity. The contents
of this register are nonvolatile.
Table 17. YINCL_OFF Bit Designations
Bit
15:9
8:0
Rev. C | Page 20 of 32
Description
Not used
Data bits
Data Sheet
ADIS16201
YINCL_SCALE Register Definition
Address
0x1F, 0x1E
1
Scale1
0.0488%
Default
0x0800
Format
Binary
Access
R/W
Scale is the weight of each LSB.
The YINCL_SCALE register is the user-controlled register for
calibrating system-level inclination sensitivity errors. For the
Y-axis inclination, it represents the A variable in the calibration
equation. The calibration range is from 0 to 2, or 0 to 4095 codes,
assuming nominal sensor sensitivity. The contents of this register
are nonvolatile.
Table 18. YINCL_SCALE Bit Designations
Bit
15:12
11:0
Description
Not used
Data bits
ALARMS
The ADIS16201 contains two independent alarm functions that are
referred to as Alarm 1 and Alarm 2. The Alarm 1 function is
managed by the ALM_MAG1 and ALM_SMPL1 control registers.
The Alarm 2 function is managed by the ALM_MAG2 and
ALM_SMPL2 control registers. Both the Alarm 1 and Alarm 2
functions share the ALM_CTRL register. For simplicity, the
following text references the Alarm 1 functionality only.
The 16-bit ALM_CTRL register serves three distinct roles in
controlling the Alarm 1 function. First, it is used to enable the
overall Alarm 1 function and select the output data variable that
is to be monitored for the alarm condition. Second, it is used to
select whether the Alarm 1 function is based upon a predefined
threshold (THR) level or a predefined rate-of-change (ROC)
slope. Third, the ALM_CTRL register can be used in setting up
one of the two general-purpose input/output lines (GPIOs) to
serve as a hardware output that indicates when an alarm
condition has occurred. Enabling the I/O alarm function,
setting its polarity, and controlling its operation are
accomplished using this register.
Note that when enabled, the hardware output indicator serves
both the Alarm 1 and Alarm 2 functions and cannot be used to
differentiate between one alarm condition and the other. It is
simply used to indicate that an alarm is active and that the user
should poll the device via the SPI to determine the source of the
alarm condition (see the STATUS Register Definition section).
Because the ALM_CTRL, MSC_CTRL, and GPIO_CTRL
control registers can influence the same GPIO pins, a priority
level has been established to avoid conflicting assignments of
the two GPIO pins. This priority level is defined as
MSC_CTRL, which has precedence over ALM_CTRL, which
has precedence over GPIO_CTRL.
The ALM_MAG1 control register used in controlling the
Alarm 1 function has two roles. The first role is to store the
value with which the output data variable is compared to
discern if an alarm condition exists or not. The second role is to
identify whether the alarm should be active for excursions
above or below the alarm limit. If 1 is written to the GT1 bit of
the ALM_MAG1 control register, the alarm is active for
excursions extending above a given limit. If 0 is written to the
GT1 bit, the alarm is active for excursions dropping below the
given limit. The comparison value contained within the
ALM_MAG1 control register is located within the lower 14 bits.
The format utilized for this 14-bit value should match that of
the output data register that is being monitored for the alarm
condition. For instance, if the YINCL_OUT output data register
is being monitored by Alarm 1, then the 14-bit value within the
ALM_MAG1 control register takes on a twos complement
format with each LSB equating to nominal 0.1° (assumes unity
scale and zero offset factors). The ALM_MAG value is
compared against the instantaneous value of the parameter
being monitored.
Use caution when monitoring the temperature output register
for the alarm conditions. Here, the negative temperature scale
factor results in the greater than and less than selections
requiring reverse logic.
When the THR function is enabled, the output data variable is
compared against the ALM_MAG1 level. When the ROC
function is enabled, the comparison of the output data variable
is against the ALM_MAG1 level averaged over the number of
samples, as identified in the ALM_SMPL1 control register. This
acts to create a comparison of (Δ units/Δ time) or the derivative
of the output data variable against a predefined slope.
Rev. C | Page 21 of 32
ADIS16201
Data Sheet
The versatility built into the alarm function is intended to allow
the user to adapt to a number of different applications. For
example, in the case of monitoring a twos complement variable,
the GT1 bit within the ALM_MAG1 control register can allow
for the detection of negative excursions below a fixed level. In
addition, the Alarm 1 and Alarm 2 functions can be set to
monitor the same variable that allows the user to discern if an
output variable remains within a predefined window.
The ALM_SMPL1 register contains the sample period
information for Alarm 1, when it is set for rate-of-change alarm
monitoring. The rate-of-change alarm function averages the
change in the output variable over the specified number of
samples and compares this change directly to the values
specified in the ALM_MAG1 register. The contents of this
register are nonvolatile.
Other options include the ROC function that can be used in
monitoring high frequency shock levels in the acceleration
outputs or slowly changing outputs in the inclination level over
a period of a minute or more. With the addition of the alarm
hardware functionality, the ADIS16201 can be left to run
independently of the main processor and interrupt the system
only when an alarm condition occurs. Conversely, the alarm
condition can be monitored through the routine polling of any
one of the seven data output registers.
Bit
15:8
7:0
Note that the alarm functions work from instantaneous data
and not averaged data that can be present when the AVG_CNT
register is not set to 0. The alarm hardware output indicator is
not latched but tracks the actual alarm conditions in real time.
The ALM_MAG2 register contains the threshold level for
Alarm 2. The contents of this register are nonvolatile.
ALM_MAG1 Register Definition
Address
0x21, 0x20
1
Default1
0x0000
Format
N/A
Table 20. ALM_SMPL1 Bit Designations
ALM_MAG2 Register Definition
Address
0x23, 0x22
1
Bit
15
14
13:0
Table 19. ALM_MAG1 Bit Designations
14
13:0
Description
Greater than active alarm bit.
1: Alarm is active for an output greater than Alarm
Magnitude 1 register setting.
0: Alarm is active for an output less than Alarm
Magnitude 1 register setting.
Not used.
Data bits. This number can be either twos
complement or straight binary. The format is set by
the value being monitored by this function.
ALM_SMPL1 Register Definition
Address
0x25, 0x24
1
Default1
0x0000
Format
Binary
Default is valid only until the first register write cycle.
Access
R/W
Format
N/A
Access
R/W
Table 21. ALM_MAG2 Bit Designations
Default is valid only until the first register write cycle.
Bit
15
Default1
0x0000
Default is valid only until the first register write cycle.
Access
R/W
The ALM_MAG1 register contains the threshold level for
Alarm 1. The contents of this register are nonvolatile.
Description
Not used
Data bits
Description
Greater than active alarm bit.
1: Alarm is active for an output greater than Alarm
Magnitude 2 register setting.
0: Alarm is active for an output less than Alarm
Magnitude 2 register setting.
Not used.
Data bits. This number can be either twos
complement or straight binary. The format is set by
the value being monitored by this function.
ALM_SMPL2 Register Definition
Address
0x27, 0x26
1
Default1
0x0000
Format
Binary
Access
R/W
Default is valid only until the first register write cycle.
The ALM_SMPL2 register contains the sample period
information for Alarm 2, when it is set for rate-of-change alarm
monitoring. The rate-of-change alarm function averages the
change in the output variable over the specified number of
samples and compares this change directly to the values
specified in the ALM_MAG1 register. The contents of this
register are nonvolatile.
Table 22. ALM_SMPL2 Bit Designations
Bit
15:8
7:0
Rev. C | Page 22 of 32
Description
Not used
Data bits
Data Sheet
ADIS16201
ALM_CTRL Register Definition
1
Default1
0x0000
Format
N/A
SAMPLE PERIOD CONTROL
Access
R/W
Default is valid only until the first register write cycle.
The ALM_CTRL register contains the alarm control variables.
Bit
15
Value
14:12
000
001
010
011
100
101
110
111
11
10:8
000
001
010
011
100
101
110
111
7:3
2
1
0
Description
Rate of change (ROC) enable for Alarm 2.
1: ROC is active.
0: ROC is inactive.
Alarm 2 source selection.
Alarm disable.
Alarm source: power supply output.
Alarm source: X-acceleration output.
Alarm source: Y-acceleration output.
Alarm source: auxiliary ADC output.
Alarm source: temperature sensor output.
Alarm source: X-inclination output.
Alarm source: Y-inclination output.
Rate of change (ROC) enable for Alarm 1.
1: ROC is active.
0: ROC is inactive.
Alarm 1 source selection.
Alarm disable.
Alarm source: power supply output.
Alarm source: X-acceleration output.
Alarm source: Y-acceleration output.
Alarm source: auxiliary ADC output.
Alarm source: temperature sensor output.
Alarm source: X-inclination output.
Alarm source: Y-inclination output.
Not used.
Alarm output enable.
1: Alarm output enabled.
0: Alarm output disabled.
Alarm output polarity.
1: Active high.
0: Active low.
Alarm output line select.
1: DIO1.
0: DIO0.
Note that the sample period given is defined as the cumulative
time required to sample, process, and update all seven data output
variables. The seven data output variables are sampled as a
group and in unison with one another. Whatever update rate is
selected for one signal, all seven output data variables are updated
at the same rate whether they are monitored via the SPI or not.
For a sample period setting of less than 1098.9 μs (SMPL_RATE ≤
0x07), the overall power dissipation in the part rises by approximately 300%. The default setting for the SMPL_RATE register is
0x04 at initial power-up, thus allowing for the maximum SPI
clock rate of 2.5 MHz.
256
192
SMPL_PRD VALUE
Table 23. ALM_CTRL Bit Designations
The seven output data variables within the ADIS16201 are
sampled and updated at a rate based upon the SMPL_PRD
control register. The sample period can be precisely controlled
over more than a 3-decade range using a time base with two
settings and a 7-bit binary count. The use of a time base that
varies with a ratio of 1:31 allows for a more optimal resolution
in the sample period than a straight binary counter. This is
reflected in Figure 36, where the frequency is presented on a
logarithmic scale. The choice of the two time base settings
results in making the sample period setting more linear vs. the
logarithmic frequency scale.
128
64
0
1
10
100
1k
FREQUENCY (Hz)
Figure 36. SMPL_PRD Values vs. Sample Frequency
Rev. C | Page 23 of 32
10k
05462-036
Address
0x29, 0x28
ADIS16201
Data Sheet
frequency response plots for the moving average filter, utilizing
various numbers of taps, are detailed in Figure 37.
SMPL_PRD Register Definition
Address
0x37, 0x36
Format
N/A
Access
R/W
H(f)
1.0
Default is valid only until the first register write cycle.
After using the manual flash update (COMMAND[3]), the data
within this register is nonvolatile, allowing for data recovery
upon reset. The initial value is set to 0x0A upon initial powerup, allowing for a sample period of ~744 μs.
NUMBER OF TAPS
Table 24. SMPL_PRD Bit Descriptions
Bit
15:8
7
6:0
N=2
N=4
Description
Not used.
ADC time base control.
0: tB = 122.1 μs
1: tB = 3.784 ms .
ADC sample period control (NS).
Relationship to the sample period control:
0.5
0
N = 16
–0.5
0
0.1
0.2
0.3
0.4
f/fs
0.5
FREQUENCY (Hz)
05462-037
1
Default
0x000A
1
Figure 37. Number of Taps vs. Sample Frequency Response
tS = tB × (NS + 1)
AVG_CNT Register Definition
FILTERING CONTROL
The ADIS16201 has the ability to perform basic filtering on the
seven output data variables through the AVG_CNT control
register. The filtering performed is that of a low-pass, moving
average filter. The size of the data being averaged (number of
filter taps) is determined through the AVG_CNT control
register. The filtering applied through the AVG_CNT control
register is applied to all seven data output variables concurrently
and, thus, one output variable cannot be filtered differently
from another.
Address
0x39, 0x38
1
Default1
0x0006
Format
Binary
Access
R/W
Default is valid only until the first register write cycle.
The AVG_CNT register contains information that represents
the number of averages to be applied to the output data. The
number of averages can be calculated by powers of 2. For
example, the default value of the register, 4, would result in 16
averages applied to the output data. The number of averages can
be set to 1, 2, 4, 8, 16, 32, 64, 128, and 256.
Table 25. AVG_CNT Bit Description
The number of taps (N) within the moving average filter is
calculated as
N 2
Bit
15:4
3:0
AVG _ CNT
where AVG_CNT is shown as a decimal value. With AVG_CNT
set to 00h, N is reduced to 1, which effectively disables the
moving average filter.
At the other extreme, when AVG_CNT is set to its maximum
setting of 08h, N increases to 256, effectively reducing the
apparent bandwidth by 256. Note that the contribution from
each tap is set to 1/(N) allowing for unity gain in the filter
response. The frequency response of the moving average filter is
given as:
H( f ) 
sin(  N  f  t s )
N sin(  f  t s )
Description
Not used
Data bits (maximum = 1000, or a decimal value of 8)
POWER-DOWN CONTROL
The ADIS16201 has the ability to power down for user-defined
amounts of time, using the PWR_MDE control register. The
amount of time specified by the PWR_MDE control register is
equal to the binary count of the 8-bit control word multiplied
by 0.5 seconds. Therefore, the 255 codes cover an overall
shutdown time period of 127.5 seconds. The PWR_MDE
register is volatile and is set to 0 upon both initial power-up and
subsequent wake-ups from the power-down period. By setting
the PWR_MDE control register to a non-zero state, the
ADIS16201 automatically powers down once the next sample
period is completed and the seven data output registers are
updated.
The more taps, the more poles, thus the steeper the slope of the
roll-off. Use caution with this filter mechanism because the
amplitudes of the sideband peaks within the stop band are not
reduced with an increasing number of taps, potentially allowing
for high frequency components to leak through. Sample
Rev. C | Page 24 of 32
Data Sheet
ADIS16201
Once the ADIS16201 is placed into the power-down mode, it
can only return to normal operation by timing out, a reset
command (using the RST hardware control line), or by cycling
the power applied to the part. Once awake, the seven data
output registers can be scanned to determine what the state of
the output registers were prior to powering down. Once the
data is recovered, the device can be powered down again by
writing a non-zero value to the PWR_MDE control register and
starting the process over.
STATUS Register Definition
Once the power-down time is complete, the recovery time for
the ADIS16201 is approximately 2 ms. This recovery time is
implemented within the device to allow for recovery of the ADC
prior to performing the next data conversion. Note that the ND
data bit within the seven data output control registers is cleared
when the ADIS16201 is powered down. Likewise, the new data
hardware I/O line is placed into an inactive state prior to being
powered down. The DAC is placed into a power-down mode as
well, which results in the DAC output dropping to 0 V during
the power-down period. All control register settings are retained
while powered down with the exception of the PWR_MDE
control register, which is reset to 0 prior to power-down.
Table 27. STATUS Bit Descriptions
Address
0x3D, 0x3C
1
1
Default1
0x0000
Format
Binary
Access
R/W
Default is valid only until the first register write cycle.
Table 26. PWR_MDE Bit Descriptions
Bit
15:8
7:0
Description
Not used
Data bits
STATUS FEEDBACK
The status control register within the ADIS16201 is utilized in
determining the present state of the device. The ability to monitor
the device becomes necessary when and if the ADIS16201 has
registered an alarm or error condition as indicated by the “alarm
enable” (14) within the seven output data registers. The 16-bit
status register is broken into two bytes. The three lower bits of the
lower data byte are used to indicate which error condition exists,
while the two lower bits of the upper data byte are utilized in
indicating which alarm condition exists.
Access
Read only
The STATUS control register contains the alarm/error flags that
indicate abnormal operating conditions. See Table 27 for each
status bit definition. All flags are cleared upon the reading of the
status register. The flags are set on a continuing basis as long as
the error or alarm conditions persist.
Bit
15:10
9
8
7:4
3
2
The power-down period is determined by multiplying the
binary value represented by the data bits times the constant
0.5 seconds. This results in a variable power-down period of
0.5 seconds to 127.5 seconds with 0.5 seconds resolution in the
setting. A setting of 0 disables the power-down mode, whereas
any non-zero entry places the device in the power-down mode
at the next update of the data output registers. The power-down
register is volatile and is set to all 0s upon initial power-up and
recovery from the power-down mode.
Format
N/A
Default is valid only until the first register write cycle.
PWR_MDE Register Definition
Address
0x3B, 0x3A
Default1
0x0000
1
0
Description
Not used.
Alarm 2 status.
1: Active
0: Normal mode
Alarm 1 status.
1: Active
0: Normal mode
Not used.
SPI communications failure.
1: Error condition
0: Normal mode
Control register update failed.
1: Error condition
0: Normal mode
Power supply above 3.625 V.
1: Error condition
0: Normal mode
Power supply below 2.975 V.
1: Error condition
0: Normal mode
COMMAND CONTROL
The COMMAND control register is utilized in sending global
commands to the ADIS16201 device. There are four separate
commands that act as global commands in the controlling of
the ADIS16201 operation. Any one of the four commands can
be implemented by writing 1 to its corresponding bit location.
The command control register has write-only capability and is
volatile.
Table 28 describes each of these global commands.
COMMAND Register Definition
Address
0x3F, 0x3E
1
Default1
0x0000
Format
N/A
Default is valid only until the first register write cycle.
Rev. C | Page 25 of 32
Access
Write only
ADIS16201
Data Sheet
Table 28. COMMAND Bit Descriptions
Bit
15:8
7
6:4
3
2
1
0
Description
Not used.
Software Reset Command. Allows for resetting of the
device via the SPI.
Not used.
Manual Flash Update Command. This command is
utilized in updating all of the nonvolatile registers to
flash. Once the command is initiated, the supply
voltage, VDD, must remain within specified limits for
50 ms to assure proper update of the nonvolatile
registers to flash.
Auxiliary DAC Latch Command. This command acts to
latch the AUX_DAC control register data into the
auxiliary DAC upon receipt of the command. This allows
for sequential loading of the upper and lower AUX_DAC
data bytes via the SPI without having the auxiliary DAC
transition into unwanted, intermediate states based
upon the individual AUX_DAC data bytes. Once the two
bytes of AUX_DAC are loaded, the DAC latch command
is initiated to move the data into the auxiliary DAC itself.
Factory Reset Command. Allows the user to reset all
four system level offset registers and all four system
level scale registers to the nominal settings (000h and
800h, respectively) upon receipt of command. Data
within the moving average filters will likewise be reset.
As the manual flash command identified below, this
command stores all of the nonvolatile registers to flash.
Once the command is initiated, the supply voltage, VDD,
must remain within specified limits for 50 ms to assure
proper update of the nonvolatile registers to flash.
Null Command. Loads the X/Y inclination offset as well
as the X/Y acceleration offset registers with values that
zero out the inclination and acceleration outputs.
Useful as a single command to simultaneously zero
both inclination and acceleration outputs. As the
manual flash command identified below, this command
stores all of the nonvolatile registers to flash. Once the
command is initiated, the supply voltage, VDD, must
remain within specified limits for 50 ms to assure
proper update of the nonvolatile registers to flash.
MISCELLANEOUS CONTROL REGISTER
The MSC_CTRL control register within the ADIS16201
provides control of two miscellaneous functions: the data-ready
hardware I/O function and the self-test function. The bits to
control these two functions are shown in Table 29.
The operation of the data-ready hardware I/O function is very
similar to the alarm hardware I/O function (controlled through
the ALM_CTRL control register). In this case, the MSC_CNTRL
register can be used in setting up one of the two GPIO pins to
serve as the hardware output pin that indicates when the
sampling, conversion, and processing of the seven data output
variables has been completed. This register provides the ability
to enable the data-ready hardware function and establish its
polarity.
The data-ready hardware I/O pin is reset automatically to an
inactive state part way through the next conversion cycle,
resulting in a pulse train with a duty cycle varying from ~15%
to 35%, depending upon the sample period setting. Upon
completion of the next sample/conversion/processing cycle, the
data ready hardware I/O line is reasserted.
The MSC_CTRL, ALM_CTRL, and GPIO_CTRL control
registers can influence the same GPIO pins. A priority level has
been established to avoid conflicting assignments of the two
GPIO pins. This priority level is defined as MSC_CTRL and has
precedence over ALM_CTRL, which has precedence over
GPIO_CTRL.
The self-test enable bit allows the user to place the ADIS16201
into a diagnostics mode for purposes of verifying the base
sensor’s operation. When this bit is set high, an electrostatic
force is generated internally to the sensor. The resulting
movement within the sensor allows the end user to test if the
accelerometer is functional. Typical change in the output is
328 mg (corresponding to 708 LSB). Once the self-test enable
bit is returned to a low state, normal operation is resumed.
MSC_CTRL Register Definition
Address
0x35, 0x34
1
Default1
0x0000
Format
N/A
Access
R/W
Default is valid only until the first register write cycle.
The 16-bit miscellaneous control register is used in the
controlling of the self-test and data-ready hardware functions.
This includes turning on and off the self-test function, as well as
enabling and configuring the data-ready function. For the dataready function, the written values are nonvolatile, allowing for
data recovery upon reset. The self-test data is volatile and is set
to 0s upon reset. This register has read/write capability.
Table 29. MSC_CTRL Bit Descriptions
Bit
15:9
8
7:3
2
1
0
Rev. C | Page 26 of 32
Description
Not used.
Self-test enable.
1: ST enabled
0: ST disabled
Not used.
Data-ready enable.
1: DR enabled
0: DR disabled
Data-ready polarity.
1: Active high
0: Active low
Data-ready line select.
1: DIO1
0: DIO0
Data Sheet
ADIS16201
PERIPHERALS
AUXILIARY ADC FUNCTION
AUXILIARY DAC FUNCTION
The auxiliary ADC function integrates a standard 12-bit ADC
into the ADIS16201 to digitize other system-level analog signals.
The output of the ADC can be monitored through the AUX_ADC
control register, as defined in Table 6 and Table 7. The ADC
consists of a 12-bit successive approximation converter. The
output data is presented in straight binary format, with the full
scale range extending from 0 V to VREF. A high precision, low
drift, factory-calibrated 2.5 V reference is also provided.
The auxiliary DAC function integrates a standard 12-bit DAC
into the ADIS16201. The DAC output is buffered and fed offchip to allow for the control of miscellaneous system-level
functions. Data is downloaded through the writing of two
adjacent data bytes, as defined in its register definition. To
prevent the DAC from transitioning through inadvertent states
during data downloads, a single command is used to
simultaneously latch both data bytes into the DAC after they
have been written into the AUX_DAC control register. This
command is implemented by writing 1 to Bit 2 of the command
control register, which, once received, results in the DAC output
transitioning to the desired state.
Figure 38 shows the equivalent circuit of the analog input
structure of the ADC. The input capacitor, C1, is typically 4 pF
and can be attributed to parasitic package capacitance. The two
diodes provide ESD protection for the analog input. Care must
be taken to ensure that the analog input signals never exceed
the supply rails by more than 300 mV. This would cause these
diodes to become forward-biased and start conducting. They
can handle 10 mA without causing irreversible damage to the
part. The resistor is a lumped component that represents the on
resistance of the switches. The value of this resistance is typically
100 Ω. Capacitor C2 represents the ADC sampling capacitor
and is typically 16 pF.
VDD
C1
D
R1 C2
AUX_DAC Register Definition
05462-038
D
The DAC output provides an output range of 0 V to 2.5 V. The
DAC output buffer features a true rail-to-rail output stage. This
means that, unloaded, the output is capable of reaching within
5 mV of ground. Moreover, the DAC’s linearity performance
(when driving a 5 kΩ resistive load to ground) is good through
the full transfer function, except for Code 0 to Code 100.
Linearity degradation near ground is caused by saturation of the
output amplifier. As the output is forced to sink more current,
the nonlinear region at the bottom of the transfer function
becomes larger. Larger current demands can significantly limit
output voltage swing.
Address
0x31, 0x30
Figure 38. Equivalent Analog Input Circuit
Conversion Phase: Switch Open
Track Phase: Switch Closed
1
For ac applications, removing high frequency components from
the analog input signal is recommended through the use of an
RC low-pass filter on the relevant analog input pins.
In applications where harmonic distortion and signal-to-noise
ratio are critical, the analog input should be driven from a low
impedance source. Large source impedances significantly affect
the ac performance of the ADC. This can necessitate the use of
an input buffer amplifier. When no input amplifier is used to
drive the analog input, the source impedance should be limited
to values lower than 1 kΩ. The maximum source impedance
depends on the amount of total harmonic distortion (THD)
that can be tolerated.
Default1
0x0000
Format
Binary
Access
R/W
Default is valid only until the first register write cycle.
The AUX_DAC register controls the ADIS16201’s DAC function.
The data bits provide a 12-bit binary format number with 0
representing 0 V and 0x0FFFh representing 2.5 V. The data
within this register is volatile and is set to 0s upon reset. This
register has read/write capability.
Table 30. AUX_DAC Bit Descriptions
Bit
15:12
11:0
Rev. C | Page 27 of 32
Description
Not used
Data bits
ADIS16201
Data Sheet
Table 31. GPIO_CTRL Bit Descriptions
GENERAL PURPOSE I/O CONTROL
As previously noted, the ADIS16201 provides two generalpurpose, bidirectional I/O pins (GPIOs) that are available to the
user for control of auxiliary circuits within the target application.
All I/O pins are 5 V tolerant, meaning that the GPIOs support
an input voltage of 5 V. All GPIO pins have an internal pull-up
resistor of approximately 100 kΩ, and their drive capability is
1.6 mA. The direction, as well as the logic level, can be
controlled for these GPIO pins through the GPIO_CTRL
control register, as defined in Table 31.
These same GPIO pins are also controllable through the
ALM_CTRL and MSC_CTRL control registers. The priority for
these three control registers in controlling the two GPIO pins is
MSC_CTRL has precedence over ALM_CTRL, which has
precedence over GPIO_CTRL.
Bit
15:10
9
8
7:2
1
0
GPIO_CTRL Register Definition
Address
0x33, 0x32
1
Default1
0x0000
Format
N/A
Access
R/W
Default is valid only until the first register write cycle.
Auxiliary Digital I/O Control Register. The data within this
register is volatile and is set to 0s upon reset.
Rev. C | Page 28 of 32
Description
Not used.
General-Purpose I/O Line 1 polarity.
0: Low
1: High
General-Purpose I/O Line 0 polarity.
0: Low
1: High
Not used.
General-Purpose I/O Line 1, data direction control.
0: Input
1: Output
General-Purpose I/O Line 0, data direction control.
0: Input
1: Output
Data Sheet
ADIS16201
APPLICATIONS
X_ACCL OUT = –2162LSB
Y_ACCL OUT = 0LSB
SERIAL PERIPHERAL INTERFACE (SPI)
1
X_ACCL OUT = 0LSB
Y_ACCL OUT = –2162LSB
1
BOTTOM
VIEW
(Not to Scale)
DOUT
The data out pin (DOUT) is an output pin used to transmit
data out of the ADIS16201. The data is transmitted in a 16-bit
(2–byte) format, MSB first.
1
X_ACCL OUT = 0LSB
Y_ACCL OUT = +2162LSB
DIN
The data-in pin (DIN) is an input pin that is used for the
reception of data from the master. The data is received in a
16-bit (2-byte) format with the W/R control bit and address
contained in the first data byte and the data contained within
the second data byte, MSB first.
1
X_ACCL OUT = +2162LSB
Y_ACCL OUT = 0LSB
EARTH’S SURFACE
SCLK
The serial clock pin (SCLK) is used to synchronize the data
being transmitted and received through the SCLK period.
Therefore, a 16-bit (2-byte) word is transmitted/received after
16 SCLK periods. The SCLK pin is configured as an input.
CS
In the ADIS16201 a transfer is initiated by the assertion of the
chip select pin (CS), which is an active-low signal. The SPI port
then transmits and receives data in 16-bit blocks until the
transfer is concluded by de-assertion of CS.
The control registers within the ADIS16201 are based upon a
16-bit (2-byte) format. Data is loaded in from the DIN pin of
the ADIS16201 on the rising edge of SCLK. This requires 16
serial clocks for every data transfer framed by the low period of
the CS line. The part operates in full duplex mode with the data
clocked out of the DOUT pin, likewise on the rising edge of the
SCLK. For each read command received, the corresponding
output data is clocked out of the DOUT pin during the
following cycle, as defined by the CS line.
OUTPUT RESPONSE
Figure 39 displays the typical output response for the
ADIS16201 for several gravitational measurement orientations.
This is a convenient plot for understanding the basic orientation
of the inertial sensor measurement axes.
NOTES
1. DATA SHOWN IN TWOS COMPLEMENT FORMAT.
05462-039
The ADIS16201 integrates a hardware SPI on-chip. SPI is an
industry-standard synchronous serial interface that allows data
to be transmitted and received simultaneously, that is, full duplex
up to a maximum bit rate of 2.5 Mbps depending upon the
sample period selection. The SPI port is configured for slave
operation and consists of four pins.
Figure 39. Output Response vs. Orientation
HARDWARE CONSIDERATIONS
The ADIS16201 can be operated from a single 3.3 V (3.0 V to
3.6 V) power supply. The ADIS16201 integrates two decoupling
capacitors that are 1 μF and 0.1 μF in value. For the local
operation of the ADIS16201, no additional power supply
decoupling capacitance is required.
However, if the system power supply presents a substantial
amount of noise, additional filtering can be required. If
additional capacitors are required, connect the ground terminal
of each of these capacitors directly to the underlying ground
plane. Finally, note that all analog and digital grounds should be
referenced to the same system ground reference point.
GROUNDING AND BOARD LAYOUT RECOMENDATIONS
Maintaining low impedance signal return paths can be very
critical in managing system-level noise effects. For best results,
use a single, continuous ground plane that is tied to each
ADIS16201 ground pin via short via and trace lengths. In
addition to maintaining a low-impedance ground structure,
routing the SPI signals away from any sensitive analog circuits,
such as the ADC and DACs (if they are in use), can help
mitigate system-level noise risks.
Rev. C | Page 29 of 32
ADIS16201
Data Sheet
BANDGAP REFERENCE
The ADIS16201 provides an on-chip band gap reference of
2.5 V, which is utilized by the on-board ADC and DAC. This
internal reference also appears on the VREF pin. This reference
can be connected to external circuits in the system. An external
buffer would be required because of the low drive capability of
the VREF output.
CRITICAL ZONE
TL TO TP
tP
TP
TEMPERATURE
RAMP-UP
TL
tL
TSMAX
TSMIN
tS
RAMP-DOWN
05462-042
PREHEAT
POWER-ON RESET OPERATION
t25°C TO PEAK
An internal power-on reset (POR) is implemented internally to
the ADIS16201. For VDD below 2.35 V, the internal POR holds
the ADIS16201 in reset. As VDD rises above 2.35 V, an internal
timer times out for typically 130 ms before the part is released
from reset. The user must ensure that the power supply has
reached a stable 3.0 V minimum level by this time. Likewise,
on power-down, the internal POR holds the ADIS16201 in reset
until VDD has dropped below 2.35 V. Figure 40 illustrates the
operation of the internal POR in detail.
TIME
Figure 41. Acceptable Solder Reflow Profiles
Table 32.
Profile Feature
Average Ramp Rate (TL to TP)
Preheat
Minimum Temperature (TSMIN)
Maximum Temperature (TSMAX)
Time (TSMIN to TSMAX) (ts)
2.35V TYP
VDD
05462-040
130ms TYP
POR
Figure 40. Internal Power-On Reset Operation
TSMAX to TL
Ramp-Up Rate
Time Maintained Above
Liquidous (TL)
Liquidous Temperature (TL)
Time (tL)
Peak Temperature (TP)
SECOND-LEVEL ASSEMBLY
The ADIS16201 can be attached to the second-level assembly
board using SN63 (or equivalent) or lead-free solder. Figure 41
and Table 32 provide acceptable solder reflow profiles for each
solder type. Note: These profiles may not be the optimum
profile for the user’s application. In no case should 260°C be
exceeded. It is recommended that the user develop a reflow
profile based upon the specific application. In general, keep in
mind that the lowest peak temperature and shortest dwell time
above the melt temperature of the solder result in less shock and
stress to the product. In addition, evaluating the cooling rate
and peak temperature can result in a more reliable assembly.
Time Within 5°C of Actual Peak
Temperature (tp)
Ramp-Down Rate
Time 25°C to Peak Temperature
Condition
Sn63/Pb37
3°C/sec max
Pb-Free
3°C/sec max
100°C
150°C
60 sec to
120 sec
150°C
200°C
60 sec to
150 sec
3°C/sec
3°C/sec
183°C
60 sec to
150 sec
240°C +
0°C/–5°C
10 sec to
30 sec
6°C/sec max
6 min max
217°C
60 sec to
150 sec
260°C +
0°C/–5°C
20 sec to
40 sec
6°C/sec max
8 min max
EXAMPLE PAD LAYOUT
1.178 BSC
(8 PLCS)
0.670 BSC
(12 PLCS)
7.873 BSC
(2 PLCS)
0.500 BSC
(16 PLCS)
Figure 42. Example Pad Layout
Rev. C | Page 30 of 32
05462-041
1.127 BSC
(16 PLCS)
Data Sheet
ADIS16201
OUTLINE DIMENSIONS
5.391
BSC
(4×)
2.6955
BSC
(8×)
9.35
9.20 SQ
9.05
13
PIN 1
INDICATOR
1.000 BSC
(16×)
16
12
1
8.373
BSC
(2×)
0.797 BSC
(12×)
9
4
8
0.200
MIN
(ALL SIDES)
TOP VIEW
5
BOTTOM VIEW
0.373 BSC
(16×)
5.00
TYP
121409-C
3.90
MAX
SIDE VIEW
Figure 43. 16-Terminal Stacked Land Grid Array [LGA]
(CC-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADIS16201CCCZ
ADIS16201/PCB
1
Temperature Range
−40°C to +125°C
Package Description
16-Terminal Stacked Land Grid Array [LGA]
Evaluation Board
Z = RoHS Compliant Part.
Rev. C | Page 31 of 32
Package Option
CC-16-2
ADIS16201
Data Sheet
NOTES
©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05462-0-8/13(C)
Rev. C | Page 32 of 32