AD AD645J Low noise, low drift fet op amp Datasheet

a
Low Noise, Low Drift
FET Op Amp
AD645
FEATURES
Improved Replacement for Burr-Brown
OPA-111 and OPA-121 Op Amp
LOW NOISE
2 mV p-p max, 0.1 Hz to 10 Hz
10 nV/√Hz max at 10 kHz
11 fA p-p Current Noise 0.1 Hz to 10 Hz
CONNECTION DIAGRAMS
TO-99 (H) Package
8-Pin Plastic Mini-DIP
(N) Package
CASE
ED
V
O T
PR RIF
M
I D
HIGH DC ACCURACY
250 mV max Offset Voltage
1 mV/8C max Drift
1.5 pA max Input Bias Current
114 dB Open-Loop Gain
Available in Plastic Mini-DIP, 8-Pin Header Packages, or
Chip Form
APPLICATIONS
Low Noise Photodiode Preamps
CT Scanners
Precision I-V Converters
PRODUCT DESCRIPTION
The AD645 is a low noise, precision FET input op amp. It offers the pico amp level input currents of a FET input device
coupled with offset drift and input voltage noise comparable to a
high performance bipolar input amplifier.
The AD645 has been improved to offer the lowest offset drift in
a FET op amp, 1 µV/°C. Offset voltage drift is measured and
trimmed at wafer level for the lowest cost possible. An inherently low noise architecture and advanced manufacturing techniques result in a device with a guaranteed low input voltage
noise of 2 µV p-p, 0.1 Hz to 10 Hz. This level of dc performance
along with low input currents make the AD645 an excellent
choice for high impedance applications where stability is of
prime concern.
OFFSET
NULL
–IN
2
+IN
3
–VS
4
AD645
8
1
7
+V
7 +VS
– IN
2
6
OUTPUT
6 OUTPUT
TOP VIEW
3
5 OFFSET
NULL
+ IN
AD645
5
4
OFFSET
NULL
–V
NC = NO CONNECT
NOTE: CASE IS CONNECTED
TO PIN 8
The AD645 is available in six performance grades. The AD645J
and AD645K are rated over the commercial temperature range
of 0°C to +70°C. The AD645A, AD645B, and the ultraprecision AD645C are rated over the industrial temperature
range of –40°C to +85°C. The AD645S is rated over the military
temperature range of –55°C to +125°C and is available
processed to MIL-STD-883B.
The AD645 is available in an 8-pin plastic mini-DIP, 8-pin
header, or in die form.
PRODUCT HIGHLIGHTS
1. Guaranteed and tested low frequency noise of 2 µV p-p max
and 20 nV/√Hz at 100 Hz makes the AD645C ideal for low
noise applications where a FET input op amp is needed.
2. Low VOS drift of 1 µV/°C max makes the AD645C an excellent choice for applications requiring ultimate stability.
3. Low input bias current and current noise (11 fA p-p 0.1 Hz to
10 Hz) allow the AD645 to be used as a high precision
preamp for current output sensors such as photodiodes, or as
a buffer for high source impedance voltage output sensors.
30
1k
25
NUMBER OF UNITS
VOLTAGE NOISE SPECTRAL DENSITY
nV/ Hz
OFFSET
NULL
8 NC
1
100
10
20
15
10
5
0
1.0
1
10
100
FREQUENCY – Hz
1k
10k
Figure 1. AD645 Voltage Noise Spectral Density vs.
Frequency
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
2.5
INPUT OFFSET VOLTAGE DRIFT– µV/ °C
Figure 2. Typical Distribution of Average Input Offset
Voltage Drift (196 Units)
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD645–SPECIFICATIONS(@ +258C, and 615 V dc, unless otherwise noted)
Model
Conditions1
INPUT OFFSET VOLTAGE 1
Initial Offset
Offset
Drift (Average)
vs. Supply (PSRR)
vs. Supply
Min
AD645J/A
Typ
Max
Min
AD645K/B
Typ Max
Min
AD645S
Typ Max
Units
100
500
4
110
95
500
1500
10
µV
µV
µV/°C
dB
dB
3
1.8
5
pA
0.5
1800
1.9
0.1
1.0
pA
pA
pA
500
1000
10/5
TMIN –TMAX
VCM = 0 V
0.7/1.8
3/5
VCM = 0 V
VCM = +10 V
VCM = 0 V
16/115
0.8/1.9
0.1
1.0
VCM = 0 V
2/6
INPUT VOLTAGE NOISE
0.1 to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
1.0
20
10
9
8
3.0
50
30
15
10
1.0
20
10
9
8
2.5
40
20
12
10
1
20
10
9
8
2
40
20
12
10
1.0
20
10
9
8
3.3
50
30
15
10
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
INPUT CURRENT NOISE
f = 0.1 to 10 Hz
f = 0.1 thru 20 kHz
11
0.6
20
1.1
11
0.6
15
0.8
11
0.6
15
0.8
11
0.6
20
1.1
fA p-p
fA/√Hz
INPUT BIAS CURRENT 2
Either Input
Either Input
@ TMAX
Either Input
Offset Current
Offset Current
@ TMAX
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew Rate, Unity Gain
SETTLING TIME 3
To 0.1%
To 0.01%
Overload Recovery 4
Total Harmonic
Distortion
INPUT IMPEDANCE
Differential
Common-Mode
INPUT VOLTAGE RANGE
Differential5
Common-Mode Voltage
Over Max Oper. Range
Common-Mode
Rejection Ratio
90
94
90
2
VO = 20 V p-p
RLOAD = 2 kΩ
VOUT = 20 V p-p
RLOAD = 2 kΩ
50
75
0.5
110
100
250
300
1
0.7/1.8 1.5/3
1.8
16/115
0.8/1.9
0.1
0.5
115
1.9
0.1
2/6
6
94
90
2
90
86
100
2
pA
2
MHz
16
32
16
32
16
32
16
32
kHz
1
2
1
2
1
2
1
2
V/µs
50% Overdrive
f = 1 kHz
RLOAD ≥ 2 kΩ
VO = 3 V rms
VDIFF = ± 1 V
± 10
± 10
VCM = ± 10 V
TMIN–TMAX
250
400
5/2
AD645C
Typ Max
100
300
3
110
100
TMIN –TMAX
50
100
1
110
100
Min
6
8
5
6
8
5
6
8
5
6
8
5
µs
µs
µs
0.0006
0.0006
0.0006
0.0006
%
1012i1
1014i2.2
1012i1
1014i2.2
1012i1
1014i2.2
1012i1
1014i2.2
ΩipF
ΩipF
± 20
+11, –10.4
V
V
V
± 20
+11, –10.4
± 10
± 10
± 20
+11, –10.4
± 10
± 10
± 20
+11, –10.4
± 10
± 10
90
110
100
94
90
110
100
94
90
110
100
90
86
110
100
dB
dB
114
130
120
114
130
120
114
130
114
110
130
dB
dB
OUTPUT CHARACTERISTICS
Voltage
RLOAD ≥ 2 kΩ
TMIN –TMAX
Current
VOUT = ± 10 V
Short Circuit
± 10
± 10
±5
± 11
± 10
± 10
±5
± 11
± 10
± 10
±5
± 11
± 10
± 10
±5
± 11
V
V
mA
mA
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Transistor Count
±5
OPEN-LOOP GAIN
VO = ± 10 V
RLOAD ≥ 2 kΩ
TMIN –TMAX
# of Transistors
± 10
± 15
± 15
3.0
62
± 18
3.5
±5
± 10
± 15
± 15
3.0
62
± 18
3.5
±5
± 10
± 15
± 15
3.0
62
± 18
3.5
±5
± 10
± 15
± 15
3.0
62
± 18
3.5
V
V
mA
NOTES
1
Input offset voltage specifications are guaranteed after 5 minutes of operation at T A = +25°C.
2
Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperature, the current doubles every 10°C.
3
Gain = –1, RLOAD = 2 kΩ.
4
Defined as the time required for the amplifier’s output to return to normal operation after removal of a 50% overload from the amplifier input.
5
Defined as the maximum continuous voltage between the inputs such that neither input exceeds ± 10 V from ground.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
–2–
REV. B
AD645
ABSOLUTE MAXIMUM RATINGS 1
AD645A/B/C . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD645S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range
(Soldering 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2 (@ TA = +25°C)
8-Pin Header Package . . . . . . . . . . . . . . . . . . . . . . 500 mW
8-Pin Mini-DIP Package . . . . . . . . . . . . . . . . . . . . 750 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage Temperature Range (H) . . . . . . . . . –65°C to +150°C
Storage Temperature Range (N) . . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD645J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2
Thermal Characteristics:
8-Pin Plastic Mini-DIP Package: θJA = 100°C/Watt
8-Pin Header Package: θJA = 200°C/Watt
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD645 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
METALIZATION PHOTOGRAPH
ORDERING GUIDE
Model1
Temperature Range
Package Option2
AD645JN
AD645KN
AD645AH
AD645BH
AD645CH
AD645SH/883B
0°C to +70°C
0°C to +70°C
– 40°C to +85°C
– 40°C to +85°C
– 40°C to +85°C
– 55°C to +125°C
N-8
N-8
H-08A
H-08A
H-08A
H-08A
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
NOTES
1
Chips are also available.
2
N = Plastic Mini-DIP; H = Metal Can.
+VS
7
2
AD645
3
6
5
1
10k
4
VOS ADJUST
–VS
Figure 3. AD645 Offset Null Configuration
25
120
800
110
700
500
400
300
200
20
90
NUMBER OF UNITS
NUMBER OF UNITS
NUMBER OF UNITS
100
600
80
70
60
50
40
30
15
10
5
20
100
10
0
–1.0 –0.8 –0.6 –0.4 –0.2 0.0
0
0.2
0.4
0.6
0.8
1.0
INPUT OFFSET VOLTAGE – mV
Figure 4. Typical Distribution of Input
Offset Voltage (1855 Units)
REV. B
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
INPUT BIAS CURRENT – pA
Figure 5. Typical Distribution of Input
Bias Current (576 Units)
–3–
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
INPUT VOLTAGE NOISE – µV p-p
Figure 6. Typical Distribution of 0.1 Hz
to 10 Hz Voltage Noise (202 Units)
AD645–Typical Characteristics (@ +258C, 615 V unless otherwise noted)
1k
1000
100
10
10
100
1k
10k
100k
1
1M
10
100
1k
10k
1
0.1
100k
Figure 7. Current Noise Spectral
Density vs. Frequency
10
VOLTAGE NOISE
–
20
NOISE BANDWIDTH: 0.1 to 10Hz
10
CURRENT NOISE
1
15
10
0.1
VOLTAGE NOISE
1.0
10 5
10 6
10 7
SOURCE RESISTANCE – Ω
10 9
10 8
Figure 10. Input Voltage Noise vs.
Source Resistance
5
– 60 – 40
– 20
0
20
40
60
80
0.01
100 120 140
CURRENT NOISE – fA/√Hz
nV/ √Hz
fo = 1kHz
100
TEMPERATURE – C
25
0
– 25
– 50
1
2
3
4
5
WARM-UP TIME – Minutes
Figure 13. Change in Input Offset
Voltage vs. Warmup Time
75
TA = 25°C TO TA = 85°C
0
–75
100
NOISE OF AD645
AND RESISTOR
10
SOURCE
RESISTANCE
RESISTOR NOISE
ONLY
1.0
100
1k
10k
100k
1M
10M
–150
1
2
3
4
TIME FROM THERMAL SHOCK – Minutes
Figure 14. Change in Input Offset
Voltage vs. Time from Thermal
Shock
–4–
100M
10 – 9
5
10 – 10
10 – 10
INPUT
BIAS
CURRENT
10 –11
10 – 11
10 –12
10 – 12
INPUT
OFFSET
CURRENT
10
0
100k
1k
10 – 9
INPUT BIAS CURRENT – Amps
CHANGE IN INPUT OFFSET VOLTAGE – µV
TA = +25 C
10k
Figure 12. Voltage Noise Spectral
Density @ 1 kHz vs. Source
Resistance
150
VS = ±15V
1k
SOURCE RESISTANCE – Ω
Figure 11. Voltage and Current
Noise Spectral Density vs.
Temperature
50
100
Figure 9. Voltage Noise Spectral
Density vs. Frequency for Various
Source Resistances
100
25
0
10
FREQUENCY – Hz
Figure 8. Voltage Noise Spectral
Density vs. Frequency
1k
10 4
1.0
FREQUENCY – Hz
FREQUENCY – Hz
10 3
RS = 100Ω
10
VOLTAGE NOISE SPECTRAL DENSITY @ 1kHz – nV/√Hz
1
INPUT VOLTAGE NOISE – µV p-p
RS = 100kΩ
0
0.1
CHANGE IN INPUT OFFSET VOLTAGE – µV
RS = 1MΩ
100
– 13
10 – 14
– 60 – 40
10
– 20
0
20
40
60
– 13
INPUT OFFSET CURRENT – Amps
1.0
VOLTAGE NOISE SPECTRAL DENSITY – nV
10
RS = 10MΩ
Hz
Hz
VOLTAGE NOISE SPECTRAL DENSITY – nV/
CURRENT NOISE SPECTRAL DENSITY – fA/√Hz
100
10 – 14
80 100 120 140
TEMPERATURE – C
Figure 15. Input Bias and Offset
Currents vs. Temperature
REV. B
AD645
1.0
100
COMMON-MODE REJECTION – dB
TA = +25°C
VS = ±15V
H PACKAGE
POWER SUPPLY REJECTION – dB
INPUT BIAS CURRENT – pA
120
120
10
+ PSRR
80
– PSRR
60
40
100
60
40
20
20
0.1
–20
80
0
0
–15 –10
–5
5
10
0
COMMON MODE VOLTAGE – Volts
15
1
10
100
1k
10k
100k
FREQUENCY – Hz
1M
1
10M
– 45
110
120
100
10k
100k
1k
FREQUENCY – Hz
1M
10M
Figure 18. Common-Mode
Rejection vs. Frequency
Figure 17. Power Supply Rejection
vs. Frequency
Figure 16. Input Bias Current vs.
Common-Mode Voltage
10
3.0
4.0
90
60
GAIN
40
–135
20
80
0
70
– 15
–5
0
5
10
15
10
Figure 19. Common-Mode
Rejection vs. Input Common-Mode
Voltage
100
1k
10k
100k
FREQUENCY – Hz
1M
0
– 60 – 40 – 20
10M
GAIN-BANDWIDTH
2.0
VS = ±15V
VO = ±10V
RL = 2kΩ
40
60
80
1.0
100 120 140
30
OUTPUT VOLTAGE – Volts p-p
2.0
OPEN-LOOP GAIN – dB
3.0
SLEW RATE
20
35
150
SLEW RATE – Volts/µs
3.0
0
Figure 21. Gain-Bandwidth Product
and Slew Rate vs. Temperature
160
4.0
2.0
TEMPERATURE – 8C
Figure 20. Open-Loop Gain and
Phase Shift vs. Frequency
4.0
GAIN-BANDWIDTH
1.0
– 20
– 10
3.0
SLEW RATE
– 180
COMMON MODE VOLTAGE – Volts
GAIN-BANDWIDTH PRODUCT – MHz
2.0
140
130
120
25
20
15
10
110
5
1.0
0
5
10
15
20
SUPPLY VOLTAGE – ±Volts
Figure 22. Gain-Bandwidth and
Slew Rate vs. Supply Voltage
REV. B
SLEW RATE – Volts/µs
100
– 90
GAIN-BANDWIDTH PRODUCT – MHz
PHASE
80
PHASE SHIFT – Degrees
110
OPEN-LOOP GAIN – dB
COMMON-MODE REJECTION – dB
100
100
– 60 – 40 – 20
0
20 40
60 80
TEMPERATURE – 8C
100 120 140
Figure 23. Open-Loop Gain vs.
Temperature
–5–
0
1k
10k
100k
FREQUENCY – Hz
1M
Figure 24. Large Signal Frequency
Response
10
100
8
90
6
80
4
FOR 10V STEP
3
0.1%
0.01%
2
0
ERROR
–2
0.1%
0.01%
70
0.01%
60
50
0.1%
40
–4
30
–6
20
–8
10
– 10
1.0
2
1
0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
SETTLING TIME – µs
Figure 25. Output Swing and Error
vs. Settling Time
7
2
10
100
CLOSED-LOOP VOLTAGE GAIN (V/V)
1k
0
–60
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE – 8C
Figure 26. Settling Time vs. ClosedLoop Voltage Gain
Figure 27. Supply Current vs.
Temperature
Figure 28b. Unity-Gain Follower
Large Signal Pulse Response
Figure 28c. Unity-Gain Follower
Small Signal Pulse Response
Figure 29b. Unity-Gain Inverter
Large Signal Pulse Response
Figure 29c. Unity-Gain Inverter
Small Signal Pulse Response
VOUT
AD645
3
1
0.1µF
+ VS
VIN
SUPPLY CURRENT – mA
4
SETTLING TIME – µs
OUTPUT SWING FROM 0V TO ±VOLTS
AD645
AD645–Typical
Characteristics
6
4
0.1µF
RL
2kΩ
– VS
CL
10pF
Figure 28a. Unity-Gain Follower
5kΩ
+VS
VIN
0.1µF
5kΩ
2
7
AD645
3
4
– VS
VOUT
6
0.1µF
RL
2kΩ
Figure 29a. Unity-Gain Inverter
CL
10pF
–6–
REV. B
AD645
Sources of noise in a typical preamp are shown in Figure 32.
The total noise contribution is defined as:
10pF
9
10 Ω
V OUT =
GUARD
2
OUTPUT
AD645
3
PHOTODIODE
6
8
FILTERED
OUTPUT
OPTIONAL 26Hz
FILTER
Figure 30. The AD645 Used as a Sensitive Preamplifier
Preamplifier Applications
The low input current and offset voltage levels of the AD645 together with its low voltage noise make this amplifier an excellent
choice for preamplifiers used in sensitive photodiode applications. In a typical preamp circuit, shown in Figure 30, the output of the amplifier is equal to:
i 2
n
+ i f 2 + is 2

Rf

  1 + s (Cf ) Rf 
2

 2 1+
+ en



 1 + s (Cd ) Rd  
Rd  1 + s (Cf ) Rf  


2
Rf
Figure 33, a spectral density versus frequency plot of each
source’s noise contribution, shows that the bandwidth of the
amplifier’s input voltage noise contribution is much greater than
its signal bandwidth. In addition, capacitance at the summing
junction results in a “peaking” of noise gain in this configuration. This effect can be substantial when large photodiodes with
large shunt capacitances are used. Capacitor Cf sets the signal
bandwidth and also limits the peak in the noise gain. Each
source’s rms or root-sum-square contribution to noise is obtained by integrating the sum of the squares of all the noise
sources and then by obtaining the square root of this sum. Minimizing the total area under these curves will optimize the
preamplifier’s overall noise performance.
Cf
10pF
Rf
9
10 Ω
VOUT = ID (Rf) = Rp (P) Rf
where:
PHOTODIODE
ID = photodiode signal current (Amps)
Rp = photodiode sensitivity (Amp/Watt)
Rd
iS
Rf = the value of the feedback resistor, in ohms.
en
if
in
iS
OUTPUT
Cd
50pF
P = light power incident to photodiode surface, in watts.
An equivalent model for a photodiode and its dc error sources is
shown in Figure 31. The amplifier’s input current, IB, will contribute an output voltage error which will be proportional to the
value of the feedback resistor. The offset voltage error, VOS, will
cause a “dark” current error due to the photodiode’s finite
shunt resistance, Rd. The resulting output voltage error, VE, is
equal to:
Figure 32. Noise Contributions of Various Sources
10µV
√
OUTPUT VOLTAGE NOISE – Volts/ Hz
is & i f
VE = (1 + Rf/Rd) VOS + Rf IB
A shunt resistance on the order of 109 ohms is typical for a
small photodiode. Resistance Rd is a junction resistance which
will typically drop by a factor of two for every 10°C rise in temperature. In the AD645, both the offset voltage and drift are
low, this helps minimize these errors.
SIGNAL BANDWIDTH
1µV
in
WITH FILTER
NO FILTER
100nV
en
en
10nV
1
Rd
ID
VOS
Cd
50pF
IB
OUTPUT
Figure 31. A Photodiode Model Showing DC Error
Sources
Minimizing Noise Contributions
The noise level limits the resolution obtainable from any preamplifier. The total output voltage noise divided by the feedback
resistance of the op amp defines the minimum detectable signal
current. The minimum detectable current divided by the photodiode sensitivity is the minimum detectable light power.
REV. B
100
1k
10k
100k
Figure 33. Voltage Noise Spectral Density of the Circuit of
Figure 32 With and Without an Output Filter
Rf
9
10 Ω
PHOTODIODE
10
FREQUENCY – Hz
Cf
10pF
An output filter with a passband close to that of the signal can
greatly improve the preamplifier’s signal to noise ratio. The photodiode preamplifier shown in Figure 32—without a bandpass
filter—has a total output noise of 50 µV rms. Using a 26 Hz
single pole output filter, the total output noise drops to 23 µV
rms, a factor of 2 improvement with no loss in signal bandwidth.
Using a “T” Network
A “T” network, shown in Figure 34, can be used to boost the effective transimpedance of an I to V converter, for a given feedback resistor value. Unfortunately, amplifier noise and offset
voltage contributions are also amplified by the “T” network
gain. A low noise, low offset voltage amplifier, such as the
AD645, is needed for this type of application.
–7–
10pF
Guarding the input lines by completely surrounding them with a
metal conductor biased near the input lines’ potential has two
major benefits. First, parasitic leakage from the signal line is
reduced, since the voltage between the input line and the guard
is very low. Second, stray capacitance at the input terminal is
minimized which in turn increases signal bandwidth. In the
header or can package, the case of the AD645 is connected to
Pin 8 so that it may be tied to the input potential (when operating as a follower) or tied to ground (when operating as an inverter). The AD645’s positive input (Pin 3) is located next to
the negative supply voltage pin (Pin 4). The negative input (Pin
2) is next to the balance adjust pin (Pin 1) which is biased at a
potential close to that of the negative supply voltage. Note that
any guard traces should be placed on both sides of the board. In
addition, the input trace should be guarded along both of its
edges, along its entire length.
RG
10kΩ
Rf
Ri
1.1kΩ
VOUT
AD645
PHOTODIODE
VOUT = ID R f (1 + RG )
Ri
Figure 34. A Photodiode Preamp Employing a “T”
Network for Added Gain
A pH Probe Buffer Amplifier
A typical pH probe requires a buffer amplifier to isolate its 106
to 109 Ω source resistance from external circuitry. Just such an
amplifier is shown in Figure 35. The low input current of the
AD645 allows the voltage error produced by the bias current
and electrode resistance to be minimal. The use of guarding,
shielding, high insulation resistance standoffs, and other such
standard methods used to minimize leakage are all needed to
maintain the accuracy of this circuit.
Contaminants such as solder flux, on the board’s surface and on
the amplifier’s package, can greatly reduce the insulation resistance and also increase the sensitivity to atmospheric humidity.
Both the package and the board must be kept clean and dry. An
effective cleaning procedure is to: first, swab the surface with
high grade isopropyl alcohol, then rinse it with deionized water,
and finally, bake it at 80°C for 1 hour. Note that if either polystyrene or polypropylene capacitors are used on the printed circuit board that a baking temperature of 70°C is safer, since both
of these plastic compounds begin to melt at approximately
+85°C.
The slope of the pH probe transfer function, 50 mV per pH unit
at room temperature, has a +3300 ppm/°C temperature coefficient. The buffer of Figure 35 provides an output voltage equal
to 1 volt/pH unit. Temperature compensation is provided by
resistor RT which is a special temperature compensation resistor, part number Q81, 1 kΩ, 1%, +3500 ppm/°C, available from
Tel Labs Inc.
VOS ADJUST
100kΩ
+VS
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
TO-99 Header (H) Package
REFERENCE PLANE
+15V
0.1µF
0.185 (4.70)
0.165 (4.19)
COM
0.1µF
– VS
0.050
(1.27)
MAX
–15V
1
GUARD
0.250 (6.35)
MIN
0.100
(2.54)
BSC
4
3
5
AD645
2
pH
PROBE
–VS
0.750 (19.05)
0.500 (12.70)
6
OUTPUT
1VOLT/pH UNIT
+ VS
0.200
(5.08)
BSC
0.370 (9.40)
0.335 (8.51)
19.6kΩ
7
3
0.100
(2.54)
BSC
0.019 (0.48)
0.016 (0.41)
0.045 (1.14)
0.010 (0.25)
0.021 (0.53)
0.016 (0.41)
0.045 (1.14)
0.027 (0.69)
8
2
0.040 (1.02) MAX
RT
1kΩ
+3500ppm/°C
6
4
0.335 (8.51)
0.305 (7.75)
7
8
0.160 (4.06)
0.110 (2.79)
5
1
0.034 (0.86)
0.027 (0.69)
45 °
BSC
BASE & SEATING PLANE
PRINTED IN U.S.A.
10 8 Ω
C1398a–24–9/91
AD645
Plastic Mini-DIP (N) Package
Figure 35. A pH Probe Amplifier
Circuit Board Notes
8
The AD645 is designed for through hole mount into PC boards.
Maintaining picoampere level resolution in that environment
requires a lot of care. Since both the printed circuit board and
the amplifier’s package have a finite resistance, the voltage difference between the amplifier’s input pin and other pins (or
traces on the PC board) will cause parasitic currents to flow into
(or out of) the signal path. These currents can easily exceed the
1.5 pA input current level of the AD645 unless special precautions are taken. Two successful methods for minimizing leakage
are: guarding the AD645’s input lines and maintaining adequate
insulation resistance.
5
0.280 (7.11)
0.240 (6.10)
PIN 1
1
4
0.325 (8.25)
0.300 (7.62)
0.430 (10.92)
0.348 (8.84)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
–8–
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
REV. B