IDT IDT82P2282PFGBLANK Dual t1/e1/j1 long haul / short haul transceiver Datasheet

Dual T1/E1/J1 Long Haul /
Short Haul Transceiver
IDT82P2282
Version 10
August 20, 2009
6024 Silver Creek Valley Road, San Jose, CA 95138
Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775
Printed in U.S.A.
© 2008 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other
rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its
safety or effectiveness.
Table of Contents
FEATURES ............................................................................................................................................................................ 12
APPLICATIONS..................................................................................................................................................................... 12
BLOCK DIAGRAM ................................................................................................................................................................ 13
1 PIN ASSIGNMENT ........................................................................................................................................................... 14
2 PIN DESCRIPTION .......................................................................................................................................................... 15
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 22
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
T1 / E1 / J1 MODE SELECTION ................................................................................................................................................................... 24
RECEIVER IMPEDANCE MATCHING .......................................................................................................................................................... 25
3.2.1 Line Monitor .................................................................................................................................................................................... 25
ADAPTIVE EQUALIZER ............................................................................................................................................................................... 28
DATA SLICER ............................................................................................................................................................................................... 28
CLOCK AND DATA RECOVERY ................................................................................................................................................................. 28
RECEIVE JITTER ATTENUATOR ................................................................................................................................................................ 29
DECODER ..................................................................................................................................................................................................... 30
3.7.1 Line Code Rule ............................................................................................................................................................................... 30
3.7.1.1 T1 / J1 Mode .................................................................................................................................................................... 30
3.7.1.2 E1 Mode ........................................................................................................................................................................... 30
3.7.2 Decode Error Detection ................................................................................................................................................................. 30
3.7.2.1 T1 / J1 Mode .................................................................................................................................................................... 30
3.7.2.2 E1 Mode ........................................................................................................................................................................... 30
3.7.3 LOS Detection ................................................................................................................................................................................ 31
FRAME PROCESSOR .................................................................................................................................................................................. 34
3.8.1 T1/J1 Mode ...................................................................................................................................................................................... 34
3.8.1.1 Synchronization Searching ............................................................................................................................................... 34
3.8.1.1.1 Super Frame (SF) Format ............................................................................................................................. 34
3.8.1.1.2 Extended Super Frame (ESF) Format ........................................................................................................... 35
3.8.1.1.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................ 36
3.8.1.1.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ...................................................................................... 37
3.8.1.2 Error Event And Out Of Synchronization Detection .......................................................................................................... 38
3.8.1.2.1 Super Frame (SF) Format ............................................................................................................................. 38
3.8.1.2.2 Extended Super Frame (ESF) Format ........................................................................................................... 38
3.8.1.2.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................ 38
3.8.1.2.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ...................................................................................... 38
3.8.1.3 Overhead Extraction (T1 Mode SLC-96 Format Only) ..................................................................................................... 39
3.8.1.4 Interrupt Summary ............................................................................................................................................................ 39
3.8.2 E1 Mode .......................................................................................................................................................................................... 41
3.8.2.1 Synchronization Searching ............................................................................................................................................... 43
3.8.2.1.1 Basic Frame .................................................................................................................................................. 43
3.8.2.1.2 CRC Multi-Frame ........................................................................................................................................... 44
3.8.2.1.3 CAS Signaling Multi-Frame ........................................................................................................................... 45
3.8.2.2 Error Event And Out Of Synchronization Detection .......................................................................................................... 45
3.8.2.2.1 Out Of Basic Frame Synchronization ............................................................................................................ 46
3.8.2.2.2 Out Of CRC Multi-Frame Synchronization .................................................................................................... 46
3.8.2.2.3 Out Of CAS Signaling Multi-Frame Synchronization ..................................................................................... 46
3.8.2.3 Overhead Extraction ......................................................................................................................................................... 46
3.8.2.3.1 International Bit Extraction ............................................................................................................................. 46
3.8.2.3.2 Remote Alarm Indication Bit Extraction ......................................................................................................... 46
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IDT82P2282
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.8.2.3.3 National Bit Extraction ................................................................................................................................... 46
3.8.2.3.4 National Bit Codeword Extraction .................................................................................................................. 46
3.8.2.3.5 Extra Bit Extraction ........................................................................................................................................ 46
3.8.2.3.6 Remote Signaling Multi-Frame Alarm Indication Bit Extraction ..................................................................... 46
3.8.2.3.7 Sa6 Code Detection Per ETS 300 233 .......................................................................................................... 46
3.8.2.4 V5.2 Link .......................................................................................................................................................................... 47
3.8.2.5 Interrupt Summary ............................................................................................................................................................ 47
PERFORMANCE MONITOR ......................................................................................................................................................................... 49
3.9.1 T1/J1 Mode ...................................................................................................................................................................................... 49
3.9.2 E1 Mode .......................................................................................................................................................................................... 51
ALARM DETECTOR ..................................................................................................................................................................................... 53
3.10.1 T1/J1 Mode ...................................................................................................................................................................................... 53
3.10.2 E1 Mode .......................................................................................................................................................................................... 55
HDLC RECEIVER .......................................................................................................................................................................................... 56
3.11.1 HDLC Channel Configuration ........................................................................................................................................................ 56
3.11.2 HDLC Mode ..................................................................................................................................................................................... 56
BIT-ORIENTED MESSAGE RECEIVER ....................................................................................................................................................... 59
INBAND LOOPBACK CODE DETECTOR (T1/J1 ONLY) ............................................................................................................................ 59
ELASTIC STORE BUFFER ........................................................................................................................................................................... 60
RECEIVE CAS/RBS BUFFER ...................................................................................................................................................................... 60
3.15.1 T1/J1 Mode ...................................................................................................................................................................................... 60
3.15.2 E1 Mode .......................................................................................................................................................................................... 61
RECEIVE PAYLOAD CONTROL .................................................................................................................................................................. 63
RECEIVE SYSTEM INTERFACE .................................................................................................................................................................. 65
3.17.1 T1/J1 Mode ...................................................................................................................................................................................... 65
3.17.1.1 Receive Clock Master Mode ............................................................................................................................................ 65
3.17.1.1.1 Receive Clock Master Full T1/J1 Mode ......................................................................................................... 65
3.17.1.1.2 Receive Clock Master Fractional T1/J1 Mode ............................................................................................... 66
3.17.1.2 Receive Clock Slave Mode .............................................................................................................................................. 66
3.17.1.3 Receive Multiplexed Mode ............................................................................................................................................... 67
3.17.1.4 Offset ................................................................................................................................................................................ 67
3.17.1.5 Output On RSDn/MRSD & RSIGn/MRSIG ....................................................................................................................... 70
3.17.2 E1 Mode .......................................................................................................................................................................................... 70
3.17.2.1 Receive Clock Master Mode ............................................................................................................................................ 70
3.17.2.1.1 Receive Clock Master Full E1 Mode ............................................................................................................. 70
3.17.2.1.2 Receive Clock Master Fractional E1 Mode ................................................................................................... 70
3.17.2.2 Receive Clock Slave Mode .............................................................................................................................................. 70
3.17.2.3 Receive Multiplexed Mode ............................................................................................................................................... 71
3.17.2.4 Offset ................................................................................................................................................................................ 71
3.17.2.5 Output On RSDn/MRSD & RSIGn/MRSIG ....................................................................................................................... 71
TRANSMIT SYSTEM INTERFACE ............................................................................................................................................................... 73
3.18.1 T1/J1 Mode ...................................................................................................................................................................................... 73
3.18.1.1 Transmit Clock Master Mode ............................................................................................................................................ 73
3.18.1.1.1 Transmit Clock Master Full T1/J1 Mode ........................................................................................................ 73
3.18.1.1.2 Transmit Clock Master Fractional T1/J1 Mode .............................................................................................. 73
3.18.1.2 Transmit Clock Slave Mode ............................................................................................................................................. 74
3.18.1.3 Transmit Multiplexed Mode .............................................................................................................................................. 75
3.18.1.4 Offset ................................................................................................................................................................................ 76
3.18.2 E1 Mode .......................................................................................................................................................................................... 79
3.18.2.1 Transmit Clock Master Mode ............................................................................................................................................ 79
3.18.2.1.1 Transmit Clock Master Full E1 Mode ............................................................................................................ 79
3.18.2.1.2 Transmit Clock Master Fractional E1 Mode .................................................................................................. 79
3.18.2.2 Transmit Clock Slave Mode ............................................................................................................................................. 79
3.18.2.3 Transmit Multiplexed Mode .............................................................................................................................................. 80
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.18.2.4 Offset ................................................................................................................................................................................ 80
3.19 TRANSMIT PAYLOAD CONTROL ............................................................................................................................................................... 81
3.20 FRAME GENERATOR .................................................................................................................................................................................. 82
3.20.1 Generation ...................................................................................................................................................................................... 82
3.20.1.1 T1 / J1 Mode .................................................................................................................................................................... 82
3.20.1.1.1 Super Frame (SF) Format ............................................................................................................................. 82
3.20.1.1.2 Extended Super Frame (ESF) Format ........................................................................................................... 82
3.20.1.1.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................ 82
3.20.1.1.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ...................................................................................... 82
3.20.1.1.5 Interrupt Summary ......................................................................................................................................... 83
3.20.1.2 E1 Mode ........................................................................................................................................................................... 84
3.20.1.2.1 Interrupt Summary ......................................................................................................................................... 85
3.20.2 HDLC Transmitter .......................................................................................................................................................................... 87
3.20.2.1 HDLC Channel Configuration ........................................................................................................................................... 87
3.20.2.2 HDLC Mode ...................................................................................................................................................................... 87
3.20.2.2.1 HDLC Mode ................................................................................................................................................... 87
3.20.2.3 Interrupt Summary ............................................................................................................................................................ 87
3.20.2.4 Reset ................................................................................................................................................................................ 87
3.20.3 Automatic Performance Report Message (T1/J1 Only) .............................................................................................................. 89
3.20.4 Bit-Oriented Message Transmitter (T1/J1 Only) .......................................................................................................................... 90
3.20.5 Inband Loopback Code Generator (T1/J1 Only) .......................................................................................................................... 90
3.20.6 All ‘Zero’s & All ‘One’s ................................................................................................................................................................... 90
3.20.7 Change Of Frame Alignment ......................................................................................................................................................... 90
3.21 TRANSMIT BUFFER ..................................................................................................................................................................................... 91
3.22 ENCODER ..................................................................................................................................................................................................... 91
3.22.1 Line Code Rule ............................................................................................................................................................................... 91
3.22.1.1 T1/J1 Mode ...................................................................................................................................................................... 91
3.22.1.2 E1 Mode ........................................................................................................................................................................... 91
3.22.2 BPV Error Insertion ........................................................................................................................................................................ 91
3.22.3 All ‘One’s Insertion ........................................................................................................................................................................ 91
3.23 TRANSMIT JITTER ATTENUATOR ............................................................................................................................................................. 92
3.24 WAVEFORM SHAPER / LINE BUILD OUT .................................................................................................................................................. 93
3.24.1 Preset Waveform Template ........................................................................................................................................................... 93
3.24.1.1 T1/J1 Mode ...................................................................................................................................................................... 93
3.24.1.2 E1 Mode ........................................................................................................................................................................... 93
3.24.2 Line Build Out (LBO) (T1 Only) ..................................................................................................................................................... 94
3.24.3 User-Programmable Arbitrary Waveform .................................................................................................................................... 94
3.25 LINE DRIVER .............................................................................................................................................................................................. 101
3.26 TRANSMITTER IMPEDANCE MATCHING ................................................................................................................................................ 102
3.27 TESTING AND DIAGNOSTIC FACILITIES ................................................................................................................................................ 103
3.27.1 PRBS Generator / Detector ......................................................................................................................................................... 103
3.27.1.1 Pattern Generator ........................................................................................................................................................... 103
3.27.1.2 Pattern Detector ............................................................................................................................................................. 103
3.27.2 Loopback ...................................................................................................................................................................................... 104
3.27.2.1 System Loopback ........................................................................................................................................................... 104
3.27.2.1.1 System Remote Loopback .......................................................................................................................... 104
3.27.2.1.2 System Local Loopback .............................................................................................................................. 104
3.27.2.2 Payload Loopback .......................................................................................................................................................... 104
3.27.2.3 Local Digital Loopback 1 ................................................................................................................................................ 104
3.27.2.4 Remote Loopback .......................................................................................................................................................... 104
3.27.2.5 Local Digital Loopback 2 ................................................................................................................................................ 104
3.27.2.6 Analog Loopback ............................................................................................................................................................ 104
3.27.3 G.772 Non-Intrusive Monitoring .................................................................................................................................................. 104
3.28 INTERRUPT SUMMARY ............................................................................................................................................................................. 107
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
4 OPERATION ................................................................................................................................................................... 108
4.1
4.2
4.3
4.4
4.5
POWER-ON SEQUENCE ............................................................................................................................................................................ 108
RESET ......................................................................................................................................................................................................... 108
RECEIVE / TRANSMIT PATH POWER DOWN .......................................................................................................................................... 108
MICROPROCESSOR INTERFACE ............................................................................................................................................................ 109
4.4.1 SPI Mode ....................................................................................................................................................................................... 109
4.4.2 Parallel Microprocessor Interface .............................................................................................................................................. 110
INDIRECT REGISTER ACCESS SCHEME ................................................................................................................................................ 111
4.5.1 Indirect Register Read Access ................................................................................................................................................... 111
4.5.2 Indirect Register Write Access ................................................................................................................................................... 111
5 PROGRAMMING INFORMATION .................................................................................................................................. 112
5.1
5.2
REGISTER MAP .......................................................................................................................................................................................... 112
5.1.1 T1/J1 Mode .................................................................................................................................................................................... 112
5.1.1.1 Direct Register ................................................................................................................................................................ 112
5.1.1.2 Indirect Register ............................................................................................................................................................. 117
5.1.2 E1 Mode ........................................................................................................................................................................................ 118
5.1.2.1 Direct Register ................................................................................................................................................................ 118
5.1.2.2 Indirect Register ............................................................................................................................................................. 123
REGISTER DESCRIPTION ......................................................................................................................................................................... 125
5.2.1 T1/J1 Mode .................................................................................................................................................................................... 126
5.2.1.1 Direct Register ................................................................................................................................................................ 126
5.2.1.2 Indirect Register ............................................................................................................................................................. 227
5.2.2 E1 Mode ........................................................................................................................................................................................ 240
5.2.2.1 Direct Register ................................................................................................................................................................ 240
5.2.2.2 Indirect Register ............................................................................................................................................................. 342
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ............................................................................................................ 357
6.1
6.2
6.3
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR) ................................................................................................................... 358
JTAG DATA REGISTER ............................................................................................................................................................................. 359
6.2.1 Device Identification Register (IDR) ........................................................................................................................................... 359
6.2.2 Bypass Register (BYP) ................................................................................................................................................................ 359
6.2.3 Boundary Scan Register (BSR) ................................................................................................................................................... 359
TEST ACCESS PORT CONTROLLER ....................................................................................................................................................... 361
7 PHYSICAL AND ELECTRICAL SPECIFICATIONS ...................................................................................................... 364
7.1
7.2
7.3
7.4
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 364
RECOMMENDED OPERATING CONDITIONS .......................................................................................................................................... 364
D.C. CHARACTERISTICS .......................................................................................................................................................................... 365
DIGITAL I/O TIMING CHARACTERISTICS ................................................................................................................................................ 366
7.4.1 In Non-Multiplexed Mode ............................................................................................................................................................. 366
7.4.2 In Multiplexed Mode ..................................................................................................................................................................... 367
7.5 CLOCK FREQUENCY REQUIREMENT ..................................................................................................................................................... 367
7.6 T1/J1 LINE RECEIVER ELECTRICAL CHARACTERISTICS .................................................................................................................... 368
7.7 E1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ......................................................................................................................... 369
7.8 T1/J1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................................................................. 370
7.9 E1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ................................................................................................................. 371
7.10 JITTER TOLERANCE ................................................................................................................................................................................. 372
7.10.1 T1/J1 Mode .................................................................................................................................................................................... 372
7.10.2 E1 Mode ........................................................................................................................................................................................ 373
7.11 JITTER TRANSFER .................................................................................................................................................................................... 374
7.11.1 T1/J1 Mode .................................................................................................................................................................................... 374
7.11.2 E1 Mode ........................................................................................................................................................................................ 375
7.12 MICROPROCESSOR TIMING SPECIFICATION ........................................................................................................................................ 376
7.12.1 Motorola Non-Multiplexed Mode ................................................................................................................................................. 376
7.12.1.1 Read Cycle Specification ............................................................................................................................................... 376
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
7.12.1.2 Write Cycle Specification ................................................................................................................................................
7.12.2 Intel Non-Multiplexed Mode .........................................................................................................................................................
7.12.2.1 Read Cycle Specification ...............................................................................................................................................
7.12.2.2 Write Cycle Specification ................................................................................................................................................
7.12.3 SPI Mode .......................................................................................................................................................................................
377
378
378
379
380
ORDERING INFORMATION .......................................................................................................................................... 381
DOCUMENT HISTORY .................................................................................................................................................. 381
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List of Tables
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Operating Mode Selection ...........................................................................................................................................................................
Related Bit / Register In Chapter 3.1 ...........................................................................................................................................................
Impedance Matching Value For The Receiver .............................................................................................................................................
Related Bit / Register In Chapter 3.2 ...........................................................................................................................................................
Related Bit / Register In Chapter 3.3 & Chapter 3.4 ....................................................................................................................................
Criteria Of Speed Adjustment Start ..............................................................................................................................................................
Related Bit / Register In Chapter 3.6 ...........................................................................................................................................................
Excessive Zero Error Definition ...................................................................................................................................................................
LOS Condition In T1/J1 Mode ......................................................................................................................................................................
LOS Condition In E1 Mode ..........................................................................................................................................................................
Related Bit / Register In Chapter 3.7 ...........................................................................................................................................................
The Structure of SF .....................................................................................................................................................................................
The Structure of ESF ...................................................................................................................................................................................
The Structure of T1 DM ...............................................................................................................................................................................
The Structure of SLC-96 ..............................................................................................................................................................................
Interrupt Source In T1/J1 Frame Processor ................................................................................................................................................
Related Bit / Register In Chapter 3.8.1 ........................................................................................................................................................
The Structure Of TS0 In CRC Multi-Frame ..................................................................................................................................................
FAS/NFAS Bit/Pattern Error Criteria ............................................................................................................................................................
Interrupt Source In E1 Frame Processor .....................................................................................................................................................
Related Bit / Register In Chapter 3.8.2 ........................................................................................................................................................
Monitored Events In T1/J1 Mode .................................................................................................................................................................
Related Bit / Register In Chapter 3.9.1 ........................................................................................................................................................
Monitored Events In E1 Mode .....................................................................................................................................................................
Related Bit / Register In Chapter 3.9.2 ........................................................................................................................................................
RED Alarm, Yellow Alarm & Blue Alarm Criteria .........................................................................................................................................
Related Bit / Register In Chapter 3.10.1 ......................................................................................................................................................
Related Bit / Register In Chapter 3.10.2 ......................................................................................................................................................
Related Bit / Register In Chapter 3.11.1 ......................................................................................................................................................
Interrupt Summarize In HDLC Mode ...........................................................................................................................................................
Related Bit / Register In Chapter 3.11.2 ......................................................................................................................................................
Related Bit / Register In Chapter 3.12 .........................................................................................................................................................
Related Bit / Register In Chapter 3.13 .........................................................................................................................................................
Related Bit / Register In Chapter 3.14 .........................................................................................................................................................
Related Bit / Register In Chapter 3.15 .........................................................................................................................................................
A-Law Digital Milliwatt Pattern .....................................................................................................................................................................
µ-Law Digital Milliwatt Pattern .....................................................................................................................................................................
Related Bit / Register In Chapter 3.16 .........................................................................................................................................................
Operating Modes Selection In T1/J1 Receive Path .....................................................................................................................................
Operating Modes Selection In E1 Receive Path ..........................................................................................................................................
Related Bit / Register In Chapter 3.17 .........................................................................................................................................................
Operating Modes Selection In T1/J1 Transmit Path ....................................................................................................................................
Operating Modes Selection In E1 Transmit Path .........................................................................................................................................
Related Bit / Register In Chapter 3.18 .........................................................................................................................................................
Related Bit / Register In Chapter 3.19 .........................................................................................................................................................
Related Bit / Register In Chapter 3.20.1.1 ...................................................................................................................................................
E1 Frame Generation ..................................................................................................................................................................................
Control Over E Bits ......................................................................................................................................................................................
List of Tables
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24
24
25
27
28
29
29
30
32
32
33
34
35
36
37
39
40
44
45
47
48
49
50
51
52
53
54
55
56
57
58
59
59
60
62
63
63
64
65
70
72
73
79
80
81
83
84
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August 20, 2009
IDT82P2282
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Interrupt Summary In E1 Mode .................................................................................................................................................................... 85
Related Bit / Register In Chapter 3.20.1.2 ................................................................................................................................................... 86
Related Bit / Register In Chapter 3.20.2.1 ................................................................................................................................................... 87
Related Bit / Register In Chapter 3.20.2.2 ~ Chapter 3.20.2.4 .................................................................................................................... 88
APRM Message Format .............................................................................................................................................................................. 89
APRM Interpretation .................................................................................................................................................................................... 89
Related Bit / Register In Chapter 3.20.3 ...................................................................................................................................................... 90
Related Bit / Register In Chapter 3.20.4 & Chapter 3.20.5 .......................................................................................................................... 90
Related Bit / Register In Chapter 3.20.6, Chapter 3.20.7 & Chapter 3.21 ................................................................................................... 91
Related Bit / Register In Chapter 3.22 ......................................................................................................................................................... 91
Related Bit / Register In Chapter 3.23 ......................................................................................................................................................... 92
PULS[3:0] Setting In T1/J1 Mode ................................................................................................................................................................ 93
LBO PULS[3:0] Setting In T1 Mode ............................................................................................................................................................. 94
Transmit Waveform Value For E1 75 Ohm .................................................................................................................................................. 95
Transmit Waveform Value For E1 120 Ohm ................................................................................................................................................ 95
Transmit Waveform Value For T1 0~133 ft ................................................................................................................................................. 96
Transmit Waveform Value For T1 133~266 ft ............................................................................................................................................. 96
Transmit Waveform Value For T1 266~399 ft ............................................................................................................................................. 97
Transmit Waveform Value For T1 399~533 ft ............................................................................................................................................. 97
Transmit Waveform Value For T1 533~655 ft ............................................................................................................................................. 98
Transmit Waveform Value For J1 0~655ft ................................................................................................................................................... 98
Transmit Waveform Value For DS1 0 dB LBO ............................................................................................................................................ 99
Transmit Waveform Value For DS1 -7.5 dB LBO ........................................................................................................................................ 99
Transmit Waveform Value For DS1 -15.0 dB LBO .................................................................................................................................... 100
Transmit Waveform Value For DS1 -22.5 dB LBO .................................................................................................................................... 100
Related Bit / Register In Chapter 3.24 ....................................................................................................................................................... 100
Impedance Matching Value For The Transmitter ...................................................................................................................................... 102
Related Bit / Register In Chapter 3.25 & Chapter 3.26 .............................................................................................................................. 102
Related Bit / Register In Chapter 3.27.1 .................................................................................................................................................... 103
Related Bit / Register In Chapter 3.27.2 & Chapter 3.27.3 ........................................................................................................................ 106
Related Bit / Register In Chapter 3.28 ....................................................................................................................................................... 107
Parallel Microprocessor Interface .............................................................................................................................................................. 110
Related Bit / Register In Chapter 4 ............................................................................................................................................................ 111
IR Code ...................................................................................................................................................................................................... 358
IDR ............................................................................................................................................................................................................. 359
Boundary Scan (BS) Sequence ................................................................................................................................................................. 359
TAP Controller State Description ............................................................................................................................................................... 361
List of Tables
9
August 20, 2009
List of Figures
Figure 1. 100-Pin TQFP (Top View) ............................................................................................................................................................................ 14
Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 25
Figure 3. Receive Path Monitoring (Twisted Pair) ....................................................................................................................................................... 26
Figure 4. Transmit Path Monitoring (Twisted Pair) ...................................................................................................................................................... 26
Figure 5. Receive Path Monitoring (COAX) ................................................................................................................................................................ 27
Figure 6. Transmit Path Monitoring(COAX) ................................................................................................................................................................ 27
Figure 7. Jitter Attenuator ............................................................................................................................................................................................ 29
Figure 8. AMI Bipolar Violation Error ........................................................................................................................................................................... 31
Figure 9. B8ZS Excessive Zero Error ......................................................................................................................................................................... 31
Figure 10. HDB3 Code Violation & Excessive Zero Error ............................................................................................................................................ 31
Figure 11. E1 Frame Searching Process ..................................................................................................................................................................... 42
Figure 12. Basic Frame Searching Process ................................................................................................................................................................ 43
Figure 13. TS16 Structure Of CAS Signaling Multi-Frame .......................................................................................................................................... 45
Figure 14. Standard HDLC Packet .............................................................................................................................................................................. 56
Figure 15. Overhead Indication In The FIFO ............................................................................................................................................................... 57
Figure 16. Signaling Output In T1/J1 Mode ................................................................................................................................................................. 61
Figure 17. Signaling Output In E1 Mode ...................................................................................................................................................................... 61
Figure 18. T1/J1 To E1 Format Mapping - G.802 Mode .............................................................................................................................................. 66
Figure 19. T1/J1 To E1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 66
Figure 20. T1/J1 To E1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 67
Figure 21. No Offset When FE = 1 & DE = 1 In Receive Path .................................................................................................................................... 68
Figure 22. No Offset When FE = 0 & DE = 0 In Receive Path .................................................................................................................................... 68
Figure 23. No Offset When FE = 0 & DE = 1 In Receive Path .................................................................................................................................... 69
Figure 24. No Offset When FE = 1 & DE = 0 In Receive Path .................................................................................................................................... 69
Figure 25. E1 To T1/J1 Format Mapping - G.802 Mode .............................................................................................................................................. 74
Figure 26. E1 To T1/J1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 74
Figure 27. E1 To T1/J1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 75
Figure 28. No Offset When FE = 1 & DE = 1 In Transmit Path ................................................................................................................................... 76
Figure 29. No Offset When FE = 0 & DE = 0 In Transmit Path ................................................................................................................................... 76
Figure 30. No Offset When FE = 0 & DE = 1 In Transmit Path ................................................................................................................................... 77
Figure 31. No Offset When FE = 1 & DE = 0 In Transmit Path ................................................................................................................................... 77
Figure 32. DSX-1 Waveform Template ........................................................................................................................................................................ 93
Figure 33. T1/J1 Pulse Template Measurement Circuit .............................................................................................................................................. 93
Figure 34. E1 Waveform Template .............................................................................................................................................................................. 93
Figure 35. E1 Pulse Template Measurement Circuit ................................................................................................................................................... 93
Figure 36. G.772 Non-Intrusive Monitor .................................................................................................................................................................... 105
Figure 37. Hardware Reset When Powered-Up ........................................................................................................................................................ 108
Figure 38. Hardware Reset In Normal Operation ...................................................................................................................................................... 108
Figure 39. Read Operation In SPI Mode ................................................................................................................................................................... 109
Figure 40. Write Operation In SPI Mode .................................................................................................................................................................... 109
Figure 41. JTAG Architecture .................................................................................................................................................................................... 357
Figure 42. JTAG State Diagram ................................................................................................................................................................................ 363
Figure 43. I/O Timing in Non-Multiplexed Mode ........................................................................................................................................................ 366
Figure 44. I/O Timing in Multiplexed Mode ................................................................................................................................................................ 367
Figure 45. T1/J1 Jitter Tolerance Performance Requirement .................................................................................................................................... 372
Figure 46. E1 Jitter Tolerance Performance Requirement ........................................................................................................................................ 373
Figure 47. T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-000009) ....................................................... 374
Figure 48. E1 Jitter Transfer Performance Requirement (G.736) .............................................................................................................................. 375
List of Figures
10
August 20, 2009
IDT82P2282
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Motorola Non-Multiplexed Mode Read Cycle ...........................................................................................................................................
Motorola Non-Multiplexed Mode Write Cycle ...........................................................................................................................................
Intel Non-Multiplexed Mode Read Cycle ..................................................................................................................................................
Intel Non-Multiplexed Mode Write Cycle ..................................................................................................................................................
SPI Timing Diagram .................................................................................................................................................................................
List of Figures
11
376
377
378
379
380
August 20, 2009
Dual T1/E1/J1 Long Haul /
IDT82P2282
Short Haul Transceiver
FEATURES
•
LINE INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Each link can be configured as T1, E1 or J1
Supports T1/E1/J1 long haul/short haul line interface
HPS for 1+1 protection without external relays
Receive sensitivity exceeds -36 dB @ 772 Hz and -43 dB @ 1024
Hz
Selectable internal line termination impedance: 100 Ω (for T1), 75
Ω / 120 Ω (for E1) and 110 Ω (for J1)
Supports AMI/B8ZS (for T1/J1) and AMI/HDB3 (for E1) line encoding/decoding
Provides T1/E1/J1 short haul pulse templates, long haul LBO (per
ANSI T1.403 and FCC68: 0 dB, -7.5 dB, -15 dB, -22 dB) and userprogrammable arbitrary pulse template
Supports G.772 non-intrusive monitoring
Supports T1.102 line monitor
Transmit line short-circuit detection and protection
Separate Transmit and Receive Jitter Attenuators (2 per link)
Indicates the interval between the write pointer and the read pointer
of the FIFO in JA
Loss of signal indication with programmable thresholds according
to ITUT-T G.775, ETS 300 233 (E1) and ANSI T1.403 (T1/J1)
Supports Analog Loopback, Digital Loopback and Remote Loopback
Each receiver and transmitter can be individually powered down
•
•
•
CONTROL INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
Supports Serial Peripheral Interface (SPI) microprocessor and parallel Intel/Motorola non-multiplexed microprocessor interface
Global hardware and software reset
One general purpose I/O pin
Per link power down
GENERAL
•
•
•
•
•
•
Flexible reference clock (N x 1.544 MHz or N x 2.048 MHz)
(0<N<5)
JTAG boundary scan
3.3 V I/O with 5 V tolerant inputs
Low power consumption (Typical 270 mW)
3.3 V and 1.8 V power supply
100-pin TQFP package
APPLICATIONS
•
•
•
•
•
•
•
•
FRAMER
•
•
Provides performance monitor to count Bipolar Violation error,
Excess Zero error, CRC error, framing bit error, far end CRC error,
out of frame and change of framing alignment position
Supports System Loopback, Payload Loopback, Digital Loopback
and Inband Loopback
Detects and generates selectable PRBS and QRSS
Transmission and Extraction of Synchronization Supply Message
(SSM) in BITS application
Each link can be configured as T1, E1 or J1
Frame alignment/generation for T1 (per ITU-T G.704, TA-TSY000278, TR-TSY-000008), E1 (per ITU-T G.704), J1 (per JT G.704)
and un-framed mode
Supports T1/J1 Super Frame and Extended Super Frame, T1 Digital Multiplexer and Switch Line Carrier - 96, E1 CRC Multi-frame
and Signaling Multi-frame
Signaling extraction/insertion for CAS and RBS signaling
Provides programmable system interface supporting MitelTM STbus, AT&TTM CHI and MVIP bus, 8.192 Mb/s multiplexed bus and
1.544 Mb/s or 2.048 Mb/s non-multiplexed bus
Three HDLC controllers per link with separate 128-byte transmit
and receive FIFOs per controller
Programmable bit insertion and bit inversion on per channel/
timeslot basis
Provides Bit Oriented Message (BOM) generation and detection
Provides Automatic Performance Report Message (APRM) generation
Detects and generates alarms (AIS, RAI)
C.O, PABX, ISDN PRI
Wireless Base Stations
T1/E1/J1 ATM Gateways, Multiplexer
T1/E1/J1 Access Networks
LAN/WAN Router
Digital Cross Connect
SONET/SDH Add/Drop Equipment
Clock recovery at 1.544 MHz / 2.048 MHz for BITS application with
SSM support
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
12
 2009 Integrated Device Technology, Inc.
August 20, 2009
DSC-6240/10
13
RSCKn
Receive
System
RSFSn Interface
RSIGn
(LP 3)
Transmit
System
Interface
(LP 1, 2)
RSDn
TSDn
TSIGn
TSFSn
TSCKn
Note:
LP1, 2 - System Loopback
LP3 - Payload Loopback
LP4 - Local Digital Loopback 1
LP5 - Remote Loopback
LP6 - Local Digital Loopback 2
LP7 - Analog Loopback
MRSCK
MRSFS
MRSIG
MRSD
MTSD
MTSIG
MTSFS
MTSCK
IEEE1149.1
JTAG
Receive
Payload
Control
PRBS
Generator /
Detector
Transmit
Payload
Control
Receive
CAS/
RBS
Buffer
Inband
Loopback Code
Detector
HDLC Receiver
#1, #2, #3
B8ZS/
HDB3/
AMI
Decoder
(LP 5)
Receive
Jitter
Attenuator
Transmit
Jitter
Attenuator
Clock Generator
Bit-Oriented
Message
Receiver
Alarm
Detector
Frame Processor
Performance Monitor
(LP 4)
Transmit
Buffer
B8ZS/
HDB3/AMI
Encoder
Data
Slicer
G.772
Monitor
CLK&Data
Recovery
(DPLL)
(LP 6)
Waveform
Shaper / Line
Build Out
One of the Two Links
REFB_OUT
REFA_OUT
CLK_SEL[2:0]
OSCO
OSCI
CLK_GEN
Control Interface
Elastic
Store
Buffer
Frame Generator
Inband Automatic
HDLC Bit-Oriented
Loopback Performance
Transmitter Message
Report
Code
#1, #2, #3 Transmitter
Generator Message
Adaptive
Equalizer
Line
Driver
RTIPn
(LP 7)
TTIPn
TRINGn
VDDAB / GNDAB
VDDAP / GNDAP
VDDAX / GNDAX
VDDAT / GNDAT
VDDAR / GNDAR
VDDDC / GNDDC
VDDDIO / GNDDIO
Receive
Internal
Termination RRINGn
Transmit
Internal
Termination
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
BLOCK DIAGRAM
GPIO
RESET
THZ
A[8:0]
D[7:1]
D[0]/SDO
CS
REFR
RW/WR/SDI
DS/RD/SCLK
MPM
SPIEN
INT
TDO
TDI
TMS
TCK
TRST
August 20, 2009
IDT82P2282
PIN ASSIGNMENT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
TMS
TDI
TCK
TRST
TDO
OSCI
OSCO
VDDDIO[0]
REFB_OUT
VDDDC[0]
REFA_OUT
GNDDIO[0]
GNDDC[0]
CLK_SEL[2]
CLK_SEL[1]
CLK_SEL[0]
RESET
IC
IC
CLK_GEN
1
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RSCK[1]/MRSCK
RSD[1]/MRSD
RSIG[1]/MRSIG
RSFS[1]/MRSFS
TSCK[1]/MTSCK
TSD[1]/MTSD
TSIG[1]/MTSIG
TSFS[1]/MTSFS
RSCK[2]
RSD[2]
RSIG[2]
RSFS[2]
TSCK[2]
TSD[2]
TSIG[2]
TSFS[2]
VDDDIO[2]
A[8]
A[7]
VDDDC[2]
A[6]
GNDDIO[2]
GNDDC[2]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
IC
IC
MPM
SPIEN
D[0]/SDO
D[1]
D[2]
D[3]
D[4]
D[5]
VDDDIO[1]
D[6]
VDDDC[1]
D[7]
GNDDIO[1]
GNDDC[1]
DS/RD/SCLK
RW/WR/SDI
CS
INT
IC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GPIO
THZ
VDDDC[3]
GNDDC[3]
GNDAP
VDDAP
GNDAB
VDDAB
REFR
GNDAR[2]
RRING[2]
RTIP[2]
VDDAR[2]
VDDAT[2]
GNDAT[2]
GNDAX[2]
TRING[2]
TTIP[2]
VDDAX[2]
VDDAX[1]
TTIP[1]
TRING[1]
GNDAX[1]
GNDAT[1]
VDDAT[1]
VDDAR[1]
RTIP[1]
RRING[1]
GNDAR[1]
NC
Figure 1. 100-Pin TQFP (Top View)
Pin Assignment
14
August 20, 2009
IDT82P2282
2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
PIN DESCRIPTION
Name
Type
Pin No.
Description
Line and System Interface
RTIP[1]
RTIP[2]
Input
RRING[1]
RRING[2]
TTIP[1]
TTIP[2]
RTIP[1:2] / RRING[1:2]: Receive Bipolar Tip/Ring for Link 1 ~ 2
These pins are the differential line receiver inputs.
28
11
Output
TRING[1]
TRING[2]
RSD[1] / MRSD
RSD[2]
27
12
21
18
22
17
Output
79
71
TTIP[1:2] / TRING[1:2]: Transmit Bipolar Tip/Ring for Link 1 ~ 2
These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic
high on the THZ pin sets all these pins to high impedance state. When the T_HZ bit (b4, T1/J1-023H,... / b4, E1023H,...) * is set to ‘1’, the TTIPn/TRINGn pins in the corresponding link are set to high impedance state.
Besides, TTIPn/TRINGn will also be set to high impedance state by other ways (refer to Chapter 3.25 Line Driver for
details).
RSD[1:2]: Receive Side System Data for Link 1 ~ 2
The processed data stream is output on these pins.
In Receive Clock Master mode, the RSDn pins are updated on the active edge of the corresponding RSCKn.
In Receive Clock Slave mode, selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSDn pins are
updated on the active edge of the corresponding RSCKn or both two RSDn pins are updated on the active edge of
RSCK[1].
MRSD: Multiplexed Receive Side System Data for Link 1 ~ 2
In Receive Multiplexed mode, the MRSD pin is used to output the processed data stream. Using a byte-interleaved
multiplexing scheme, the MRSD pin outputs the data from Link 1 and Link 2. The data on the MRSD pin is updated on
the active edge of the MRSCK.
RSIG[1] / MRSIG
RSIG[2]
Output
78
70
RSIG[1:2]: Receive Side System Signaling for Link 1 ~ 2
The extracted signaling bits are output on these pins. They are located in the lower nibble (b5 ~ b8) and are channel/
timeslot-aligned with the data output on the corresponding RSDn pin.
In Receive Clock Master mode, the RSIGn pins are updated on the active edge of the corresponding RSCKn.
In Receive Clock Slave mode, selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSIGn pins are
updated on the active edge of the corresponding RSCKn or both two RSIGn are updated on the active edge of
RSCK[1].
MRSIG: Multiplexed Receive Side System Signaling for Link 1 ~ 2
In Receive Multiplexed mode, the MRSIG pin is used to output the extracted signaling bits. The signaling bits are
located in the lower nibble (b5 ~ b8) and are channel/timeslot-aligned with the data output on the MRSD pin. Using the
byte-interleaved multiplexing scheme, the MRSIG pin outputs the signaling bits from Link 1 and Link 2. The signaling
bits on the MRSIG pin is updated on the active edge of the MRSCK.
Note:
* The contents in the brackets indicate the position of the preceding bit and the address of the register. After the address, if the punctuation ‘,...’ is followed, this bit is in a per-link control register and the listed address belongs to Link 1. Users can find the omitted addresses in Chapter 5. If there is no punctuation followed the address, this bit is in a global control register.
Pin Description
15
August 20, 2009
IDT82P2282
Name
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Type
RSFS[1] / MRSFS Output / Input
RSFS[2]
Pin No.
Description
77
69
RSFS[1:2]: Receive Side System Frame Pulse for Link 1 ~ 2
In T1/J1 Receive Clock Master mode, RSFSn outputs the pulse to indicate each F-bit, every second F-bit in SF frame,
the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame or the first F-bit of every second SF multi-frame.
In T1/J1 Receive Clock Slave mode, RSFSn inputs the pulse at a rate of integer multiple of 125 µs to indicate the start
of a frame.
In E1 Receive Clock Master mode, RSFSn outputs the pulse to indicate the Basic frame, CRC Multi-frame, Signaling
Multi-frame, or both the CRC Multi-frame and Signaling Multi-frame, or the TS1 and TS16 overhead.
In E1 Receive Clock Slave mode, RSFSn inputs the pulse at a rate of integer multiple of 125 µs to indicate the start of
a frame.
RSFSn is updated/sampled on the active edge of the corresponding RSCKn. The active polarity of RSFSn is selected
by the FSINV bit (b4, T1/J1-048H,... / b4, E1-048H,...).
MRSFS: Multiplexed Receive Side System Frame Pulse for Link 1 ~ 2
In Receive Multiplexed mode, MRSFS inputs the pulse at a rate of integer multiple of 125 µs to indicate the start of a
frame on the multiplexed data bus. MRSFS is sampled on the active edge of MRSCK. The active polarity of MRSFS is
selected by the FSINV bit (b4, T1/J1-048H,... / b4, E1-048H,...).
RSFS[1:2]/MRSCK are Schmitt-triggered inputs/outputs with pull-up resistors.
RSCK[1] / MRSCK Output / Input
RSCK[2]
80
72
RSCK[1:2]: Receive Side System Clock for Link 1 ~ 2
In Receive Clock Master mode, the RSCKn pins output a (gapped) 1.544 MHz (for T1/J1 mode) / 2.048 MHz (for E1
mode) clock used to update the signal on the corresponding RSDn, RSIGn and RSFSn pins.
In Receive Clock Slave mode, the RSCKn pins input a 1.544 MHz (for T1/J1 mode only), 2.048 MHz or 4.096 MHz
clock used to update the signals on the corresponding RSDn and RSIGn pins and sample the signals on the corresponding RSFSn pins. Selected by the RSLVCK bit (b4, T1/J1-010H / b4, E1-010H), the RSCK[1] pin can be used for
both two links.
MRSCK: Multiplexed Receive Side System Clock for Link 1 ~ 2
In Receive Multiplexed mode, MRSCK inputs a 8.192 MHz or 16.384 MHz clock used to update the signals on the
MRSD and MRSIG pins and sample the signal on the MRSFS pin.
RSCK[1:2]/MRSCK are Schmitt-triggered inputs/outputs with pull-up resistors.
TSD[1] / MTSD
TSD[2]
Input
75
67
TSD[1:2]: Transmit Side System Data for Link 1 ~ 2
The data stream from the system side is input on these pins.
In Transmit Clock Master mode, the TSDn pins are sampled on the active edge of the corresponding TSCKn.
In Transmit Clock Slave mode, selected by the TSLVCK bit (b1, T1/J1-010H / b1, E1-010H), the TSDn pins are sampled on the active edge of the corresponding TSCKn or both two TSDn pins are sampled on the active edge of
TSCK[1].
MTSD: Multiplexed Transmit Side System Data for Link 1 ~ 2
In Transmit Multiplexed mode, the MTSD pin is used to input the data stream. Using a byte-interleaved multiplexing
scheme, the MTSD pin inputs the data for Link 1 and Link 2. The data on the MTSD pin is sampled on the active edge
of MTSCK.
TSD[1]/MTSD is a Schmitt-triggered input. TSD[2] is a Schmitt-triggered input with pull-up resistor.
Pin Description
16
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Name
Type
Pin No.
Description
TSIG[1] / MTSIG
TSIG[2]
Input
74
66
TSIG[1:2]: Transmit Side System Signaling for Link 1 ~ 2
The signaling bits are input on these pins. They are located in the lower nibble (b5 ~ b8) and are channel/timeslotaligned with the data input on the corresponding TSDn pin.
In Transmit Clock Master mode, TSIGn is sampled on the active edge of the corresponding TSCKn.
In Transmit Clock Slave mode, selected by the TSLVCK bit (b1, T1/J1-010H / b1, E1-010H), TSIGn is sampled on the
active edge of the corresponding TSCKn or both two TSIGn are updated on the active edge of TSCK[1].
MTSIG: Multiplexed Transmit Side System Signaling for Link 1 ~ 2
In Transmit Multiplexed mode, the MTSIG pin is used to input the signaling bits. The signaling bits are located in the
lower nibble (b5 ~ b8) and are channel/timeslot-aligned with the data input on the MTSD pin. Using the byte-interleaved
multiplexing scheme, the MTSIG pin inputs the signaling bits for Link 1 and Link 2. The signaling bits on the MTSIG pin
is sampled on the active edge of MTSCK.
TSIG[1]/MTSIG is a Schmitt-triggered input. TSIG[2] is a Schmitt-triggered input with pull-up resistor.
TSFS[1] / MTSFS Output / Input
TSFS[2]
73
65
TSFS[1:2]: Transmit Side System Frame Pulse for Link 1 ~ 2
In T1/J1 Transmit Clock Master mode, TSFSn outputs the pulse to indicate each F-bit or the first F-bit of every SF/ESF/
T1 DM/SLC-96 multi-frame.
In T1/J1 Transmit Clock Slave mode, TSFSn inputs the pulse to indicate each F-bit or the first F-bit of every SF/ESF/T1
DM/SLC-96 multi-frame.
In E1 Transmit Clock Master mode, TSFSn outputs the pulse to indicate the Basic frame, CRC Multi-frame and/or Signaling Multi-frame.
In E1 Transmit Clock Slave mode, TSFSn inputs the pulse to indicate the Basic frame, CRC Multi-frame and/or Signaling Multi-frame.
TSFSn is updated/sampled on the active edge of the corresponding TSCKn. The active polarity of TSFSn is selected
by the FSINV bit (b1, T1/J1-042H,... / b1, E1-042H,...).
MTSFS: Multiplexed Transmit Side System Frame Pulse for Link 1 ~ 2
In T1/J1 Transmit Multiplexed mode, MTSFS inputs the pulse to indicate each F-bit or the first F-bit of every SF/ESF/T1
DM/SLC-96 multi-frame of one link on the multiplexed data bus.
In E1 Transmit Multiplexed mode, MTSFS inputs the pulse to indicate each Basic frame, CRC Multi-frame and/or Signaling Multi-frame of one link on the multiplexed data bus.
MTSFS is sampled on the active edge of MTSCK. The active polarity of MTSFS is selected by the FSINV bit (b1, T1/
J1-042H,... / b1, E1-042H,...).
TSFS[1:2]/MTSFS are Schmitt-triggered inputs/outputs with pull-up resistors.
TSCK[1] / MTSCK Output / Input
TSCK[2]
76
68
TSCK[1:2]: Transmit Side System Clock for Link 1 ~ 2
In Transmit Clock Master mode, TSCKn outputs a (gapped) 1.544 MHz (for T1/J1 mode) / 2.048 MHz (for E1 mode)
clock used to sample the signal on the corresponding TSDn and TSIGn pins and update the signal on the corresponding TSFSn pin.
In Transmit Clock Slave mode, TSCKn inputs a 1.544 MHz (for T1/J1 mode only), 2.048 MHz or 4.096 MHz clock used
to sample the signal on the corresponding TSDn, TSIGn and TSFSn pins. Selected by the TSLVCK bit (b1, T1/J1-010H
/ b1, E1-010H), the TSCK[1] can be used for both two links.
MTSCK: Multiplexed Transmit Side System Clock for Link 1 ~ 2
In Transmit Multiplexed mode, MTSCK inputs a 8.192 MHz or 16.384 MHz clock used to sample the signal on the
MTSD, MTSIG and MTSFS pins.
TSCK[1:2]/MTSCK are Schmitt-triggered inputs/outputs with pull-up resistors.
Clock Generator
OSCI
Pin Description
Input
95
OSCI: Crystal Oscillator Input
This pin is connected to an external clock source.
The clock frequency of OSCI is defined by CLK_SEL[2:0]. The clock accuracy should be ±32 ppm and duty cycle
should be from 40% to 60%.
Hardware or software reset can only be applied when the clock on this pin is available.
17
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Name
Type
Pin No.
Description
OSCO
Output
94
OSCO: Crystal Oscillator Output
This pin outputs the inverted, buffered clock input from OSCI.
CLK_SEL[0]
CLK_SEL[1]
CLK_SEL[2]
Input
85
86
87
CLK_SEL[2:0]: Clock Selection
These three pins select the input clock signal:
When the CLK_SEL[2] pin is low, the input clock signal is N X 1.544 MHz;
when the CLK_SEL[2] pin is high, the input clock signal is N X 2.048 MHz.
When the CLK_SEL[1:0] pins are ‘00’, the N is 1;
When the CLK_SEL[1:0] pins are ‘01’, the N is 2;
When the CLK_SEL[1:0] pins are ‘10’, the N is 3;
When the CLK_SEL[1:0] pins are ‘11’, the N is 4.
CLK_SEL[2:0] are Schmitt-trigger inputs.
CLK_GEN
Output
81
CLK_GEN: Clock Generator
This pin outputs the 1.544/2.048 MHz clock signal generated by the Clock Generator.
REFA_OUT
Output
90
REFA_OUT: Reference Clock Output A
The frequecy is 2.048 MHz (E1) or 1.544 MHz (T1/J1).
When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function block of one
of the two links. The link is selected by the RO10 bit (b0, T1/J1-007H / b0, E1-007H).
When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (b0, T1/J1-03EH, b0,
E1-03EH).
Note: MCLK is a clock derived from OSCI using an internal PLL, and the frequency is 2.048 MHz (E1) or 1.544 MHz
(T1/J1).
REFB_OUT
Output
92
REFB_OUT: Reference Clock Output B
The frequecy is 2.048 MHz(E1) or 1.544 MHz(T1/J1).
When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function block of one
of the two links. The link is selected by the RO20 bit (b3, T1/J1-007H / b3, E1-007H).
When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (b0, T1/J1-03EH/ b0,
E1-03EH).
Control Interface
RESET
Input
84
RESET: Reset (Active Low)
A low pulse for more than 100 ns on this pin resets the device. All the registers are accessible 2 ms after the reset.
Reset can only be applied when the clock on the OSCI pin is available.
The RESET pin is a Schmitt-trigger input with a weak pull-up resistor. The OSCI clock must exist when the device is
reset.
GPIO
Output / Input
1
General Purpose I/O
This pin can be defined as input pin or output pin by the DIR0 bit (b0, T1/J1-006H / b0, E1-006H). When the pin is
input, its polarity is indicated by the LEVEL0 bit (b2, T1/J1-006H / b2, E1-006H). When the pin is output, its polarity is
controlled by the LEVEL0 bit (b2, T1/J1-006H / b2, E1-006H).
GPIO is a Schmitt-trigger input/output with a pull-up resistor.
THZ
Input
2
THZ: Transmit High-Z
A high level on this pin puts all the TTIPn/TRINGn pins into high impedance state.
THZ is a Schmitt-trigger input.
INT
Output
49
INT: Interrupt (Active Low)
This is the open drain, active low interrupt output. This pin will stay low until all the active unmasked interrupt indication
bits are cleared.
REFR
Output
9
REFR:
This pin should be connected to ground via an external 10K resistor.
CS
Input
48
CS: Chip Select (Active Low)
This pin must be asserted low to enable the microprocessor interface. The signal must be asserted high at least once
after power up to clear the internal test modes. A transition from high to low must occur on this pin for each Read/Write
operation and can not return to high until the operation is completed.
CS is a Schmitt-trigger input.
Pin Description
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Name
Type
Pin No.
Description
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
Input
52
53
54
55
56
57
60
62
63
A[8:0]: Address Bus
In parallel mode, the signals on these pins select the register for the microprocessor to access.
In SPI mode, these pins should be connected to the ground.
A[8:0] are Schmitt-trigger inputs with pull-down resistor.
D[0] / SDO
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
Output / Input
34
35
36
37
38
39
41
43
D[7:0]: Bi-directional Data Bus
In parallel mode, the signals on these pins are the data for Read / Write operation.
In SPI mode, the D[7:1] pins should be connected to the ground through a 10 K resistor.
D[7:0] are Schmitt-trigger inputs/outputs.
MPM
Input
32
MPM: Micro Controller Mode
In parallel mode, set this pin low for Motorola mode or high for Intel mode.
In SPI mode, set this pin to a fixed level (high or low). This pin is useless in SPI mode.
MPM is a Schmitt-trigger input.
RW / WR / SDI
Input
47
RW: Read / Write Select
In parallel Motorola mode, this pin is active high for read operation and active low for write operation.
SDO: Serial Data Output
In SPI mode, the data is serially output on this pin.
WR: Write Strobe (Active Low)
In parallel Intel mode, this pin is active low for write operation.
SDI: Serial Data Input
In SPI mode, the address/control and/or data are serially input on this pin.
RW / WR / SDI is a Schmitt-trigger input.
DS / RD / SCLK
Input
46
DS: Data Strobe (Active Low)
In parallel Motorola mode, this pin is active low.
RD: Read Strobe (Active Low)
In parallel Intel mode, this pin is active low for read operation.
SCLK: Serial Clock
In SPI mode, this pin inputs the timing for the SDO and SDI pins. The signal on the SDO pin is updated on the falling
edge of SCLK, while the signal on the SDI pin is sampled on the rising edge of SCLK.
DS / RD / SCLK is a Schmitt-trigger input.
SPIEN
Input
33
SPIEN: Serial Microprocessor Interface Enable
When this pin is low, the microprocessor interface is in parallel mode.
When this pin is high, the microprocessor interface is in SPI mode.
SPIEN is a Schmitt-trigger input.
JTAG (per IEEE 1149.1)
TRST
Pin Description
Input
97
TRST: Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. This pin is a Schmitt-triggered input with an internal pull-up resistor. It
must be connected to the RESET pin or ground when JTAG is not used.
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Name
Type
Pin No.
Description
TMS
Input
100
TMS: Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK. This pin is a
Schmitt-triggered input with an internal pull-up resistor.
TCK
Input
98
TCK: Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO is
clocked out of the device on the falling edge of TCK. This pin is a Schmitt-triggered input with an internal pull-up resistor.
TDI
Input
99
TDI: Test Input
The test data is sampled at this pin on the rising edge of TCK. This pin has an internal pull-up resistor. This pin is a
Schmitt-triggered input with an internal pull-up resistor.
TDO
High-Z
96
TDO: Test Output
The test data are output on this pin. It is updated on the falling edge of TCK. This pin is High-Z except during the process of data scanning.
Power & Ground
VDDDIO[0]
VDDDIO[1]
VDDDIO[2]
Power
93
40
64
VDDDIO[2:0]: 3.3 V I/O Power Supply
GNDDIO[0]
GNDDIO[1]
GNDDIO[2]
Ground
89
44
59
GNDDIO[2:0]: Digital Pad Ground
VDDDC[0]
VDDDC[1]
VDDDC[2]
VDDDC[3]
Power
91
42
61
3
VDDDC[3:0]: 1.8 V Digital Core Power Supply
GNDDC[0]
GNDDC[1]
GNDDC[2]
GNDDC[3]
Ground
88
45
58
4
GNDDC[3:0]: Digital Core Ground
VDDAR[1]
VDDAR[2]
Power
26
13
VDDAR[2:1]: 3.3 V Power Supply for Receiver
GNDAR[1]
GNDAR[2]
Ground
29
10
GNDAR[2:1]: Analog Ground for Receiver
VDDAT[1]
VDDAT[2]
Power
25
14
VDDAT[2:1]: 3.3 V Power Supply for Transmitter
GNDAT[1]
GNDAT[2]
Ground
24
15
GNDAT[2:1]: Analog Ground for Transmitter
VDDAX[1]
VDDAX[2]
Power
20
19
VDDAX[2:1]: 3.3 V Power Supply for Transmit Driver
GNDAX[1]
GNDAX[2]
Ground
23
16
GNDAX[2:1]: Analog Ground for Transmitter Driver
VDDAP
Power
6
VDDAP: 3.3 V Power Analog PLL
GNDAP
Ground
5
GNDAP: Analog Ground PLL
VDDAB
Power
8
VDDAB: 3.3 V Power Analog Bias
GNDAB
Ground
7
GNDAB: Analog Ground Bias
TEST
Pin Description
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August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Name
Type
Pin No.
IC
-
31
50
51
82
83
IC: Internal Connected
These pins are for IDT use only and should be connected to ground.
NC
-
30
NC: Not Connected
Pin Description
Description
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August 20, 2009
IDT82P2282
3
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
FUNCTIONAL DESCRIPTION
various operating modes can be selected to output signals to the system.
The IDT82P2282 is a highly featured single device solution for T1/
E1/J1 trunks. Each link of the IDT82P2282 can be independently configured. The configuration is performed through an SPI or parallel microprocessor interface.
SYSTEM INTERFACE
On the system side, if the device is in T1/J1 mode, the data stream
of 1.544 Mbit/s can be converted to/from the data stream of 2.048 Mbit/s
by software configuration. In addition, the two links can be multiplexed to
or de-multiplexed from a 8.192 Mbit/s bus. If the device is in E1 mode,
the two links can be multiplexed to or de-multiplexed from a 8.192 Mbit/s
bus.
LINE INTERFACE - RECEIVE PATH
In the receive path, the signals from the line side are coupled into
the RTIPn and RRINGn pins and pass through an Impedance Terminator. An Adaptive Equalizer is provided to increase the sensitivity for small
signals. Clock and data are recovered from the digital pulses output from
the slicer. After passing through the Receive Jitter Attenuator (can be
enabled or disabled), the recovered data is decoded using B8ZS (for T1/
J1) / HDB3 (for E1) or AMI line code rules and clocked into the Frame
Processor. Loss of signal, line code violations and excessive zero are
detected.
FRAMER - TRANSMIT PATH
In the transmit path, the Transmit System Interface inputs the signals with various operating modes. In T1/J1 mode, the signals can be
processed by a Transmit Payload Control to execute the signaling insertion, idle code substitution, data insertion, data inversion and test pattern
generation or detection on a per-channel basis. The transmit path of
each transceiver can be configured to generate SF, ESF, T1 DM or SLC96. The framer can also be disabled (unframed mode). The Framer can
transmit Yellow alarm and AIS alarm. Inband loopback codes and bit oriented message can be transmitted. Up to three HDLC links (in ESF and
T1 DM format) or two HDLC links (in SF and SLC-96 format) are provided to insert the HDLC message on the DL bit (in ESF format) / D bit in
CH24 (in T1 DM format) or any arbitrary position. After passing through
a Transmit Buffer, the processed data and clock are input to the
Encoder.
In E1 mode, the signals can be processed by a Transmit Payload
Control to execute the signaling insertion, idle code substitution, data
insertion, data inversion and test pattern generation or detection on a
per-timeslot basis. The transmit path of each transceiver can be configured to generate Basic Frame, CRC Multi-Frame and Signaling MultiFrame. The framer can be disabled (unframed mode). The Framer can
transmit Remote Alarm Indication signal, the Remote Signaling MultiFrame Alarm Indication signal, AIS alarm and FEBE. Three HDLC links
are provided to insert the HDLC message on TS16, the Sa National bits
or any arbitrary timeslot. The processed data and clock are input to the
Encoder.
FRAMER - RECEIVE PATH
In T1/J1 Mode, the recovered data and clock of each link can be
configured in Super Frame (SF), Extended Super Frame (ESF), T1 Digital Multiplexer (DM) or Switch Line Carrier - 96 (SLC-96) formats. (The
T1 DM and SLC-96 formats only exist in T1 mode). The framing can also
be bypassed (unframed mode). The Framer detects and indicates the
out of SF/ESF/DM/SLC-96 synchronization event, the Yellow, Red and
AIS alarms. The Framer also detects the presence of inband loopback
codes and bit-oriented messages. Frame Alignment Signal errors, CRC6 errors, out of SF/ESF/T1 DM/SLC-96 events and Frame Alignment
position changes are counted. Up to three HDLC links (in ESF and T1
DM format) or two HDLC links (in SF and SLC-96 format) are provided
to extract the HDLC message on the DL bit (in ESF format) / D bit in
CH24 (in T1 DM format) or any arbitrary position. In the T1/J1 receive
path, signaling debounce, signaling freeze, idle code substitution, digital
milliwatt code insertion, idle code insertion, data inversion and pattern
generation or detection are supported on a per-channel basis. An Elastic
Store Buffer that supports controlled slip and adaptation to backplane
timing may be enabled. In the Receive System Interface, various operating modes can be selected to output signals to the system.
In E1 Mode, the recovered data and clock of each link can be configured to frame to Basic Frame, CRC Multi-Frame and Signaling MultiFrame. The framing can be bypassed (unframed mode). The Framer
detects and indicates the following event: out of Basic Frame Sync, out
of CRC Multi-Frame, out of Signaling Multi-Frame, Remote Alarm Indication signal and Remote Signaling Multi-Frame Alarm Indication signal.
The Framer also monitors Red and AIS alarms. Basic Frame Alignment
Signal errors, Far End Block Errors (FEBE) and CRC errors are
counted. Up to three HDLC links are provided to extract the HDLC message on TS16, the Sa National bits or any arbitrary timeslot. In the E1
receive path, signaling debounce, signaling freezing, idle code substitution, digital milliwatt code insertion, trunk conditioning, data inversion
and pattern generation or detection are also supported on a per-timeslot
basis. An Elastic Store Buffer that supports slip buffering and adaptation
to backplane timing may be enabled. In the Receive System Interface,
Functional Description
LINE INTERFACE - TRANSMIT PATH
The data is encoded using AMI or B8ZS (for T1/J1) and HDB3 (for
E1) line code rules. The Transmit Jitter Attenuator, if enabled, is provided with a FIFO in the transmit data path. A de-jittered clock is generated by an integrated digital phase-locked loop and is used to read data
from the FIFO. The shapes of the pulses are user programmable to
ensure that the T1/E1/J1 pulse template is met after the signal passing
through different cable lengths and types. Bipolar violation can be
inserted for diagnostic purposes if AMI line code rule is enabled. The
signal is transmitted on the TTIPn and TRINGn pins through an Impedance Terminator.
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TEST AND DIAGNOSES
To facilitate the testing and diagnostic functions, Analog Loopback,
Remote Digital Loopback, Remote Loopback, Local Digital Loopback,
Payload Loopback and System Loopback are also integrated in the
IDT82P2282. A programmable pseudo random bit sequence can be
generated in receive/transmit direction and detected in the opposite
direction for testing purpose.
The G.772 Non-intrusive monitoring and JTAG are also supported
by the IDT82P2282.
Functional Description
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August 20, 2009
IDT82P2282
3.1
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1 / E1 / J1 MODE SELECTION
ing formats can be selected. When it is in J1 mode, Super Frame (SF)
and Extended Super Frame (ESF) formats can be selected. All the
selections are made by the TEMODE bit, the T1/J1 bit and the FM[1:0]
bits as shown in Table 1.
Each link in the IDT82P2282 can be configured as a duplex T1
transceiver, or a duplex E1 transceiver, or a duplex J1 transceiver. When
it is in T1 mode, Super Frame (SF), Extended Super Frame (ESF), T1
Digital Multiplexer (T1 DM) and Switch Line Carrier - 96 (SLC-96) framTable 1: Operating Mode Selection
TEMODE
T1/J1
0
1
1
0
X
FM[1:0]
Operating Mode
00
01
10
11
00
01
X
T1 mode SF format
T1 mode ESF format
T1 mode T1 DM format
T1 mode SLC-96 format
J1 mode SF format
J1 mode ESF format
E1 mode
Table 2: Related Bit / Register In Chapter 3.1
Bit
Register
Address (Hex)
TEMODE
T1/J1
FM[1:0]
T1/J1 Or E1 Mode
020, 120
Functional Description
24
August 20, 2009
IDT82P2282
RECEIVER IMPEDANCE MATCHING
The receiver impedance matching can be realized by using internal
impedance matching circuit or external impedance matching circuit.
When the R_TERM[2] bit is ‘0’, the internal impedance matching
circuit is enabled. 100 Ω, 110 Ω, 75 Ω or 120 Ω internal impedance
matching circuit can be selected by the R_TERM[1:0] bits.
When the R_TERM[2] bit is ‘1’, the internal impedance matching
circuit is disabled, and different external resistors should be used to realize different impedance matching.
Figure 2 shows the appropriate components to connect with the
cable for one link. Table 3 lists the recommended matching resistor values for the receiver.
A
•
1:1
•
•
RX Line
RR
•
B
2:1
• •
TX Line
RT
VDDAR
D8
·
D7
VDDAR
D6
D5
·
Table 3: Impedance Matching Value For The Receiver
Cp
VDDAX
D2
RT
D1
Note: 1. Common decoupling capacitor
2. Cp 0-560 (pF)
3. D1 - D8, Motorola - MBR0540T1;
·
R_TERM[2:0]
75 Ω (E1)
120 Ω (E1)
100 Ω (T1)
110 Ω (J1)
000
001
010
011
External Termination
RR
R_TERM[2:0]
RR
1XX
75 Ω
120 Ω
100 Ω
110 Ω
120 Ω
3.3 V
VDDAR
RTIP
VDDAX RRING
D4
· TTIP
D3
Internal Termination
Cable
Configuration
IDT82P2282
(one of the two identical links)
3.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
68µF 1
0.1µF
•
GNDA
3.3 V
VDDAX
68µF 1
0.1µF
GNDA
•
TRING
International Rectifier - 11DQ04 or 10BQ060
Figure 2. Receive / Transmit Line Circuit
3.2.1
attenuation of this bridge is 20lg(r/(2R+r)) dB for Twisted Pair or 20lg(r/
(R+r)) dB for COAX. The value of resistive attenuation should be consistent with the setting of Monitor Gain (22 dB).
LINE MONITOR
In both T1/J1 and E1 short haul applications, the Protected NonIntrusive Monitoring per T1.102 can be performed between two devices.
The monitored link of one device is in normal operation, and the monitoring link of the other device taps the monitored one through a high
impedance bridging circuit. Refer to Figure 3&Figure 4 (Twisted Pair)
and Figure 5&Figure 6 (COAX).
In case of LOS, REFH_LOS bit (b0, T1/J1-03EH) determines the
outputs on the REFA_OUT and REFB_OUT pins. When set to 0, the
output is MCLK; when set to 1, the output is high level.
After the high resistance bridging circuit, the signal arriving at RTIPn/
RRINGn of the monitoring link is dramatically attenuated. To compensate this bridge resistive attenuation, Monitor Gain can be used to boost
the signal by 22 dB, as selected by the MG[1:0] bits (b1~0, T1/J102AH,...). For normal operation, the Monitor Gain should be set to 0 dB,
i.e., the Monitor Gain of the monitored link should be 0 dB.
The monitoring link can be configured to any of the External or
Partially Internal Impedance Matching mode. Here the external r or
internal IM is used for voltage division, not for impedance matching. That
is, the r (IM) and the R make up of a resistance bridge. The resistive
Functional Description
25
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
DSX cross
connect point
RTIPn
RR
monitor gain
= 0 dB
RRINGn
R
monitored link
RTIPn
R
monitor gain
= 22 dB
r
RRINGn
monitoring link
Figure 3. Receive Path Monitoring (Twisted Pair)
DSX cross
connect point
TTIPn
TRINGn
monitored link
R
R
RTIPn
r
monitor gain
= 22 dB
RRINGn
monitoring link
Figure 4. Transmit Path Monitoring (Twisted Pair)
Functional Description
26
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
DSX cross connect point
RTIPn
RR
Monitor Gain
=0 dB
RRINGn
R
Monitored Link
RTIPn
r
Monitor Gain
=22 dB
RRINGn
Monitoring Link
Figure 5. Receive Path Monitoring (COAX)
DSX cross connect point
TTIPn
TRINGn
R
Monitored Link
RTIPn
r
Monitor Gain
=22 dB
RRINGn
Monitoring Link
Figure 6. Transmit Path Monitoring(COAX)
Table 4: Related Bit / Register In Chapter 3.2
Bit
Register
Address (Hex)
R_TERM[2:0]
MG[1:0]
Transmit And Receive Termination Configuration
Receive Configuration 2
032, 132
02A, 12A
Functional Description
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August 20, 2009
IDT82P2282
3.3
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
ADAPTIVE EQUALIZER
In short haul application, the receive sensitivity is -10 dB in both T1/
J1 and E1 modes. In long haul application, the receive sensitivity is -36
dB in T1/J1 mode or -43 dB in E1 mode.
The Adaptive Equalizer can remove most of the signal distortion
due to intersymbol interference caused by cable attenuation and distortion. Usually, the Adaptive Equalizer is off in short haul applications and
is on in long haul applications, which is configured by the EQ_ON bit.
The peak detector keeps on measuring the peak value of the
incoming signals during a selectable observation period. The observation period is selected by the UPDW[1:0] bits. A shorter observation
period allows quicker response to pulse amplitude variation, while a
longer observation period can minimize the possible overshoots.
Based on the observed peak value for a period, the equalizer will
be adjusted to achieve a normalized signal. The LATT[4:0] bits indicate
the signal attenuation introduced by the cable in approximately 2 dB per
step.
3.4
DATA SLICER
The Data Slicer is used to generate a standard amplitude mark or a
space according to the amplitude of the input signals. The criteria of
mark or space generation are based on a selected ratio of the incoming
signal amplitude against the peak value detected during the observation
period. This ratio is selected by the SLICE[1:0] bits. The output of the
Data Slicer is forwarded to the Clock and Data Recovery unit.
Table 5: Related Bit / Register In Chapter 3.3 & Chapter 3.4
3.5
Bit
Register
Address (Hex)
EQ_ON
UPDW[1:0]
SLICE[1:0]
LATT[4:0]
REFH_LOS
Receive Configuration 1
029, 129
Receive Configuration 2
02A, 12A
Line Status Register 1
Reference Clock Output Control
037, 137
03E,13E
CLOCK AND DATA RECOVERY
The Clock and Data Recovery is used to recover the clock signal
from the received data. It is accomplished by Digital Phase Locked Loop
(DPLL). The recovered clock tracks the jitter in the data output from the
Data Slicer and keeps the phase relationship between data and clock
during the absence of the incoming pulse.
SJET provides two reference clock outputs REFA_OUT and
REFB_OUT. These pins output a recovered clock from the Clock and
Data Recovery function block of one of the two links. The link is selected
by the RO1[0] for REFA_OUT and with RO2[0] for REFB_OUT.
When Loss of Signal (LOS) is detected (Chapter 3.7.3 LOS Detection) on the link selected for REFA_OUT/REFB_OUT, this pin outputs
MCLK (delivered from OSCI input) or a high level signal as selected by
the REFH_LOS bit.
Functional Description
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August 20, 2009
IDT82P2282
3.6
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RECEIVE JITTER ATTENUATOR
Selected by the RJITT_TEST bit, the real time interval between the
read and write pointer of the FIFO or the peak-peak interval between the
read and write pointer of the FIFO can be indicated in the RJITT[6:0]
bits. When the RJITT_TEST bit is ‘0’, the current interval between the
read and write pointer of the FIFO will be written into the RJITT[6:0] bits.
When the RJITT_TEST bit is ‘1’, the current interval will be compared
with the old one in the RJITT[6:0] bits and the larger one will be indicated by the RJITT[6:0] bits.
The performance of Receive Jitter Attenuator meets the ITU-T
I.431, G.703, G.736 - 739, G.823, G.824, ETSI 300011, ETSI TBR 12/
13, AT&T TR62411, TR43802, TR-TSY 009, TR-TSY 253, TR-TRY 499
standards. Refer to Chapter 7.10 Jitter Tolerance and Chapter 7.11 Jitter
Transfer for details.
The Receive Jitter Attenuator of each link can be chosen to be
used or not. This selection is made by the RJA_E bit.
The Jitter Attenuator consists of a FIFO and a DPLL, as shown in
Figure 7.
Jittered Data
Jittered Clock
De-jittered Data
FIFO
32/64/128
write
pointer
DPLL
read
pointer De-jittered Clock
Table 7: Related Bit / Register In Chapter 3.6
Figure 7. Jitter Attenuator
Bit
The FIFO is used as a pool to buffer the jittered input data, then the
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the RJA_DP[1:0]
bits. Accordingly, the constant delay produced by the Jitter Attenuator is
16 bits, 32 bits or 64 bits. The 128-bit FIFO is used when large jitter tolerance is expected, while the 32-bit FIFO is used in delay sensitive
applications.
The DPLL is used to generate a de-jittered clock to clock out the
data stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF). The jitter whose frequency is lower than the CF passes through the DPLL without any attenuation. In T1/J1 applications, the CF of the DPLL can be 5 Hz or 1.26
Hz, as selected by the RJA_BW bit. In E1 applications, the CF of the
DPLL can be 6.77 Hz or 0.87 Hz, as selected by the RJA_BW bit. The
lower the CF is, the longer time is needed to achieve synchronization.
If the incoming data moves faster than the outgoing data, the FIFO
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow or underflow is captured by the
RJA_IS bit. When the RJA_IS bit is ‘1’, an interrupt will be reported on
the INT pin if enabled by the RJA_IE bit.
To avoid overflow or underflow, the JA-Limit function can be
enabled by setting the RJA_LIMT bit. When the JA-Limit function is
enabled, the speed of the outgoing data will be adjusted automatically if
the FIFO is close to its full or emptiness. The criteria of speed adjustment start are listed in Table 6. Though the JA-Limit function can reduce
the possibility of FIFO overflow and underflow, the quality of jitter attenuation is deteriorated.
Register
RJA_E
RJA_DP[1:0]
RJA_BW
Receive Jitter Attenuation Configuration
RJA_LIMT
RJITT_TEST
RJA_IS
Interrupt Status 1
RJA_IE
Interrupt Enable Control 1
RJITT[6:0] Receive Jitter Measure Value Indication
Address (Hex)
027, 127
03B, 13B
034, 134
039, 139
Table 6: Criteria Of Speed Adjustment Start
FIFO Depth
Criteria Of Speed Adjustment Start
32 bits
64 bits
128 bits
2-bit close to full or empty
3-bit close to full or empty
4-bit close to full or empty
Functional Description
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3.7
3.7.1
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
DECODER
3.7.2.2
E1 Mode
The decode errors can be divided into three types in E1 mode:
1. Bipolar Violation (BPV) Error: When AMI line code rule is used,
the BPV error will be detected if two consecutive pulses are received
with the same polarity (refer to Figure 8). The event of the Bipolar Violation (BPV) Error is forwarded to the Performance Monitor.
2. HDB3 Code Violation (CV) Error: When HDB3 line code rule is
used, a CV error is detected if two consecutive BPV errors are detected,
and the pulses that have the same polarity as the previous pulse are not
the HDB3 zero substitution pulsed (refer to Figure 10).
3. Excessive Zero (EXZ) Error: EXZ error can be detected in both
AMI and HDB3 line code rules. There are two standards defining the
EXZ error: ANSI and FCC. The EXZ_DEF bit chooses a standard for the
corresponding link to judge the EXZ error. Table 8 shows the definition of
EXZ. To count the event of the Excessive Zero (EXZ) Error, the
EXZ_ERR[1:0] bits should be set to ‘01’. The Excessive Zero (EXZ)
Error is counted in an internal 16-bit EXZ counter. The content in the
EXZ counter is transferred to the EXZ Error Counter L-Byte & H-Byte
registers in two ways:
a. When the CNT_MD bit is ‘0’, the Manual-Report mode is
selected. The EXZ counter transfers its content to the EXZ Error
Counter L-Byte & H-Byte registers when there is a transition from ‘0’ to
‘1’ on the CNT_TRF bit;
b. When the CNT_MD bit is ‘1’, the Auto-Report mode is selected.
The EXZ counter transfers its content to the EXZ Error Counter L-Byte &
H-Byte registers every one second automatically.
After the content in the counter is transferred to the EXZ Error
Counter L-Byte & H-Byte registers, the counter will be cleared to ‘0’ and
start a new round counting automatically. No error event is lost during
data transferring.
The overflow of the counter is reflected by the CNTOV_IS bit, and
can trigger an interrupt if the corresponding CNT_IE bit is set.
When the Bipolar Violation (BPV) Error or the HDB3 Code Violation
(CV) Error is detected, it will be indicated by the CV_IS bit. When the
Excessive Zero (EXZ) Error is detected, it will be indicated by the
EXZ_IS bit. When the CV_IS bit or the EXZ_IS bit is ‘1’, an interrupt will
be reported by the INT pin if enabled by the corresponding CV_IE bit or
the EXZ_IE bit.
LINE CODE RULE
3.7.1.1
T1 / J1 Mode
In T1/J1 mode, the AMI and B8ZS line code rules are provided. The
selection is made by the R_MD bit.
3.7.1.2
E1 Mode
In E1 mode, the AMI and HDB3 line code rules are provided. The
selection is made by the R_MD bit.
3.7.2
DECODE ERROR DETECTION
3.7.2.1
T1 / J1 Mode
The decode errors can be divided into three types in T1/J1 mode:
1. Bipolar Violation (BPV) Error: When AMI line code rule is used,
the BPV error will be detected if two consecutive pulses are received
with the same polarity (refer to Figure 8). The event of the Bipolar Violation (BPV) Error is forwarded to the Performance Monitor.
2. B8ZS Code Violation (CV) Error: When B8ZS line code rule is
used, a CV error is detected when the received code does not match the
standard B8ZS line code pattern (expect the Excessive Zero error).
3. Excessive Zero (EXZ) Error: EXZ error can be detected in both
AMI and B8ZS line code rules. There are two standards defining the
EXZ error: ANSI and FCC. The EXZ_DEF bit chooses a standard for the
corresponding link to judge the EXZ error. Table 8 shows the definition of
EXZ. To count the event of the Excessive Zero (EXZ) Error, the
EXZ_ERR[1:0] bits should be set to ‘01’. The Excessive Zero (EXZ)
Error is counted in an internal 16-bit EXZ counter. The content in the
EXZ counter is transferred to the EXZ Error Counter L-Byte & H-Byte
registers in two ways:
a. When the CNT_MD bit is ‘0’, the Manual-Report mode is
selected. The EXZ counter transfers its content to the EXZ Error
Counter L-Byte & H-Byte registers when there is a transition from ‘0’ to
‘1’ on the CNT_TRF bit;
b. When the CNT_MD bit is ‘1’, the Auto-Report mode is selected.
The EXZ counter transfers its content to the EXZ Error Counter L-Byte &
H-Byte registers every one second automatically.
After the content in the counter is transferred to the EXZ Error
Counter L-Byte & H-Byte registers, the counter will be cleared to ‘0’ and
start a new round counting automatically. No error event is lost during
data transferring.
The overflow of the counter is reflected by the CNTOV_IS bit, and
can trigger an interrupt if the corresponding CNT_IE bit is set.
When the Bipolar Violation (BPV) Error or the B8ZS Code Violation
(CV) Error is detected, it will be indicated by the CV_IS bit. When the
Excessive Zero (EXZ) Error is detected, it will be indicated by the
EXZ_IS bit. When the CV_IS bit or the EXZ_IS bit is ‘1’, an interrupt will
be reported by the INT pin if enabled by the corresponding CV_IE bit or
the EXZ_IE bit.
Functional Description
Table 8: Excessive Zero Error Definition
ANSI
FCC
More than 15 consecutive 0s are More than 80 consecutive 0s are
AMI
detected.
detected.
More than 7 consecutive 0s are More than 7 consecutive 0s are
B8ZS
detected (refer to Figure 9).
detected (refer to Figure 9).
More than 3 consecutive 0s are More than 3 consecutive 0s are
HDB3
detected (refer to Figure 10).
detected (refer to Figure 10).
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
clock
RTIPn
1
RRINGn
3
5
2
V
4
7
6
Bipolar violation
Figure 8. AMI Bipolar Violation Error
clock
RTIPn
RRINGn
2
4
1
6
3
5
8
8 consecutive
zeros
7
9
Excessive zero
Figure 9. B8ZS Excessive Zero Error
Code violation
clock
RTIPn
RRINGn
1
2
4 consecutive
zeros
3
5
4
V
V
6
Excessive zero
Figure 10. HDB3 Code Violation & Excessive Zero Error
When the LOS is detected, it will be indicated by the LOS_S bit.
Selected by the LOS_IES bit, a transition from '0' to '1' on the LOS_S bit
or any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LOS_S bit will set
the LOS_IS bit to ‘1’. When the LOS_IS bit is ‘1’, an interrupt will be
reported by the INT pin if enabled by the LOS_IE bit.
During LOS, if the RAISE bit is set to ‘1’, all ’One’s will be inserted
to the received data stream.
3.7.3
LOS DETECTION
The Loss of Signal (LOS) Detector monitors the amplitude and density of the received signal. When the received signal is below an amplitude for continuous intervals, the LOS is detected. When the received
signal is above the amplitude and the density of marks meets the
requirement, the LOS is cleared.
The different criteria for LOS Declaring/Clearing are illustrated in
Table 9 and Table 10. In T1/J1 mode, the LOS detection supports ANSI
T1.231 and I.431. In E1 mode, the LOS detection supports ITU-T G.775
and I.431. The criteria are selected by the LAC bit.
Functional Description
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 9: LOS Condition In T1/J1 Mode
Loss of Signal in T1/J1 Mode
Short Haul Application
ANSI T1.231
Amplitude
below 800 mVpp
LOS
Detected Continuous Intervals 175 bits
Amplitude
LOS
Cleared
Mark Density
above 1 Vpp
12.5% (16 marks in a hopping
128-bit window **) with less
than 100 continuous zeros
Long Haul Application
I.431
ANSI T1.231
I.431
below 800 mVpp
1544 bits
below Q dB *
175 bits
below Q dB *
1544 bits
above 1 Vpp
12.5% (16 marks in a hopping
128-bit window **) with less
than 100 continuous zeros
above Q + 4 dB *
12.5% (16 marks in a hopping
128-bit window **) with less
than 100 continuous zeros
above Q + 4 dB *
12.5% (16 marks in a hopping
128-bit window **) with less
than 100 continuous zeros
Note:
* The Q dB is set in the LOS[4:0] bits.
** A hopping 128-bit window means this: An entire 128 bits is taken from the data stream and is checked. If the criteria are not met, all the 128 bits are thrown and another 128 bits are
caught for checking.
Table 10: LOS Condition In E1 Mode
Loss of Signal in E1 Mode
Short Haul Application
G.775
Amplitude
below 800 mVpp
LOS
Detected Continuous Intervals 32 bits
Amplitude
LOS
Cleared
Mark Density
above 1 Vpp
12.5% (4 marks in a hopping
32-bit window **) with less than
16 continuous zeros
Long Haul Application
I.431
G.775
I.431
below 800 mVpp
2048 bits
below Q dB *
32 bits
below Q dB *
2048 bits
above 1 Vpp
12.5% (4 marks in a hopping
32-bit window **) with less than
16 continuous zeros
above Q + 4 dB *
12.5% (4 marks in a hopping
32-bit window **) with less than
16 continuous zeros
above Q + 4 dB *
12.5% (4 marks in a hopping
32-bit window **) with less than
16 continuous zeros
Note:
* The Q dB is set in the LOS[4:0] bits.
** A hopping 32-bit window means this: An entire 32 bits is taken from the data stream and is checked. If the criteria are not met, all the 32 bits are thrown and another 32 bits are caught
for checking.
Functional Description
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Table 11: Related Bit / Register In Chapter 3.7
Bit
Register
Address (Hex)
R_MD
EXZ_ERR
EXZ_DEF
CNT_MD
CNT_TRF
CNTL[7:0]
CNTH[7:0]
CV_IS
EXZ_IS
CNTOV_IS
CV_IE
EXZ_IE
CNT_IE
LAC
RAISE
LOS_S
LOS_IES
LOS_IS
LOS_IE
LOS[4:0]
Receive Configuration 0
028, 128
Maintenance Function Control 2
031, 131
EXZ Error Counter L-Byte
EXZ Error Counter H-Byte
03D, 13D
03C, 13C
Interrupt Status 1
03B, 13B
Interrupt Enable Control 1
034, 134
Maintenance Function Control 1
02C, 12C
Line Status Register 0
Interrupt Trigger Edges Select
Interrupt Status 0
Interrupt Enable Control 0
Receive Configuration 1
036, 136
035, 135
03A, 13A
033, 133
029, 129
Functional Description
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3.8
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
FRAME PROCESSOR
3.8.1.1
Synchronization Searching
3.8.1.1.1
Super Frame (SF) Format
The structure of T1/J1 SF is illustrated in Table 12. The SF is made
up of 12 frames. Each frame consists of one overhead bit (F-bit) and 24
8-bit channels. Its Frame Alignment Pattern is ‘100011011100’ for T1
and ‘10001101110X’ for J1 located in the F-bit position. The same pattern is a mimic pattern if it is received in the data stream other than F-bit.
The synchronization criteria of SF format is selected by the MIMICC bit.
When the MIMICC bit is set to ‘1’, the SF synchronization is acquired if
two consecutive Frame Alignment Patterns are received error free in the
data stream without a mimic pattern. When the MIMICC bit is set to ‘0’,
the SF synchronization is acquired if two consecutive Frame Alignment
Patterns are received error free in the data stream. In this case, the
existence of mimic patterns is ignored. If a mimic pattern exists during
the frame searching procedure, the MIMICI bit will be set to indicate the
presence of a mimic pattern.
The SF synchronization is indicated by ‘0’ in the OOFV bit. The
RMFBI bit is set at the first bit of each SF frame.
3.8.1
T1/J1 MODE
In T1/J1 mode, the Frame Processor searches for the frame alignment patterns in the standard Super-Frame (SF), Extended SuperFrame (ESF), T1 Digital Multiplexer (DM) or Switch Line Carrier - 96
(SLC-96) framing formats. The T1 DM and SLC-96 formats are only supported in T1 mode. The Frame Processor acquires frame alignment per
ITU-T requirement.
When frame alignment is achieved, the Framer Processor continues to monitor the received data stream. The Frame Processor will
declare framing bit errors or bit error events if any. The Frame Processor
can also detect out-of-frame events based on selected criteria.
The Frame Processor can also be bypassed by setting the UNFM
bit.
Table 12: The Structure of SF
Frame No. In The SF
1
2
3
4
5
6
7
8
9
10
11
12
F-Bit (Frame Alignment)
Ft
The Bit In Each Channel
Fs
1
0
0
0
1
1
0
1
1
1
0
X
Data Bit
Signaling Bit
1-8
1-8
1-8
1-8
1-8
1-7
1-8
1-8
1-8
1-8
1-8
1-7
A (bit 8)
B (bit 8)
Note:
‘X’ should be logic 0 in T1 FAS.
‘X’ can be logic 0 or 1 in J1 FAS because this position is used as Yellow Alarm Indication bit.
Functional Description
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
ment Patterns are detected error free in the received data stream without a mimic pattern. When the MIMICC bit is set to ‘0’, the ESF
synchronization is acquired if a single correct Frame Alignment Pattern
and a single correct CRC-6 based on this correct Frame Alignment Pattern are found. In this case, the existence of mimic patterns is ignored. If
a mimic pattern exists during the frame searching procedure, the MIMICI
bit will be set to indicate the presence of a mimic pattern.
The ESF synchronization is indicated by ‘0’ in the OOFV bit. The
RMFBI bit is set at the first bit of each ESF frame.
3.8.1.1.2
Extended Super Frame (ESF) Format
The structure of T1/J1 ESF is illustrated in Table 13. The ESF is
made up of 24 frames. Each frame consists of one overhead bit (F-bit)
and 24 8-bit channels. The F-bit in Frame (4n) (0<n<7) is for Frame
Alignment; the F-bit in Frame (2n-1) (0<n<13) is for Data Link; and the
F-bit in Frame (4n-2) (0<n<7) is for CRC checking.
The Frame Alignment Pattern is ‘001011’, which is located in
Frame (4n) (0<n<7). The same pattern is a mimic pattern if it is received
in the data stream other than F-bit. The synchronization criteria of ESF
format is selected by the MIMICC bit. When the MIMICC bit is set to ‘1’,
the ESF synchronization is acquired if four consecutive Frame AlignTable 13: The Structure of ESF
Frame No. In The ESF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Functional Description
F-Bit Assignment
The Bit In Each Channel
Frame Alignment
Data Link
CRC
Data Bit
Signaling Bit
0
0
1
0
1
1
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
DL
-
C1
C2
C3
C4
C5
C6
-
1-8
1-8
1-8
1-8
1-8
1-7
1-8
1-8
1-8
1-8
1-8
1-7
1-8
1-8
1-8
1-8
1-8
1-7
1-8
1-8
1-8
1-8
1-8
1-7
A (bit 8)
B (bit 8)
C (bit 8)
D (bit 8)
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
acquired if one correct DDS pattern is received before the first F-bit of a
single correct Frame Alignment Pattern. When the DDSC bit is ‘1’, the
T1 DM synchronization is acquired if a single correct Frame Alignment
Pattern is received and twelve correct DDS patterns before each F-bit of
the correct Frame Alignment Pattern are all detected.
The T1-DM synchronization is indicated by ‘0’ in the OOFV bit. The
RMFBI bit is set at the first bit of each T1 DM frame.
3.8.1.1.3
T1 Digital Multiplexer (DM) Format (T1 only)
The structure of T1 DM is illustrated in Table 14. The T1 DM is
made up of 12 frames. Each frame consists of one overhead bit (F-bit)
and 24 8-bit channels. Except for channel 24, all other channels carry
data. Channel 24 should be ‘0DY11101’. Its Frame Alignment Pattern is
‘100011011100’ in the F-bit. The fixed 6 bits in channel 24 are called
DDS.
The synchronization criteria of T1 DM format are selected by the
DDSC bit. When the DDSC bit is ‘0’, the T1 DM synchronization is
Table 14: The Structure of T1 DM
Frame No. In The T1 DM
1
2
3
4
5
6
7
8
9
10
11
12
F-Bit (Frame Alignment)
Ft
Fs
1
0
0
0
1
1
0
1
1
1
0
0
Channel 24
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
Note:
In Channel 24, the ‘D’ bit is used for data link, and the ‘Y’ bit is used for alarm. The other 6 bits are fixed and they are called ‘DDS’ pattern.
Functional Description
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
positions in the data stream, the SLC-96 synchronization is acquired.
The first frame is numbered from the frame whose F-bit contains the first
‘1’ of the Frame Alignment Pattern.
The SLC-96 synchronization is indicated by ‘0’ in the OOFV bit.
The RMFBI bit is set at the first bit of each SLC-96 frame.
3.8.1.1.4
Switch Line Carrier - 96 (SLC-96) Format (T1 only)
The structure of SLC-96 is illustrated in Table 15. The SLC-96 is
made up of 6 SFs, but some F-bit are used as Concentrator Bits, Spoiler
Bits, Maintenance Bits, Alarm Bits and Switch Bits. Each frame consists
of one overhead bit (F-bit) and 24 8-bit channels. Its Frame Alignment
Pattern is ‘001000110111001000110111’ in 24 consecutive F-bit positions. If the Frame Alignment Pattern is found in 24 consecutive F-bit
Table 15: The Structure of SLC-96
Frame No.
F-Bit (Frame Alignment) - Ft
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Functional Description
The Bit In Each Channel
Data Bit
Signaling Bit
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
1-8
-
37
Frame No.
F-Bit (Frame Alignment) - Fs
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
0
0
1
1
1
0
0
0
1
1
1
C1 (Concentrator Bit)
C2 (Concentrator Bit)
C3 (Concentrator Bit)
C4 (Concentrator Bit)
C5 (Concentrator Bit)
C6 (Concentrator Bit)
C7 (Concentrator Bit)
C8 (Concentrator Bit)
C9 (Concentrator Bit)
C10 (Concentrator Bit)
C11 (Concentrator Bit)
0 (Spoiler Bit)
1 (Spoiler Bit)
0 (Spoiler Bit)
M1 (Maintenance Bit)
M2 (Maintenance Bit)
M3 (Maintenance Bit)
A1 (Alarm Bit)
A2 (Alarm Bit)
S1 (Switch Bit)
S2 (Switch Bit)
S3 (Switch Bit)
S4 (Switch Bit)
1 (Spoiler Bit)
0
The Bit In Each Channel
Data Bit
Signaling Bit
1-8
1-8
1-7
1-8
1-8
1-7
1-8
1-8
1-7
1-8
1-8
1-7
1-8
1-8
1-7
1-8
1-8
1-7
1-8
1-8
1-7
1-8
1-8
1-7
1-8
1-8
1-7
1-8
1-8
1-7
1-8
1-8
1-7
1-8
1-8
1-7
A (bit 8)
B (bit 8)
C (bit 8)
D (bit 8)
A (bit 8)
B (bit 8)
C (bit 8)
D (bit 8)
A (bit 8)
B (bit 8)
C (bit 8)
D (bit 8)
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
except for manually setting. The manual reframe is executed by a transition from ‘0’ to ‘1’ on the REFR bit. During out of synchronization state,
the error event detection is suspended.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Performance Monitor.
3.8.1.2
Error Event And Out Of Synchronization Detection
After the frame is in synchronization, the Frame Processor continues to monitor the received data stream to detect errors and judge if it is
out of synchronization.
3.8.1.2.1
Super Frame (SF) Format
In SF format, two kinds of errors are detected:
1. Severely Ft Bit Error: Each received Ft bit is compared with the
expected one (refer to Table 12). Each unmatched Ft bit leads to an Ft
bit error event. When 2 or more Ft bit errors are detected in a 6-basicframe fixed window, the severely Ft bit error occurs. This error event is
captured by the SFEI bit.
2. F Bit Error: Each received F bit is compared with the expected
one (refer to Table 12). Each unmatched F bit leads to an F bit error
event. This error event is captured by the FERI bit and is forwarded to
the Performance Monitor.
When the F Bit Error number exceeds the ratio set in the M2O[1:0]
bits, it is out of synchronization. Then if the REFEN bit is ‘1’, the Frame
Processor will start to search for synchronization again. If the REFEN bit
is ‘0’, no error can lead to reframe except for manually setting. The manual reframe is executed by a transition from ‘0’ to ‘1’ on the REFR bit.
During out of synchronization state, the error event detection is suspended.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Performance Monitor.
3.8.1.2.3
T1 Digital Multiplexer (DM) Format (T1 only)
In T1 DM format, three kinds of errors are detected:
1. Severely Ft Bit Error: Each received Ft bit is compared with the
expected one (refer to Table 14). Each unmatched Ft bit leads to an Ft
bit error event. When 2 or more Ft bit errors are detected in a 6-basicframe fixed window, the severely Ft bit error occurs. This error event is
captured by the SFEI bit.
2. F Bit Error: Each received F bit is compared with the expected
one (refer to Table 14). Each unmatched F bit leads to an F bit error
event. This error event is captured by the FERI bit and is forwarded to
the Performance Monitor.
3. DDS Pattern Error: The received 6-bit DDS in each CH24 is
compared with the DDS pattern - ‘0XX11101’ (MSB left and ‘X’ is not
cared). When one or more bits do not match the DDS pattern, a single
DDS pattern error event is generated. This error event is forwarded to
the Performance Monitor.
The 6-bit DDS pattern and its following F-bit make up a 7-bit pattern. When one or more bits do not match its pattern (refer to Table 14),
a single error is generated. When this error number exceeds the ratio
set in the M2O[1:0] bits, it is out of synchronization. Then if the REFEN
bit is ‘1’, the Frame Processor will start to search for synchronization
again. If the REFEN bit is ‘0’, no error can lead to reframe except for
manually setting. The manual reframe is executed by a transition from
‘0’ to ‘1’ on the REFR bit. During out of synchronization state, the error
event detection is suspended.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Performance Monitor.
3.8.1.2.2
Extended Super Frame (ESF) Format
In ESF format, four kinds of errors are detected:
1. Frame Alignment Bit Error: Each received Frame Alignment bit is
compared with the expected one (refer to Table 13). Each unmatched bit
leads to a frame alignment bit error event. This error event is captured
by the FERI bit and is forwarded to the Performance Monitor.
2. CRC-6 Error: When the local calculated CRC-6 of the current
received ESF frame does not match the received CRC-6 of the next
received ESF frame, a single CRC-6 error event is generated. This error
event is captured by the BEEI bit and is forwarded to the Performance
Monitor.
3. Excessive CRC-6 Error: Once the accumulated CRC-6 errors
exceed 319 occasions (> 319) in a 1 second fixed window, an excessive
CRC-6 error event is generated. This error event is captured by the
EXCRCERI bit and is forwarded to the Performance Monitor.
4. Severely Frame Alignment Bit Error: When 2 or more frame
alignment bit errors are detected in a 1-ESF-frame fixed window, the
severely frame alignment bit error occurs. This error event is captured
by the SFEI bit.
When the Frame Alignment Bit Error number exceeds the ratio set
in the M2O[1:0] bits, it is out of synchronization. Then if the REFEN bit is
‘1’, the Frame Processor will start to search for synchronization again.
Additionally, the Excessive CRC-6 Error also leads to out of ESF synchronization. In this condition, both the REFEN bit being ‘1’ and the
REFCRCE bit being ‘1’ will allow the Frame Processor to search for synchronization again. If the REFEN bit is ‘0’, no error can lead to reframe
Functional Description
3.8.1.2.4
Switch Line Carrier - 96 (SLC-96) Format (T1 only)
In SLC-96 format, only one kind of error is detected:
1. F Bit Error: The Ft bit in each odd frame and the Fs bit in Frame
(2n) (0<n<12 and n=36) is compared with the expected one (refer to
Table 15). Each unmatched bit leads to a F-bit error event. This error
event is captured by the FERI bit and is forwarded to the Performance
Monitor.
Each unmatched Ft bit in the odd frame and each unmatched Fs bit
in Frame (2n) (0<n<12 and n=36) are also counted separately. When the
number of either of them exceeds the ratio set in the M2O[1:0] bits, it is
out of synchronization. Then if the REFEN bit is ‘1’, the Frame Processor will start to search for synchronization again. If the REFEN bit is ‘0’,
no error can lead to reframe except for manually setting. The manual
reframe is executed by a transition from ‘0’ to ‘1’ on the REFR bit. During
out of synchronization state, the error event detection is suspended.
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The value in the RDL0, RDL1 & RDL2 registers is held during out of
SLC-96 synchronization state.
Once resynchronized, if the new-found F bit position differs from
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Performance Monitor.
3.8.1.4
Interrupt Summary
The interrupt sources in this block are summarized in Table 16.
When there are conditions meeting the interrupt sources, the corresponding Status bit will be asserted high. When there is a transition
(from ‘1’ to ‘0’ or from ‘0’ to ‘1’) on the Status bit, the corresponding Status Interrupt Indication bit will be set to ‘1’ (If the Status bit does not
exist, the source will cause its Status Interrupt Indication bit to ‘1’
directly) and the Status Interrupt Indication bit will be cleared by writing
‘1’. A ‘1’ in the Status Interrupt Indication bit indicates an interrupt
occurred. The interrupt is reported by the INT pin if its Status Interrupt
Enable bit was set to ‘1’.
3.8.1.3
Overhead Extraction (T1 Mode SLC-96 Format Only)
In SLC-96 format, the Concentrator bits, Maintenance bits, Alarm
bits and Switch bits are all extracted to the RDL0, RDL1 & RDL2 registers respectively.
All these extractions will be set to de-bounce if the SCDEB bit is set
to ‘1’. Thus, the value in the RDL0, RDL1 & RDL2 registers are updated
if the received corresponding code is the same for 2 consecutive SLC96 frames. Whether de-bounced or not, a change indication will be set in
the SCCI bit, SCMI bit, SCAI bit and SCSI bit respectively if the corresponding codes in the RDL0, RDL1 & RDL2 registers differ from the previous ones.
Table 16: Interrupt Source In T1/J1 Frame Processor
Sources
Status Bit
It is out of synchronization.
The first bit of each SF / ESF / T1 DM / SLC-96 frame is received.
The new-found F bit position differs from the previous one.
In SF / T1 DM / SLC-96 format, the F Bit Error occurs.
In ESF format, the Frame Alignment Bit Error occurs.
In ESF format, the CRC-6 Error occurs.
(This interrupt does not exist in other formats.)
In SF / T1 DM format, the Severely Ft Bit Error occurs.
In ESF format, the Severely Frame Alignment Bit Error occurs.
(This interrupt does not exist in SLC-96 format.)
In SLC-96 format, the Concentrator bits differ from the previous ones.
In SLC-96 format, the Maintenance bits differ from the previous ones.
In SLC-96 format, the Alarm bits differ from the previous ones.
In SLC-96 format, the Switch bits differ from the previous ones.
Functional Description
39
Interrupt Indication Bit Interrupt Enable Bit
OOFV
-
OOFI
RMFBI
COFAI
FERI
OOFE
RMFBE
COFAE
FERE
-
BEEI
BEEE
-
SFEI
SFEE
-
SCCI
SCMI
SCAI
SCSI
SCCE
SCME
SCAE
SCSE
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 17: Related Bit / Register In Chapter 3.8.1
Bit
UNFM
REFEN
REFR
REFCRCE
MIMICC
M2O[1:0]
DDSC
OOFV
MIMICI
EXCRCERI
OOFI
RMFBI
SFEI
BEEI
FERI
COFAI
OOFE
RMFBE
SFEE
BEEE
FERE
COFAE
C[11:1]
M[3:1]
A[2:1]
S[4:1]
SCAI
SCSI
SCMI
SCCI
SCDEB
SCAE
SCSE
SCME
SCCE
Functional Description
Register
T1/J1 Address (Hex)
FRMR Mode 0
04D, 14D
FRMR Mode 1
04E, 14E
FRMR Status
04F, 14F
FRMR Interrupt Indication 0
052, 152
FRMR Interrupt Indication 1
053, 153
FRMR Interrupt Control 0
050, 150
FRMR Interrupt Control 1
051, 151
RDL1 & RDL0
RDL1
057, 157 & 056, 156
057, 157
RDL2
058, 158
DLB Interrupt Indication
05D, 15D
DLB Interrupt Control
05C, 15C
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3.8.2
E1 MODE
In E1 mode, the Frame Processor searches for Basic Frame synchronization, CRC Multi-frame synchronization, and Channel Associated
Signaling (CAS) Multi-frame synchronization in the received data
stream. Figure 11 shows the searching process.
Once the frame is synchronized, the Frame Processor keeps on
monitoring the received data stream. If there are any framing bit errors,
CAS Multi-Frame alignment pattern errors, CRC Multi-Frame alignment
pattern errors or CRC errors, the Frame Processor will indicate these
errors. The status of loss of frame, loss of Signaling Multi-Frame and
loss of CRC Multi-Frame can also be detected and declared based on
user-selectable criteria. A software reset can also make the Frame Processor reframe.
The Frame Processor can extract the data stream in TS16, and
output the extracted data on a separate pin. The Frame Processor also
extracts the contents of the International bits (from both the FAS and the
NFAS frames), the National bits and the Extra bits (from TS16 in the
frame 0 of the Signaling Multi-Frame), and stores these data in registers.
The CRC Sub Multi-Frame alignment 4 bit codeword in the National bit
positions Sa4 to Sa8 can also be extracted and stored in registers, and
updated every CRC Sub Multi-Frame.
The Framer Processor identifies the Remote Alarm bit (bit 3 of TS0
of NFAS frames) and Remote Signaling Multi-Frame Alarm (bit 6 of
TS16 of the frame 0 of the Signaling Multi-Frame). The ‘de-bounced’
Remote Alarm and Remote Signaling Multi-Frame Alarm can be indicated if the corresponding bit has been a certain logic for 1 or 4 consecutive times. The AIS (Alarm Indication Signal) Alarm can also be
detected. The Frame Processor can also declare a Red Alarm if the outof-frame condition has persisted for at least 100 ms.
An interrupt output is provided to indicate status changes and the
occurrence of some events. The interrupts may be generated every
Basic Frame, CRC Sub Multi-Frame, CRC Multi-Frame or Signaling
Multi-Frame.
The Frame Processor can also be bypassed by setting the UNFM
bit.
Functional Description
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Out of sync.
OOFV = 1, OOCMFV = 1,
OOSMFV = 1, OOOFV = 0
search for Basic Fframe alignment pattern
(refer to Basic Frame)
find FAS in
th
N frame
No (N=N+1)
Yes
3 consecutive FAS or NFAS
errors (criteria selected by the
BIT2C) or manually re-frame
find NFAS in
(N+1)th frame
No (skip one
frame, N=N+3)
Yes
find FAS in
(N+2)th frame
Yes
No (N=N+3)
Basic Frame sync. acquired
OOFV = 0
Start to check FAS errors
> 914
CRC
search for CRC Multi-Frame
errors in
alignment pattern if CRCEN =
one
1 (refer to CRC Multi-Frame)
second
search for Signaling Multi-Frame
alignment if CASEN = 1 (refer to
Signaling Multi-Frame)
Start 8ms and
400ms timer
find Signaling
Multi-Frame alignment
pattern
No
find 2 CRC Multi-Frame
alignment patterns within 8ms, with the
interval time of each pattern being a
multiple of 2ms
Yes
No, and
8ms
expired
Lock the Sync. Position
Start Offline Frame
search OOOFV = 1
find FAS in
nth frame
No (n = n+1)
Yes
CRC Multi-Frame sync.
acquired; Start CRC and
E-bits processing;
OOCMFV = 0, OOFV = 0 CRC
to CRC interworking
find NFAS in
(n+1)th frame
No (skip one
frame, n=n+3)
Yes
Yes
Signaling
Multi-Frame sync.
acquired
check for out
of Signaling Multi-Frame
Sync conditions which criteria
are set in the SMFASC
& TS16C
No
Yes
find FAS in
th
(n+2) frame
Yes
No (n=n+3)
Basic Frame sync. acquired
OOOFV = 0
Start 8ms timer
No, and
8ms
expired
find 2 CRC Multi-Frame
alignment patterns within 8ms, with the
interval time of each pattern being a
multiple of 2ms
Yes
No, and 400ms
expired with
basic frame sync.
C2NCIWV = 1
CRC to non-CRC
interworking
Stop CRC processing if
C2NCIWCK = 0
Figure 11. E1 Frame Searching Process
Functional Description
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Synchronization Searching
3.8.2.1.1
Basic Frame
The algorithm used to search for the E1 Basic Frame alignment
pattern (as shown in Figure 12) meets the ITU-T Recommendation
G.706 4.1.2 and 4.2.
Generally, it is performed by detecting a successive FAS/NFAS/
FAS sequence. If STEP 2 is not met, a new searching will start after the
following frame is skipped. If STEP 3 is not met, a new searching will
start immediately in the next frame. Once the Basic Frame alignment
pattern is detected in the received PCM data stream, the Basic Frame
synchronization is found and the OOFV bit will be set to ‘0’ for indication.
STEP1: Search
for 7-bit Frame Alignment
Sequence (FAS) (X0011011)
th
in the N frame
No (skip
one frame,
N=N+3)
No (N=N+1)
Yes
STEP 2: Find logic 1 in the
2nd bit of TS0 of the (N+1)th frame to ensure
that this is a non-frame alignment
sequence (NFAS)
Yes
STEP 3: Search for
the correct 7-bit FAS (X0011011)
th
in the TS0 in the (N+2)
frame
No
(N=N+3)
Yes
Basic Frame
Synchronization Found
Figure 12. Basic Frame Searching Process
Functional Description
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The first bit of TS0 of each frame is called the International (Si) bit.
The Si bit in each even frame is the CRC bit. Thus, there are C1, C2,
C3, C4 in each SMF. The C1 is the most significant bit, while the C4 is
the least significant bit. The Si bit in the first six odd frames is the CRC
Multi-Frame alignment pattern. Its pattern is ‘001011’. The Si bit in
Frame 13 and Frame 15 are E1 and E2 bits. The value of the E bits can
indicate the Far End Block Errors (FEBE).
3.8.2.1.2
CRC Multi-Frame
The CRC Multi-Frame is provided to enhance the ability of verifying
the data stream. The structure of TS0 of the CRC Multi-Frame is illustrated in Table 18.
A CRC Multi-Frame consists of 16 continuous Basic Frames (No. 0
– 15) which are numbered from a Basic Frame with FAS. Each CRC
Multi-Frame can be divided into two Sub Multi-Frames (SMF I & SMF II).
Table 18: The Structure Of TS0 In CRC Multi-Frame
SMF
SMF I
CRC-4
Multi-Frame
SMF II
the Eight Bits in Timeslot 0
Basic Frame
No. / Type
1 (Si bit)
2
3
4
5
6
7
8
0 / FAS
1 / NFAS
2 / FAS
3 / NFAS
4 / FAS
5 / NFAS
6 / FAS
7 / NFAS
8 / FAS
9 / NFAS
10 / FAS
11 / NFAS
12 / FAS
13 / NFAS
14 / FAS
15 / NFAS
C1
0
C2
0
C3
1
C4
0
C1
1
C2
1
C3
E1
C4
E2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
A
0
A
0
A
0
A
0
A
0
A
0
A
0
A
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa5
1
Sa5
1
Sa5
1
Sa5
1
Sa5
1
Sa5
1
Sa5
1
Sa5
0
Sa6
0
Sa6
0
Sa6
0
Sa6
0
Sa6
0
Sa6
0
Sa6
0
Sa6
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa8
1
Sa8
1
Sa8
1
Sa8
1
Sa8
1
Sa8
1
Sa8
1
Sa8
this process, the CRC Multi-Frame alignment pattern can still be
searched if the C2NCIWCK bit is logic 1.
After the Basic Frame has been synchronized, the Frame Processor initiates an 8 and a 400 ms timer to check the CRC Multi-Frame
alignment signal if the CRCEN bit is ‘1’. The CRC Multi-Frame synchronization is declared with a ‘0’ in the OOCMFV bit only if at least two CRC
Multi-Frame alignment patterns are found within 8 ms, with the interval
time of each pattern being a multiple of 2 ms. Then if the received CRC
Multi-Frame alignment signal does not meet its pattern, it will be indicated by the CMFERI bit.
If the 2 CRC Multi-Frame alignment patterns can not be found
within 8ms with the interval time being a multiple of 2 ms, an offline
search for the Basic Frame alignment pattern will start which is indicated
in the OOOFV bit. The process is the same as shown in Figure 12. This
offline operation searches in parallel with the pre-found Basic Frame
synchronization searching process. After the new Basic Frame synchronization is found by this offline search, the 8 ms timer is restarted to
check whether the two CRC Multi-Frame alignment patterns are found
within 8 ms, with the interval time of each pattern being a multiple of 2
ms again. If the condition can not be met, the procedure will go on until
the 400 ms timer ends. If the condition still can not be met at that time
and the Basic Frame is still synchronized, the device declares by the
C2NCIWV bit to run under the CRC to non-CRC interworking process. In
Functional Description
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3.8.2.2
Error Event And Out Of Synchronization Detection
After the frame is in synchronization, the Frame Processor keeps
on monitoring the received data stream to detect errors and judge if it is
out of synchronization.
The following ten kinds of errors are detected:
1. FAS/NFAS Bit/Pattern Error: The criteria of this error are determined by the WORDERR bit and the CNTNFAS bit (refer to Table 19).
This error event is captured by the FERI bit and is forwarded to the Performance Monitor.
3.8.2.1.3
CAS Signaling Multi-Frame
After the Basic Frame has been synchronized, the Frame Processor starts to search for CAS Signaling Multi-Frame alignment signal if
the CASEN bit is ‘1’.
The Signaling Multi-Frame alignment pattern is located in the high
nibble (Bit 1 ~ Bit 4) of TS16. Its pattern is ‘0000’. When the pattern is
found in TS16 and the high nibble of the previous TS16 are not all zeros,
the Signaling Multi-Frame synchronization is acquired and it is indicated
with a ‘0’ in the OOSMFV bit. The frame containing the Signaling MultiFrame alignment pattern is Frame 0 of Signaling Multi-Frame. The TS16
structure of the Signaling Multi-Frame is shown in Figure 13. The entire
content in TS16 of Frame 0 of Signaling Multi-Frame is ‘0000XYXX’. ‘Y’
is for remote Signaling Multi-Frame alarm indication and ‘X’s are extra
bits. The codeword ‘ABCD’ are the signaling bits for different timeslots.
Table 19: FAS/NFAS Bit/Pattern Error Criteria
WORDERR CNTNFAS
TS16 (Bit 1 - Bit 8)
F0
0
0
0
0
X0
Signaling Multi-Frame
alignment pattern
F1
A
B
C
D
A
B
C
A
A
B
C
for TS15
X2
B
C
D
A
B
C
D
D
for TS18
D
A
B
C
D
for TS31
Figure 13. TS16 Structure Of CAS Signaling MultiFrame
Functional Description
0
0
1
1
1
Error Generation
Each bit error in FAS is counted as an error event.
A FAS pattern error is counted as an error event.
Each bit error in FAS or NFAS error is counted as an
error event.
A FAS pattern error or NFAS error is counted as an
error event.
2. CRC Multi-Frame Alignment Pattern Error: The received CRC
Multi-Frame alignment signals are compared with the expected ones
(‘001011’). When one or more bits do not match, a single CRC MultiFrame alignment pattern error event is generated. This error event is
captured by the CMFERI bit.
3. CRC-4 Error: When the local calculated CRC-4 of the current
received CRC Sub Multi-Frame does not match the received CRC-4 of
the next received CRC Sub Multi-Frame, a single CRC-4 error event is
generated. This error event is captured by the CRCEI bit and is forwarded to the Performance Monitor.
4. Excessive CRC-4 Error: Once the accumulated CRC-4 errors
are not less than 915 occasions (915 is included) in a 1 second fixed
window, an excessive CRC-4 error event is generated. This error event
is captured by the EXCRCERI bit.
5. CAS Signaling Multi-Frame Alignment Pattern Error: The
received Signaling Multi-Frame alignment signals are compared with the
expected ones (‘0000’). When one or more bits do not match, a single
CAS Signaling Multi-Frame alignment pattern error event is generated.
This error event is captured by the SMFERI bit.
6. Far End Block Error (FEBE): When any of the CRC error indication (E1 or E2) bits is received as a logic 0, a far end block error event is
generated. This error event is captured by the FEBEI bit and is forwarded to the Performance Monitor.
7. Continuous RAI & FEBE Error: When a logic 1 is received in the
A bit and a logic 0 is received in any of the E1 or E2 bit for 10 ms, the
RAICRCV bit is set. This bit is cleared if any of the conditions is not met.
8. Continuous FEBE Error: When a logic 0 is received in any of the
E1 or E2 bits on ≥ 990 occasions per second for the latest 5 consecutive
seconds, the CFEBEV bit is set, otherwise this bit will be cleared.
9. NT FEBE Error (per ETS 300 233): If the 4-bit Sa6 codeword of a
CRC Sub Multi-Frame is matched with ‘0001’ or ‘0011’, the Network Terminal Far End Block Error event is generated. This error event is captured by the TFEBEI bit and is forwarded to the Performance Monitor.
for TS17
for TS2
F15
X1
RMAI
Extra Bits
for TS1
F2
Y
0
1
0
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.8.2.3
10. NT CRC Error (per ETS 300 233): If the 4-bit Sa6 codeword of
a CRC Sub Multi-Frame is matched with ‘0010’ or ‘0011’, the Network
Terminal CRC Error event is generated. This error event is captured by
the TCRCEI bit and is forwarded to the Performance Monitor.
Overhead Extraction
3.8.2.3.1
International Bit Extraction
The International bits (Si bits, refer to Table 18) are extracted to the
Si[0:1] bits in the TS0 International / National register. The Si[0:1] bits in
the TS0 International / National register are updated on the boundary of
the associated FAS/NFAS frame and are held during out of Basic frame
state.
Various errors will lead to out of synchronization:
3.8.2.2.1
Out Of Basic Frame Synchronization
If there is one or more bit errors in a FAS pattern, a FAS pattern
error will occur. If the NFAS bit position is received as zero, a NFAS error
will occur. Determined by the BIT2C bit, if this bit is ‘0’, 3 consecutive
FAS pattern errors lead to out of Basic frame synchronization; if this bit
is ‘1’, 3 consecutive FAS pattern errors or 3 consecutive NFAS errors
lead to out of Basic frame synchronization. Then if the REFEN bit is ‘1’,
the Frame Processor will start to search for synchronization again. Additionally, Excessive CRC-4 Error also leads to out of Basic frame synchronization. In this condition, both the REFEN bit being ‘1’ and the
REFCRCE bit being ‘1’ will allow the Frame Processor to search for synchronization again. If the REFEN bit is ‘0’, no error can lead to reframe
except for manually setting. The manual reframe searches from Basic
frame and is executed by a transition from ‘0’ to ‘1’ on the REFR bit. During out of Basic frame synchronization state, the FAS/NFAS Bit/Pattern
Error detection is suspended.
Once resynchronized, if the new-found Basic frame alignment pattern position differs from the previous one, the change of frame alignment event is generated. This event is captured by the COFAI bit and is
forwarded to the Performance Monitor.
3.8.2.3.2
Remote Alarm Indication Bit Extraction
The Remote Alarm Indication bit (A bit, refer to Table 18) is
extracted to the A bit in the TS0 International / National register. The A
bit in the TS0 International / National register is updated on the boundary of the associated NFAS frame and is held during out of Basic frame
state.
3.8.2.3.3
National Bit Extraction
The National bits (Sa bits, refer to Table 18) are extracted to the
Sa[4:8] bits in the TS0 International / National register. The Sa[4:8] bits
in the TS0 International / National register are updated on the boundary
of the associated NFAS frame and are held during out of Basic frame.
3.8.2.3.4
National Bit Codeword Extraction
The five sets of the National Bit codewords (Sa4[1:4] to Sa8[1:4] in
the CRC Sub Multi-Frame, refer to Table 18) are extracted to the corresponding SaX Codeword register. Here the ‘X’ is from 4 through 8. The
National Bit codeword extraction will be set to de-bounce if the SaDEB
bit is set to ‘1’. Thus, the SaX Codeword registers are updated if the
received National Bit codeword is the same for 2 consecutive CRC Sub
Multi-Frames. Whether de-bounced or not, a change indication will be
set in the SaXI bit (‘X’ is from 4 through 8) if the corresponding codeword
in the SaX Codeword register differs from the previous one.
The value in the SaX Codeword registers is held during out of CRC
Multi-Frame synchronization state.
3.8.2.2.2
Out Of CRC Multi-Frame Synchronization
The conditions introducing out of Basic frame synchronization will
also cause out of CRC Multi-Frame synchronization. During out of CRC
Multi-Frame synchronization state, the FAS/NFAS Bit/Pattern Error
detection, CRC Multi-Frame Alignment Pattern Error detection, CRC-4
Error detection, Excessive CRC-4 Error detection, Far End Block Error
detection, Continuous RAI & FEBE Error detection, Continuous FEBE
Error detection, NT CRC Error detection and NT FEBE Error detection
are suspended.
3.8.2.3.5
Extra Bit Extraction
The Extra bits (X bits, refer to Figure 13) are extracted to the X[0:2]
bits in the TS16 Spare register. The X[0:2] bits in the TS16 Spare register are updated at the first bit of the next CAS Signaling Multi-Frame and
are held during out of CAS Signaling Multi-Frame state.
3.8.2.2.3
Out Of CAS Signaling Multi-Frame Synchronization
The conditions introducing out of Basic frame synchronization will
also cause out of CAS Signaling Multi-Frame synchronization.
In addition, determined by the SMFASC bit and the TS16C bit, if the
CAS Signaling Multi-Frame Alignment Pattern Error occurs or all the
contents in TS16 are zeros, it is out of CAS Signaling Multi-Frame synchronization. Then no matter what the value in the REFEN bit is, the
Frame Processor will search for the CAS Signaling Multi-Frame synchronization again only if the Basic frame is in synchronization. During
out of CAS Signaling Multi-Frame synchronization state, the CAS Signaling Multi-Frame Alignment Pattern Error detection is suspended.
3.8.2.3.6
Remote Signaling Multi-Frame Alarm Indication Bit
Extraction
The Remote Signaling Multi-Frame Alarm Indication bit (Y bit, refer
to Figure 13) are extracted to the Y bit in the TS16 Spare register. The Y
bit in the TS16 Spare register is updated at the first bit of the next CAS
Signaling Multi-Frame and is held during out of CAS Signaling MultiFrame state.
3.8.2.3.7
Sa6 Code Detection Per ETS 300 233
When Basic frame is synchronized, any 12 consecutive Sa6 bits
(MSB is the first received bit) are compared with 0x888, 0xAAA, 0xCCC,
0xEEE and 0xFFF. When CRC Multi-Frame is synchronized, any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are com-
Functional Description
46
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
sponding Status bit will be asserted high. When there is a transition
(from ‘1’ to ‘0’ or from ‘0’ to ‘1’) on the Status bit, the corresponding Status Interrupt Indication bit will be set to ‘1’ (If the Status bit does not
exist, the source will cause its Status Interrupt Indication bit to ‘1’
directly) and the Status Interrupt Indication bit will be cleared by a write
signal. A ‘1’ in the Status Interrupt Indication bit means an interrupt
occurred. The interrupt will be reported by the INT pin if its Status Interrupt Enable bit is ‘1’.
pared if the Sa6SYN bit is ‘1’. If a matched code is detected, the
corresponding indication bit in the Sa6 Code Indication register will be
set.
3.8.2.4
V5.2 Link
The V5.2 link ID signal, i.e., 2 out of 3 sliding Sa7 bits being logic 0,
is detected with the indication in the V52LINKV bit. This detection is disabled when the Basic Frame is out of synchronization.
3.8.2.5
Interrupt Summary
The interrupt sources in this block are summarized in Table 20.
When there are conditions meeting the interrupt sources, the correTable 20: Interrupt Source In E1 Frame Processor
Sources
In CRC to Non-CRC inter-working.
It is out of Basic frame synchronization.
It is out of CRC multi-frame synchronization.
It is out of CAS Signaling multi-frame synchronization.
The new-found Basic frame alignment pattern position differs from the previous one.
FAS/NFAS Bit/Pattern Error occurs.
CRC Multi-Frame Alignment Pattern Error occurs.
CAS Signaling Multi-Frame Alignment Pattern Error occurs.
CRC-4 Error occurs.
Offline Basic frame search indication.
Far End Block Error occurs.
Continuous RAI & FEBE Error occurs.
Continuous FEBE Error occurs.
At the first bit of each CRC Multi-Frame.
At the first bit of each CRC Sub Multi-Frame.
At the first bit of each CAS Signaling Multi-Frame.
There is change in the corresponding SaX[1:4] bits. The ‘X’ is from 4 through 8.
Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords are matched
with 0x888, 0xAAA, 0xCCC, 0xEEE or 0xFFF.
NT FEBE Error occurs.
NT CRC Error occurs.
2 out of 3 sliding Sa7 bits are received as logic 0.
Functional Description
47
Status Bit
Interrupt Indication Bit
Interrupt Enable Bit
C2NCIWV
OOFV
OOCMFV
OOSMFV
OOOFV
RAICRCV
CFEBEV
-
C2NCIWI
OOFI
OOCMFI
OOSMFI
COFAI
FERI
CMFERI
SMFERI
CRCEI
OOOFI
FEBEI
RAICRCI
CFEBEI
ICMFPI
ICSMFPI
ISMFPI
Sa4I / Sa5I / Sa6I / Sa7I /
Sa8I
Sa6SCI
C2NCIWE
OOFE
OOCMFE
OOSMFE
COFAE
FERE
CMFERE
SMFERE
CRCEE
OOOFE
FEBEE
RAICRCE
CFEBEE
ICMFPE
ICSMFPE
ISMFPE
Sa4E / Sa5E / Sa6E /
Sa7E / Sa8E
Sa6SCE
V52LINKV
TFEBEI
TCRCEI
V52LINKI
TFEBEE
TCRCEE
V52LINKE
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 21: Related Bit / Register In Chapter 3.8.2 (Continued)
Bit
Table 21: Related Bit / Register In Chapter 3.8.2
Bit
UNFM
REFEN
REFCRCE
REFR
CRCEN
C2NCIWCK
CASEN
WORDERR
CNTNFAS
BIT2C
SMFASC
TS16C
OOFV
OOCMFV
OOOFV
C2NCIWV
OOSMFV
EXCRCERI
C2NCIWI
OOFI
OOCMFI
OOSMFI
OOOFI
OOFE
OOCMFE
OOOFE
C2NCIWE
OOSMFE
CMFERI
FERI
CRCEI
SMFERI
COFAI
ICMFPI
ICSMFPI
ISMFPI
CMFERE
FERE
CRCEE
SMFERE
COFAE
ICMFPE
ICSMFPE
ISMFPE
Register
E1 Address (Hex)
FRMR Mode 0
04D, 14D
FRMR Mode 1
FRMR Status
FRMR Interrupt Indication 0
FRMR Interrupt Control 0
04E, 14E
04F, 14F
052, 152
050, 150
FRMR Interrupt Indication 1
053, 153
FRMR Interrupt Control 1
051, 151
Functional Description
RAICRCV
CFEBEV
V52LINKV
FEBEI
TFEBEI
TCRCEI
RAICRCI
CFEBEI
V52LINKI
FEBEE
TFEBEE
TCRCEE
RAICRCE
CFEBEE
V52LINKE
Si[0:1]
A
Sa[4:8]
X[0:2]
Y
SaX[1:4] (‘X’ is
from 4 to 8)
SaXI (‘X’ is
from 4 to 8)
Sa6SCI
SaXE (‘X’ is
from 4 to 8)
SaDEB
Sa6SYN
Sa6SCE
Sa6-8I
Sa6-AI
Sa6-CI
Sa6-EI
Sa6-FI
48
Register
E1 Address (Hex)
Overhead Error Status
05F, 15F
Overhead Interrupt Indication
061, 161
Overhead Interrupt Control
060, 160
TS0 International / National
054, 154
TS16 Spare
055, 155
Sa4 Codeword ~ Sa8 Codeword
056 ~ 05A, 156 ~ 15A
Sa Codeword Interrupt Indication
05D, 15D
Sa Codeword Interrupt Control
05C, 15C
Sa6 Codeword Indication
05B, 15B
August 20, 2009
IDT82P2282
3.9
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
PERFORMANCE MONITOR
2. Manual-Update: Content in the internal counters is transferred to
indirect registers when there is a transition from ‘0’ to ‘1’ on the UPDAT
bit, no matter whether the AUTOUPD bit is ‘1’ or ‘0’.
All the internal counters will be resetted after the update and will
start a new round of counting. No error event is lost during the update.
The indirect registers are addressed by the LINKSEL and
ADDR[3:0] bits. The LINKSEL bit selects the link and the ADDR[3:0] bits
select the specific PMON indirect register. Data read from the indirect
register is held in the DAT[7:0] bits.
3.9.1
T1/J1 MODE
Several internal counters are used to count different events for performance monitoring. For different framing format, the counters are used
differently. The overflow of each counter is reflected by an Overflow Indication Bit, and can trigger an interrupt if the corresponding Overflow
Interrupt Enable Bit is set. This is shown in Table 22.
The internal counters can be updated in two ways:
1. Auto-Update: Content in the internal counters is transferred to
indirect registers every one second automatically if the AUTOUPD bit is
‘1’;
Table 22: Monitored Events In T1/J1 Mode
Format
Event
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS
Violation (CV) Error (in B8ZS decoding)
F Bit Error
SF
The new-found F bit position differs from the previous one
Out of SF synchronization
PRGD Bit Error
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS
Violation (CV) Error (in B8ZS decoding)
Frame Alignment Bit Error
CRC-6 Error
ESF
The new-found F bit position differs from the previous one
Out of ESF synchronization
PRGD Bit Error
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS
Violation (CV) Error (in B8ZS decoding)
T1 DM F Bit Error
DDS Pattern Error
(T1 only) The new-found F bit position differs from the previous one
Out of T1 DM synchronization
PRGD Bit Error
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS
Violation (CV) Error (in B8ZS decoding)
SLC-96 F Bit Error
The new-found F bit position differs from the previous one
(T1 only)
Out of SLC-96 synchronization
PRGD Bit Error
Functional Description
Counter
Overflow Interrupt Indication Bit Overflow Interrupt Enable Bit
Code
LCV[15:0]
LCVOVI
LCVOVE
Code
FER[11:0]
COFA[2:0]
OOF[4:0]
PRGD[15:0]
LCV[15:0]
FEROVI
COFAOVI
OOFOVI
PRGDOVI
LCVOVI
FEROVE
COFAOVE
OOFOVE
PRGDOVE
LCVOVE
Code
FER[11:0]
CRCE[9:0]
COFA[2:0]
OOF[4:0]
PRGD[15:0]
LCV[15:0]
FEROVI
CRCOVI
COFAOVI
OOFOVI
PRGDOVI
LCVOVI
FEROVE
CRCOVE
COFAOVE
OOFOVE
PRGDOVE
LCVOVE
Code
FER[11:0]
DDSE[9:0]
COFA[2:0]
OOF[4:0]
PRGD[15:0]
LCV[15:0]
FEROVI
DDSOVI
COFAOVI
OOFOVI
PRGDOVI
LCVOVI
FEROVE
DDSOVE
COFAOVE
OOFOVE
PRGDOVE
LCVOVE
FER[11:0]
COFA[2:0]
OOF[4:0]
PRGD[15:0]
FEROVI
COFAOVI
OOFOVI
PRGDOVI
FEROVE
COFAOVE
OOFOVE
PRGDOVE
49
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 23: Related Bit / Register In Chapter 3.9.1
Bit
Register
T1/J1 Address (Hex)
LCV[15:0]
FER[11:0]
COFA[2:0]
OOF[4:0]
PRGD[15:0]
CRCE[9:0]
DDSE[9:0]
LCVOVI
FEROVI
COFAOVI
OOFOVI
PRGDOVI
CRCOVI
DDSOVI
LCVOVE
FEROVE
COFAOVE
OOFOVE
PRGDOVE
CRCOVE
DDSOVE
LINKSEL
ADDR[3:0]
DATA[7:0]
UPDAT
AUTOUPD
ID* - LCV Counter Mapping 1 & 0
ID - FER Counter Mapping 1 & 0
ID - COFA Counter Mapping
ID - OOF Counter Mapping
ID - PRGD Counter Mapping 1 & 0
ID - CRCE Counter Mapping 1 & 0
ID - DDSE Counter Mapping 1 & 0
PMON Interrupt 1
PMON ID - 09 & 08
PMON ID - 03 & 02
PMON ID - 04
PMON ID - 05
PMON ID - 07 & 06
PMON ID - 01 & 00
PMON ID - 0B & 0A
0C6, 1C6
PMON Interrupt 0
0C5, 1C5
PMON Interrupt Control 1
0C4, 1C4
PMON Interrupt Control 0
0C3, 1C3
PMON Access Port
00E
PMON Access Data
00F
PMON Control
0C2, 1C2
Note:
* ID means Indirect Register in the Performance Monitor function block.
Functional Description
50
August 20, 2009
IDT82P2282
3.9.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
2. Manual-Update: Content in the internal counters is transferred to
indirect registers when there is a transition from ‘0’ to ‘1’ on the UPDAT
bit, no matter whether the AUTOUPD bit is ‘1’ or ‘0’.
All the internal counters will be resetted after the update and will
start a new round of counting. No error event is lost during the update.
The indirect registers are addressed by the LINKSEL and
ADDR[3:0] bits. The LINKSEL bit selects the link and the ADDR[3:0] bits
select the specific PMON indirect register. Data read from the indirect
register is held in the DAT[7:0] bits.
E1 MODE
Several internal counters are used to count different events for performance monitoring. For different framing format, the counters are used
differently. The overflow of each counter is reflected by an Overflow Indication Bit, and can trigger an interrupt if the corresponding Overflow
Interrupt Enable Bit is set. This is shown in Table 22.
The internal counters can be updated in two ways:
1. Auto-Update: Content in the internal counters is transferred to
indirect registers every one second automatically if the AUTOUPD bit is
‘1’;
Table 24: Monitored Events In E1 Mode
Event
Counter
Bipolar Violation (BPV) Error (in AMI decoding) or HDB3 Code Violation (CV) Error (in HDB3 decoding)
FAS/NFAS Bit/Pattern Error
CRC-4 Error
Far End Block Error
The the new-found Basic frame alignment pattern position differs from the previous one
Out of Basic frame synchronization
PRGD Bit Error
NT FEBE Error
NT CRC Error
LCV[15:0]
FER[11:0]
CRCE[9:0]
FEBE[9:0]
COFA[2:0]
OOF[4:0]
PRGD[15:0]
TFEBE[9:0]
TCRCE[9:0]
Functional Description
51
Overflow Interrupt Overflow Interrupt
Indication Bit
Enable Bit
LCVOVI
FEROVI
CRCOVI
FEBEOVI
COFAOVI
OOFOVI
PRGDOVI
TFEBEOVI
TCRCOVI
LCVOVE
FEROVE
CRCOVE
FEBEOVE
COFAOVE
OOFOVE
PRGDOVE
TFEBEOVE
TCRCOVE
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 25: Related Bit / Register In Chapter 3.9.2
Bit
Register
E1 Address (Hex)
LCV[15:0]
FER[11:0]
CRCE[9:0]
FEBE[9:0]
COFA[2:0]
OOF[4:0]
PRGD[15:0]
TFEBE[9:0]
TCRCE[9:0]
LCVOVI
FEROVI
CRCOVI
FEBEOVI
COFAOVI
OOFOVI
PRGDOVI
TFEBEOVI
TCRCOVI
LCVOVE
FEROVE
CRCOVE
FEBEOVE
COFAOVE
OOFOVE
PRGDOVE
TFEBEOVE
TCRCOVE
LINKSEL
ADDR[3:0]
DATA[7:0]
UPDAT
AUTOUPD
ID* - LCV Counter Mapping 1 & 0
ID - FER Counter Mapping 1 & 0
ID - CRCE Counter Mapping 1 & 0
ID - FEBE Counter Mapping 1 & 0
ID - COFA Counter Mapping
ID - OOF Counter Mapping
ID - PRGD Counter Mapping 1 & 0
ID - TFEBE Counter Mapping 1 & 0
ID - TCRCE Counter Mapping 1 & 0
PMON Interrupt 1
PMON ID - 09 & 08
PMON ID - 03 & 02
PMON ID - 01 & 00
PMON ID - 0D & 0C
PMON ID - 04
PMON ID - 05
PMON ID - 07 & 06
PMON ID - 0F & 0E
PMON ID - 0B & 0A
0C6, 1C6
PMON Interrupt 0
0C5, 1C5
PMON Interrupt Control 1
0C4, 1C4
PMON Interrupt Control 0
0C3, 1C3
PMON Access Port
00E
PMON Access Data
00F
PMON Control
0C2, 1C2
Note:
* ID means Indirect Register in the Performance Monitor function block.
Functional Description
52
August 20, 2009
IDT82P2282
3.10
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
ALARM DETECTOR
The status of the RED alarm, Yellow alarm and Blue alarm are indicated by the corresponding Status bit. Any transition (from ‘0’ to ‘1’ or
from ‘1’ to ‘0’) on the Status bit will set the corresponding Interrupt Indication bit to ‘1’ and the Interrupt Indication bit will be cleared by writing a
‘1’. A ‘1’ in the Interrupt Indication bit means there is an interrupt. The
interrupt will be reported by the INT pin if its Interrupt Enable bit is ‘1’.
3.10.1
T1/J1 MODE
The RED alarm, Yellow alarm and Blue alarm are detected in this
block (refer to Table 26).
Table 26: RED Alarm, Yellow Alarm & Blue Alarm Criteria
Declare Condition
RED Alarm
(per T1.403,
T1.231)
Clear Condition
The out of SF/ESF/T1 DM/SLC-96 syn- The in SF/ESF/T1 DM/SLC-96 synchrochronization status persists Nx40 ms. Here nization status persists Mx120 ms. Here
‘N’ is decided by the REDDTH[7:0] bits.
‘M’ is decided by the REDCTH[7:0] bits.
Less than 77 ’One’s are detected on the Bit
T1 SF/ 2 of each channel during a 40 ms fixed winSLC-96 dow and this status persists for Nx40 ms.
Format Here ‘N’ is decided by the YELDTH[7:0]
bits.
More than 7 ‘0xFF00’ (MSB first) are
detected on the DL bits during a 40 ms
T1 ESF
fixed window and this status persists for
Format
Nx40 ms. Here ‘N’ is decided by the
YELDTH[7:0] bits.
Yellow
Less than 4 ’One’s are detected on the Y
bit (Bit 6 in each CH 24) during a 40 ms
T1 DM
fixed window and this status persists for
Format
Alarm*
Nx40 ms. Here ‘N’ is decided by the
YELDTH[7:0] bits.
Less than 4 zeros are detected on the F-bit
of the 12nd frame during a 40 ms fixed winJ1 SF
dow and this status persists for Nx40 ms.
Format
Here ‘N’ is decided by the YELDTH[7:0]
bits.
Less than 3 zeros are detected on the DL
J1 ESF bits during a 40 ms fixed window and this
Format status persists for Nx40 ms. Here ‘N’ is
decided by the YELDTH[7:0] bits.
Less than 61 zeros are detected in a 40 ms
Blue Alarm
fixed window and this status persists for
(per T1.231)
Nx40 ms. Here ‘N’ is decided by the AISDTH[7:0] bits.
More than 76 ’One’s are detected on the
Bit 2 of each channel during a 40 ms
fixed window and this status persists for
Mx40 ms. Here ‘M’ is decided by the
YELCTH[7:0] bits.
Less than 8 ‘0xFF00’ (MSB first) are
detected on the DL bits during a 40 ms
fixed window and this status persists for
Mx40 ms. Here ‘M’ is decided by the
YELCTH[7:0] bits.
More than 3 ’One’s are detected on the
Y bit (Bit 6 in each CH 24) during a 40
ms fixed window and this status persists
for Mx40 ms. Here ‘M’ is decided by the
YELCTH[7:0] bits.
More than 3 zeros are detected on the
F-bit of the 12nd frame during a 40 ms
fixed window and this status persists for
Mx40 ms. Here ‘M’ is decided by the
YELCTH[7:0] bits.
More than 2 zeros are detected on the
DL bits during a 40 ms fixed window and
this status persists for Mx40 ms. Here
‘M’ is decided by the YELCTH[7:0] bits.
More than 60 zeros are detected in a 40
ms fixed window and this status persists
for Mx40 ms. Here ‘M’ is decided by the
AISCTH[7:0] bits.
Status Bit Interrupt Indication Bit Interrupt Enable Bit
RED
REDI
REDE
YEL
YELI
YELE
YEL
YELI
YELE
YEL
YELI
YELE
YEL
YELI
YELE
YEL
YELI
YELE
AIS
AISI
AISE
Note: * The Yellow Alarm can only be detected when the frame is synchronized.
Functional Description
53
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 27: Related Bit / Register In Chapter 3.10.1
Bit
Register
T1/J1 Address (Hex)
REDDTH[7:0]
REDCTH[7:0]
YELDTH[7:0]
YELCTH[7:0]
AISDTH[7:0]
AISCTH[7:0]
RED
YEL
AIS
REDI
YELI
AISI
REDE
YELE
AISE
RED Declare Threshold
RED Clear Threshold
Yellow Declare Threshold
Yellow Clear Threshold
AIS Declare Threshold
AIS Clear Threshold
0BC, 1BC
0BD, 1BD
0BE,1BE
0BF, 1BF
0C0, 1C0
0C1, 1C1
Alarm Status
0B9, 1B9
Alarm Indication
0BB, 1BB
Alarm Control
0BA, 1BA
Functional Description
54
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TS16AISV bit will set the TS16AISI bit to ‘1’ and the TS16AISI bit will be
cleared by writing a ‘1’. A ‘1’ in the TS16AISI bit means there is an interrupt. The interrupt will be reported by the INT pin if the TS16AISE bit is
‘1’.
The LOS in TS16 is detected on the base of Basic frame synchronization. The LOS in TS16 will be declared when 16 consecutive TS16 are
all received as ‘0’. The LOS in TS16 will be cleared when 16 consecutive
TS16 are not all received as ‘0’. The LOS in TS16 status is reflected by
the TS16LOSV bit. Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the
TS16LOSV bit will set the TS16LOSI bit to ‘1’ and the TS16LOSI bit will
be cleared by writing a ‘1’. A ‘1’ in the TS16LOSI bit means there is an
interrupt. The interrupt will be reported by the INT pin if the TS16LOSE
bit is ‘1’.
3.10.2
E1 MODE
The Remote alarm, Remote Signaling Multi-Frame alarm, RED
alarm, AIS alarm, AIS in TS16 and LOS in TS16 are detected in this
block.
The Remote Alarm Indication bit is the A bit (refer to Table 18). It is
detected on the base of Basic frame synchronization. The criteria of
Remote alarm detection are defined by the RAIC bit. If the RAIC bit is
‘0’, the Remote alarm will be declared when 4 consecutive A bits are
received as ‘1’, and the Remote alarm will be cleared when a single A bit
is received as ‘0’. If the RAIC bit is ‘1’, the Remote alarm will be declared
when a single A bit is received as ‘1’, and the Remote alarm will be
cleared when a single A bit is received as ‘0’. The Remote alarm status
is reflected by the RAIV bit. Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’)
on the RAIV bit will set the RAII bit to ‘1’ and the RAII bit will be cleared
by writing a ‘1’. A ‘1’ in the RAII bit means there is an interrupt. The interrupt will be reported by the INT pin if the RAIE bit is ‘1’.
The Remote Signaling Multi-Frame Alarm Indication bit is the Y bit
(refer to Figure 13). It is detected on the base of CAS Signaling MultiFrame synchronization. The Remote Signaling Multi-Frame alarm will be
declared when 3 consecutive Y bits are received as ‘1’, and the Remote
Signaling Multi-Frame alarm will be cleared when a single Y bit is
received as ‘0’. The Remote Signaling Multi-Frame alarm status is
reflected by the RMAIV bit. Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’)
on the RMAIV bit will set the RMAII bit to ‘1’ and the RMAII bit will be
cleared by writing a ‘1’. A ‘1’ in the RMAII bit means there is an interrupt.
The interrupt will be reported by the INT pin if the RMAIE bit is ‘1’.
The criteria of RED alarm detection meet I.431. The RED alarm will
be declared when out of Basic frame synchronization persists for 100
ms, and the RED alarm will be cleared when in Basic frame synchronization persists for 100 ms. The RED alarm status is reflected by the
RED bit. Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the RED bit will
set the REDI bit to ‘1’ and the REDI bit will be cleared by writing a ‘1’. A
‘1’ in the REDI bit means there is an interrupt. The interrupt will be
reported by the INT pin if the REDE bit is ‘1’.
The AIS alarm is detected whether it is in synchronization or not.
The criteria of AIS alarm are defined by the AISC bit. When the AISC bit
is ‘0’, the criteria meet I.431. The AIS alarm will be declared when less
than 3 zeros are detected in a 512-bit fixed window and it is out of Basic
frame synchronization, and the AIS alarm will be cleared when more
than 2 zeros are detected in a 512-bit fixed window. When the AISC bit
is ‘1’, the criteria meet G.775. The AIS alarm will be declared when less
than 3 zeros are detected in each of 2 consecutive 512-bit fixed windows, and the AIS alarm will be cleared when more than 2 zeros are
detected in each of 2 consecutive 512-bit fixed windows. The AIS alarm
status is reflected by the AIS bit. Any transition (from ‘0’ to ‘1’ or from ‘1’
to ‘0’) on the AIS bit will set the AISI bit to ‘1’ and the AISI bit will be
cleared by writing a ‘1’. A ‘1’ in the AISI bit means there is an interrupt.
The interrupt will be reported by the INT pin if the AISE bit is ‘1’.
The AIS in TS16 is detected on the base of Basic frame synchronization. The AIS in TS16 will be declared when TS16 contains less than 4
zeros in each of two 16-consecutive-Basic-frame periods. The AIS in
TS16 will be cleared when TS16 contains more than 3 zeros in a 16consecutive-Basic-frame period. The AIS in TS16 status is reflected by
the TS16AISV bit. Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the
Functional Description
Table 28: Related Bit / Register In Chapter 3.10.2
Bit
RAIC
AISC
RAIV
RMAIV
RED
AIS
TS16AISV
TS16LOSV
RAII
RMAII
REDI
AISI
TS16AISI
TS16LOSI
RAIE
RMAIE
REDE
AISE
TS16AISE
TS16LOSE
55
Register
E1 Address (Hex)
Alarm Criteria Control
0BC, 1BC
Alarm Status
0B9, 1B9
Alarm Indication
0BB, 1BB
Alarm Control
0BA, 1BA
August 20, 2009
IDT82P2282
3.11
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
HDLC RECEIVER
HDLC #1 is fixed in the DL bit (in ESF format) and D bit in CH24 (in T1
DM format) respectively (refer to Table 13 & Table 14), the other HDLC
channels are configured as follows:
1. Set the EVEN bit and/or the ODD bit to select the even and/or
odd frames;
2. Set the TS[4:0] bits to define the channel/timeslot of the
assigned frame;
3. Set the BITEN[7:0] bits to select the bits of the assigned channel/
timeslot.
Then all the functions of the HDLC Receiver will be enabled only if
the corresponding RDLEN bit is set to ‘1’.
The HDLC Receiver extracts the HDLC data stream from the
selected position and processes the data according to the selected
mode.
3.11.1
HDLC CHANNEL CONFIGURATION
In T1/J1 mode ESF & T1 DM formats, three HDLC Receivers (#1,
#2 & #3) per link are provided for HDLC extraction from the received
data stream. In T1/J1 mode SF & SLC-96 formats, two HDLC Receivers
(#2 & #3) per link are provided for HDLC extraction. In E1 mode, three
HDLC Receivers (#1, #2 & #3) per link are provided for HDLC extraction.
Except in T1/J1 mode ESF & T1 DM formats, the HDLC channel of
Table 29: Related Bit / Register In Chapter 3.11.1
Bit
Register
Address (Hex)
EVEN
ODD
TS[4:0]
RHDLC1 Assignment (E1 only) / RHDLC2 Assignment /
RHDLC3 Assignment
08C, 18C (E1 only) / 08D, 18D / 08E, 18E
BITEN[7:0]
RHDLC1 Bit Select (E1 only) / RHDLC2 Bit Select /
RHDLC3 Bit Select
08F, 18F (E1 only) / 090, 190 / 091, 191
RDLEN3
RDLEN2
RDLEN1
RHDLC Enable Control
08B, 18B
serve as the opening flag of the next HDLC packet. Following the opening flag, two-byte address is compared if the address comparison mode
is selected. Before the closing flag, two bytes of CRC-CCITT frame
check sequences (FCS) are provided to check all the HDLC packet
(excluding the opening flag and closing flag).
3.11.2
HDLC MODE
Setting the RHDLCM bit to ‘0’ (default) in the corresponding HDLC
Receiver selects the HDLC mode (per Q.921).
The structure of a standard HDLC packet consists of the following
parts as shown in Figure 14. Each HDLC packet starts with a 7E (Hex)
opening flag and ends with the same flag. The closing flag may also
Flag
one byte
'01111110'
FCS
two bytes
Information
Control
Address
(optional)
Flag
n bytes
one byte
low byte high byte
address address
one byte one byte
one byte
'01111110'
b7
b0 b7
C/R b0
Figure 14. Standard HDLC Packet
After the stuffed zero (the zero following five consecutive ’One’s) is
discarded, the data stream between the opening flag and the FCS is
divided into blocks. Each block (except the last block) has 32 bytes. The
- The data between the opening flag and the closing flag is less
Functional Description
block will be pushed into a FIFO with one-byte overhead ahead until any
of the following invalid packet conditions occurs:
- A packet with error FCS;
than 5 bytes (including the FCS, excluding the flags);
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
comparison is required, the high byte address position is compared with
the value in the HA[7:0] bits, or with ‘0xFC’ or ‘0xFE’. Here the ‘C/R’ bit
position is excluded to compare. And the low byte position (the byte following the high byte address position) is compared with the value in the
LA[7:0] bits.
If any of the above conditions is detected, the current block will be
discarded, but the one-byte overhead will still be written into the FIFO.
The overhead consists of the M[2:0] bits and the length indication bits as
shown in Figure 15.
- The extracted HDLC packet does not consist of an integral number of octets;
- A 7F (Hex) abort sequence is received;
- Address is not matched if the address comparison is enabled.
(The address comparison mode is selected by the ADRM[1:0] bits. If
high byte address comparison is required, the high byte address position (the byte following the opening flag) is compared with the value in
the HA[7:0] bits, or with ‘0xFC’ or ‘0xFE’. Here the ‘C/R’ bit position is
excluded to compare. If low byte address comparison is required, the
high byte address position is compared with the value in the LA[7:0] bits.
Here the ‘C/R’ bit position is included to compare. If both bytes address
overhead (one byte)
bit 7
M2
M1
M0
bit 0
Length Indication
M[2:0]:
= 000: A valid short HDLC packet is received, i.e., the data stream between the opening flag and the FCS is less than 32 bytes (including 32
bytes).
= 001: The current block is not the last block of the HDLC packet.
= 010: The current block is the last block of a valid long (more than 32 bytes) HDLC packet.
= 011: Reserved.
= 100: An invalid short HDLC packet is received and the current block is discarded.
= 101: The current block is the last block of an invalid long HDLC packet and the block is discarded.
= 110: Reserved.
= 111: Reserved.
The Length Indication is valid when the M2 bit is zero: Length Indication = N - 1 (N is the number of byte).
Otherwise, the Length Indication is zero.
Figure 15. Overhead Indication In The FIFO
The HDLC Receiver will be reset when there is a transition from ‘0’
to ‘1’ on the RRST bit. The reset will clear the FIFO, the PACK bit and
the EMP bit.
The FIFO depth is 128 bytes. The FIFO is accessed by the
DAT[7:0] bits. When the overhead is read from the FIFO, it will be indicated by the PACK bit. When all valid HDLC blocks are pushed into the
FIFO or all the blocks are read from the FIFO, it will be indicated by the
EMP bit.
The interrupt sources in this block are summarized in Table 30.
When there are conditions meeting the interrupt sources, the corresponding Interrupt Indication bit will be set to ‘1’ and the Interrupt Indication bit will be cleared by writing a ‘1’. A ‘1’ in the Interrupt Indication bit
means there is an interrupt. The interrupt will be reported by the INT pin
if its Interrupt Enable bit is ‘1’.
Table 30: Interrupt Summarize In HDLC Mode
Sources
A block is pushed into the FIFO.
Data is still attempted to write
into the FIFO when the FIFO
has been already full (128
bytes).
Functional Description
Interrupt Indication Bit Interrupt Enable Bit
RMBEI
OVFLI
RMBEE
OVFLE
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Table 31: Related Bit / Register In Chapter 3.11.2
Bit
RHDLCM
ADRM[1:0]
RRST
HA[7:0]
LA[7:0]
DAT[7:0]
PACK
EMP
RMBEI
OVFLI
RMBEE
OVFLE
Register
Address (Hex)
RHDLC1 Control Register / RHDLC2 Control Register / RHDLC3 Control
Register
092, 192 / 093, 193 / 094, 194
RHDLC1 High Address / RHDLC2 High Address / RHDLC3 High Address
RHDLC1 Low Address / RHDLC2 Low Address / RHDLC3 Low Address
RHDLC1 Data / RHDLC2 Data / RHDLC3 Data
0A1, 1A1 / 0A2, 1A2 / 0A3, 1A3
0A4, 1A4 / 0A5, 1A5 / 0A6, 1A6
098, 198 / 099, 199 / 09A, 19A
RHDLC1 RFIFO Access Status /
095, 195 / 096, 196 / 097, 197
RHDLC1 Interrupt Indication / RHDLC2 Interrupt Indication / RHDLC3
Interrupt Indication
09E, 19E / 09F, 19F / 0A0, 1A0
RHDLC1 Interrupt Control / RHDLC2 Interrupt Control / RHDLC3 Interrupt
Control
09B, 19B / 09C, 19C / 09D, 19D
Functional Description
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3.12
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
BIT-ORIENTED MESSAGE RECEIVER
3.13 INBAND LOOPBACK CODE DETECTOR (T1/J1
ONLY)
The Bit-Oriented Message (BOM) can only be received in the ESF
format in T1/J1 mode.
The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of
the F-bit in the ESF format (refer to Table 13). The six ‘X’s represent the
message. The BOM is declared only when the pattern is matched and
the received message is identical 4 out of 5 consecutive times or 8 out of
10 consecutive times and differs from the previous message. The identification time is selected by the AVC bit. After a new BOM is declared, the
message is loaded into the BOC[5:0] bits. Every time when the BOC[5:0]
bits are updated, it will be indicated by the BOCI bit. A ‘1’ in the BOCI bit
means there is an interrupt. The interrupt will be reported by the INT pin
if the BOCE bit is ‘1’.
In BITS application, network timing recovery is required. In addition
to timing recovery, the incoming line can carry Synchronization Status
Messages, or SSM, to indicate the quality level of the incoming clock.
SSM (in code words) are transmitted and/or received through the data
link bits (DS1 ESF formats) in T1/J1 mode. XBOC[5:0] and BOC[5:0]
mode can be used to transmit and receive the code words of SSM,
respectively. In E1 mode, Sa bits in Time Slot 0 can be used for transmit
or receive SSM code words.
In T1/J1 ESF mode, the BOC[5:0] bits can be used to hold the
received codeword in SSM application. The XBOC[5:0] bits, on the other
hand, can be used to transmit the SSM codeword to the network far end.
In E1 mode, each of the Sa[4:8] bits can be used for the same purpose. For example, if the Sa[4] bit is used in transmit direction, SSM is
transmitted by using the Sa[4] bit; in receive direction, the E1 Sa4 Codeword Register contains the received SSM codeword.
The Inband Loopback Code Detector tracks the loopback activate/
deactivate codes only in framed or unframed T1/J1 data stream, and
meets ANSI T1.403 9.3.1.
The received data stream is compared with the target activate/
deactivate code whose length and content are programmed in the
ASEL[1:0]/DSEL[1:0] bits and the ACT[7:0]/DACT[7:0] bits respectively.
In framed mode, the F-bit is selected by the IBCDIDLE bit to compare
with the target activate/deactivate code or not. In unframed mode, all
193 bits are compared with the target activate/deactivate code.
After four consecutive correct activate/deactivate codes are found
in the received data stream, the Inband Loopback Code Detector keeps
on monitoring the bit error, i.e., the bit differs from the target activate/
deactivate code. If in more than 126 consecutive 39.8ms fixed periods,
less than 600 bit errors are detected in each 39.8ms, the activate/deactivate code is detected and the corresponding LBA/LBD bit will indicate it.
Once more than 600 bit errors are detected in a 39.8ms fixed period, the
activate/deactivate code is out of synchronization and the corresponding
LBA/LBD bit will be cleared. However, even if the F-bit is compared,
whether it is matched or not, the result will not cause bit errors, that is,
the comparison result of the F-bit is discarded.
Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LBA/LBD bit
will set the LBAI/LBDI bit, which means there is an interrupt. The interrupt will be reported by the INT pin if the corresponding LBAE/LBDE bit
is set to ‘1’.
Table 33: Related Bit / Register In Chapter 3.13
Bit
Table 32: Related Bit / Register In Chapter 3.12
Bit
AVC
BOCE
BOC[5:0]
BOCI
XBOC[5:0]
Sa[4:8]
Sa4[1:4]
Register
T1/J1 Address (Hex)
BOC Control
081, 181
RBOC Code
BOC Interrupt Indication
T1/J1 XBOC Code
E1 TS0 International / National
E1 Sa4 Codeword
083, 183
082, 182
080, 180
054, 154
056, 156
Functional Description
ASEL[1:0]
DSEL[1:0]
IBCDIDLE
ACT[7:0]
DACT[7:0]
LBA
LBD
LBAI
LBDI
LBAE
LBDE
59
Register
T1/J1 Address (Hex)
IBCD Detector Configuration
076, 176
IBCD Activate Code
IBCD Deactivate Code
078, 178
079, 179
IBCD Detector Status
077, 177
IBCD Interrupt Indication
07B, 17B
IBCD Interrupt Control
07A, 17A
August 20, 2009
IDT82P2282
3.14
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
ELASTIC STORE BUFFER
3.15
In Receive Clock Slave mode and Receive Multiplexed mode, a 2basic-frame depth Elastic Store Buffer is used to synchronize the incoming frames to the (Multiplexed) Receive Side System Clock derived from
the RSCKn/MRSCK pin, and to the (Multiplexed) Receive Side System
Frame Pulse derived from the RSFSn/MRSFS pin. A write pointer is
used to write the data to the Elastic Store Buffer, while a read pointer is
used to read the data from the Elastic Store Buffer.
When the average frequency of the incoming data is greater than
the average frequency of the (Multiplexed) Receive Side System Clock
(RSCKn/MRSCK), the write pointer will be faster than the read pointer
and the Elastic Store Buffer will be filled. Until there is less than or equal
to 2 bytes between the write pointer and the read pointer, a frame will be
deleted after its prior frame is read. When the read pointer crosses the
frame boundary, a controlled slip will occur with a ‘1’ indicated in the
SLIPD bit.
When the average frequency of the incoming data is less than the
average frequency of the RSCKn/MRSCK, the write pointer will be
slower than the read pointer and the Elastic Store Buffer will be empty.
Until there is less than or equal to 2 bytes between the write pointer and
the read pointer, the frame will be repeated after it is read. When the
read pointer crosses the next frame boundary, a controlled slip will occur
with a ‘0’ indicated in the SLIPD bit.
When the slip occurs, the SLIPI bit will indicate it. An interrupt on
the INT pin will occur if the SLIPE bit is ‘1’.
In Receive Clock Slave mode and Receive Multiplexed mode, if it is
out of synchronization, the trunk code programmed in the TRKCODE[7:0] bits will be set to replace the data if the TRKEN bit is set to
‘1’.
In Receive Clock Master mode, the Elastic Store Buffer is
bypassed unless the device is in the Payload Loopback diagnosis mode
(refer to Chapter 3.27.2.2 Payload Loopback).
The Receive CAS/RBS Buffer extracts the signaling bits from the
received data stream.
3.15.1
T1/J1 MODE
In SF/ESF/SLC-96 format, the signaling bits are located in the Bit 8
of Frame 6n (n = 1,2 in SF format; 1 ≤ n ≤ 4 in ESF format; 1 ≤ n ≤ 12 in
SLC-96 format) (refer to Table 12, Table 13 and Table 15 respectively).
The signaling codewords (AB or ABCD) are clocked out on the RSIGn/
MRSIG pins. They are in the lower nibble of the channel with its corresponding data serializing on the RSDn/MRSD pins (as shown in
Figure 16).
When the EXTRACT bit is set to ‘1’, the signaling bits in its corresponding channel are extracted to the A,B,C,D bits in the Extracted Signaling Data/Extract Enable register. In SF format, the C,D bits in the
register are the repetition of the signaling bits A,B. The data in the
A,B,C,D bits in the Extracted Signaling Data/Extract Enable register are
the data to be output on the RSIGn/MRSIG pins. However, in T1-DM format, there is no signaling bits.
Signaling de-bounce will be executed when the DEB bit is set to ‘1’.
Thus, the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register are updated only if 2 consecutive received AB/ABCD codewords
of the same channel are identical.
Signaling freezing is performed automatically when it is out of
frame synchronization or when slips occurs in the Elastic Store Buffer. It
is also performed when the FREEZE bit is set to ‘1’. The signaling freezing freezes the signaling data in the A,B,C,D bits in the Extracted Signaling Data/Extract Enable register as the previous valid value.
In the ESF and SLC-96 format, if the SIGF bit is set to ‘0’, the
extracted signaling bits are in 4 states signaling, i.e., the signaling bits
on Framer 6 & 18 of a signaling multi-frame are recognized as ‘A’ and
the signaling bits on Framer 12 & 24 are recognized as ‘B’. Only the signaling bits A & B will be saved in the Extracted Signaling Data/Extract
Enable register, and the C & D bits in the Extracted Signaling Data/
Extract Enable register are Don’t-Care. If the SIGF bit is set to ‘1’, the
extracted signaling bits are in 16 states signaling, i.e., four signaling bits
A, B, C & D are all saved in the Extracted Signaling Data/Extract Enable
register.
Each time the extracted signaling bits stored in the Extracted Signaling Data/Extract Enable register are changed, it is captured by the
corresponding COSI[X] bit (1 ≤ X ≤ 24). When the SIGE bit is set to ‘1’,
any one of the COSI[X] bits being ‘1’ will generate an interrupt and will
be reported by the INT pin.
The EXTRACT bit and the A,B,C,D bits are in the indirect registers
of the Receive CAS/RBS Buffer. They are accessed by specifying the
address in the ADDRESS[6:0] bits. Whether the data is read from or
written into the specified indirect register is determined by the RWN bit
and the data is in the D[7:0] bits. The access status is indicated in the
BUSY bit. Refer to Chapter 4.5 Indirect Register Access Scheme for
details about the indirect registers write/read access.
Table 34: Related Bit / Register In Chapter 3.14
Bit
SLIPD
SLIPE
TRKEN
SLIPI
TRKCODE[7:0]
Register
Address (Hex)
ELST Configuration
07C, 17C
ELST Interrupt Indication
ELST Trunk Code
07D, 17D
07E, 17E
Functional Description
RECEIVE CAS/RBS BUFFER
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Channel 24
RSDn/MRSD
Channel 1
Channel 2
Channel 24
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
RSIGn/MRSIG
A B C D
A B C D
Channel 1
1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8
A B C D
A B C D
F-bit
A B C D
F-bit
Figure 16. Signaling Output In T1/J1 Mode
slips occurs in the Elastic Store Buffer. It is also performed when the
FREEZE bit is set to ‘1’. The signaling freezing freezes the signaling
data in the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register as the previous valid value.
Each time the extracted signaling bits in the A,B,C,D bits in the
Extracted Signaling Data/Extract Enable register are changed, it is captured by the corresponding COSI[X] bit (1 ≤ X ≤ 30). When the SIGE bit
is set to ‘1’, any one of the COSI[X] bits being ‘1’ will generate an interrupt and will be reported by the INT pin.
The EXTRACT bit and the A,B,C,D bits are in the indirect registers
of the Receive CAS/RBS Buffer. They are accessed by specifying the
address in the ADDRESS[6:0] bits. Whether the data is read from or
written into the specified indirect register is determined by the RWN bit
and the data is in the D[7:0] bits. The access status is indicated in the
BUSY bit. Refer to Chapter 4.5 Indirect Register Access Scheme for
details about the indirect registers write/read access.
3.15.2
E1 MODE
In Signaling Multi-Frame, the signaling bits are located in TS16
(refer to Figure 13), which are Channel Associated Signalings (CAS).
The signaling codewords (ABCD) are clocked out on the RSIGn/MRSIG
pins. They are in the lower nibble of the timeslot with its corresponding
data serializing on the RSDn/MRSD pins (as shown in Figure 17).
When the EXTRACT bit is set to ‘1’, the signaling bits in its corresponding timeslot are extracted to the A,B,C,D bits in the Extracted Signaling Data/Extract Enable register. The data in the A,B,C,D bits in the
register are the data to be output on the RSIGn/MRSIG pins. The bits
corresponding to TS0 and TS16 output on the RSIGn/MRSIG pins are
Don’t-Care.
Signaling de-bounce will be executed when the DEB bit is set to ‘1’.
Thus, the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register are updated only if 2 consecutive received ABCD codewords of
the same timeslot are identical.
Signaling freezing is performed automatically when it is out of Basic
frame synchronization, out of Signaling multi-frame synchronization or
TS31
TS0
TS1
RSDn/MRSD 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78
RSIGn/MRSIG
ABCD
ABCD
TS15
TS16
TS17
1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78
ABCD
ABCD
TS31
TS0
1 2 3 4 5 6 78 1 2 3 4 5 6 78
ABCD
Figure 17. Signaling Output In E1 Mode
Functional Description
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Table 35: Related Bit / Register In Chapter 3.15
Bit
EXTRACT
A,B,C,D
DEB
FREEZE
SIGF (T1/J1 only)
SIGE
COSI[X] (1 ≤ X ≤ 24 in T1/J1) (1 ≤ X ≤ 30
in E1)
ADDRESS[6:0]
RWN
D[7:0]
BUSY
Register
Address (Hex)
ID* - Extracted Signaling Data/Extract Enable
RCRB ID - 01~18 (for T1/J1) / 01~0F & 11~1F (for E1)
RCRB Configuration
0D2, 1D2
RCRB State Change Indication 3 (E1 only) & RCRB State
Change Indication 2 ~ 0
0D9, 1D9 (E1 only) & 0D8, 1D8 & 0D7, 1D7 & 0D6,
1D6
RCRB Access Control
0D4, 1D4
RCRB Access Data
RCRB Access Status
0D5, 1D5
0D3, 1D3
Note:
* ID means Indirect Register in the Receive CAS/RBS Buffer function block.
Functional Description
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3.16
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RECEIVE PAYLOAD CONTROL
Different test patterns can be inserted in the received data stream
or the received data stream can be extracted to the PRBS Generator/
Detector for test in this block.
To enable all the functions in the Receive Payload Control, the
PCCE bit must be set to ‘1’.
The following methods can be executed on the data to be output on
the RSDn/MRSD pins on a per-channel/per-TS basis or on a global
basis of the corresponding link (the methods are arranged from the highest to the lowest in priority):
- When the TESTEN bit is enabled and the PRBSDIR bit is ‘0’, the
received data will be extracted to the PRBS Generator/Detector. The
received data can be extracted in unframed mode, in 8-bit-based mode
or in 7-bit-based mode. This selection is made by the PRBSMODE[1:0]
bits. In unframed mode, all the received data stream is extracted and the
per-channel/per-TS configuration in the TEST bit is ignored. In 8-bitbased mode or in 7-bit-based mode, the received data will only be
extracted on the channel/timeslot configured by the TEST bit. Refer to
Chapter 3.27.1 PRBS Generator / Detector for details.
- Selected by the GSUBST[2:0] bits, the data of all channels/
timeslots of the corresponding link will be replaced by the data trunk
code set in the DTRK[7:0] bits, or the milliwatt pattern defined in the
Table 36 and Table 37. When the GSUBST[2:0] bits are set to ‘000’,
these replacements will be performed on a per-channel/per-TS basis by
setting the SUBST[2:0] bits in the corresponding channel/timeslot.
- When the SIGFIX bit is set to ‘1’, the signaling bits (ABCD) will be
fixed to the value set in the POL bit. This function is only supported in
the SF, ESF and SLC-96 formats in T1/J1 mode.
- Invert the most significant bit, the even bits and/or the odd bits by
setting the SINV, OINV, EINV bits.
- When the TESTEN bit is enabled and the PRBSDIR bit is ‘1’, the
received data will be replaced by the test pattern generated from the
PRBS Generator/Detector. The received data can be replaced in
unframed mode, in 8-bit-based mode or in 7-bit-based mode. This selection is made by the PRBSMODE[1:0] bits. In unframed mode, all the
received data stream is replaced and the per-channel/per-TS configuration in the TEST bit is ignored. In 8-bit-based mode or in 7-bit-based
mode, the received data will only be replaced on the channel/timeslot
configured by the TEST bit. Refer to Chapter 3.27.1 PRBS Generator /
Detector for details.
Functional Description
Table 36: A-Law Digital Milliwatt Pattern
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Byte 1
0
0
1
1
0
1
0
0
Byte 2
0
0
1
0
0
0
0
1
Byte 3
0
0
1
0
0
0
0
1
Byte 4
0
0
1
1
0
1
0
0
Byte 5
1
0
1
1
0
1
0
0
Byte 6
1
0
1
0
0
0
0
1
Byte 7
1
0
1
0
0
0
0
1
Byte 8
1
0
1
1
0
1
0
0
Table 37: µ-Law Digital Milliwatt Pattern
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Byte 1
0
0
0
1
1
1
1
0
Byte 2
0
0
0
0
1
0
1
1
Byte 3
0
0
0
0
1
0
1
1
Byte 4
0
0
0
1
1
1
1
0
Byte 5
1
0
0
1
1
1
1
0
Byte 6
1
0
0
0
1
0
1
1
Byte 7
1
0
0
0
1
0
1
1
Byte 8
1
0
0
1
1
1
1
0
The following methods can be executed on the signaling bits to be
output on the RSIGn/MRSIG pins on a per-channel/per-TS basis or on a
global basis of the corresponding link (the methods are arranged from
the highest to the lowest in priority):
- Selected by the ABXX bit, the signaling bits can be valid in the
upper 2-bit positions of the lower nibble of each channel or in the lower
nibble of each channel. The other bits of the channel are Don’t Care
conditions. This function is only supported in T1/J1 mode ESF/SLC-96
format.
- Enabled by the SIGSNAP bit, the signaling snapshot will be executed. The signaling snapshot means that the signaling bits of the first
basic frame are locked and output as the signaling bits of the current
whole multi-frame. This function is not supported in T1 DM format.
- Enabled by the GSTRKEN bit, the signaling bits (ABCD) of all
channels/timeslots of the corresponding link will be replaced by the signaling trunk conditioning code in the A,B,C,D bits. When the GSTRKEN
bit is ‘0’, the replacement will be performed on a per-channel/per-TS
basis by setting the STRKEN bit in the corresponding channel/timeslot.
The indirect registers of the Receive Payload Control are accessed
by specifying the address in the ADDRESS[6:0] bits. Whether the data is
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read from or written into the specified indirect register is determined by
the RWN bit and the data is in the D[7:0] bits. The access status is indi-
cated in the BUSY bit. Refer to Chapter 4.5 Indirect Register Access
Scheme for details about the indirect registers write/read access.
Table 38: Related Bit / Register In Chapter 3.16
Bit
PCCE
SIGFIX (T1/J1 only)
POL (T1/J1 only)
ABXX (T1/J1 only)
TESTEN
PRBSDIR
PRBSMODE[1:0]
TEST
STRKEN
A,B,C,D
GSUBST[2:0]
SIGSNAP
GSTRKEN
DTRK[7:0]
SUBST[2:0]
SINV
OINV
EINV
ADDRESS[6:0]
RWN
D[7:0]
BUSY
Register
Address (Hex)
RPLC Control Enable
0D1, 1D1
TPLC / RPLC / PRGD Test Configuration
0C7, 1C7
ID * - Signaling Trunk Conditioning Code
RPLC ID - 41~58 (for T1/J1) / 41~4F & 51~5F (for E1)
RPLC Configuration
0D0, 1D0
ID - Data Trunk Conditioning Code
RPLC ID - 21~38 (for T1/J1) / 20~3F (for E1)
ID - Channel Control (for T1/J1) / Timeslot Control (for E1)
RPLC ID - 01~18 (for T1/J1) / 00~1F (for E1)
RPLC Access Control
0CE, 1CE
RPLC Access Data
RPLC Access Status
0CF, 1CF
0CD, 1CD
Note:
* ID means Indirect Register in the Receive Payload Control function block.
Functional Description
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IDT82P2282
3.17
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RECEIVE SYSTEM INTERFACE
In the Receive Clock Master mode, the device outputs clock
(M)RSCKn/(M)RSFSn. This clock is derived from line side signal or
MCLK (When LOSS).
In the Receive Clock Master mode, if RSCKn outputs pulses during
the entire T1/J1 frame, the Receive System Interface is in Receive Clock
Master Full T1/J1 mode. If only the clocks aligned to the selected channels are output on RSCKn, the Receive System Interface is in Receive
Clock Master Fractional T1/J1 mode.
In the Receive Clock Slave mode, outside inputs clock (M)RSCKn/
(M)RSFSn to the device. To avoid shatter data, this clock should keep
the same source with line side. If the backplane data rate is 2.048 Mb/s,
means T1 mode E1 rate, the receive data(1.544 Mb/s) should be
mapped to 2.048 Mb/s,there are 3 kinds of mapping schemes.
In the Receive Multiplexed mode, since the received data from the
two links should be converted to 2.048 Mb/s format first and then multiplexed to 8.192 Mb/s, there are still 3 kinds of schemes to be selected.
Table 39 summarizes how to set the Receive System Interface of
each link into various operating modes and the pins’ direction of the
Receive System Interface in different operating modes.
The Receive System Interface determines how to output the
received data stream to the system backplane. The data from the two
links can be aligned with each other or be output independently. The timing clocks and framing pulses can be provided by the system backplane
or obtained from the far end. The Receive System Interface supports
various configurations to meet various requirements in different applications.
3.17.1
T1/J1 MODE
In T1/J1 mode, the Receive System Interface can be set in Nonmultiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the RSDn pin is used to output the received data from each link at the bit
rate of 1.544 Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed Mode, the received data from the two links is converted to 2.048
Mb/s format and byte interleaved to form one high speed data stream
and output on the MRSD pin at the bit rate of 8.192 Mb/s.
Table 39: Operating Modes Selection In T1/J1 Receive Path
RMUX
RMODE
0
G56K, GAP /
2
FBITGAP MAP[1:0]
00 / 0
not all 0s 1
0
1
1
X
X
X
Operating Mode
Receive System Interface Pin
Input
Output
X
RSCKn, RSFSn,
RSDn, RSIGn
X
Receive Clock Master Full T1/J1
Receive Clock Master Fractional T1/J1
00
01
10
11
01
10
11
Receive Clock Slave - T1/J1 Rate
Receive Clock Slave - T1/J1 Mode E1 Rate per G.802
RSCKn, RSFSn
Receive Clock Slave - T1/J1 Mode E1 Rate per One Filler Every Four CHs
Receive Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
Receive Multiplexed - T1/J1 Mode E1 Rate per G.802
Receive Multiplexed - T1/J1 Mode E1 Rate per One Filler Every Four CHs MRSCK, MRSFS
Receive Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
RSDn, RSIGn
MRSD, MRSIG
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Receive Multiplexed mode.
CMFS bit and the ALTIFS bit. The active polarity of the RSFSn is
selected by the FSINV bit.
The Receive Clock Master mode includes two sub-modes: Receive
Clock Master Full T1/J1 mode and Receive Clock Master Fractional T1/
J1 mode.
3.17.1.1
Receive Clock Master Mode
In the Receive Clock Master mode, each link uses its own timing
signal on the RSCKn pin and framing pulse on the RSFSn pin to output
the data on each RSDn pin. The signaling bits on the RSIGn pin are perchannel aligned with the data on the RSDn pin.
In the Receive Clock Master mode, the data on the system interface is clocked by the RSCKn. The active edge of the RSCKn used to
update the pulse on the RSFSn is determined by the FE bit. The active
edge of the RSCKn used to update the data on the RSDn and RSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFSn is ahead.
In the Receive Clock Master mode, the RSFSn can indicate each
F-bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. In SF
format, the RSFSn can also indicate every second F-bit or the first F-bit
of every second SF multi-frame. All the indications are selected by the
Functional Description
3.17.1.1.1
Receive Clock Master Full T1/J1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
standard 1.544 MHz clock, and the data in the F-bit and all 24 channels
in a standard T1/J1 frame are clocked out by the RSCKn.
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tem side. The F-bit of Frame N from the device is converted into the first
bit of TS26 of Frame (N-1) on the system side. TS0, TS16, TS27~TS31
and the other 7 bits in TS26 on the system side are all filled with ‘0’s and
they are meaningless.
2. T1/J1 Mode E1 Rate per One Filler Every Fourth CH (refer to
Figure 19): One dummy byte is inserted on the system side before 3
bytes of Frame N from the device are converted. This process repeats 8
times and the conversion of Frame N of 1.544 Mb/s data rate to 2.048
Mb/s data rate is completed. However, the F-bit of Frame N of the 1.544
Mb/s data rate is inserted as the 8th bit of Frame N of the 2.048 Mb/s
data rate. The dummy bytes are filled with all ‘0’s and they are meaningless.
3. T1/J1 Mode E1 Rate per Continuous CHs (refer to Figure 20):
Channel 1 to Channel 24 of Frame N from the device are converted into
TS1 to TS24 of Frame N on the system side. The F-bit of Frame N from
the device is converted into the 8th bit of Frame N on the system side.
The first 7 bits and TS25 to TS31 on the system side are all filled with
‘0’s and they are meaningless.
3.17.1.1.2
Receive Clock Master Fractional T1/J1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
gapped 1.544 MHz clock (no clock signal during the selected position).
The RSCKn is gapped during the F-bit if the FBITGAP bit is set to
‘1’. The RSCKn is also gapped during the channels or the Bit 8 duration
by selecting the G56K & GAP bits in the Receive Payload Control. The
data in the corresponding gapped duration is a don't care condition.
3.17.1.2
Receive Clock Slave Mode
In the Receive Clock Slave mode, the system data rate can be
1.544 Mb/s or 2.048 Mb/s. If the system data rate is 1.544 Mb/s, it works
in T1/J1 mode. If the system data rate is 2.048 Mb/s, the received data
stream (1.544 Mb/s) should be mapped to the same rate as the system
side, that is, to work in T1/J1 mode E1 rate. Three kinds of schemes are
provided by selecting the MAP[1:0] bits:
1. T1/J1 Mode E1 Rate per G.802 (refer to Figure 18): Channel 1 to
Channel 15 of Frame N from the device are converted into TS1 to TS15
of Frame N on the system side; Channel 16 to Channel 24 of Frame N
from the device are converted into TS17 to TS25 of Frame N on the sys1.544
Mb/s
F CH1
2.048
Mb/s
TS0
CH2
TS1
CH14
TS2
CH15
CH16
CH17
CH23
TS14 TS15 TS16 TS17 TS18
filler
CH24 F
TS24 TS25
CH1
CH23
TS26 TS27~TS31
the 1st bit filler
filler
CH2
TS0
filler
TS1
filler
Figure 18. T1/J1 To E1 Format Mapping - G.802 Mode
1.544
Mb/s
F CH1
2.048
Mb/s
TS0
CH2
TS1
filler the 8th bit
TS2
CH3
TS3
CH4
TS4
filler
CH5
TS5
CH6
TS6
CH7
TS7
CH22
TS8
filler
TS9
CH23
CH24 F CH1
CH2
TS28 TS29 TS30 TS31 TS0
filler
TS1
filler the 8th bit
Figure 19. T1/J1 To E1 Format Mapping - One Filler Every Fourth Channel Mode
Functional Description
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1.544
Mb/s
F
2.048
Mb/s
TS0
filler
CH1
TS1
CH2
CH3
TS2
TS3
CH24 F
CH23
TS23
TS24
TS25~TS31
filler
the 8th bit
CH1
CH2
TS0
CH24 F
TS1
TS2
CH1
TS24
filler the 8th bit
Figure 20. T1/J1 To E1 Format Mapping - Continuous Channels Mode
interleaved output on the multiplexed bus. When the data from the two
links is output on one multiplexed bus, the sequence of the data is
arranged by setting the channel offset. The data from different links on
one multiplexed bus must be shifted at a different channel offset to avoid
data mixing.
In the Receive Multiplexed mode, the timing signal on the MRSCK
pin and the framing pulse on the MRSFS pin are provided by the system
side and common to both two links. The signaling bits on the MRSIG pin
are per-channel aligned with the corresponding data on the MRSD pin.
In the Receive Multiplexed mode, the data on the system interface
is clocked by the MRSCK. The active edge of the MRSCK used to sample the pulse on the MRSFS is determined by the FE bit. The active
edge of the MRSCK used to update the data on the MRSD and MRSIG
is determined by the DE bit. The FE bit and the DE bit of the two links
should be set to the same value respectively. If the FE bit and the DE bit
are not equal, the pulse on the MRSFS is ahead. The MRSCK can be
selected by the CMS bit to be the same rate as the data rate on the system side (8.192 MHz) or double the data rate (16.384 MHz). The CMS
bit of the two links should be set to the same value. If the speed of the
MRSCK is double the data rate, there will be two active edges in one bit
duration. In this case, the EDGE bit determines the active edge to
update the data on the MRSD and MRSIG pins. The pulse on the
MRSFS pin is always sampled on its first active edge.
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. The FSINV bit of the
two links should be set to the same value. If the pulse on the MRSFS pin
is not an integer multiple of 125 µs, this detection will be indicated by the
RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will be reported
by the INT pin when the RCOFAI bit is ‘1’.
In the Receive Clock Slave mode, the timing signal on the RSCKn
pin and the framing pulse on the RSFSn pin to output the data on the
RSDn pin are provided by the system side. When the RSLVCK bit is set
to ‘0’, each link uses its own RSCKn and RSFSn; when the RSLVCK bit
is set to ‘1’ and both two links are in the Receive Clock Slave mode, the
two links use the RSCK[1] and RSFS[1] to output the data. The signaling
bits on the RSIGn pin are per-channel aligned with the data on the
RSDn pin.
In the Receive Clock Slave mode, the data on the system interface
is clocked by the RSCKn. The active edge of the RSCKn used to sample
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is determined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead. The data rate of the system side is 1.544 Mb/s
or 2.048 Mb/s. When it is 2.048 Mb/s, the RSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
MHz) or double the data rate (4.096 MHz). If both two links use the
RSCK[1] and RSFS[1] to output the data, the CMS bit of the two links
should be set to the same value. If the speed of the RSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to update the data on the
RSDn and RSIGn pins. The pulse on the RSFSn pin is always sampled
on its first active edge.
In the Receive Clock Slave mode, the RSFSn asserts at a rate of
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the RSFSn is selected by the FSINV bit. If the pulse on the
RSFSn pin is not an integer multiple of 125 µs, this detection will be indicated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.1.3
Receive Multiplexed Mode
In the Receive Multiplexed mode, since the received data from the
two links should be mapped to 2.048 Mb/s format first, the 3 kinds of
schemes should be selected by the MAP[1:0] bits. The mapping per
G.802, per One Filler Every Four CHs and per Continuous CHs are the
same as the description in Chapter 3.17.1.2 Receive Clock Slave Mode.
In the Receive Multiplexed mode, a multiplexed bus is used to output the data from both two links. The data of Link 1 to Link 2 is byte-
Functional Description
3.17.1.4
Offset
Bit offset and channel offset are both supported in all the operating
modes. The offset is between the framing pulse on RSFSn/MRSFS pin
and the start of the corresponding frame output on the RSDn/MRSD pin.
The signaling bits on the RSIGn/MRSIG pin are always per-channel
aligned with the data on the RSDn/MRSD pin.
Figure 21 to Figure 24 show the base line without offset.
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FE = 1, DE = 1
Receive Clock Slave mode / Receive Multiplexed mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSD
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Receive Clock Master mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSD
Figure 21. No Offset When FE = 1 & DE = 1 In Receive Path
FE = 0, DE = 0
Receive Clock Slave mode / Receive Multiplexed mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSD
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Receive Clock Master mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSD
Figure 22. No Offset When FE = 0 & DE = 0 In Receive Path
Functional Description
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FE = 0, DE = 1
Receive Clock Slave mode / Receive Multiplexed mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSD
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Receive Clock Master mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSD
Figure 23. No Offset When FE = 0 & DE = 1 In Receive Path
FE = 1, DE = 0
Receive Clock Slave mode / Receive Multiplexed mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSD
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Receive Clock Master mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSD
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Figure 24. No Offset When FE = 1 & DE = 0 In Receive Path
When the CMS bit is ‘1’ (i.e., in double clock mode) and the
BOFF[2:0] bits are set, the start of the corresponding frame output on
the RSDn/MRSD pin will delay ‘2 x N’ clock cycles to the framing pulse
on the RSFSn/MRSFS pin. (Here ‘N’ is defined by the BOFF[2:0] bits.)
When the CMS bit is ‘1’ (i.e., in double clock mode) and the TSOFF[6:0]
bits are set, the start of the corresponding frame output on the RSDn/
MRSD pin will delay ‘16 x M’ clock cycles to the framing pulse on the
RSFSn/MRSFS pin. (Here ‘M’ is defined by the TSOFF[6:0].)
The bit offset and channel offset are configured when the
BOFF[2:0] bits and the TSOFF[6:0] bits are not ‘0’ respectively.
When the CMS bit is ‘0’ and the BOFF[2:0] bits are set, the start of
the corresponding frame output on the RSDn/MRSD pin will delay ‘N’
clock cycles to the framing pulse on the RSFSn/MRSFS pin. (Here ‘N’ is
defined by the BOFF[2:0] bits.) When the CMS bit is ‘0’ and the
TSOFF[6:0] bits are set, the start of the corresponding frame output on
the RSDn/MRSD pin will delay ‘8 x M’ clock cycles to the framing pulse
on the RSFSn/MRSFS pin. (Here ‘M’ is defined by the TSOFF[6:0].)
Functional Description
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3.17.2
E1 MODE
In E1 mode, the Receive System Interface can be set in Non-multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
RSDn pin is used to output the received data from each link at the bit
rate of 2.048 Mb/s. While in the Multiplexed Mode, the received data
from the two links is byte interleaved to form one high speed data stream
and output on the MRSD pin at the bit rate of 8.192 Mb/s.
In the Non-multiplexed mode, if the RSCK is from outside, the
receive system interface is in Receive Clcok Slave mode, otherwise if
the device outputs clock to RSCK from itself, the receive system interface is in Receive Clcok Master mode.
In the Receive Clock Master mode, if RSCKn outputs pulses during
the entire E1 frame, the Receive System Interface is in Receive Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on RSCKn, the Receive System Interface is in Receive Clock
Master Fractional E1 mode.
Table 40 summarizes how to set the receive system interface of
each link into various operating modes and the pins’ direction of the
receive system interface in different operating modes.
In Non-multiplexed mode, the channel offset can be configured
from 0 to 23 channels (0 & 23 are included). In Multiplexed mode, the
channel offset can be configured from 0 to 127 channels (0 & 127 are
included).
3.17.1.5
Output On RSDn/MRSD & RSIGn/MRSIG
The output on the RSDn/MRSD and the RSIGn/MRSIG pins can be
configured by the TRI bit of the corresponding link to be in high impedance state or to output the processed data stream.
Table 40: Operating Modes Selection In E1 Receive Path
RMUX
0
1
RMODE
0
1
X
G56K, GAP
Receive System Interface Pin
Operating Mode
Receive Clock Master Full E1
1
not both 0s Receive Clock Master Fractional E1
X
Receive Clock Slave
X
Receive Multiplexed
Input
Output
X
RSCKn, RSFSn, RSDn, RSIGn
RSCKn, RSFSn
MRSCK, MRSFS
RSDn, RSIGn
MRSD, MRSIG
00
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
3.17.2.1.1
Receive Clock Master Full E1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame is clocked out by the RSCKn.
3.17.2.1
Receive Clock Master Mode
In the Receive Clock Master mode, each link uses its own timing
signal on the RSCKn pin and framing pulse on the RSFSn pin to output
the data on each RSDn pin. The signaling bits on the RSIGn pin are pertimeslot aligned with the data on the RSDn pin.
In the Receive Clock Master mode, the data on the system interface is clocked by the RSCKn. The active edge of the RSCKn used to
update the pulse on the RSFSn is determined by the FE bit. The active
edge of the RSCKn used to update the data on the RSDn and RSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFSn is ahead.
In the Receive Clock Master mode, the RSFSn can indicate the
Basic frame, CRC Multi-frame, Signaling Multi-frame, or both the CRC
Multi-frame and Signaling Multi-frame, or the TS1 and TS 16 overhead.
All the indications are selected by the OHD bit, the SMFS bit and the
CMFS bit. The active polarity of the RSFSn is selected by the FSINV bit.
The Receive Clock Master mode includes two sub-modes: Receive
Clock Master Full E1 mode and Receive Clock Master Fractional E1
mode.
Functional Description
3.17.2.1.2
Receive Clock Master Fractional E1 Mode
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCKn is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
The RSCKn is gapped during the timeslots or the Bit 8 duration by
selecting the G56K & GAP bits in the Receive Payload Control. The data
in the corresponding gapped duration is a don't care condition.
3.17.2.2
Receive Clock Slave Mode
In the Receive Clock Slave mode, the timing signal on the RSCKn
pin and framing pulse on the RSFSn pin to output the data on the RSDn
pin are provided by the system side. When the RSLVCK bit is set to ‘0’,
each link uses its own RSCKn and RSFSn; when the RSLVCK bit is set
to ‘1’ and both two links are in the Receive Clock Slave mode, the two
links use the RSCK[1] and RSFS[1] to output the data. The signaling bits
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RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will be reported
by the INT pin when the RCOFAI bit is ‘1’.
on the RSIGn pin are per-timeslot aligned with the data on the RSDn
pin.
In the Receive Clock Slave mode, the data on the system interface
is clocked by the RSCKn. The active edge of the RSCKn used to sample
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is determined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead. The speed of the RSCKn can be selected by
the CMS bit to be the same rate as the data rate on the system side
(2.048 MHz) or double the data rate (4.096 MHz). If both two links use
the RSCK[1] and RSFS[1] to output the data, the CMS bit of the two
links should be set to the same value. If the speed of the RSCKn is double the data rate, there will be two active edges in one bit duration. In
this case, the EDGE bit determines the active edge to update the data
on the RSDn and RSIGn pins. The pulse on the RSFSn pin is always
sampled on its first active edge.
In the Receive Clock Slave mode, the RSFSn asserts at a rate of
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the RSFSn is selected by the FSINV bit. If the pulse on the
RSFSn pin is not an integer multiple of 125 µs, this detection will be indicated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.4
Offset
Except that in the Receive Master mode, when the OHD bit, the
SMFS bit and the CMFS bit are set to TS1 and TS16 overhead indication, the bit offset and timeslot offset are both supported in all the other
conditions. The offset is between the framing pulse on RSFSn/MRSFS
pin and the start of the corresponding frame output on the RSDn/MRSD
pin. The signaling bits on the RSIGn/MRSIG pin are always per-timeslot
aligned with the data on the RSDn/MRSD pin.
Refer to Chapter 3.17.1.4 Offset for the base line without offset in
different operating modes and the configuration of the offset.
In Non-multiplexed mode, the timeslot offset can be configured
from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the
timeslot offset can be configured from 0 to 127 timeslots (0 & 127 are
included).
3.17.2.5
Output On RSDn/MRSD & RSIGn/MRSIG
The output on the RSDn/MRSD and the RSIGn/MRSIG pins can be
configured by the TRI bit of the corresponding link to be in high impedance state or to output the processed data stream.
3.17.2.3
Receive Multiplexed Mode
In the Receive Multiplexed mode, one multiplexed bus is used to
output the data from both two links. The data of Link 1 to Link 2 is byteinterleaved output on the multiplexed bus. When the data from the two
links is output on one multiplexed bus, the sequence of the data is
arranged by setting the timeslot offset. The data from different links on
one multiplexed bus must be shifted at a different timeslot offset to avoid
data mixing.
In the Receive Multiplexed mode, the timing signal on the MRSCK
pin and the framing pulse on the MRSFS pin are provided by the system
side and common to both two links. The signaling bits on the MRSIG pin
are per-timeslot aligned with the corresponding data on the MRSD pin.
In the Receive Multiplexed mode, the data on the system interface
is clocked by the MRSCK. The active edge of the MRSCK used to sample the pulse on the MRSFS is determined by the FE bit. The active
edge of the MRSCK used to update the data on the MRSD and MRSIG
is determined by the DE bit. The FE bit and the DE bit of the two links
should be set to the same value respectively. If the FE bit and the DE bit
are not equal, the pulse on the MRSFS is ahead. The MRSCK can be
selected by the CMS bit to be the same rate as the data rate on the system side (8.192 MHz) or double the data rate (16.384 MHz). The CMS
bit of the two links should be set to the same value. If the speed of the
MRSCK is double the data rate, there will be two active edges in one bit
duration. In this case, the EDGE bit determines the active edge to
update the data on the MRSD and MRSIG pins. The pulse on the
MRSFS pin is always sampled on its first active edge.
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. The FSINV bit of the
two links should be set to the same value. If the pulse on the MRSFS pin
is not an integer multiple of 125 µs, this detection will be indicated by the
Functional Description
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Table 41: Related Bit / Register In Chapter 3.17
Bit
Register
Address (Hex)
RMUX
Backplane Global Configuration
010
RSLVCK
RMODE
RBIF Mode
047, 147
MAP[1:0] (T1/J1
only)
G56K
ID * - Channel Control (for T1/ RPLC ID - 01~18 (for
J1) / Timeslot Control (for E1) T1/J1) / 00~1F (for E1)
GAP
FBITGAP (T1/J1
only)
FE
RBIF Operation
046, 146
DE
CMS
TRI
PCCE
RPLC Control Enable
0D1, 1D1
CMFS
ALTIFS (T1/J1 only)
FSINV
RBIF Frame Pulse
048, 148
OHD (E1 only)
SMFS (E1 only)
EDGE
RBIF Bit Offset
04A, 14A
BOFF[2:0]
RCOFAI
RTSFS Change Indication
04BH, 14B
RCOFAE
RTSFS Interrupt Control
04C, 14C
TSOFF[6:0]
RBIT TS Offset
049, 149
Note:
* ID means Indirect Register in the Receive Payload Control function block.
Functional Description
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3.18
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TRANSMIT SYSTEM INTERFACE
In Transmit Clock Master mode, the device output TSCKn and
TSFSn, however in Transmit Clock Slave mode, TSCKn & TSFSn are
input the device from outside.
In the Transmit Clock Master mode, if TSCKn outputs pulses during
the entire T1/J1 frame, the Transmit System Interface is in Transmit
Clock Master Full T1/J1 mode. If only the clocks aligned to the selected
channels are output on TSCKn, the Transmit System Interface is in
Transmit Clock Master Fractional T1/J1 mode.
In the Transmit Clock Slave mode, the backplane data rate may be
equal to 1.544 Mb/s (i.e., the line data rate) or 2.048 Mb/s or 8.192 Mb/s.
If the backplane data rate is 2.048 Mb/s or 8.192 Mb/s, the Transmit
System Interface is in T1/J1 mode E1 rate and the data to be transmitted
will be mapped to 1.544 Mb/s i device per 3 kinds of schemes.
Table 42 summarizes how to set the transmit system interface of
each link into various operating modes and the pins’ direction of the
transmit system interface in different operating modes.
The Transmit System Interface determines how to input the data to
the device. The data input to the two links can be aligned with each
other or input independently. The timing clocks and framing pulses can
be provided by the system backplane or obtained from the processed
data of each link. The Transmit System Interface supports various configurations to meet various requirements in different applications.
3.18.1
T1/J1 MODE
In T1/J1 mode, the Transmit System Interface can be set in Nonmultiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the TSDn pin is used to input the data to each link at the bit rate of 1.544
Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed
Mode, the data is byte-interleaved from one high speed data stream and
inputs on the MTSD pin at the bit rate of 8.192 Mb/s. The demultiplexed
data input to the two links is 2.048 Mb/s on the system side and converted into 1.544 Mb/s format to the device.
Table 42: Operating Modes Selection In T1/J1 Transmit Path
TMUX TMODE
0
G56K, GAP /
MAP[1:0] 2
FBITGAP
00 / 0
not all 0s 1
X
00
01
0
1
X
10
11
01
1
X
X
10
11
Operating Mode
Transmit Clock Master Full T1/J1
Transmit Clock Master Fractional T1/J1
Transmit System Interface Pin
Input
Output
TSDn, TSIGn
TSCKn, TSFSn
Transmit Clock Slave - T1/J1 Rate
Transmit Clock Slave - T1/J1 Mode E1 Rate per G.802
Transmit Clock Slave - T1/J1 Mode E1 Rate per One Filler Every TSDn, TSIGn, TSCKn, TSFSn
Four CHs
Transmit Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
Transmit Multiplexed - T1/J1 Mode E1 Rate per G.802
Transmit Multiplexed - T1/J1 Mode E1 Rate per One Filler Every MTSCK, MTSFS, MTSD,
Four CHs
MTSIG
Transmit Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
X
X
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Transmit Multiplexed mode.
The Transmit Clock Master mode includes two sub-modes: Transmit Clock Master Full T1/J1 mode and Transmit Clock Master Fractional
T1/J1 mode.
3.18.1.1
Transmit Clock Master Mode
In the Transmit Clock Master mode, each link uses its own timing
signal on the TSCKn pin and framing pulse on the TSFSn pin to input
the data on each TSDn pin. The signaling bits on the TSIGn pin are perchannel aligned with the data on the TSDn pin.
In the Transmit Clock Master mode, the data on the system interface is clocked by the TSCKn. The active edge of the TSCKn used to
update the pulse on the TSFSn is determined by the FE bit. The active
edge of the TSCKn used to sample the data on the TSDn and TSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the TSFSn is ahead.
In the Transmit Clock Master mode, the TSFSn can indicate each
F-bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
TSFSn is selected by the FSINV bit.
3.18.1.1.1
Transmit Clock Master Full T1/J1 Mode
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCKn is a
standard 1.544 MHz clock, and the data in the F-bit and all 24 channels
in a standard T1/J1 frame are clocked in by the TSCKn.
3.18.1.1.2
Transmit Clock Master Fractional T1/J1 Mode
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCKn is a
gapped 1.544 MHz clock (no clock signal during the selected channel).
The TSCKn is gapped during the F-bit if the FBITGAP bit is set to
‘1’. The TSCKn is also gapped during the channels or the Bit 8 duration
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verted into the F-bit of Frame N to the device. TS0, TS16, TS27~TS31
and the other 7 bits in TS26 on the system side are all discarded.
2. T1/J1 Mode E1 Rate per One Filler Every Fourth CHs (refer to
Figure 26): The 8th bit of Frame N on the system side is converted to the
F-bit of the Frame N to the device. Then one byte of the system side is
discarded after the previous three bytes are converted into the device.
This process repeats 8 times and the conversion of one frame is completed. Then the process goes on.
3. T1/J1 Mode E1 Rate per Continuous CHs (refer to Figure 27):
TS1 to TS24 of Frame N on the system side are converted into Channel
1 to Channel 24 of Frame N to the device. The 8th bit of Frame N on the
system side is converted into the F-bit of Frame N to the device. The first
7 bits and TS25 to TS31 on the system side are all discarded.
by selecting the G56K & GAP bits in the Transmit Payload Control. The
data in the corresponding gapped duration is a Don't Care condition.
3.18.1.2
Transmit Clock Slave Mode
In the Transmit Clock Slave mode, the system data rate can be
1.544 Mb/s or 2.048 Mb/s. If the system data rate is 1.544 Mb/s, it works
in T1/J1 mode. If the system data rate is 2.048 Mb/s, the data stream to
be transmitted should be mapped to 1.544 Mb/s, that is, to work in T1/J1
mode E1 rate. Three kinds of schemes are provided by selecting the
MAP[1:0] bits:
1. T1/J1 Mode E1 Rate per G.802 (refer to Figure 25): TS1 to TS15
of Frame N on the system side are converted into Channel 1 to Channel
15 of Frame N to the device; TS17 to TS25 of Frame N on the system
side are converted into Channel 16 to Channel 24 of Frame N to the
device. The first bit of TS26 of Frame (N-1) on the system side is condiscarded
2.048
Mb/s
TS0
1.544
Mb/s
F CH1
the 1st bit discarded discarded discarded
discarded
TS1
TS2
TS14 TS15 TS16 TS17 TS18
CH2
CH14
CH15
CH16
CH17
TS24 TS25
CH23
CH24 F
TS26 TS27~TS31
CH1
TS0
CH2
TS1
CH23
Figure 25. E1 To T1/J1 Format Mapping - G.802 Mode
discarded
discarded the 8th bit
2.048
Mb/s
TS0
1.544
Mb/s
F CH1
TS1
TS2
CH2
TS3
CH3
TS4
CH4
discarded
TS5
CH5
TS6
CH6
TS7
TS8
CH7
discarded
TS9
discarded the 8th bit
TS28 TS29 TS30 TS31 TS0
CH22
CH23
CH24 F CH1
TS1
CH2
Figure 26. E1 To T1/J1 Format Mapping - One Filler Every Fourth Channel Mode
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discarded the 8th bit
2.048
Mb/s
TS0
1.544
Mb/s
F
TS1
CH1
discarded discarded the 8th bit
TS2
TS3
CH2
CH3
TS23
TS24
TS25~TS31
CH24 F
CH23
CH1
TS0
TS1
TS2
CH2
TS24
CH24 F
CH1
Figure 27. E1 To T1/J1 Format Mapping - Continuous Channels Mode
In the Transmit Multiplexed mode, one multiplexed bus is used to
transmit the data to both two links. The data of Link 1 to Link 2 is byteinterleaved input from the multiplexed bus. When the data on the multiplexed bus is input to two links, the sequence of the data is arranged by
setting the channel offset. The data to different links from one multiplexed bus must be shifted at a different channel offset to avoid data
mixing.
In the Transmit Multiplexed mode, the timing signal on the MTSCK
pin and the framing pulse on the MTSFS pin are provided by the system
side and common to allboth two links. The signaling bits on the MTSIG
pin are per-channel aligned with the corresponding data on the MTSD
pin.
In the Transmit Multiplexed mode, the data on the system interface
is clocked by the MTSCK. The active edge of the MTSCK used to sample the pulse on the MTSFS is determined by the FE bit. The active
edge of the MTSCK used to sample the data on the MTSD and MTSIG
is determined by the DE bit. The FE bit and the DE bit of the two links
should be set to the same value respectively. If the FE bit and the DE bit
are not equal, the pulse on the MTSFS is ahead. The MTSCK can be
selected by the CMS bit to be the same rate as the data rate on the system side (8.192 MHz) or double the data rate (16.384 MHz). The CMS
bit of the two links should be set to the same value. If the speed of the
MTSCK is double the data rate, there will be two active edges in one bit
duration. In this case, the EDGE bit determines the active edge to sample the data on the MTSD and MTSIG pins. The pulse on the MTSFS pin
is always sampled on its first active edge.
In the Transmit Multiplexed mode, the MTSFS can indicate each Fbit of the first link or the first F-bit of every SF/ESF/T1 DM/SLC-96 multiframe of the first link. The indications are selected by the FSTYP bit. The
active polarity of the MTSFS is selected by the FSINV bit. The FSTYP
bit and the FSINV bit of the two links should be set to the same value. If
the pulse on the MTSFS pin is not an integer multiple of 125 µs, this
detection will be indicated by the TCOFAI bit. If the TCOFAE bit is
enabled, an interrupt will be reported by the INT pin when the TCOFAI
bit is ‘1’.
In the Transmit Clock Slave mode, the timing signal on the TSCKn
pin and the framing pulse on the TSFSn pin to input the data on the
TSDn pin are provided by the system side. When the TSLVCK bit is set
to ‘0’, each link uses its own TSCKn and TSFSn; when the TSLVCK bit
is set to ‘1’ and both two links are in the Transmit Clock Slave mode, the
two links use the TSCK[1] and TSFS[1] to input the data. The signaling
bits on the TSIGn pin are per-channel aligned with the data on the TSDn
pin.
In the Transmit Clock Slave mode, the data on the system interface
is clocked by the TSCKn. The active edge of the TSCKn used to sample
the pulse on the TSFSn is determined by the FE bit. The active edge of
the TSCKn used to sample the data on the TSDn and TSIGn is determined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the TSFSn is ahead. The data rate of the system side is 1.544 Mb/s
or 2.048 Mb/s. When it is 2.048 Mb/s, the TSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
MHz) or double the data rate (4.096 MHz). If both two links use the
TSCK[1] and TSFS[1] to input the data, the CMS bit of the two links
should be set to the same value. If the speed of the TSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to sample the data on the
TSDn and TSIGn pins. The pulse on the TSFSn pin is always sampled
on its first active edge.
In the Transmit Clock Slave mode, the TSFSn can indicate each Fbit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
TSFSn is selected by the FSINV bit. If the pulse on the TSFSn pin is not
an integer multiple of 125 µs, this detection will be indicated by the
TCOFAI bit. If the TCOFAE bit is enabled, an interrupt will be reported by
the INT pin when the TCOFAI bit is ‘1’.
3.18.1.3
Transmit Multiplexed Mode
In the Transmit Multiplexed mode, since the demultiplexed data
rate on the system side (2.048 Mb/s) should be mapped to the data rate
in the line side (1.544 Mb/s), 3 kinds of schemes should be selected by
the MAP[1:0] bits. The schemes per G.802, per One Filler Every Four
CHs and per Continuous CHs are the same as the description in
Chapter 3.18.1.2 Transmit Clock Slave Mode.
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pin. The signaling bits on the TSIGn/MTSIG pin are always per-channel
aligned with the data on the TSDn/MTSD pin.
Figure 28 to Figure 31 show the base line without offset.
3.18.1.4
Offset
Bit offset and channel offset are both supported in all the operating
modes. The offset is between the framing pulse on the TSFSn/MTSFS
pin and the start of the corresponding frame input on the TSDn/MTSD
FE = 1, DE = 1
Transmit Clock Slave mode / Transmit Multiplexed mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSD
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Transmit Clock Master mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSD
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Figure 28. No Offset When FE = 1 & DE = 1 In Transmit Path
FE = 0, DE = 0
Transmit Clock Slave mode / Transmit Multiplexed mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSD
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Transmit Clock Master mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSD
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Figure 29. No Offset When FE = 0 & DE = 0 In Transmit Path
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FE = 0, DE = 1
Transmit Clock Slave mode / Transmit Multiplexed mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSD
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Transmit Clock Master mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSD
Figure 30. No Offset When FE = 0 & DE = 1 In Transmit Path
FE = 1, DE = 0
Transmit Clock Slave mode / Transmit Multiplexed mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSD
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 3 (E1)
Transmit Clock Master mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSD
Figure 31. No Offset When FE = 1 & DE = 0 In Transmit Path
When the CMS bit is ‘1’ (i.e., in double clock mode) and the
BOFF[2:0] bits are set, the start of the corresponding frame input on the
TSDn/MTSD pin will delay ‘2 x N’ clock cycles to the framing pulse on
the TSFSn/MTSFS pin. (Here ‘N’ is defined by the BOFF[2:0] bits.)
When the CMS bit is ‘1’ (i.e., in double clock mode) and the TSOFF[6:0]
bits are set, the start of the corresponding frame input on the TSDn/
MTSD pin will delay ‘16 x M’ clock cycles to the framing pulse on the
TSFSn/MTSFS pin. (Here ‘M’ is defined by the TSOFF[6:0].)
The bit offset and channel offset are configured when the
BOFF[2:0] bits and the TSOFF[6:0] bits are not ‘0’ respectively.
When the CMS bit is ‘0’ and the BOFF[2:0] bits are set, the start of
the corresponding frame input on the TSDn/MTSD pin will delay ‘N’
clock cycles to the framing pulse on the TSFSn/MTSFS pin. (Here ‘N’ is
defined by the BOFF[2:0] bits.) When the CMS bit is ‘0’ and the
TSOFF[6:0] bits are set, the start of the corresponding frame input on
the TSDn/MTSD pin will delay ‘8 x M’ clock cycles to the framing pulse
on the TSFSn/MTSFS pin. (Here ‘M’ is defined by the TSOFF[6:0].)
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In Non-multiplexed mode, the channel offset can be configured
from 0 to 23 channels (0 & 23 are included). In Multiplexed mode, the
channel offset can be configured from 0 to 127 channels (0 & 127 are
included).
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In the Transmit Clock Master mode, if TSCKn outputs pulses during
the entire E1 frame, the Transmit System Interface is in Transmit Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on TSCKn, the Transmit System Interface is in Transmit
Clock Master Fractional E1 mode.
Table 43 summarizes how to set the transmit system interface of
each link into various operating modes and the pins’ direction of the
transmit system interface in different operating modes.
3.18.2
E1 MODE
In E1 mode, the Transmit System Interface can be set in Non-multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
TSDn pin is used to input the data to each link at the bit rate of 2.048
Mb/s. While in the Multiplexed Mode, the data is byte interleaved from
one high speed data stream and inputs on the MTSD pin at the bit rate
of 8.192 Mb/s.
In the Non-multiplexed mode, if the TSCK is from outside, the
transmit system interface is in Transmit Clock Slave mode, otherwise if
the device outputs clock to TSCK itself, the transmit system interface is
in Transmit Clock Master mode.
Table 43: Operating Modes Selection In E1 Transmit Path
TMUX
0
1
TMODE
0
1
X
G56K, GAP
00
not both 0s 1
X
X
Transmit System Interface Pin
Operating Mode
Transmit Clock Master Full E1
Transmit Clock Master Fractional E1
Transmit Clock Slave
Transmit Multiplexed
Input
Output
TSDn, TSIGn
TSCKn, TSFSn
TSCKn, TSFSn, TSDn, TSIGn
MTSCK, MTSFS, MTSD, MTSIG
X
X
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to ‘1’.
3.18.2.1
Transmit Clock Master Mode
In the Transmit Clock Master mode, each link uses its own timing
signal on the TSCKn pin and framing pulse on the TSFSn pin to input
the data on each TSDn pin. The signaling bits on the TSIGn pin are pertimeslot aligned with the data on the TSDn pin.
In the Transmit Clock Master mode, the data on the system interface is clocked by the TSCKn. The active edge of the TSCKn used to
update the pulse on the TSFSn is determined by the FE bit. The active
edge of the TSCKn used to sample the data on the TSDn and TSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the TSFSn is ahead.
In the Transmit Clock Master mode, the TSFSn can indicate the
Basic frame, CRC Multi-frame and/or Signaling Multi-frame. The indications are selected by the FSTYP bit. The active polarity of the TSFSn is
selected by the FSINV bit.
The Transmit Clock Master mode includes two sub-modes: Transmit Clock Master Full E1 mode and Transmit Clock Master Fractional E1
mode.
The TSCKn is gapped during the timeslots or the Bit 8 duration by
selecting the G56K & GAP bits in the Transmit Payload Control. The
data in the corresponding gapped duration is a don't care condition.
3.18.2.2
Transmit Clock Slave Mode
In the Transmit Clock Slave mode, the timing signal on the TSCKn
pin and the framing pulse on the TSFSn pin to input the data on the
TSDn pin are provided by the system side. When the TSLVCK bit is set
to ‘0’, each link uses its own TSCKn and TSFSn; when the TSLVCK bit
is set to ‘1’ and both two links are in the Transmit Clock Slave mode, the
two links use the TSCK[1] and TSFS[1] to input the data. The signaling
bits on the TSIGn pin are per-timeslot aligned with the data on the TSDn
pin.
In the Transmit Clock Slave mode, the data on the system interface
is clocked by the TSCKn. The active edge of the TSCKn used to sample
the pulse on the TSFSn is determined by the FE bit. The active edge of
the TSCKn used to sample the data on the TSDn and TSIGn is determined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the TSFSn is ahead. The speed of the TSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
Mb/s) or double the data rate (4.096 Mb/s). If both two links use the
TSCK[1] and TSFS[1] to input the data, the CMS bit of the two links
should be set to the same value. If the speed of the TSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to sample the data on the
TSDn and TSIGn pins. The pulse on the TSFSn pin is always sampled
on its first active edge.
In the Transmit Clock Slave mode, the TSFSn can indicate the
Basic frame, CRC Multi-frame and/or Signaling Multi-frame. The indications are selected by the FSTYP bit. The active polarity of the TSFSn is
3.18.2.1.1
Transmit Clock Master Full E1 Mode
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCKn is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame are clocked in by the TSCKn.
3.18.2.1.2
Transmit Clock Master Fractional E1 Mode
Besides all the common functions described in the Transmit Clock
Master mode, the special feature in this mode is that the TSCKn is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
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selected by the FSINV bit. If the pulse on the TSFSn pin is not an integer
multiple of 125 µs, this detection will be indicated by the TCOFAI bit. If
the TCOFAE bit is enabled, an interrupt will be reported by the INT pin
when the TCOFAI bit is ‘1’.
3.18.2.3
Transmit Multiplexed Mode
In the Transmit Multiplexed mode, one multiplexed bus is used to
transmit the data to both two links. The data of Link 1 to Link 2 is byteinterleaved input from the multiplexed bus. When the data on the multiplexed bus is input to two links, the sequence of the data is arranged by
setting the timeslot offset. The data to different links from one multiplexed bus must be shifted at a different timeslot offset to avoid data
mixing.
In the Transmit Multiplexed mode, the timing signal on the MTSCK
pin and the framing pulse on the MTSFS pin are provided by the system
side and common to both two links. The signaling bits on the MTSIG pin
are per-timeslot aligned with the corresponding data on the MTSD pin.
In the Transmit Multiplexed mode, the data on the system interface
is clocked by the MTSCK. The active edge of the MTSCK used to sample the pulse on the MTSFS is determined by the FE bit. The active
edge of the MTSCK used to sample the data on the MTSD and MTSIG
is determined by the DE bit. The FE bit and the DE bit of the two links
should be set to the same value respectively. If the FE bit and the DE bit
are not equal, the pulse on the MTSFS is ahead. The MTSCK can be
selected by the CMS bit to be the same rate as the data rate on the system side (8.192 MHz) or double the data rate (16.384 MHz). The CMS
bit of the two links should be set to the same value. If the speed of the
MTSCK is double the data rate, there will be two active edges in one bit
duration. In this case, the EDGE bit determines the active edge to sample the data on the MTSD and MTSIG pins. The pulse on the MTSFS pin
is always sampled on its first active edge.
In the Transmit Multiplexed mode, the MTSFS can indicate the
Basic frame, CRC Multi-frame and/or Signaling Multi-frame of the first
link. The indications are selected by the FSTYP bit. The active polarity of
the MTSFS is selected by the FSINV bit. The FSTYP bit and the FSINV
bit of the two links should be set to the same value. If the pulse on the
MTSFS pin is not an integer multiple of 125 µs, this detection will be
indicated by the TCOFAI bit. If the TCOFAE bit is enabled, an interrupt
will be reported by the INT pin when the TCOFAI bit is ‘1’.
Table 44: Related Bit / Register In Chapter 3.18
Bit
TMUX
MTSDA
TSLVCK
TMODE
MAP[1:0]
(T1/J1 only)
G56K
GAP
PCCE
FBITGAP
(T1/J1 only)
FE
DE
FSTYP
FSINV
CMS
EDGE
BOFF[2:0]
TCOFAI
TCOFAE
TSOFF[6:0]
Register
Address (Hex)
Backplane Global Configuration
010
TBIF Operating Mode
043, 143
ID * - Channel Control (for T1/J1) /
Timeslot Control (for E1)
TPLC ID * - 01~18 (for
T1/J1) / 00~1F (for E1)
TPLC Control Enable
0CC, 1CC
TBIF Option Register
042, 142
TBIF Bit Offset
045, 145
RTSFS Change Indication
RTSFS Interrupt Control
TBIF TS Offset
04B, 14B
04C, 14C
044, 144
Note:
* ID means Indirect Register in the Transmit Payload Control function block.
3.18.2.4
Offset
Bit offset and timeslot offset are both supported in all the operating
modes. The offset is between the framing pulse on the TSFSn/MTSFS
pin and the start of the corresponding frame input on the TSDn/MTSD
pin. The signaling bits on the TSIGn/MTSIG pin are always per-timeslot
aligned with the data on the TSDn/MTSD pin.
Refer to Chapter 3.18.1.4 Offset for the base line without offset in
different operating modes and the configuration of the offset.
In Non-multiplexed mode, the timeslot offset can be configured
from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the
timeslot offset can be configured from 0 to 127 timeslots (0 & 127 are
included).
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TRANSMIT PAYLOAD CONTROL
conditions. This function is only supported in T1/J1 mode ESF/SLC-96
format.
- Enabled by the SIGSNAP bit, the signaling snapshot will be executed. The signaling snapshot means that the signaling bits of the first
basic frame are locked and output as the signaling bits of the current
whole multi-frame. This function is not supported in T1 DM format.
- Enabled by the GSTRKEN bit, the signaling bits (ABCD) of all
channels/timeslots of the corresponding link will be replaced by the signaling trunk conditioning code in the A,B,C,D bits. When the GSTRKEN
bit is ‘0’, the replacement can be performed on a per-channel/per-TS
basis by setting the STRKEN bit in the corresponding channel/timeslot.
The indirect registers of the Transmit Payload Control are accessed
by specifying the address in the ADDRESS[6:0] bits. Whether the data is
read from or written into the specified indirect register is determined by
the RWN bit and the data is in the D[7:0] bits. The access status is indicated in the BUSY bit. Refer to Chapter 4.5 Indirect Register Access
Scheme for details about the indirect registers write/read access.
Different test patterns can be inserted in the data stream to be
transmitted or the data stream to be transmitted can be extracted to the
PRBS Generator/Detector for test in this block.
To enable all the functions in the Transmit Payload Control, the
PCCE bit must be set to ‘1’.
The following methods can be executed on the data input from the
TSDn/MTSD pins on a per-channel/per-TS basis or on a global basis of
the corresponding link (the methods are arranged from the highest to the
lowest in priority):
- When the TESTEN bit is enabled and the PRBSDIR bit is ‘1’, the
data to be transmitted will be extracted to the PRBS Generator/Detector.
The data to be transmitted can be extracted in unframed mode, in 8-bitbased mode or in 7-bit-based mode. This selection is made by the PRBSMODE[1:0] bits. In unframed mode, all the data stream to be transmitted is extracted and the per-channel/per-TS configuration in the TEST
bit is ignored. In 8-bit-based mode or in 7-bit-based mode, the data will
only be extracted on the channel/timeslot configured by the TEST bit.
Refer to Chapter 3.27.1 PRBS Generator / Detector for details.
- Configured by the ZCS[2:0] bits, four types of Zero Code Suppression can be selected to implement to the data of all the channels of
the corresponding link. This function is only supported in T1/J1 mode.
- Selected by the GSUBST[2:0] bits, the data of all channels/
timeslots of the corresponding link will be replaced by the trunk code set
in the DTRK[7:0] bits, the milliwatt pattern defined in Table 36 and
Table 37, or the payload loopback data from the Elastic Store Buffer
(refer to Chapter 3.27.2.2 Payload Loopback). When the GSUBST[2:0]
bits are set to ‘000’, these replacements will be performed on a perchannel/per-TS basis by setting the SUBST[2:0] bits in the corresponding channel/timeslot.
- Controlled by the SIGINS bit, the signaling bits input from the
TSIGn/MTSIG pins (after processed by the signaling trunk conditioning
replacement and/or valid signaling bits selection) can be inserted into its
signaling bit position of the data stream to be transmitted.
- Invert the most significant bit, the even bits and/or the odd bits by
setting the SINV, OINV, EINV bits.
- When the TESTEN bit is enabled and the PRBSDIR bit is ‘0’, the
data to be transmitted will be replaced by the test pattern generated
from the PRBS Generator/Detector. The data to be transmitted can be
replaced in unframed mode, in 8-bit-based mode or in 7-bit-based
mode. This selection is made by the PRBSMODE[1:0] bits. In unframed
mode, all the data stream to be transmitted is replaced and the perchannel/per-TS configuration in the TEST bit is ignored. In 8-bit-based
mode or in 7-bit-based mode, the data will only be replaced on the channel/timeslot configured by the TEST bit. Refer to Chapter 3.27.1 PRBS
Generator / Detector for details.
The following methods can be executed on the signaling bits input
from the TSIGn/MTSIG pins on a per-channel/per-TS basis or on a global basis of the corresponding link. The processed signaling bits will be
inserted to the data stream to be transmitted if frame is generated. The
methods are arranged from the highest to the lowest in priority:
- Selected by the ABXX bit, the signaling bits can be valid in the
upper 2-bit positions of the lower nibble of each channel or in the lower
nibble of each channel. The other bits of the channel are Don’t Care
Table 45: Related Bit / Register In Chapter 3.19
Bit
Register
PCCE
TPLC Control Enable
ABXX (T1/J1 only)
TESTEN
TPLC / RPLC / PRGD Test
PRBSDIR
Configuration
PRBSMODE[1:0]
TEST
SIGINS (T1/J1 only) ID * - Signaling Trunk Conditioning Code
A,B,C,D
STRKEN
ZCS[2:0] (T1/J1 only)
GSUBST[2:0]
TPLC Configuration
SIGSNAP
GSTRKEN
ID * - Data Trunk Conditioning
DTRK[7:0]
Code
SUBST[2:0]
SINV
ID * - Channel Control (for T1/
J1) / Timeslot Control (for E1)
OINV
EINV
ADDRESS[6:0]
RWN
D[7:0]
BUSY
Address (Hex)
0CC, 1CC
0C7, 1C7
TPLC ID * - 41~58 (for
T1/J1) / 41~4F & 51~5F
(for E1)
0CB, 1CB
TPLC ID * - 21~38 (for
T1/J1) / 20~3F (for E1)
TPLC ID * - 01~18 (for
T1/J1) / 00~1F (for E1)
TPLC Access Control
0C9, 1C9
TPLC Access Data
TPLC Access Status
0CA, 1CA
0C8, 1C8
Note:
* ID means Indirect Register in the Transmit Payload Control function block.
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FRAME GENERATOR
Bit-Oriented Code, Automatic Performance Report Message, HDLC
data and idle code.
The Yellow alarm signal will be manually inserted in the data
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The Yellow
alarm signal is transmitted in the DL bit position. Its pattern is ‘FF00’ in
T1 mode or ‘FFFF’ in J1 mode.
When the FDIS bit is ‘0’, configured by the MIMICEN bit, the mimic
pattern can be inserted into the bit right after each F-bit. The content of
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
GENERATION
3.20.1.1
T1 / J1 Mode
In T1/J1 mode, the data to be transmitted can be generated as
Super-Frame (SF), Extended Super-Frame (ESF), T1 Digital Multiplexer
(DM) or Switch Line Carrier - 96 (SLC-96) format.
3.20.1.1.1
Super Frame (SF) Format
The SF is generated when the FDIS bit is ‘0’.
The Frame Alignment Pattern (‘100011011100’ for T1 /
‘10001101110X’ for J1) will replace the F-bit of each frame if the FDIS bit
is set to ‘0’. The F-bit of the 12th frame in J1 mode should be ‘0’ unless
Yellow alarm signal is transmitted.
When the FDIS bit is ‘0’, one Ft bit (the F-bit in odd frame, refer to
Table 12) will be inverted if the FtINV bit is set; one Fs bit (the F-bit in
even frame, refer to Table 12) will be inverted if the FsINV bit is set.
When the FDIS bit is ‘0’, configured by the MIMICEN bit, the mimic
pattern can be inserted into the bit right after each F-bit. The content of
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
The Yellow alarm signal will be manually inserted in the data
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The pattern
and the position of the Yellow alarm is different in T1 and J1 modes:
- In T1 mode, the Yellow alarm signal is logic 0 on the 2nd bit of
each channel;
- In J1 mode, the Yellow alarm signal is logic 1 on the 12th F-bit
position.
3.20.1.1.3
T1 Digital Multiplexer (DM) Format (T1 only)
The T1 DM is generated when the FDIS bit is ‘0’.
The Frame Alignment Pattern (‘100011011100’) will replace the Fbit of each frame if the FDIS bit is set to ‘0’.
When the FDIS bit is ‘0’, one Ft bit (the F-bit in odd frame, refer to
Table 14) will be inverted if the FtINV bit is set; one Fs bit (the F-bit in
even frame, refer to Table 14) will be inverted if the FsINV bit is set.
When the FDIS bit is ‘0’, configured by the MIMICEN bit, the mimic
pattern can be inserted into the bit right after each F-bit. The content of
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
When the FDIS bit is ‘0’, the DDS pattern (‘0XX11101’) will replace
the Bit 8 & 5~1 of each Channel 24 (refer to Table 14).
When the FDIS bit is ‘0’, one 6-bit DDS pattern will be inverted if the
DDSINV bit is set.
The ‘D’ bit in Bit 7 of each Channel 24 can be replaced with the
HDLC data when the FDIS bit and the FDLBYP bit are both ‘0’s. (Refer
to Chapter 3.20.2 HDLC Transmitter for details).
The Yellow alarm signal will be manually inserted in the data
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The Yellow
alarm signal is ‘0’ transmitted in the ‘Y’ bit in Bit 6 of each Channel 24.
The ‘Y’ bit should be ‘1’ when there is no Yellow alarm signal to be transmitted.
3.20.1.1.2
Extended Super Frame (ESF) Format
The ESF is generated when the FDIS bit is ‘0’.
The Frame Alignment Pattern (‘001011’) will replace the F-bit in
Frame (4n) (0<n<7) if the FDIS bit is set to ‘0’.
When the FDIS bit is ‘0’, one Frame Alignment bit (refer to Table 13
for its position) will be inverted if the FsINV bit is set.
When the FDIS bit and the CRCBYP bit are both ‘0’s, the calculated 6-bit CRC of the previous ESF frame will be inserted in the current
CRC-bit positions in every 4th frame starting with Frame 2 (refer to
Table 13) of the current ESF frame.
When the FDIS bit is ‘0’, one 6-bit CRC pattern will be inverted if
the CRCINV bit is set.
When the FDIS bit is ‘0’, the DL bit (refer to Table 13) can be
replaced with the Yellow alarm signal, the Bit-Oriented Code (refer to
Chapter 3.20.4 Bit-Oriented Message Transmitter (T1/J1 Only)), the
Automatic Performance Report Message (refer to Chapter 3.20.3 Automatic Performance Report Message (T1/J1 Only)), the HDLC data (refer
to Chapter 3.20.2 HDLC Transmitter) or the idle code (‘FFFF’ for T1 /
‘FF7E’ for J1). The latter four kinds of replacements are enabled only if
the FDLBYP bit is set to ‘0’. When all of the five kinds of replacements
are enabled, the priority from highest to lowest is: Yellow alarm signal,
3.20.1.1.4
Switch Line Carrier - 96 (SLC-96) Format (T1 only)
The SLC-96 is generated when the FDIS bit is ‘0’.
The Frame Alignment Pattern (‘001000110111001000110111’), the
Spoiler Bit and all the other Ft bits (the F-bit in odd frame) will replace
their F-bit (refer to Table 15 for their values and positions) if the FDIS bit
is set to ‘0’.
When the FDIS bit is ‘0’, one Synchronization Fs bit will be inverted
if the FsINV bit is set; one Ft bit will be inverted if the FtINV bit is set.
When the FDIS bit and the FDLBYP bit are both ‘0’s, the contents
in the XDL0, XDL1 & XDL2 registers will replace the Concentrator (C)
bits, the Maintenance (M) bits, the Alarm (A) bits and the Switch (S) bits
respectively (refer to Table 15).
When the FDIS bit is ‘0’, configured by the MIMICEN bit, the mimic
pattern can be inserted into the bit right after each F-bit. The content of
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the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
The Yellow alarm signal will be manually inserted in the data
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The Yellow
alarm signal is logic 0 on the 2nd bit of each channel.
3.20.1.1.5
Interrupt Summary
At the first bit of each basic frame, the BFI bit will be set. In this condition, if the BFE bit is enabled, an interrupt will be reported by the INT
pin.
At the first bit of each SF/ESF/T1 DM/SLC-96 multiframe, the MFI
bit will be set. In this condition, if the MFE bit is enabled, an interrupt will
be reported by the INT pin.
Table 46: Related Bit / Register In Chapter 3.20.1.1
Bit
FDIS
CRCBYP
FDLBYP
FtINV
FsINV
CRCINV
DDSINV
MIMICEN
XYEL
AUTOYELLOW
C[11:1]
M[3:1]
A[2:1]
S[4:1]
BFI
MFI
BFE
MFE
Register
T1/J1 Address (Hex)
T1/J1 Mode
062, 162
Error Insertion
06F, 16F
FGEN Maintenance 1
06C, 16C
FGEN Maintenance 0
06B, 16B
XDL1 & XDL0
XDL1
066, 166 & 065, 165
066, 166
XDL2
067, 167
FGEN Interrupt Indication
06E, 16E
FGEN Interrupt Control
06D, 16D
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FASALLINV bit is set, one 7-bit FAS pattern will be inverted; if the NFASINV bit is set, one NFAS bit will be inverted.
When the Basic frame is generated, if the SiDIS bit is ‘0’, the value
set in the Si[1] and Si[0] bits will replace the International bit (Bit 1) of
FAS frame and NFAS frame respectively.
When the Basic frame is generated, the Remote Alarm Indication
(RAI) can be transmitted as logic 1 in the A bit position. It is transmitted
manually when the REMAIS bit is ‘1’. It can also be transmitted automatically when the AUTOYELLOW bit is set to ‘1’. In this case, the RAI
transmission criteria are selected by the G706RAI bit.
When the Basic frame is generated, the setting in the SaX[1] bit will
be transmitted in the Sa bit position if enabled by the corresponding
SaXEN bit (‘X’ is from 4 to 8).
The CRC Multi-Frame is generated on the base of the Basic frame
generation. When it is generated, the CRC Multi-Frame alignment pattern (‘001011’) will replace the Bit 1 of TS0 of the first 6 odd frames; the
calculated 4-bit CRC of the previous Sub-Multi-Frame will be inserted in
the CRC-bit positions of the current Sub-Multi-Frame. The CRC-bit position is the Bit 1 of TS0 of each even frame. Refer to Table 18 for the
CRC Multi-Frame structure. If the CRCPINV bit is set, one 6-bit CRC
Multi-Frame alignment pattern will be inverted; if the CRCINV bit is set,
all 4 calculated CRC bits in one Sub-Multi-Frame will be inverted.
When the CRC Multi-Frame is generated, since 14 International bit
positions have been occupied by the CRC Multi-Frame alignment pattern and CRC-4 checking bits, the remaining 2 International bit positions
are inserted by the E bits. The control over the E bits is illustrated in
Table 48.
3.20.1.2
E1 Mode
In E1 mode, the Frame Generator can generate Basic Frame,
CRC-4 Multi-Frame and Channel Associated Signaling (CAS) MultiFrame. The Frame Generator can also transmit alarm indication signal
when special conditions occurs in the received data stream. International bits, National bits and Extra bits replacements and data inversions
are all supported in the Frame Generator.
The generation of the Basic frame, CRC Multi-Frame and Channel
Associated Signaling (CAS) Multi-Frame are controlled by the FDIS bit,
the GENCRC bit, the CRCM bit and the SIGEN bit. Refer to Table 47 for
details.
Table 47: E1 Frame Generation
Desired Frame Type
FDIS GENCRC CRCM SIGEN
Basic Frame
CRC Multi-Frame
Modified CRC Multi-Frame
Channel Associated Signaling (CAS) MultiFrame
0
0
0
0
0
0
0
1
1
1
0
1
X
0
0
1
X
0
X
X
X
X
1
1
When the Basic frame is generated, the Frame Alignment
Sequence (FAS) (‘0011011’) will replace the Bit 2 ~ Bit 8 of TS0 of each
even frame; the NFAS bit (‘1’) will replace the Bit 2 of TS0 of each odd
frame. If the FAS1INV bit is set, one FAS bit will be inverted; if the
Table 48: Control Over E Bits
FEBEDIS OOCMFV
SiDIS
0
0
X
0
1
1
1
X
X
X
0
1
E Bits Insertion
A single zero is inserted into the E bit when a CRC-4 Error event is detected in the receive path. (the E1 bit corresponds to SMFI
and the E2 bit corresponds to SMFII)
The value in the Si[1] bit is inserted into the E1 bit position. The value in the Si[0] bit is inserted into the E2 bit position.
The value in the Si[1] bit is inserted into the E1 bit position. The value in the Si[0] bit is inserted into the E2 bit position.
The E bit positions are unchanged.
When the Signaling Multi-Frame is generated, all the bits in TS16
can be overwritten by all ‘Zero’s or all ’One’s by setting the TS16LOS bit
or the TS16AIS bit respectively. The all zeros overwritten takes a higher
priority.
When the Modified CRC Multi-Frame is generated, only the Sa bit
position and the calculated CRC-4 bit position can be changed. All the
other bits are transparently transmitted unless all ’One’s or all ‘Zero’s are
transmitted (refer to Chapter 3.20.6 All ‘Zero’s & All ‘One’s).
The frame can only be generated on the base of the FDIS bit being
‘0’. If the FDIS bit is set to ‘1’, the data received from the Transmit Payload Control will be transmitted transparently to the HDLC Transmitter.
When the CRC Multi-Frame is generated, the setting in the
SaX[1:4] bits will be transmitted in the Sa bit position if enabled by the
corresponding SaXEN bit (‘X’ is from 4 to 8).
The Channel Associated Signaling (CAS) Multi-Frame is generated
on the base of the Basic frame generation. When it is generated, the
Signaling Multi-Frame alignment pattern (‘0000’) will replace the high
nibble (Bit 1 ~ Bit 4) of TS16 of every 16 Basic frames. If the CASPINV
bit is set, one 4-bit Signaling Multi-Frame alignment pattern will be
inverted.
When the Signaling Multi-Frame is generated, if the XDIS bit is ‘0’,
the value set in the FGEN Extra register will be inserted into the Extra
bits (the Bit 5, 7 & 8 of TS16 of Frame 0 of the Signaling Multi-Frame).
When the Signaling Multi-Frame is generated, the value in the
MFAIS bit will be continuously transmitted in the Y bit position (the Bit 6
of TS16 of Frame 0 of the Signaling Multi-Frame).
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bit is ‘1’, if enabled by the corresponding Interrupt Enable bit, an interrupt will be reported by the INT pin.
3.20.1.2.1
Interrupt Summary
In E1 mode, the interrupt is summarized in Table 49.
When there are conditions meeting the interrupt sources, the corresponding Interrupt Indication bit will be set. When the Interrupt Indication
Table 49: Interrupt Summary In E1 Mode
Interrupt Sources
At the first bit of each FAS.
At the first bit of each Basic frame.
At the first bit of each CRC Multi-Frame.
At the first bit of each CRC Sub Multi-Frame.
At the first bit of each Signaling Multi-Frame.
85
Interrupt Indication Bit
Interrupt Enable Bit
FASI
BFI
MFI
SMFI
SIGMFI
FASE
BFE
MFE
SMFE
SIGMFE
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Table 50: Related Bit / Register In Chapter 3.20.1.2
Bit
FDIS
GENCRC
CRCM
SIGEN
SiDIS
FEBEDIS
XDIS
FAS1INV
FASALLINV
NFASINV
CRCPINV
CASPINV
CRCINV
Si[1]
Si[0]
REMAIS
AUTOYELLOW
G706RAI
MFAIS
TS16LOS
TS16AIS
SaX[1:4] (‘X’ is from 4 to 8)
SaXEN (‘X’ is from 4 to 8)
OOCMFV
X[0:2]
FASI
BFI
MFI
SMFI
SIGMFI
FASE
BFE
MFE
SMFE
SIGMFE
Register
E1 Address (Hex)
E1 Mode
062, 162
Error Insertion
06F, 16F
FGEN International Bit
063, 163
FGEN Maintenance 0
06B, 16B
Sa4 Code-word ~ Sa8 Code-word
FGEN Sa Control
FRMR Status
FGEN Extra
065 ~ 069, 165 ~ 169
064, 164
04F, 14F
06A, 16A
FGEN Interrupt Indication
06E, 16E
FGEN Interrupt Control
06D, 16D
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3.20.2
HDLC TRANSMITTER
The HDLC Transmitter inserts the data into the selected position to
form HDLC packet data stream.
3.20.2.2
HDLC Mode
Setting the THDLCM bit to ‘0’ (default) in the HDLC Transmitter
selects the HDLC mode (per Q.921).
3.20.2.1
HDLC Channel Configuration
In T1/J1 mode ESF & T1 DM formats, three HDLC Transmitters
(#1, #2 & #3) per link are provided for HDLC insertion to the data stream
to be transmitted. In T1/J1 mode SF & SLC-96 formats, two HDLC
Transmitters (#2 & #3) per link are provided for HDLC insertion. In E1
mode, three HDLC Transmitters (#1, #2 & #3) per link are provided for
HDLC insertion. Except in T1/J1 mode ESF & T1 DM formats, the HDLC
channel of HDLC Transmitter #1 is fixed in the DL bit (in ESF format)
and D bit in CH24 (in T1 DM format) respectively (refer to Table 13 &
Table 14), the other HDLC channel is configured as the follows:
1. Set the EVEN bit and/or the ODD bit to select the even and/or
odd frames;
2. Set the TS[4:0] bits to define the channel/timeslot of the
assigned frame;
3. Set the BITEN[7:0] bits to select the bits of the assigned channel/
timeslot.
Then all the functions of the HDLC Transmitter will be enabled only
if the corresponding TDLEN bit is set to ‘1’.
3.20.2.2.1
HDLC Mode
A FIFO buffer is used to store the HDLC data written in the
DAT[7:0] bits. The FIFO depth is 128 bytes. When it is full, it will be indicated by the FUL bit. When it is empty, it will be indicated by the EMP bit.
If an entire HDLC packet is stored in the FIFO indicated by the
EOM bit, or if the data in the FIFO exceeds the upper threshold set by
the HL[1:0] bits, the data in the FIFO will be transmitted. The opening
flag (‘01111110’) will be prepended before the data automatically. The
transmission will not stop until the entire HDLC data are transmitted.
Then the 2-byte FCS and the closing flag (‘01111110’) will be added to
the end of the HDLC data automatically. During the HDLC data transmission, a zero is stuffed automatically into the serial output data if there
are five consecutive ’One’s ahead.
The abort sequence (‘01111111’) will be inserted to the HDLC
packet anytime when the ABORT bit is set. Or when the FIFO is empty
and the transmitted last byte is not the end of the current HDLC packet,
the abort sequence will be transmitted automatically.
If the TDLEN bit is enabled and there is no HDLC packet in the
FIFO to be transmitted, the 7E (Hex) flag will always be transmitted.
Table 51: Related Bit / Register In Chapter 3.20.2.1
3.20.2.3
Interrupt Summary
In the HDLC mode, when the data in the FIFO is below the lower
threshold set by the LL[1:0] bits, it will be indicated by the RDY bit. When
there is a transition (from ‘0’ to ‘1’) on the RDY bit, the RDYI bit will be
set. In this case, if enabled by the RDYE bit, an interrupt will be reported
by the INT pin.
In the HDLC mode, when the FIFO is empty and the last transmitted byte is not the end of the current HDLC packet, the UDRUNI bit will
be set. In this case, if enabled by the UDRUNE bit, an interrupt will be
reported by the INT pin.
Bit
EVEN
ODD
TS[4:0]
Register
Address (Hex)
THDLC1 Assignment (E1
085, 185(E1 only) / 086, 186 / 087,
only) / THDLC2 Assign187
ment / THDLC3 Assignment
BITEN[7:0]
THDLC1 Bit Select (E1
only) / THDLC2 Bit Select /
THDLC3 Bit Select
088, 188 (E1 only) / 089, 189 /
08A, 18A
TDLEN3
TDLEN2
TDLEN1
THDLC Enable Control
084, 184
3.20.2.4
Reset
The HDLC Transmitter will be reset when there is a transition from
‘0’ to ‘1’ on the TRST bit. The reset will clear the FIFO.
87
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 52: Related Bit / Register In Chapter 3.20.2.2 ~ Chapter 3.20.2.4
Bit
THDLCM
EOM
ABORT
TRST
DAT[7:0]
FUL
EMP
RDY
TDLEN3
TDLEN2
TDLEN1
HL[1:0]
LL[1:0]
RDYI
UDRUNI
RDYE
UDRUNE
Register
Address (Hex)
THDLC1 Control / THDLC2 Control / THDLC3 Control
0A7, 1A7 / 0A8, 1A8 / 0A9, 1A9
THDLC1 Data / THDLC2 Data / THDLC3 Data
0AD, 1AD / 0AE, 1AE / 0AF, 1AF
TFIFO1 Status / TFIFO2 Status / TFIFO3 Status
0B0 / 0B1, 1B1 / 0B2, 1B2
THDLC Enable Control
084, 184
TFIFO1 Threshold / TFIFO2 Threshold / TFIFO3 Threshold
0AA, 1AA / 0AB, 1AB / 0AC, 1AC
THDLC1 Interrupt Indication / THDLC2 Interrupt Indication /
THDLC3 Interrupt Indication
0B6, 1B6 / 0B7, 1B7 / 0B8, 1B8
THDLC1 Interrupt Control / THDLC2 Interrupt Control / THDLC3
Interrupt Control
0B3, 1B3 / 0B4, 1B4 / 0B5, 1B5
88
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3. The Frame Alignment Bit Error event detected in the Frame Processor;
4. The Severely Frame Alignment Bit Error event detected in the
Frame Processor;
5. The Buffer Slip event occurred in the Elastic Store Buffer.
Enabled by the AUTOPRM bit, the Automatic Performance Report
Message is generated every one second and transmitted on the DL bit
positions. The APRM format is illustrated in Table 53.
3.20.3
AUTOMATIC PERFORMANCE REPORT MESSAGE (T1/
J1 ONLY)
The Automatic Performance Report Message (APRM) can only be
transmitted in the ESF format in T1/J1 mode.
Five kinds of events are counted every second in the APRM:
1. The Bipolar Violation (BPV) Error / HDB3 Code Violation (CV)
Error event detected in the B8ZS/HDL3/AMI Decoder;
2. The CRC-6 Error event detected in the Frame Processor;
Table 53: APRM Message Format
Octet No.
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
1
Flag (‘01111110’)
2
SAPI (‘001110C/R0’)
3
TEI (‘00000001’)
4
Control (‘00000011’)
Bit 3
Bit 2
Bit 1
5
G3
LV
G4
U1
U2
G5
SL
G6
6
FE
SE
LB
G1
R
G2
Nm
Ni
7
G3
LV
G4
U1
U2
G5
SL
G6
8
FE
SE
LB
G1
R
G2
Nm
Ni
9
G3
LV
G4
U1
U2
G5
SL
G6
10
FE
SE
LB
G1
R
G2
Nm
Ni
11
G3
LV
G4
U1
U2
G5
SL
G6
12
FE
SE
LB
G1
R
G2
Nm
Ni
13
FCS
14
The Nm and Ni bit position is a module 4 counter.
The remaining bits in Octet No.5 to Octet No. 12 interpret the event
numbers counted by the APRM. The details are listed in Table 54. Their
default value are ‘0’s.
The APRM is transmitted bit by bit from Bit 1 to Bit 8 and from Octet
No. 1 to Octet No. 14. In the above table, the value in the C/R bit position, the R bit position, the U1 bit position, the U2 bit position and the LB
bit position are determined by the CRBIT bit, the RBIT bit, the U1BIT bit,
the U2BIT bit and the LBBIT bit in the APRM Control register respectively.
Table 54: APRM Interpretation
A Logic 1 In The Following Bit Position
Interpretation
G1
G2
G3
G4
G5
G6
SE
FE
LV
SL
CRC-6 Error event = 1
1 < CRC-6 Error event ≤ 5
5 < CRC-6 Error event ≤ 10
10 < CRC-6 Error event ≤ 100
100 < CRC-6 Error event ≤ 319
CRC-6 Error event > 320
Severely Frame Alignment Bit Error event ≥ 1
Frame Alignment Bit Error event ≥ 1
Bipolar Violation (BPV) Error / HDB3 Code Violation (CV) Error event ≥ 1
Buffer Slip event ≥ 1
89
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.20.6
ALL ‘ZERO’S & ALL ‘ONE’S
After all the above processes, all ’One’s or all ‘Zero’s will overwrite
all the data stream if the TAIS bit and the TXDIS bit are set. The all zeros
transmission takes a higher priority.
Table 55: Related Bit / Register In Chapter 3.20.3
Bit
AUTOPRM
CRBIT
RBIT
U1BIT
U2BIT
LBBIT
Register
APRM Control
T1/J1 Address (Hex)
3.20.7
CHANGE OF FRAME ALIGNMENT
Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the COFAEN bit
will lead to one-bit deletion or one-bit repetition in the data stream to be
transmitted, that is, to change the frame alignment position. The one-bit
deletion or repetition occurs randomly.
07F, 17F
3.20.4
BIT-ORIENTED MESSAGE TRANSMITTER (T1/J1 ONLY)
The Bit Oriented Message (BOM) can only be transmitted in the
ESF format in T1/J1 mode.
The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of
the F-bit in the ESF format. The six ‘X’s represent the code that is programmed in the XBOC[5:0] bits. The BOM is transmitted only if the
XBOC[5:0] bits are not all ’One’s.
3.20.5
INBAND LOOPBACK CODE GENERATOR (T1/J1 ONLY)
The Inband Loopback Code Generator can only transmit inband
loopback code in a framed or unframed T1/J1 data stream.
The length and the content of the inband loopback code are programmed in the CL[1:0] bits and the IBC[7:0] bits respectively. The code
can only be transmitted when the IBCDEN bit is enabled. In framed
mode, which is configured by the IBCDUNFM bit, the bits in all 24 channels are overwritten with the inband loopback code and the F-bit is not
changed. In unframed mode, which is configured by the IBCDUNFM bit,
all the bits in 24 channels and the F-bit are overwritten with the inband
loopback code.
Table 56: Related Bit / Register In Chapter 3.20.4 & Chapter 3.20.5
Bit
Register
T1/J1 Address (Hex)
XBOC[5:0]
IBC[7:0]
CL[1:0]
IBCDEN
IBCDUNFM
XBOC Code
XIBC Code
080, 180
075, 175
XIBC Control
074, 174
90
August 20, 2009
IDT82P2282
3.21
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TRANSMIT BUFFER
3.22
Transmit Buffer can be used in the circumstances that backplane
timing is different from the line side timing in Transmit Slave mode.
The function of timing option is also integrated in this block. The
source of the transmit clock can be selected in the recovered clock from
the line side, the processed clock from the backplane or the master
clock generated by the clock generator.
In Transmit Master mode, the Transmit Buffer is bypassed automatically. The source of the transmit clock can be selected between the
recovered clock from the line side and the master clock generated by
the internal clock generator (1.544 MHz in T1/J1 mode or 2.048 MHz in
E1 mode). The selection is made by the XTS bit.
In Transmit Clock Slave T1/J1 mode E1 rate, for the backplane timing is 2.048 MHz from backplane and the line timing is 1.544 MHz from
the internal clock generator, the Transmit Buffer is selected automatically to absorb high frequency mapping jitter due to the E1 to T1/J1
mapping scheme. In this case, 1.544 MHz must be locked to 2.048 MHz
by PLL of the internal clock generator. The XTS bit in the Transmit Timing Option register does not take effect.
In other Transmit Clock Slave modes, whether the Transmit Buffer
is bypassed and the source of the transmit clock selection are selected
by the XTS bit. When the XTS bit is set to ‘1’, line side timing is from
internal clock generator, but backplane timing is from backplane, so the
Transmit Buffer is selected to accommodate the different clocks. If these
two clocks are not locked, an internal slip will occur in the Transmit
Buffer. The source of the transmit clock is from the master clock generated by the internal clock generator (1.544 MHz in T1/J1 mode or 2.048
MHz in E1 mode). When the XTS bit is set to ‘0’, the line side timing is
also from the backplane timing, so the Transmit Buffer is bypassed. The
source of the transmit clock is from the processed clock from the backplane.
In Transmit Multiplexed mode, whether the Transmit Buffer is
bypassed and the source of the transmit clock selection are the same as
that described in other Transmit Clock Slave modes.
In most applications of Transmit Clock Slave mode, the XTS bit can
be set to ‘0’ to bypass the Transmit Buffer (The Transmit Buffer is
selected automatically in T1/J1 mode E1 rate).
ENCODER
3.22.1
LINE CODE RULE
3.22.1.1
T1/J1 Mode
In T1/J1 mode, the B8ZS line code rule or the AMI line code rule
can be selected by the T_MD bit.
3.22.1.2
E1 Mode
In E1 mode, the HDB3 line code rule or the AMI line code rule can
be selected by the T_MD bit.
3.22.2
BPV ERROR INSERTION
For test purpose, a BPV error can be inserted to the data stream to
be transmitted by a transition from ‘0’ to ‘1’ on the BPV_INS bit.
3.22.3
ALL ‘ONE’S INSERTION
When the LOS is detected in the receive path, all ‘One’s will be
inserted automatically to the data stream to be transmitted by setting the
ATAO bit.
Table 58: Related Bit / Register In Chapter 3.22
Bit
Register
Address (Hex)
T_MD
BPV_INS
ATAO
Transmit Configuration 0
Maintenance Function Control 2
Maintenance Function Control 1
022, 122
031, 131
02C, 12C
Table 57: Related Bit / Register In Chapter 3.20.6, Chapter 3.20.7 &
Chapter 3.21
Bit
TAIS
TXDIS
COFAEN
XTS
Register
Address (Hex)
FGEN Maintenance 1
06C, 16C
Transmit Timing Option
070, 170
91
August 20, 2009
IDT82P2282
3.23
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TRANSMIT JITTER ATTENUATOR
The Transmit Jitter Attenuator of each link can be chosen to be
used or not. This selection is made by the TJA_E bit.
The Jitter Attenuator consists of a FIFO and a DPLL, as shown in
Figure 7.
The FIFO is used as a pool to buffer the jittered input data, then the
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the TJA_DP[1:0]
bits. Accordingly, the constant delay produced by the Jitter Attenuator is
16 bits, 32 bits or 64 bits. The 128-bit FIFO is used when large jitter tolerance is expected, and the 32-bit FIFO is used in delay sensitive applications.
The DPLL is used to generate a de-jittered clock to clock out the
data stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF). The jitter which frequency is lower than the CF passes through the DPLL without any attenuation. In T1/J1 applications, the CF of the DPLL can be 5 Hz or 1.26
Hz, as selected by the TJA_BW bit. In E1 applications, the CF of the
DPLL can be 6.77 Hz or 0.87 Hz, as selected by the TJA_BW bit. The
lower the CF is, the longer time is needed to achieve synchronization.
If the incoming data moves faster than the outgoing data, the FIFO
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow or underflow is captured by the
TJA_IS bit. When the TJA_IS bit is ‘1’, an interrupt will be reported on
the INT pin if enabled by the TJA_IE bit.
To avoid overflowing or underflowing, the JA-Limit function can be
enabled by setting the TJA_LIMT bit. When the JA-Limit function is
enabled, the speed of the outgoing data will be adjusted automatically if
the FIFO is close to its full or emptiness. The criteria of speed adjustment start are listed in Table 6. Though the LA-Limit function can reduce
the possibility of FIFO overflow and underflow, the quality of jitter attenuation is deteriorated.
Selected by the TJITT_TEST bit, the real time interval between the
read and write pointer of the FIFO or the peak-peak interval between the
read and write pointer of the FIFO can be indicated in the TJITT[6:0]
bits. When the TJITT_TEST bit is ‘0’, the current interval between the
read and write pointer of the FIFO will be written into the TJITT[6:0] bits.
When the TJITT_TEST bit is ‘1’, the current interval is compared with
the old one in the TJITT[6:0] bits and the larger one will be indicated by
the TJITT[6:0] bits.
The performance of Receive Jitter Attenuator meets the ITUT
I.431, G.703, G.736 - 739, G.823, G.824, ETSI 300011, ETSI TBR 12/
13, AT&T TR62411, TR43802, TR-TSY 009, TR-TSY 253, TR-TRY 499
standards. Refer to Chapter 7.10 Jitter Tolerance and Chapter 7.11 Jitter
Transfer for details.
Table 59: Related Bit / Register In Chapter 3.23
Bit
Register
TJA_E
TJA_DP[1:0]
TJA_BW
Transmit Jitter Attenuation Configuration
TJA_LIMT
TJITT_TEST
TJA_IS
Interrupt Status 1
TJA_IE
Interrupt Enable Control 1
TJITT[6:0] Transmit Jitter Measure Value Indication
92
Address (Hex)
021, 121
03B, 13B
034, 134
038, 138
August 20, 2009
IDT82P2282
3.24
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
WAVEFORM SHAPER / LINE BUILD OUT
According to the various cables, configured by the PULS[3:0] bits,
three ways of manipulating the waveform shaper can be selected before
the data is transmitted:
1. Preset Waveform Template;
2. Line Build Out (LBO) Filter (T1 only);
3. User-Programmable Arbitrary Waveform.
Table 60: PULS[3:0] Setting In T1/J1 Mode
3.24.1
PRESET WAVEFORM TEMPLATE
3.24.1.1
T1/J1 Mode
In T1/J1 applications, the waveform template is shown in Figure 32,
which meets T1.102 and G.703, and it is measured in the far end as
shown in Figure 33.
Cable Configuration
PULS[3:0]
T1 - 0 ~ 133 ft
T1 - 133 ~ 266 ft
T1 - 266 ~ 399 ft
T1 - 399 ~ 533 ft
T1 - 533 ~ 655 ft
J1 - 0 ~ 655 ft
0010
0011
0100
0101
0110
0010
3.24.1.2
E1 Mode
In E1 applications, the waveform template is shown in Figure 34,
which meets G.703, and it is measured on the near line side as shown in
Figure 35.
1.2
1
1.20
0.6
1.00
0.4
0.2
Normalized Amplitude
Normalized Amplitude
0.8
0
-0.2
-0.4
-0.6
0
250
500
750
1000
1250
Time (ns)
0.80
0.60
0.40
0.20
Figure 32. DSX-1 Waveform Template
0.00
-0.20
TTIPn
-0.6
-0.4
Cable
IDT82P2282
-0.2
0
0.2
0.6
0.4
Time In Unit Intervals
RLOAD VOUT
TRINGn
Figure 34. E1 Waveform Template
Note: RLOAD = 100 Ω + 5%
TTIPn
Figure 33. T1/J1 Pulse Template Measurement Circuit
IDT82P2282
In T1 applications, to meet the template, five preset waveform templates are provided corresponding to five grades of cable length. The
selection is made by the PULS[3:0] bits. In J1 applications, the
PULS[3:0] bits should be set to ‘0010’. The details are listed in Table 60.
RLOAD
VOUT
TRINGn
Note: RLOAD = 75 Ω or 120 Ω (+ 5%)
Figure 35. E1 Pulse Template Measurement Circuit
93
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
and the scaling percentage ratio are different. The values are listed in
Table 62 to Table 73.
Do the followings step by step, the desired waveform can be programmed based on the selected waveform template:
1. Select the UI by the UI[1:0] bits;
2. Specify the sample address in the selected UI by the SAMP[3:0]
bits;
3. Write sample data to the WDAT[6:0] bits. It contains the data to
be stored in the RAM, addressed by the selected UI and the corresponding sample address;
4. Set the RW bit to ‘0’ to write data to RAM, or to ‘1’ to read data
from RAM;
5. Set the DONE bit to implement the read or write operation;
(Repeat the above steps until all the sample data are written to or
read from the internal RAM).
6. Write the scaling data to the SCAL[5:0] bits to scale the amplitude of the waveform based on the selected standard pulse amplitude.
Table 62 to Table 73 give all the sample data based on preset pulse
templates and LBOs in details for reference. For preset pulse templates
and LBOs, scaling up/down against the pulse amplitude is not supported.
1. Table 62 - Transmit Waveform Value For E1 75 Ω
2. Table 63 - Transmit Waveform Value For E1 120 Ω
3. Table 64 - Transmit Waveform Value For T1 0~133 ft
4. Table 65 - Transmit Waveform Value For T1 133~266 ft
5. Table 66 - Transmit Waveform Value For T1 266~399 ft
6. Table 67 - Transmit Waveform Value For T1 399~533 ft
7. Table 68 - Transmit Waveform Value For T1 533~655 ft
8. Table 69 - Transmit Waveform Value For J1 0~655 ft
9. Table 70 - Transmit Waveform Value For DS1 0 dB LBO
10. Table 71 - Transmit Waveform Value For DS1 -7.5 dB LBO
11. Table 72 - Transmit Waveform Value For DS1 -15.0 dB LBO
12. Table 73 - Transmit Waveform Value For DS1 -22.5 dB LBO
To meet the template, two preset waveform templates are provided
corresponding to two kinds of cable impedance. The selection is made
by the PULS[3:0] bits. In internal impedance matching mode, if the cable
impedance is 75 Ω, the PULS[3:0] bits should be set to ‘0000’; if the
cable impedance is 120 Ω, the PULS[3:0] bits should be set to ‘0001’. In
external impedance matching mode, for both 75 Ω and 120 Ω cable
impedance, the PULS[3:0] bits should be set to ‘0001’.
3.24.2
LINE BUILD OUT (LBO) (T1 ONLY)
In long haul applications, the output on the TTIPn/TRINGn pins
should be attenuated before transmission to prevent the cross-talk in the
far end. Three LBOs are used to implement the pulse attenuation. Four
grades of attenuation with each step of 7.5 dB are specified in the FCC
Part 68 Regulations. The attenuation grade is selected by the PULS[3:0]
bits. The details are listed in Table 61.
Table 61: LBO PULS[3:0] Setting In T1 Mode
Cable Configuration
PULS[3:0]
0 dB LBO
-7.5 dB LBO
-15.0 dB LBO
-22.5 dB LBO
0010
1001
1010
1011
3.24.3
USER-PROGRAMMABLE ARBITRARY WAVEFORM
User-programmable arbitrary waveform can be used in both short
haul applications and long haul applications if the PULS[3:0] bits are set
to ‘11XX’ in the corresponding link. This allows the transmitter performance to be tuned for a wide variety of line condition or special application.
Each pulse shape can extend up to 4 UIs (Unit Interval) addressed
by the UI[1:0] bits, and each UI is divided into 16 sub-phases addressed
by the SAMP[3:0] bits. The pulse amplitude of each phase is represented by a binary byte, within the range from +63 to -63, stored in the
WDAT[6:0] bits in signed magnitude form. The maximum number +63
(D) represents the positive maximum amplitude of the transmit pulse
while the most negative number -63 (D) represents the maximum negative amplitude of the transmit pulse. Thus, up to 64 bytes are used. For
each channel, a 64 bytes RAM is available.
There are twelve standard templates which are stored in a local
ROM. One of them can be selected as reference and made some
changes to get the desired waveform.
To do this, the first step is to choose a set of waveform value, which
is the most similar to the desired pulse shape, from the following 12
tables (Table 62 to Table 73), and set the SCAL[5:0] bits to the corresponding standard value. Table 62 to Table 73 list the sample data and
the standard scaling value of each of the 12 templates.
Modifying the corresponding sample data can get the desired
transmit pulse shape. By increasing or decreasing by ‘1’ from the standard value in the SCAL[5:0] bits, the pulse amplitude can be scaled up
or down at the percentage ratio against the standard pulse amplitude if
necessary. For different pulse shapes, the value of the SCAL[5:0] bits
94
August 20, 2009
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 62: Transmit Waveform Value For E1 75 Ohm
Table 63: Transmit Waveform Value For E1 120 Ohm
UI 1
UI 2
UI 3
UI 4
UI 1
UI 2
UI 3
UI 4
Sample 1
0000000
0000000
0000000
0000000
Sample 1
0000000
0000000
0000000
0000000
Sample 2
0000000
0000000
0000000
0000000
Sample 2
0000000
0000000
0000000
0000000
Sample 3
0000000
0000000
0000000
0000000
Sample 3
0000000
0000000
0000000
0000000
Sample 4
0001100
0000000
0000000
0000000
Sample 4
0001111
0000000
0000000
0000000
Sample 5
0110000
0000000
0000000
0000000
Sample 5
0111100
0000000
0000000
0000000
Sample 6
0110000
0000000
0000000
0000000
Sample 6
0111100
0000000
0000000
0000000
Sample 7
0110000
0000000
0000000
0000000
Sample 7
0111100
0000000
0000000
0000000
Sample 8
0110000
0000000
0000000
0000000
Sample 8
0111100
0000000
0000000
0000000
Sample 9
0110000
0000000
0000000
0000000
Sample 9
0111100
0000000
0000000
0000000
Sample 10
0110000
0000000
0000000
0000000
Sample 10
0111100
0000000
0000000
0000000
Sample 11
0110000
0000000
0000000
0000000
Sample 11
0111100
0000000
0000000
0000000
Sample 12
0110000
0000000
0000000
0000000
Sample 12
0111100
0000000
0000000
0000000
Sample 13
0000000
0000000
0000000
0000000
Sample 13
0000000
0000000
0000000
0000000
Sample 14
0000000
0000000
0000000
0000000
Sample 14
0000000
0000000
0000000
0000000
Sample 15
0000000
0000000
0000000
0000000
Sample 15
0000000
0000000
0000000
0000000
Sample 16
0000000
0000000
0000000
0000000
Sample 16
0000000
0000000
0000000
0000000
The standard value of the SCAL[5:0] bits is ‘100001’. One step change of this value
results in 3% scaling up/down against the pulse amplitude.
The standard value of the SCAL[5:0] bits is ‘100001’. One step change of this value
results in 3% scaling up/down against the pulse amplitude.
95
August 20, 2009
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 64: Transmit Waveform Value For T1 0~133 ft
Table 65: Transmit Waveform Value For T1 133~266 ft
UI 1
UI 2
UI 3
UI 4
UI 1
UI 2
UI 3
UI 4
Sample 1
0010111
1000010
0000000
0000000
Sample 1
0011011
1000011
0000000
0000000
Sample 2
0100111
1000001
0000000
0000000
Sample 2
0101100
1000010
0000000
0000000
Sample 3
0100111
0000000
0000000
0000000
Sample 3
0101011
1000001
0000000
0000000
Sample 4
0100110
0000000
0000000
0000000
Sample 4
0101010
0000000
0000000
0000000
Sample 5
0100101
0000000
0000000
0000000
Sample 5
0101000
0000000
0000000
0000000
Sample 6
0100101
0000000
0000000
0000000
Sample 6
0101000
0000000
0000000
0000000
Sample 7
0100101
0000000
0000000
0000000
Sample 7
0100111
0000000
0000000
0000000
Sample 8
0100100
0000000
0000000
0000000
Sample 8
0100110
0000000
0000000
0000000
Sample 9
0100011
0000000
0000000
0000000
Sample 9
0100101
0000000
0000000
0000000
Sample 10
1001010
0000000
0000000
0000000
Sample 10
1010000
0000000
0000000
0000000
Sample 11
1001010
0000000
0000000
0000000
Sample 11
1001111
0000000
0000000
0000000
Sample 12
1001001
0000000
0000000
0000000
Sample 12
1001101
0000000
0000000
0000000
Sample 13
1000111
0000000
0000000
0000000
Sample 13
1001010
0000000
0000000
0000000
Sample 14
1000101
0000000
0000000
0000000
Sample 14
1001000
0000000
0000000
0000000
Sample 15
1000100
0000000
0000000
0000000
Sample 15
1000110
0000000
0000000
0000000
Sample 16
1000011
0000000
0000000
0000000
Sample 16
1000100
0000000
0000000
0000000
The standard value of the SCAL[5:0] bits is ‘110110’. One step change of this value
results in 2% scaling up/down against the pulse amplitude.
The standard value of the SCAL[5:0] bits is ‘110110’. One step change of this value
results in 2% scaling up/down against the pulse amplitude.
96
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Table 66: Transmit Waveform Value For T1 266~399 ft
Table 67: Transmit Waveform Value For T1 399~533 ft
UI 1
UI 2
UI 3
UI 4
UI 1
UI 2
UI 3
UI 4
Sample 1
0011111
1000011
0000000
0000000
Sample 1
0100000
1000011
0000000
0000000
Sample 2
0110001
1000010
0000000
0000000
Sample 2
0111000
1000010
0000000
0000000
Sample 3
0101111
1000001
0000000
0000000
Sample 3
0110011
1000001
0000000
0000000
Sample 4
0101100
0000000
0000000
0000000
Sample 4
0101111
0000000
0000000
0000000
Sample 5
0101011
0000000
0000000
0000000
Sample 5
0101110
0000000
0000000
0000000
Sample 6
0101010
0000000
0000000
0000000
Sample 6
0101101
0000000
0000000
0000000
Sample 7
0101001
0000000
0000000
0000000
Sample 7
0101100
0000000
0000000
0000000
Sample 8
0101000
0000000
0000000
0000000
Sample 8
0101010
0000000
0000000
0000000
Sample 9
0100101
0000000
0000000
0000000
Sample 9
0101000
0000000
0000000
0000000
Sample 10
1010111
0000000
0000000
0000000
Sample 10
1011000
0000000
0000000
0000000
Sample 11
1010011
0000000
0000000
0000000
Sample 11
1011000
0000000
0000000
0000000
Sample 12
1010000
0000000
0000000
0000000
Sample 12
1010011
0000000
0000000
0000000
Sample 13
1001011
0000000
0000000
0000000
Sample 13
1001100
0000000
0000000
0000000
Sample 14
1001000
0000000
0000000
0000000
Sample 14
1001000
0000000
0000000
0000000
Sample 15
1000110
0000000
0000000
0000000
Sample 15
1000110
0000000
0000000
0000000
Sample 16
1000100
0000000
0000000
0000000
Sample 16
1000100
0000000
0000000
0000000
The standard value of the SCAL[5:0] bits is ‘110110’. One step change of this value
results in 2% scaling up/down against the pulse amplitude.
The standard value of the SCAL[5:0] bits is ‘110110’. One step change of this value
results in 2% scaling up/down against the pulse amplitude.
97
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 68: Transmit Waveform Value For T1 533~655 ft
Table 69: Transmit Waveform Value For J1 0~655ft
UI 1
UI 2
UI 3
UI 4
UI 1
UI 2
UI 3
UI 4
Sample 1
0100000
1000011
0000000
0000000
Sample 1
0010111
1000010
0000000
0000000
Sample 2
0111111
1000010
0000000
0000000
Sample 2
0100111
1000001
0000000
0000000
Sample 3
0111000
1000001
0000000
0000000
Sample 3
0100111
0000000
0000000
0000000
Sample 4
0110011
0000000
0000000
0000000
Sample 4
0100110
0000000
0000000
0000000
Sample 5
0101111
0000000
0000000
0000000
Sample 5
0100101
0000000
0000000
0000000
Sample 6
0101110
0000000
0000000
0000000
Sample 6
0100101
0000000
0000000
0000000
Sample 7
0101101
0000000
0000000
0000000
Sample 7
0100101
0000000
0000000
0000000
Sample 8
0101100
0000000
0000000
0000000
Sample 8
0100100
0000000
0000000
0000000
Sample 9
0101001
0000000
0000000
0000000
Sample 9
0100011
0000000
0000000
0000000
Sample 10
1011111
0000000
0000000
0000000
Sample 10
1001010
0000000
0000000
0000000
Sample 11
1011110
0000000
0000000
0000000
Sample 11
1001010
0000000
0000000
0000000
Sample 12
1010111
0000000
0000000
0000000
Sample 12
1001001
0000000
0000000
0000000
Sample 13
1001111
0000000
0000000
0000000
Sample 13
1000111
0000000
0000000
0000000
Sample 14
1001001
0000000
0000000
0000000
Sample 14
1000101
0000000
0000000
0000000
Sample 15
1000111
0000000
0000000
0000000
Sample 15
1000100
0000000
0000000
0000000
Sample 16
1000100
0000000
0000000
0000000
Sample 16
1000011
0000000
0000000
0000000
The standard value of the SCAL[5:0] bits is ‘110110’. One step change of this value
results in 2% scaling up/down against the pulse amplitude.
The standard value of the SCAL[5:0] bits is ‘110110’. One step change of this value
results in 2% scaling up/down against the pulse amplitude.
98
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Table 70: Transmit Waveform Value For DS1 0 dB LBO
Table 71: Transmit Waveform Value For DS1 -7.5 dB LBO
UI 1
UI 2
UI 3
UI 4
UI 1
UI 2
UI 3
UI 4
Sample 1
0010111
1000010
0000000
0000000
Sample 1
0000000
0010100
0000010
0000000
Sample 2
0100111
1000001
0000000
0000000
Sample 2
0000010
0010010
0000010
0000000
Sample 3
0100111
0000000
0000000
0000000
Sample 3
0001001
0010000
0000010
0000000
Sample 4
0100110
0000000
0000000
0000000
Sample 4
0010011
0001110
0000010
0000000
Sample 5
0100101
0000000
0000000
0000000
Sample 5
0011101
0001100
0000010
0000000
Sample 6
0100101
0000000
0000000
0000000
Sample 6
0100101
0001011
0000001
0000000
Sample 7
0100101
0000000
0000000
0000000
Sample 7
0101011
0001010
0000001
0000000
Sample 8
0100100
0000000
0000000
0000000
Sample 8
0110001
0001001
0000001
0000000
Sample 9
0100011
0000000
0000000
0000000
Sample 9
0110110
0001000
0000001
0000000
Sample 10
1001010
0000000
0000000
0000000
Sample 10
0111010
0000111
0000001
0000000
Sample 11
1001010
0000000
0000000
0000000
Sample 11
0111001
0000110
0000001
0000000
Sample 12
1001001
0000000
0000000
0000000
Sample 12
0110000
0000101
0000001
0000000
Sample 13
1000111
0000000
0000000
0000000
Sample 13
0101000
0000100
0000000
0000000
Sample 14
1000101
0000000
0000000
0000000
Sample 14
0100000
0000100
0000000
0000000
Sample 15
1000100
0000000
0000000
0000000
Sample 15
0011010
0000011
0000000
0000000
Sample 16
1000011
0000000
0000000
0000000
Sample 16
0010111
0000011
0000000
0000000
The standard value of the SCAL[5:0] bits is ‘110110’. One step change of this value
results in 2% scaling up/down against the pulse amplitude.
The standard value of the SCAL[5:0] bits is ‘010001’. One step change of this value
results in 6.25% scaling up/down against the pulse amplitude.
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 72: Transmit Waveform Value For DS1 -15.0 dB LBO
Table 73: Transmit Waveform Value For DS1 -22.5 dB LBO
UI 1
UI 2
UI 3
UI 4
UI 1
UI 2
UI 3
UI 4
Sample 1
0000000
0110101
0001111
0000011
Sample 1
0000000
0101100
0011110
0001000
Sample 2
0000000
0110011
0001101
0000010
Sample 2
0000000
0101110
0011100
0000111
Sample 3
0000000
0110000
0001100
0000010
Sample 3
0000000
0110000
0011010
0000110
Sample 4
0000001
0101101
0001011
0000010
Sample 4
0000000
0110001
0011000
0000101
Sample 5
0000100
0101010
0001010
0000010
Sample 5
0000001
0110010
0010111
0000101
Sample 6
0001000
0100111
0001001
0000001
Sample 6
0000011
0110010
0010101
0000100
Sample 7
0001110
0100100
0001000
0000001
Sample 7
0000111
0110010
0010100
0000100
Sample 8
0010100
0100001
0000111
0000001
Sample 8
0001011
0110001
0010011
0000011
Sample 9
0011011
0011110
0000110
0000001
Sample 9
0001111
0110000
0010001
0000011
Sample 10
0100010
0011100
0000110
0000001
Sample 10
0010101
0101110
0010000
0000010
Sample 11
0101010
0011010
0000101
0000001
Sample 11
0011001
0101100
0001111
0000010
Sample 12
0110000
0010111
0000101
0000001
Sample 12
0011100
0101001
0001110
0000010
Sample 13
0110101
0010101
0000100
0000001
Sample 13
0100000
0100111
0001101
0000001
Sample 14
0110111
0010100
0000100
0000000
Sample 14
0100011
0100100
0001100
0000001
Sample 15
0111000
0010010
0000011
0000000
Sample 15
0100111
0100010
0001010
0000001
Sample 16
0110111
0010000
0000011
0000000
Sample 16
0101010
0100000
0001001
0000001
The standard value of the SCAL[5:0] bits is ‘001000’. One step change of the value
results in 12.5% scaling up/down against the pulse amplitude.
The standard value of the SCAL[5:0] bits is ‘000100’. One step change of this value
results in 25% scaling up/down against the pulse amplitude.
When more than one UI are used to compose the pulse template
and the pulse amplitude is not set properly, the overlap of two consecutive pulses will make the pulse amplitude overflow (exceed the maximum limitation). This overflow is captured by the DAC_IS bit, and if
enabled by the DAC_IE bit, an interrupt will be reported by the INT pin.
Table 74: Related Bit / Register In Chapter 3.24
100
Bit
Register
Address (Hex)
PULS[3:0]
UI[1:0]
SAMP[3:0]
RW
DONE
WDAT[6:0]
SCAL[5:0]
DAC_IS
DAC_IE
Transmit Configuration 1
023, 123, 223
Transmit Configuration 3
025, 125
Transmit Configuration 4
Transmit Configuration 2
Interrupt Status 1
Interrupt Enable Control 1
026, 126
024, 124
03B, 13B
034, 134
August 20, 2009
IDT82P2282
3.25
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
LINE DRIVER
The Line Driver can be set to High-Z for redundant application.
The following ways will set the drivers to High-Z:
1. Setting the THZ pin to high will globally set both the Line Drivers
to High-Z;
2. When there is no clock input on the OSCI pin, both the Line Drivers will be High-Z (no clock means this: the input on the OSCI pin is in
high/low level, or the duty cycle is less than 30% or larger than 70%);
3. After software reset, hardware reset or power on, both the Line
Drivers will be High-Z;
4. Setting the T_HZ bit to ‘1’ will set the corresponding Line Driver
to High-Z;
5. In Transmit Clock Master mode, if the XTS bit is ‘1’, the source of
the transmit clock is from the recovered clock from the line side. When
the recovered clock from the line side is lost, the Line Driver in the corresponding link will be High-Z;
6. In Transmit Clock Slave mode, if the XTS bit is ‘0’, the source of
the transmit clock is from the backplane timing clock. When the backplane timing clock is lost (i.e., no transition for more than 72 T1/E1/J1
cycles), the Line Driver in the corresponding link will be High-Z. However, there is an exception in this case. That is, if the link is in Remote
Loopback mode, the Line Driver will not be High-Z.
7. When the transmit path is power down, the Line Driver in the corresponding link will be High-Z.
By these ways, the TTIPn and TRINGn pins will enter into high
impedance state immediately.
Controlled by the DFM_ON bit, the output driver short-circuit protection can be enabled. The driver’s output current (peak to peak) is limited to 110 mA typically. When the output current exceeds the limitation,
the transmit driver failure will be captured by the DF_S bit. Selected by
the DF_IES bit, a transition from ‘0’ to ‘1’ on the DF_S bit or any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the DF_S bit will set the DF_IS bit.
When the DF_IS bit is ‘1’, an interrupt on the INT pin will be reported if
enabled by the DF_IE bit.
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TRANSMITTER IMPEDANCE MATCHING
In T1/J1 mode, the transmitter impedance matching can be realized by using internal impedance matching circuit. 100 Ω, 110 Ω, 75 Ω
or 120 Ω internal impedance matching circuit can be selected by the
T_TERM[1:0] bits. The external impedance circuitry is not supported in
T1/J1 mode.
In E1 mode, the transmitter impedance matching can be realized
by using internal impedance matching circuit or external impedance
matching circuit. When the T_TERM[2] bit is ‘0’, the internal impedance
matching circuit is enabled. 100 Ω, 110 Ω, 75 Ω or 120 Ω internal
impedance matching circuit can be selected by the T_TERM[1:0] bits.
When the T_TERM[2] bit is ‘1’, the internal impedance matching circuit
is disabled, and different external resistors should be used to realize different impedance matching.
Figure 2 shows the appropriate components to connect with the
cable for one link. Table 75 lists the recommended impedance matching
values for the transmitter.
Table 75: Impedance Matching Value For The Transmitter
Internal Termination
Cable
Configuration
T_TERM[2:0]
RT
75 Ω (E1)
120 Ω (E1)
100 Ω (T1)
110 Ω (J1)
000
001
010
011
0Ω
External Termination
T_TERM[2:0]
RT
1XX
9.4 Ω
-
-
Table 76: Related Bit / Register In Chapter 3.25 & Chapter 3.26
Bit
T_HZ
DFM_ON
XTS
DF_S
DF_IES
DF_IS
DF_IE
T_TERM[2:0]
Register
Address (Hex)
Transmit Configuration 1
023, 123
Transmit Timing Option
Line Status Register 0
Interrupt Trigger Edges Select
Interrupt Status 0
Interrupt Enable Control 0
Transmit And Receive Termination Configuration
070, 170
036, 136
035, 135
03A, 13A
033, 133
032, 132
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TESTING AND DIAGNOSTIC FACILITIES
A single bit error will be inserted to the generated pattern when the
INV bit is set to ‘1’. Before the insertion, the generated pattern can be
inverted when the TINV bit is set.
3.27.1
PRBS GENERATOR / DETECTOR
The PRBS Generator / Detector generates test pattern to either the
transmit or receive direction, and detects the pattern in the opposite
direction. The direction is determined by the PRBSDIR bit. The pattern
can be generated or detected in unframed mode, in 8-bit-based mode or
in 7-bit-based mode. This selection is made by the PRBSMODE[1:0]
bits. In unframed mode, all the data streams are extracted or replaced
and the per-channel/per-TS configuration in the TEST bit is ignored. In
8-bit-based mode or in 7-bit-based mode, the extracted or replaced
channel/timeslot is specified by the TEST bit. (In 7-bit-based mode, only
the higher 7 bits of the selected channel/timeslot are used for PRBS
test).
3.27.1.2
Pattern Detector
When there is a transition from ‘0’ to ‘1’ on the TESTEN bit, the pattern detector starts to extract the data. The extracted data is used to regenerate a desired pattern which is selected by the PATS[1:0] bits. The
extracted data is compared with the re-generated pattern. If the
extracted data coincides with the pattern, the pattern is synchronized
and it will be indicated by the SYNCV bit. In synchronization state, each
mismatched bit will generate a PRGD Bit Error event. This event is captured by the BERI bit and is forwarded to the Performance Monitor. An
interrupt reported on the INT pin will be enabled by the BERE bit if the
BERI bit is ‘1’. When there are more than 10-bit errors detected in the
fixed 48-bit window, the extracted data is out of synchronization and it
also will be indicated by the SYNCV bit. Any transition (from ‘1’ to ‘0’ or
from ‘0’ to ‘1’) on the SYNCV bit will set the SYNCI bit. An interrupt
reported on the INT pin will be enabled by the SYNCE bit if the SYNCI
bit is ‘1’.
Before the data extracted to the pattern detector, the data can be
inverted by setting the RINV bit.
3.27.1.1
Pattern Generator
Three patterns are generated: 211-1 pattern per O.150, 215-1 pattern per O.152 and 220-1 pattern per O.150-4.5. They are selected by
the PATS[1:0] bits.
The selected pattern is generated once there is a transition from ‘0’
to ‘1’ on the TESTEN bit.
Table 77: Related Bit / Register In Chapter 3.27.1
Bit
PRBSDIR
PRBSMODE[1:0]
TESTEN
TEST
PATS[1:0]
TINV
RINV
INV
SYNCV
BERE
SYNCE
BERI
SYNCI
Register
Address (Hex)
TPLC / RPLC / PRGD Test Configuration
0C7, 1C7
ID * - Signaling Trunk Conditioning Code
RPLC & TPLC ID * - 41~58 (for T1/J1) / 41~4F & 51~5F (for E1)
PRGD Control
071, 171
PRGD Status/Error Control
072, 172
PRGD Interrupt Indication
073, 173
Note:
* ID means Indirect Register in the Receive & Transmit Payload Control function blocks.
103
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3.27.2.2
Payload Loopback
By programming the GSUBST[2:0] bits or the SUBST[2:0] bits, the
Payload Loopback can be implemented. The received data output from
the Elastic Store Buffer is internally looped to the Transmit Payload Control.
In Payload Loopback mode, the received data is still output to the
system side, while the data to be transmitted from the system side is
replaced by the Payload Loopback data.
3.27.2
LOOPBACK
System Loopback, Payload Loopback, Local Digital Loopback 1 &
2, Remote Loopback and Analog Loopback are all supported in the
IDT82P2282. Their routes are shown in the Functional Block Diagram.
3.27.2.1
System Loopback
The System Loopback can only be implemented when the Receive
System Interface and the Transmit System Interface are in different
Non-multiplexed operating modes (one in Clock Master mode and the
other in Clock Slave mode). However, in T1/J1 mode, when either the
receive path or the transmit path is in T1/J1 mode E1 rate, the System
Loopback is not supported.
Distinguished by the loopback direction, the System Loopback can
be divided into System Remote Loopback and System Local Loopback.
When the data and signaling bits from the transmit path are looped to
the receive path, it is System Remote Loopback. When the data and signaling bits from the receive path are looped to the transmit path, it is
System Local Loopback.
3.27.2.3
Local Digital Loopback 1
Enabled by the DLLP bit, the Local Digital Loopback 1 is implemented. The data stream output from the Transmit Buffer is internally
looped to the Frame Processor.
In Local Digital Loopback 1 mode, the data stream to be transmitted is still output to the line side, while the data stream received from the
line side is replaced by the Local Digital Loopback 1 data.
3.27.2.4
Remote Loopback
Enabled by the RLP bit, the Remote Loopback is implemented. The
data stream output from the optional Receive Jitter Attenuator is internally looped to the optional Transmit Jitter Attenuator.
In Remote Loopback mode, the data stream received from the line
side is still output to the system, while the data stream to be transmitted
is replaced by the Remote Loopback data.
3.27.2.1.1
System Remote Loopback
Enabled by the SRLP bit, the System Remote Loopback is implemented. The data and signaling bits to be transmitted on the TSDn and
TSIGn pins are internally looped to the RSDn and RSIGn pins. When
the receive path is in Receive Clock Master mode and the transmit path
is in Transmit Clock Slave mode, the clock signal and the framing pulse
from the system side on the TSCKn and TSFSn pins are looped to the
RSCKn and RSFSn pins respectively. When the transmit path is in
Transmit Clock Master mode and the receive path is in Receive Clock
Slave mode, the clock signal and the framing pulse from the system side
on the RSCKn and RSFSn pins are looped to the TSCKn and TSFSn
pins respectively.
In System Remote Loopback mode, the data stream to be transmitted is still output to the line side, while the data stream received from the
line side is replaced by the System Remote Loopback data.
3.27.2.5
Local Digital Loopback 2
Enabled by the DLP bit, the Local Digital Loopback 2 is implemented. The data stream output from the optional Transmit Jitter Attenuator is internally looped to the Optional Receive Jitter Attenuator.
In Local Digital Loopback 2 mode, the data stream to be transmitted is still output to the line side, while the data stream received from the
line side is replaced by the Local Digital Loopback 2 data.
3.27.2.6
Analog Loopback
Enabled by the ALP bit, the Analog Loopback is implemented. The
data stream to be transmitted on the TTIPn/TRINGn pins is internally
looped to the RTIPn/RRINGn pins.
In Analog Loopback mode, the data stream to be transmitted is still
output to the line side, while the data stream received from the line side
is replaced by the Analog Loopback data.
If analog loopback is enabled, line driver should be set to normal
(T_HZ=0 & THZ pin is tied to ground).
3.27.2.1.2
System Local Loopback
Enabled by the SLLP bit, the System Local Loopback is implemented. The received data and signaling bits to be output on the RSDn
and RSIGn pins are internally looped to the TSDn and TSIGn pins.
When the receive path is in Receive Clock Master mode and the transmit path is in Transmit Clock Slave mode, the recovered clock signal and
framing pulse on the RSCKn and RSFSn pins are looped to the TSCKn
and TSFSn pins respectively. When the transmit path is in Transmit
Clock Master mode and the receive path is in Receive Clock Slave
mode, the TSCKn and TSFSn pins are looped to the RSCKn and
RSFSn pins respectively.
In System Local Loopback mode, the data stream received from
the line side is still output to the system through the RSDn and RSIGn
pins, while the data stream to be transmitted through the TSDn and
TSIGn pins are replaced by the System Local Loopback data.
3.27.3
G.772 NON-INTRUSIVE MONITORING
When the G.772 Non-Intrusive Monitoring is implemented, only the
Link 2 is in normal operation and the Link 1 is configured to monitor the
receive path or transmit path of Link 2.
Whether the G.772 Non-Intrusive Monitoring is implemented and
which direction (receive/transmit) and link is monitored are both determined by the MON[3] and MON[0] bits.
The G.772 Non-Intrusive Monitoring meets the ITU-T G.772. It is
shown in Figure 36. The data stream of Link 1 is received from Link 2,
then processed as normal. The operation of the monitored link is not
effected.
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Link 1
TSD1 / MTSD
TTIP1
TSIG1 / MTSIG
TSFS1 / MTSFS
Transmit System
Interface
Transmit Internal
Termination
TRING1
TSCK1 / MTSCK
RSCK1 / MRSCK
RTIP1
RSFS1 / MRSFS
RSIG1 / MRSIG
Receive System
Interface
Receive Internal
Termination
RRING1
RSD1 / MRSD
G.772 NonIntrusive Monitor
Link 2
TSD2
TTIP2
TSIG2
TSFS2
Transmit System
Interface
Transmit Internal
Termination
TRING2
TSCK2
RSCK2
RTIP2
RSFS2
RSIG2
Receive System
Interface
Receive Internal
Termination
RRING2
RSD2
Figure 36. G.772 Non-Intrusive Monitor
105
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 78: Related Bit / Register In Chapter 3.27.2 & Chapter 3.27.3
Bit
SRLP
SLLP
DLLP
RLP
DLP
ALP
GSUBST[2:0]
SUBST[2:0]
MON3
MON0
Register
Address (Hex)
Maintenance Function Control 0
02B, 12B
TPLC Configuration
ID * - Channel Control (for T1/J1) / Timeslot Control (for E1)
0CB, 1CB
TPLC ID * - 01~18 (for T1/J1) / 00~1F (for E1)
G.772 Monitor Control
005
Note:
* ID means Indirect Register in the Transmit Payload Control function block.
106
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3.28
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
INTERRUPT SUMMARY
second timer of the device generates an interrupt. Then the source is
served after it is found.
After reading the Interrupt Requisition Link ID register, the Interrupt
Module Indication registers of the interrupting link are read. The Interrupt
Module Indication bits will be ‘1’ if there are interrupts in the corresponding function block. To find the eventual interrupt sources, the Interrupt
Indication and Status bits in the block are polled if their Interrupt Enable
bits are enabled. Then the sources are served after they are found.
When the INT pin is asserted low, it means at least one interrupt
has occurred in the device. Reading the Timer Interrupt Indication register and Interrupt Requisition Link ID register will find whether the timer
interrupt occurs or in which link the interrupt occurs.
If the TMOVI bit in the Timer Interrupt Indication register is ‘1’ and
the TMOVE bit in the Timer Interrupt Control register is enabled, the one
Table 79: Related Bit / Register In Chapter 3.28
Bit
Register
Address (Hex)
TMOVI
INT[2:1]
TMOVE
LIU
IBCD (T1/J1 only)
RBOC (T1/J1 only)
ALARM
PMON
PRGD
RCRB
FGEN
FRMR
THDLC3
THDLC2
THDLC1
RHDLC3
RHDLC2
RHDLC1
ELST
TRSI/RESI
Timer Interrupt Indication
Interrupt Requisition Link ID
Timer Interrupt Control
Interrupt Module Indication 2
00B
009
00A
03F, 13F
Interrupt Module Indication 0
040, 140
Interrupt Module Indication 1
041, 141
107
August 20, 2009
IDT82P2282
4
4.1
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
OPERATION
100 ns
POWER-ON SEQUENCE
To power on the device, the following sequence should be followed:
1. Apply ground;
2. Apply 3.3 V;
3. Apply 1.8 V.
4.2
RESET
2ms
Microprocessor
Interface
RESET
When the device is powered-up, all the registers contain random
values.
The hardware reset pin RESET must be asserted low during the
power-up and the low signal should last at least 10 ms to initialize the
device. After the RESET pin is asserted high, all the registers are in their
default values and can be accessed after 2 ms (refer to Figure 37).
During normal operation, the device can be reset by hardware or
software anytime. When it is hardware reset, the RESET pin should be
asserted low for at least 100 ns. Then all the registers are in their default
values and can be accessed after 2 ms (refer to Figure 38). When it is
software reset, a write signal to the Software Reset register will reset all
the registers except the T1/J1 Or E1 Mode register to their default values. Then the registers are accessible after 2 ms. However, the T1/J1
Or E1 Mode register can not be reset by the software reset. It can only
be reset by the hardware reset.
Hardware or software reset can only be applied when the clock on
the OSCI pin is available.
It should be mentioned that when the setting in the T1/J1 Or E1
Mode register is changed, a software reset must be applied.
Vdd
access
Figure 38. Hardware Reset In Normal Operation
4.3
RECEIVE / TRANSMIT PATH POWER DOWN
The receive path of any of the two links can be power down by setting the R_OFF bit. During the receive path power down, the output of
the corresponding path is low.
The transmit path of any of the two links can be set to power down
by the T_OFF bit. During the transmit path power down, the output of the
corresponding path is High-Z.
10ms
RESET
2ms
Microprocessor
Interface
access
Figure 37. Hardware Reset When Powered-Up
Operation
108
August 20, 2009
IDT82P2282
4.4
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
MICROPROCESSOR INTERFACE
4.4.1
SPI MODE
Pull the SPIEN pin to high, and the microprocessor interface will be
set in SPI mode.
In this mode, only the CS, SCLK, SDI and SDO pins are interfaced
with the microprocessor. A falling transition on CS pin indicates the start
of a read/write operation, and a rising transition indicates the end of the
operation. After the CS pin is set to low, two bytes include instruction
and address bytes on the SDI pin is input to the device on the rising
edge of the SCLK pin. First byte consists of one instruction bit at MSB
and three address bits at LSB, the second byte is low 8 address bits. If
the MSB is ‘1’, it is read operation. If the MSB is ‘0’, it is write operation.
If the device is in read operation, the data read from the specified register is output on the SDO pin on the falling edge of the SCLK (refer to
Figure 39). If the device is in write operation, the data written to the
specified register is input on the SDI pin following the address byte (refer
to Figure 40).
The microprocessor interface provides access to read and write the
registers in the device. The interface consists of Serial Peripheral Interface (SPI) and parallel microprocessor interface.
CS
1
0
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Instruction
Register Address
X
SDI
X
X A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
High Impedance
SDO
Don't Care
D7 D6 D5 D4 D3 D2 D1 D0
Figure 39. Read Operation In SPI Mode
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Instruction
SDI
SDO
Register Address
X
X
Data Byte
X A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
High Impedance
Figure 40. Write Operation In SPI Mode
Operation
109
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
4.4.2
PARALLEL MICROPROCESSOR INTERFACE
Pull the SPIEN pin to low, the microprocessor interface will be set in
parallel mode. In this mode, the interface is compatible with the Motorola
and the Intel microprocessor, which is selected by the MPM pin. The
IDT82P2282 uses separate address bus and data bus. The mode selection and the interfaced pin are tabularized in Table 80.
Table 80: Parallel Microprocessor Interface
Pin MPM
Microprocessor Interface
Interfaced Pin
Low
Motorola
CS, DS, RW, A[8:0], D[7:0]
High
Intel
CS, RD, WR, A[8:0], D[7:0]
Operation
110
August 20, 2009
IDT82P2282
4.5
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
INDIRECT REGISTER ACCESS SCHEME
- Read the indirect register data from the Access Data register.
An indirect register access request is completed within 4 µs.
In Receive CAS/RBS Buffer, Receive Payload Control and Transmit Payload Control blocks, per-channel/per-timeslot indirect register is
accessed by using an indirect register access scheme.
4.5.2
INDIRECT REGISTER WRITE ACCESS
The indirect register write access is as follows:
- Read the BUSY bit in the Access Status register to confirm the bit
is ‘0’;
- Write the Access Data register;
- Write the Access Control register to initiate the write operation and
specify the indirect register address.
An indirect register access request is completed within 4 µs.
4.5.1
INDIRECT REGISTER READ ACCESS
The indirect register read access is as follows:
- Read the BUSY bit in the Access Status register to confirm the bit
is ‘0’;
- Write the Access Control register to initiate the read operation and
specify the indirect register address;
- Read the BUSY bit in the Access Status register again to confirm
the bit is ‘0’;
Table 81: Related Bit / Register In Chapter 4
Bit
Register
Address (Hex)
T1/J1
FM[1:0]
TEMODE
R_OFF
T_OFF
BUSY
RWN
ADDRESS[6:0]
D[7:0]
Software Reset
004
T1/J1 Or E1 Mode
020, 120
Receive Configuration 0
Transmit Configuration 0
TPLC Access Status / RPLC Access Status / RCRB Access Status
028, 128
022, 122
0C8, 1C8 / 0CD, 1CD / 0D3, 1D3
TPLC Access Control / RPLC Access Control
/ RCRB Access Control
0C9, 1C9 / 0CE, 1CE / 0D4, 1D4
TPLC Access Data / RPLC Access Data / RCRB Access Data
0CA, 1CA / 0CF, 1CF / 0D5, 1D5, 2D5, 3D5
Operation
111
August 20, 2009
IDT82P2282
5
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
PROGRAMMING INFORMATION
5.1
REGISTER MAP
In the ‘Reg’ column, the ‘X’ represents 0 ~ 1, corresponding to the two links.
5.1.1
5.1.1.1
T1/J1 MODE
Direct Register
T1/J1 Reg
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Name
000
001 ~ 003
004
005
006
007
008
009
00A
00B
00C ~ 00D
00E
00F
010
ID7
DAT7
-
ID6
DAT6
-
ID5
LINKSEL0
DAT5
-
ID4
DAT4
RSLVCK
ID3
MON3
RO20
ADDR3
DAT3
RMUX
ID2
LEVEL0
ADDR2
DAT2
-
ID1
INT2
ADDR1
DAT1
TSLVCK
ID0
MON0
DIR0
RO10
INT1
TMOVE
TMOVI
ADDR0
DAT0
TMUX
011 ~ 01F
X20
X21
-
-
T1/J1
TJA_E
FM1
TJA_DP1
FM0
TJA_DP0
TEMODE
TJA_BW
X22
X23
X24
X25
X26
X27
DONE
-
RW
WDAT6
-
PULS3
SCAL3
SAMP3
WDAT3
RJA_E
PULS2
SCAL2
SAMP2
WDAT2
RJA_DP1
PULS1
SCAL1
SAMP1
WDAT1
RJA_DP0
T_MD
PULS0
SCAL0
SAMP0
WDAT0
RJA_BW
X28
X29
X2A
X2B
-
EQ_ON
DLLP
LOS3
UPDW1
-
LOS2
UPDW0
RLP
LOS1
MG1
ALP
R_MD
LOS0
MG0
DLP
X2C
-
-
-
-
LAC
RAISE
ATAO
X2D ~ X30
X31
-
BPV_INS
-
EXZ_DEF EXZ_ERR1 EXZ_ERR0
CNT_MD
CNT_TRF
X32
-
-
T_TERM2
T_TERM1
T_TERM0
R_TERM2
R_TERM1 R_TERM0
X33
-
-
-
-
-
DF_IE
Chip ID For Dual Transceiver
Reserved
Software Reset
G.772 Monitor Control
GPIO Control
Reference Clock Output Select
Reserved
Interrupt Requisition Link ID
Timer Interrupt Control
Timer Interrupt Indication
Reserved
PMON Access Port
PMON Access Data
Backplane Global Configuration
Reserved
T1/J1 Or E1 Mode
Transmit Jitter Attenuation
Configuration
Transmit Configuration 0
Transmit Configuration 1
Transmit Configuration 2
Transmit Configuration 3
Transmit Configuration 4
Receive Jitter Attenuation Configuration
Receive Configuration 0
Receive Configuration 1
Receive Configuration 2
Maintenance Function Control
0
Maintenance Function Control
1
Reserved
Maintenance Function Control
2
Transmit And Receive Termination Configuration
Interrupt Enable Control 0
Programming Information
TJITT_TES TJA_LIMT
T
T_OFF
DFM_ON
T_HZ
SCAL5
SCAL4
UI1
UI0
WDAT5
WDAT4
RJITT_TES RJA_LIMT
T
R_OFF
LOS4
SLICE1
SLICE0
SLLP
SRLP
-
112
-
LOS_IE
Reference
Page
P 126
P 126
P 127
P 128
P 129
P 130
P 130
P 130
P 131
P 131
P 132
P 125
P 133
P 134
P 135
P 136
P 137
P 138
P 138
P 139
P 140
P 141
P 142
P 143
P 144
P 145
P 145
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Reg
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Name
X34
X35
X36
X37
X38
-
DAC_IE
TJITT6
TJA_IE
TJITT5
RJA_IE
LATT4
TJITT4
LATT3
TJITT3
EXZ_IE
DF_IES
DF_S
LATT2
TJITT2
CV_IE
LATT1
TJITT1
CNT_IE
LOS_IES
LOS_S
LATT0
TJITT0
X39
-
RJITT6
RJITT5
RJITT4
RJITT3
RJITT2
RJITT1
RJITT0
X3A
X3B
X3C
X3D
X3E
CNTH[7]
CNTL[7]
-
DAC_IS
CNTH[6]
CNTL[6]
-
TJA_IS
CNTH[5]
CNTL[5]
-
RJA_IS
CNTH[4]
CNTL[4]
-
CNTH[3]
CNTL[3]
-
DF_IS
EXZ_IS
CNTH[2]
CNTL[2]
-
CV_IS
CNTH[1]
CNTL[1]
-
LOS_IS
CNTOV_IS
CNTH[0]
CNTL[0]
REFH_LOS
X3F
X40
X41
X42
X43
X44
X45
X46
X47
X48
X49
X4A
X4B
X4C
X4D
X4E
X4F
X50
X51
X52
X53
X54 ~ X55
X56
X57
X58
X59 ~ X5B
X5C
X5D
X5E ~ X61
X62
X63 ~ X64
X65
X66
X67
IBCD
THDLC3
C8
-
RBOC
THDLC2
TSOFF6
TSOFF6
C7
-
C8
-
C7
-
ALARM
PMON
THDLC1
RHDLC3
FBITGAP
DE
TSOFF5
TSOFF4
FBITGAP
FSINV
TSOFF5
TSOFF4
RMFBE
EXCRCERI MIMICI
RMFBI
C6
C5
M3
M2
S4
S3
SCDEB
C6
C5
M3
M2
S4
S3
PRGD
RHDLC2
FE
TSOFF3
EDGE
DE
TSOFF3
EDGE
UNFM
DDSC
SFEE
SFEI
C4
M1
S2
SCAE
SCAI
C4
M1
S2
RCRB
RHDLC1
CMS
MAP1
TSOFF2
BOFF2
FE
MAP1
TSOFF2
BOFF2
REFCRCE
MIMICC
BEEE
BEEI
C3
C11
S1
SCSE
SCSI
FDLBYP
C3
C11
S1
FGEN
ELST
FSINV
MAP0
TSOFF1
BOFF1
CMS
MAP0
CMFS
TSOFF1
BOFF1
RCOFAI
RCOFAE
REFEN
M2O1
FERE
FERI
C2
C10
A2
SCME
SCMI
CRCBYP
C2
C10
A2
LIU
FRMR
TRSI/RESI
FSTYP
TMODE
TSOFF0
BOFF0
TRI
RMODE
ALTFIS
TSOFF0
BOFF0
TCOFAI
TCOFAE
REFR
M2O0
OOFV
OOFE
COFAE
OOFI
COFAI
C1
C9
A1
SCCE
SCCI
FDIS
C1
C9
A1
Interrupt Enable Control 1
Interrupt Trigger Edges Select
Line Status Register 0
Line Status Register 1
Transmit Jitter Measure Value
Indication
Receive Jitter Measure Value
Indication
Interrupt Status 0
Interrupt Status 1
EXZ Error Counter H-Byte
EXZ Error Counter L-Byte
T1/J1 Reference Clock Output
Control
Interrupt Module Indication 2
Interrupt Module Indication 0
Interrupt Module Indication 1
TBIF Option Register
TBIF Operating Mode
TBIF TS Offset
TBIF Bit Offset
RBIF Option Register
RBIF Mode
RBIF Frame Pulse
RBIF TS Offset
RBIF Bit Offset
RTSFS Change Indication
RTSFS Interrupt Control
FRMR Mode 0
FRMR Mode 1
FRMR Status
FRMR Interrupt Control 0
FRMR Interrupt Control 1
FRMR Interrupt Indication 0
FRMR Interrupt Indication 1
Reserved
RDL0
RDL1
RDL2
Reserved
DLB Interrupt Control
DLB Interrupt Indication
Reserved
T1/J1 Mode
Reserved
XDL0
XDL1
XDL2
Programming Information
113
Reference
Page
P 146
P 147
P 147
P 148
P 149
P 149
P 150
P 151
P 152
P 152
P 152
P 153
P 154
P 155
P 156
P 157
P 158
P 158
P 159
P 160
P 161
P 162
P 162
P 163
P 163
P 164
P 165
P 166
P 166
P 167
P 168
P 169
P 170
P 170
P 171
P 172
P 173
P 174
P 175
P 175
P 176
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Reg
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
X68 ~ X6A
X6B
-
-
-
-
-
-
X6C
X6D
X6E
X6F
X70
X71
X72
X73
X74
X75
X76
X77
X78
X79
X7A
X7B
X7C
X7D
X7E
X7F
X80
X81
X82
X83
X84
X85
X86
X87
X88
X89
X8A
X8B
X8C
X8D
X8E
X8F
X90
X91
X92
X93
X94
X95
X96
X97
Bit 1
Bit 0
Reference
Page
Register Name
Reserved
AUTOYELXYEL
FGEN Maintenance 0
LOW
MIMICEN COFAEN
TXDIS
TAIS
FGEN Maintenance 1
MFE
BFE
FGEN Interrupt Control
MFI
BFI
FGEN Interrupt Indication
DDSINV
CRCINV
FsINV
FtINV
Error Insertion
XTS
Transmit Timing Option
RINV
TINV
PATS1
PATS0 PRGD Control
BERE
INV
SYNCV
SYNCE PRGD Status/Error Control
BERI
SYNCI PRGD Interrupt Indication
IBCDEN IBCDUNFM
CL1
CL0
XIBC Control
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
XIBC Code
IBCDIDLE
DSEL1
DSEL0
ASEL1
ASEL0 IBCD Detector Configuration
LBA
LBD
IBCD Detector Status
ACT7
ACT6
ACT5
ACT4
ACT3
ACT2
ACT1
ACT0
IBCD Activate Code
DACT7
DACT6
DACT5
DACT4
DACT3
DACT2
DACT1
DACT0 IBCD Deactivate Code
LBAE
LBDE
IBCD Interrupt Control
LBAI
LBDI
IBCD Interrupt Indication
TRKEN
SLIPD
SLIPE ELST Configuration
SLIPI
ELST Interrupt Indication
TRKCODE TRKCODE TRKCODE TRKCODE TRKCODE TRKCODE2 TRKCODE TRKCODE ELST Trunk Code
7
6
5
4
3
1
0
LBBIT
U2BIT
U1BIT
RBIT
CRBIT
AUTOPRM APRM Control
XBOC5
XBOC4
XBOC3
XBOC2
XBOC1
XBOC0 XBOC Code
AVC
BOCE BOC Control
BOCI
BOC Interrupt Indication
BOC5
BOC4
BOC3
BOC2
BOC1
BOC0 RBOC Code
TDLEN3
TDLEN2
TDLEN1 THDLC Enable Control
Reserved
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
THDLC2 Assignment
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
THDLC3 Assignment
Reserved
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0 THDLC2 Bit Select
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0 THDLC3 Bit Select
RDLEN3
RDLEN2
RDLEN1 RHDLC Enable Control
Reserved
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
RHDLC2 Assignment
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
RHDLC3 Assignment
Reserved
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0 RHDLC2 Bit Select
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0 RHDLC3 Bit Select
ADRM1
ADRM0
RHDLCM
RRST RHDLC1 Control Register
ADRM1
ADRM0
RHDLCM
RRST RHDLC2 Control Register
ADRM1
ADRM0
RHDLCM
RRST RHDLC3 Control Register
EMP
PACK
RHDLC1 RFIFO Access Status
EMP
PACK
RHDLC2 RFIFO Access Status
EMP
PACK
RHDLC3 RFIFO Access Status
Programming Information
114
P 176
P 177
P 178
P 178
P 179
P 180
P 180
P 181
P 181
P 182
P 182
P 183
P 184
P 184
P 184
P 185
P 185
P 186
P 186
P 186
P 187
P 188
P 188
P 189
P 189
P 190
P 191
P 191
P 192
P 192
P 193
P 194
P 194
P 195
P 195
P 196
P 196
P 196
P 197
P 197
P 197
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Reg
(Hex)
Bit 7
X98
X99
X9A
X9B
X9C
X9D
X9E
X9F
XA0
XA1
XA2
XA3
XA4
XA5
XA6
XA7
XA8
XA9
XAA
XAB
XAC
XAD
XAE
XAF
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
XB8
XB9
XBA
XBB
XBC
XBD
XBE
XBF
XC0
XC1
XC2
XC3
XC4
XC5
XC6
DAT7
DAT7
DAT7
HA7
HA7
HA7
LA7
LA7
LA7
DAT7
DAT7
DAT7
REDDTH7
REDCTH7
YELDTH7
YELCTH7
AISDTH7
AISCTH7
PRDGOVE
PRDGOVI
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reference
Page
Register Name
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
RHDLC1 Data
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
RHDLC2 Data
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
RHDLC3 Data
OVFLE
RMBEE RHDLC1 Interrupt Control
OVFLE
RMBEE RHDLC2 Interrupt Control
OVFLE
RMBEE RHDLC3 Interrupt Control
OVFLI
RMBEI RHDLC1 Interrupt Indication
OVFLI
RMBEI RHDLC2 Interrupt Indication
OVFLI
RMBEI RHDLC3 Interrupt Indication
HA6
HA5
HA4
HA3
HA2
HA1
HA0
RHDLC1 High Address
HA6
HA5
HA4
HA3
HA2
HA1
HA0
RHDLC2 High Address
HA6
HA5
HA4
HA3
HA2
HA1
HA0
RHDLC3 High Address
LA6
LA5
LA4
LA3
LA2
LA1
LA0
RHDLC1 Low Address
LA6
LA5
LA4
LA3
LA2
LA1
LA0
RHDLC2 Low Address
LA6
LA5
LA4
LA3
LA2
LA1
LA0
RHDLC3 Low Address
EOM
ABORT
THDLCM
TRST
THDLC1 Control
EOM
ABORT
THDLCM
TRST
THDLC2 Control
EOM
ABORT
THDLCM
TRST
THDLC3 Control
LL1
LL0
HL1
HL0
TFIFO1 Threshold
LL1
LL0
HL1
HL0
TFIFO2 Threshold
LL1
LL0
HL1
HL0
TFIFO3 Threshold
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
THDLC1 Data
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
THDLC2 Data
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
THDLC3 Data
FUL
EMP
RDY
TFIFO1 Status
FUL
EMP
RDY
TFIFO2 Status
FUL
EMP
RDY
TFIFO3 Status
UDRUNE
RDYE THDLC1 Interrupt Control
UDRUNE
RDYE THDLC2 Interrupt Control
UDRUNE
RDYE THDLC3 Interrupt Control
UDRUNI
RDYI
THDLC1 Interrupt Indication
UDRUNI
RDYI
THDLC2 Interrupt Indication
UDRUNI
RDYI
THDLC3 Interrupt Indication
AIS
YEL
RED
Alarm Status
AISE
YELE
REDE Alarm Control
AISI
YELI
REDI
Alarm Indication
REDDTH6 REDDTH5 REDDTH4 REDDTH3 REDDTH2 REDDTH1 REDDTH0 RED Declare Threshold
REDCTH6 REDCTH5 REDCTH4 REDCTH3 REDCTH2 REDCTH1 REDCTH0 RED Clear Threshold
YELDTH6 YELDTH5 YELDTH4 YELDTH3 YELDTH2 YELDTH1 YELDTH0 Yellow Declare Threshold
YELCTH6 YELCTH5 YELCTH4 YELCTH3 YELCTH2 YELCTH1 YELCTH0 Yellow Clear Threshold
AISDTH6 AISDTH5 AISDTH4 AISDTH3 AISDTH2 AISDTH1 AISDTH0 AIS Declare Threshold
AISCTH6 AISCTH5 AISCTH4 AISCTH3 AISCTH2 AISCTH1 AISCTH0 AIS Clear Threshold
UPDAT AUTOUPD PMON Control
DDSOVE COFAOVE OOFOVE FEROVE CRCOVE PMON Interrupt Control 0
LCVOVE PMON Interrupt Control 1
DDSOVI/ COFAOVI OOFOVI
FEROVI
CRCOVI PMON Interrupt Indication 0
LCVOVI PMON Interrupt Indication 1
Programming Information
115
P 198
P 198
P 198
P 199
P 199
P 199
P 200
P 200
P 200
P 201
P 201
P 201
P 202
P 202
P 202
P 203
P 203
P 203
P 204
P 204
P 204
P 205
P 205
P 205
P 206
P 206
P 206
P 207
P 207
P 207
P 208
P 208
P 208
P 209
P 210
P 210
P 211
P 211
P 212
P 212
P 213
P 213
P 214
P 215
P 215
P 216
P 216
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Reg
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
XC7
-
-
-
-
XC8
XC9
RWN
XCA
XCB
XCC
XCD
XCE
D7
SIGSNAP
RWN
XCF
XD0
XD1
XD2
XD3
XD4
D7
SIGSNAP
RWN
XD5
XD6
D7
COSI8
XD7
COSI16
COSI15
COSI14
COSI13
COSI12
COSI11
COSI10
COSI9
XD8
COSI24
COSI23
COSI22
COSI21
COSI20
COSI19
COSI18
COSI17
Bit 3
PRBSMOD
E1
ADDRESS ADDRESS ADDRESS ADDRESS
6
5
4
3
D6
D5
D4
D3
GSTRKEN
ZCS2
ZCS1
ZCS0
ABXX
ADDRESS ADDRESS ADDRESS ADDRESS
6
5
4
3
D6
D5
D4
D3
GSTRKEN
ABXX
FREEZE
ADDRESS ADDRESS ADDRESS ADDRESS
6
5
4
3
D6
D5
D4
D3
COSI7
COSI6
COSI5
COSI4
Programming Information
Bit 2
Bit 1
Bit 0
PRBSMOD PRBSDIR TESTEN
E0
BUSY
ADDRESS2 ADDRESS ADDRESS
1
0
D2
D1
D0
GSUBST2 GSUBST1 GSUBST0
PCCE
BUSY
ADDRESS2 ADDRESS ADDRESS
1
0
D2
D1
D0
GSUBST2 GSUBST1 GSUBST0
SIGFIX
POL
PCCE
DEB
SIGE
SIGF
BUSY
ADDRESS2 ADDRESS ADDRESS
1
0
D2
D1
D0
COSI3
COSI2
COSI1
116
Reference
Page
Register Name
TPLC / RPLC / PRGD Test
Configuration
TPLC Access Status
TPLC Access Control
P 217
P 218
P 218
TPLC Access Data
TPLC Configuration
TPLC Control Enable
RPLC Access Status
RPLC Access Control
P 218
P 219
P 220
P 221
P 221
RPLC Access Data
RPLC Configuration
RPLC Control Enable
RCRB Configuration
RCRB Access Status
RCRB Access Control
P 221
P 222
P 223
P 224
P 225
P 225
RCRB Access Data
RCRB State Change Indication
0
RCRB State Change Indication
1
RCRB State Change Indication
2
P 225
P 226
P 226
P 226
August 20, 2009
IDT82P2282
5.1.1.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Indirect Register
PMON
Address (Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
Reference Page
00
01
02
03
04
05
06
07
08
09
0A
0B
CRCE7
FER7
PRGD7
PRGD15
LCV7
LCV15
DDSE7
-
CRCE6
FER6
PRGD6
PRGD14
LCV6
LCV14
DDSE6
-
CRCE5
FER5
PRGD5
PRGD13
LCV5
LCV13
DDSE5
-
CRCE4
FER4
OOF4
PRGD4
PRGD12
LCV4
LCV12
DDSE4
-
CRCE3
FER3
FER11
OOF3
PRGD3
PRGD11
LCV3
LCV11
DDSE3
-
CRCE2
FER2
FER10
COFA2
OOF2
PRGD2
PRGD10
LCV2
LCV10
DDSE2
-
CRCE1
CRCE9
FER1
FER9
COFA1
OOF1
PRGD1
PRGD9
LCV1
LCV9
DDSE1
DDSE9
CRCE0
CRCE8
FER0
FER8
COFA0
OOF0
PRGD0
PRGD8
LCV0
LCV8
DDSE0
DDSE8
CRCE Counter Mapping 0
CRCE Counter Mapping 1
FER Counter Mapping 0
FER Counter Mapping 1
COFA Counter Mapping
OOF Counter Mapping
PRGD Counter Mapping 0
PRGD Counter Mapping 1
LCV Counter Mapping 0
LCV Counter Mapping 1
DDSE Counter Mapping 0
DDSE Counter Mapping 1
P 227
P 227
P 228
P 228
P 229
P 229
P 230
P 230
P 231
P 231
P 232
P 232
Address (Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
Reference Page
01 ~ 18
-
-
-
EXTRACT
A
B
C
D
Extracted Signaling Data/Extract
Enable Register for CH1 ~ CH24
P 233
Address (Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01 ~ 18
SUBST2
SUBST1
SUBST0
SINV
OINV
EINV
G56K
GAP
21 ~ 38
DTRK7
DTRK6
DTRK5
DTRK4
DTRK3
DTRK2
DTRK1
41 ~ 58
-
TEST
-
STRKEN
A
B
C
Address (Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
Reference Page
01 ~ 18
SUBST2
SUBST1
SUBST0
SINV
OINV
EINV
G56K
GAP
P 237
21 ~ 38
DTRK7
DTRK6
DTRK5
DTRK4
DTRK3
DTRK2
DTRK1
DTRK0
41 ~ 58
-
TEST
SIGINS
STRKEN
A
B
C
D
Channel Control Register for CH1
~ CH24
Data Trunk Conditioning Code
Register for CH1 ~ CH24
Signaling Trunk Conditioning
Code Register for CH1 ~ CH24
RCRB
RPLC
Register
Channel Control Register for CH1
~ CH24
DTRK0
Data Trunk Conditioning Code
Register for CH1 ~ CH24
D
Signaling Trunk Conditioning Code
Register for CH1 ~ CH24
Reference Page
P 234
P 235
P 236
TPLC
Programming Information
117
P 238
P 239
August 20, 2009
IDT82P2282
5.1.2
5.1.2.1
E1 Reg
(Hex)
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 MODE
Direct Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ID7
-
ID6
-
ID5
-
ID4
-
ID3
-
ID2
-
ID1
-
ID0
-
-
-
-
-
MON3
RO20
-
LEVEL0
-
INT2
-
DAT7
-
DAT6
-
LINKSEL0
DAT5
-
DAT4
RSLVCK
-
ADDR3
DAT3
RMUX
-
ADDR2
DAT2
-
ADDR1
DAT1
TSLVCK
-
-
-
T1/J1
TJA_E
FM1
TJA_DP1
FM0
TJA_DP0
X22
X23
X24
X25
X26
X27
DONE
-
RW
WDAT6
-
PULS3
SCAL3
SAMP3
WDAT3
RJA_E
PULS2
SCAL2
SAMP2
WDAT2
RJA_DP1
PULS1
SCAL1
SAMP1
WDAT1
RJA_DP0
X28
X29
X2A
X2B
X2C
X2D ~
X30
X31
X32
-
EQ_ON
DLLP
-
LOS3
UPDW1
-
LOS2
UPDW0
RLP
LAC
-
LOS1
MG1
ALP
RAISE
-
-
BPV_INS
-
T_TERM2
X33
X34
X35
X36
X37
-
DAC_IE
-
TJA_IE
-
000
001 ~
003
004
005
006
007
008
009
00A
00B
00C ~
00D
00E
00F
010
011 ~
01F
X20
X21
Programming Information
TJITT_TES TJA_LIMT
T
T_OFF
DFM_ON
T_HZ
SCAL5
SCAL4
UI1
UI0
WDAT5
WDAT4
RJITT_TES RJA_LIMT
T
R_OFF
LOS4
SLICE1
SLICE0
SLLP
SRLP
-
EXZ_DEF EXZ_ERR1 EXZ_ERR0 CNT_MD
T_TERM1 T_TERM0 R_TERM2 R_TERM1
RJA_IE
LATT4
LATT3
DF_IE
EXZ_IE
DF_IES
DF_S
LATT2
118
CV_IE
LATT1
Reference
Page
Register Name
Chip ID For Dual Transceiver
Reserved
P 240
-
MON0
DIR0
RO10
INT1
TMOVE
TMOVI
-
Software Reset
G.772 Monitor Control
GPIO Control
Reference Clock Output Select
Reserved
Interrupt Requisition Link ID
Timer Interrupt Control
Timer Interrupt Indication
Reserved
P 240
P 241
P 242
P 243
P 244
P 244
P 244
-
ADDR0
DAT0
TMUX
-
PMON Access Port
PMON Access Data
Backplane Global Configuration
Reserved
P 245
P 245
P 246
-
TEMODE T1/J1 Or E1 Mode
TJA_BW Transmit Jitter Attenuation Configuration
T_MD
Transmit Configuration 0
PULS0 Transmit Configuration 1
SCAL0 Transmit Configuration 2
SAMP0 Transmit Configuration 3
WDAT0 Transmit Configuration 4
RJA_BW Receive Jitter Attenuation Configuration
R_MD
Receive Configuration 0
LOS0
Receive Configuration 1
MG0
Receive Configuration 2
DLP
Maintenance Function Control 0
ATAO
Maintenance Function Control 1
Reserved
P 125
P 247
CNT_TRF Maintenance Function Control 2
R_TERM0 Transmit And Receive Termination Configuration
LOS_IE Interrupt Enable Control 0
CNT_IE Interrupt Enable Control 1
LOS_IES Interrupt Trigger Edges Select
LOS_S Line Status Register 0
LATT0
Line Status Register 1
P 248
P 249
P 250
P 251
P 252
P 253
P 254
P 255
P 256
P 257
P 258
P 259
P 260
P 260
P 261
P 262
P 262
P 263
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Reg
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Name
X38
-
TJITT6
TJITT5
TJITT4
TJITT3
TJITT2
TJITT1
TJITT0
X39
-
RJITT6
RJITT5
RJITT4
RJITT3
RJITT2
RJITT1
RJITT0
X3A
X3B
X3C
X3D
X3E
CNTH[7]
CNTL[7]
-
DAC_IS
CNTH[6]
CNTL[6]
-
TJA_IS
CNTH[5]
CNTL[5]
-
RJA_IS
CNTH[4]
CNTL[4]
-
CNTH[3]
CNTL[3]
-
DF_IS
EXZ_IS
CNTH[2]
CNTL[2]
-
CV_IS
CNTH[1]
CNTL[1]
-
LOS_IS
CNTOV_IS
CNTH[0]
CNTL[0]
REFH_LOS
X3F
X40
X41
X42
X43
X44
X45
X46
X47
X48
X49
X4A
X4B
X4C
X4D
X4E
X4F
X50
X51
X52
X53
X54
X55
X56
X57
X58
X59
X5A
X5B
X5C
X5D
THDLC3
BIT2C
ISMFPE
ISMFPI
Si0
Sa6SYN
-
ALARM
PMON
PRGD
RCRB
THDLC2
THDLC1
RHDLC3
RHDLC2
RHDLC1
DE
FE
CMS
TSOFF6
TSOFF5
TSOFF4
TSOFF3
TSOFF2
EDGE
BOFF2
DE
FE
FSINV
OHD
SMFS
TSOFF6
TSOFF5
TSOFF4
TSOFF3
TSOFF2
EDGE
BOFF2
UNFM
REFCRCE
CASEN
CRCEN
CNTNFAS WORDERR TS16C
C2NCIWV OOSMFV OOCMFV
C2NCIWE OOSMFE OOCMFE
ICSMFPE SMFERE
ICMFPE
CMFERE
CRCEE
EXCRCERI C2NCIWI
OOSMFI
OOCMFI
ICSMFPI
SMFERI
ICMFPI
CMFERI
CRCEI
Si1
A
Sa4
Sa5
Sa6
X0
Y
Sa41
Sa42
Sa51
Sa52
Sa61
Sa62
Sa71
Sa72
Sa81
Sa82
Sa6-FI
Sa6-EI
Sa6-CI
SaDEB
Sa6SCE
Sa4E
Sa5E
Sa6E
Sa6SCI
Sa4I
Sa5I
Sa6I
FGEN
ELST
FSINV
TSOFF1
BOFF1
CMS
CMFS
TSOFF1
BOFF1
RCOFAI
RCOFAE
REFEN
SMFASC
OOOFV
OOOFE
FERE
OOOFI
FERI
Sa7
X1
Sa43
Sa53
Sa63
Sa73
Sa83
Sa6-AI
Sa7E
Sa7I
LIU
FRMR
TRSI/RESI
FSTYP
TMODE
TSOFF0
BOFF0
TRI
RMODE
TSOFF0
BOFF0
TCOFAI
TCOFAE
REFR
C2NCIWCK
OOFV
OOFE
COFAE
OOFI
COFAI
Sa8
X2
Sa44
Sa54
Sa64
Sa74
Sa84
Sa6-8I
Sa8E
Sa8I
X5E
X5F
X60
X61
X62
X63
-
CFEBEV
CFEBEE
CFEBEI
GENCRC
Si0
V52LINKV
V52LINKE
V52LINKI
FDIS
Si1
Transmit Jitter Measure Value
Indication
Receive Jitter Measure Value
Indication
Interrupt Status 0
Interrupt Status 1
EXZ Error Counter H-Byte
EXZ Error Counter L-Byte
E1 Reference Clock Output
Control
Interrupt Module Indication 2
Interrupt Module Indication 0
Interrupt Module Indication 1
TBIF Option Register
TBIF Operating Mode
TBIF TS Offset
TBIF Bit Offset
RBIF Option Register
RBIF Mode
RBIF Frame Pulse
RBIF TS Offset
RBIF Bit Offset
RTSFS Change Indication
RTSFS Interrupt Control
FRMR Mode 0
FRMR Mode 1
FRMR Status
FRMR Interrupt Control 0
FRMR Interrupt Control 1
FRMR Interrupt Indication 0
FRMR Interrupt Indication 1
TS0 International / National
TS16 Spare
Sa4 Codeword
Sa5 Codeword
Sa6 Codeword
Sa7 Codeword
Sa8 Codeword
Sa6 Codeword Indication
Sa Codeword Interrupt Control
Sa Codeword Interrupt Indication
Reserved
Overhead Error Status
Overhead Interrupt Control
Overhead Interrupt Indication
E1 Mode
FGEN International Bit
XDIS
-
Programming Information
TCRCEE
TCRCEI
SiDIS
-
TFEBEE
TFEBEI
FEBEDIS
-
FEBEE
FEBEI
CRCM
-
RAICRCV
RAICRCE
RAICRCI
SIGEN
-
119
Reference
Page
P 264
P 264
P 265
P 266
P 267
P 267
P 267
P 268
P 268
P 269
P 270
P 271
P 272
P 272
P 273
P 274
P 274
P 275
P 275
P 276
P 276
P 277
P 278
P 279
P 280
P 281
P 282
P 283
P 284
P 285
P 285
P 286
P 286
P 287
P 287
P 288
P 289
P 290
P 291
P 292
P 293
P 294
P 295
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Reg
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X64
X65
X66
X67
X68
X69
X6A
X6B
-
-
TS16LOS
Sa4EN
TS16AIS
Sa5EN
Sa41
Sa51
Sa61
Sa71
Sa81
X0
MFAIS
Sa6EN
Sa42
Sa52
Sa62
Sa72
Sa82
G706RAI
Sa7EN
Sa43
Sa53
Sa63
Sa73
Sa83
X1
AUTOYELLOW
TXDIS
MFE
MFI
FASALLINV
PATS1
SYNCV
-
Sa8EN
Sa44
Sa54
Sa64
Sa74
Sa84
X2
REMAIS
Reference
Page
Register Name
FGEN Sa Control
Sa4 Code-word
Sa5 Code-word
Sa6 Code-word
Sa7 Code-word
Sa8 Code-word
FGEN Extra
FGEN Maintenance 0
P 296
P 297
P 297
P 297
P 298
P 298
P 298
P 299
X6C
COFAEN
TAIS
FGEN Maintenance 1
X6D
SMFE
FASE
SIGMFE
BFE
FGEN Interrupt Control
X6E
SMFI
FASI
SIGMFI
BFI
FGEN Interrupt Indication
X6F
CRCINV CRCPINV CASPINV NFASINV
FAS1INV Error Insertion
X70
XTS
Transmit Timing Option
X71
RINV
TINV
PATS0 PRGD Control
X72
BERE
INV
SYNCE PRGD Status/Error Control
X73
BERI
SYNCI PRGD Interrupt Indication
X74 ~
Reserved
X7B
X7C
TRKEN
SLIPD
SLIPE
ELST Configuration
X7D
SLIPI
ELST Interrupt Indication
X7E TRKCODE7 TRKCODE TRKCODE TRKCODE TRKCODE TRKCODE2 TRKCODE1 TRKCODE0 ELST Trunk Code
6
5
4
3
X7F ~
Reserved
X83
X84
TDLEN3
TDLEN2
TDLEN1 THDLC Enable Control
X85
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
THDLC1 Assignment
X86
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
THDLC2 Assignment
X87
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
THDLC3 Assignment
X88
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0 THDLC1 Bit Select
X89
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0 THDLC2 Bit Select
X8A
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0 THDLC3 Bit Select
X8B
RDLEN3
RDLEN2
RDLEN1 RHDLC Enable Control
X8C
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
RHDLC1 Assignment
X8D
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
RHDLC2 Assignment
X8E
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
RHDLC3 Assignment
X8F
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0 RHDLC1 Bit Select
X90
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0 RHDLC2 Bit Select
X91
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0 RHDLC3 Bit Select
X92
ADRM1
ADRM0
RHDLCM
RRST
RHDLC1 Control Register
X93
ADRM1
ADRM0
RHDLCM
RRST
RHDLC2 Control Register
X94
ADRM1
ADRM0
RHDLCM
RRST
RHDLC3 Control Register
X95
EMP
PACK
RHDLC1 RFIFO Access Status
X96
EMP
PACK
RHDLC2 RFIFO Access Status
X97
EMP
PACK
RHDLC3 RFIFO Access Status
X98
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
RHDLC1 Data
X99
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
RHDLC2 Data
X9A
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
RHDLC3 Data
Programming Information
120
P 300
P 301
P 302
P 303
P 304
P 304
P 305
P 305
P 306
P 306
P 306
P 307
P 308
P 308
P 308
P 309
P 309
P 309
P 310
P 311
P 311
P 311
P 312
P 312
P 312
P 313
P 313
P 313
P 313
P 314
P 314
P 315
P 315
P 315
August 20, 2009
IDT82P2282
E1 Reg
(Hex)
Bit 7
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Bit 6
X9B
X9C
X9D
X9E
X9F
XA0
XA1
HA7
HA6
XA2
HA7
HA6
XA3
HA7
HA6
XA4
LA7
LA6
XA5
LA7
LA6
XA6
LA7
LA6
XA7
XA8
XA9
XAA
XAB
XAC
XAD
DAT7
DAT6
XAE
DAT7
DAT6
XAF
DAT7
DAT6
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
XB8
XB9
XBA
XBB
XBC
XBD ~
XC1
XC2
XC3 PRDGOVE TFEBEOVE
XC4
XC5
PRDGOVI TFEBEOVI
XC6
XC7
XC8
XC9
XCA
XCB
XCC
Bit 5
Bit 4
HA5
HA4
HA5
HA4
HA5
HA4
LA5
LA4
LA5
LA4
LA5
LA4
EOM
EOM
EOM
DAT5
DAT4
DAT5
DAT4
DAT5
DAT4
TS16LOSV TS16AISV
TS16LOSE TS16AISE
TS16LOSI TS16AISI
-
Bit 3
Bit 2
Bit 1
Bit 0
HA3
HA3
HA3
LA3
LA3
LA3
LL1
LL1
LL1
DAT3
DAT3
DAT3
RMAIV
RMAIE
RMAII
-
HA2
HA2
HA2
LA2
LA2
LA2
ABORT
ABORT
ABORT
LL0
LL0
LL0
DAT2
DAT2
DAT2
FUL
FUL
FUL
AIS
AISE
AISI
-
OVFLE
OVFLE
OVFLE
OVFLI
OVFLI
OVFLI
HA1
HA1
HA1
LA1
LA1
LA1
THDLCM
THDLCM
THDLCM
HL1
HL1
HL1
DAT1
DAT1
DAT1
EMP
EMP
EMP
UDRUNE
UDRUNE
UDRUNE
UDRUNI
UDRUNI
UDRUNI
RAIV
RAIE
RAII
AISC
-
RMBEE
RMBEE
RMBEE
RMBEI
RMBEI
RMBEI
HA0
HA0
HA0
LA0
LA0
LA0
TRST
TRST
TRST
HL0
HL0
HL0
DAT0
DAT0
DAT0
RDY
RDY
RDY
RDYE
RDYE
RDYE
RDYI
RDYI
RDYI
RED
REDE
REDI
RAIC
-
FEBEOVE TCRCOVE COFAOVE
FEBEOVI TCRCOVI COFAOVI
PRBSMOD
E1
RWN
ADDRESS6 ADDRESS5 ADDRESS4 ADDRESS3
D7
D6
D5
D4
D3
SIGSNAP GSTRKEN
-
Programming Information
Reference
Page
Register Name
RHDLC1 Interrupt Control
RHDLC2 Interrupt Control
RHDLC3 Interrupt Control
RHDLC1 Interrupt Indication
RHDLC2 Interrupt Indication
RHDLC3 Interrupt Indication
RHDLC1 High Address
RHDLC2 High Address
RHDLC3 High Address
RHDLC1 Low Address
RHDLC2 Low Address
RHDLC3 Low Address
THDLC1 Control
THDLC2 Control
THDLC3 Control
TFIFO1 Threshold
TFIFO2 Threshold
TFIFO3 Threshold
THDLC1 Data
THDLC2 Data
THDLC3 Data
TFIFO1 Status
TFIFO2 Status
TFIFO3 Status
THDLC1 Interrupt Control
THDLC2 Interrupt Control
THDLC3 Interrupt Control
THDLC1 Interrupt Indication
THDLC2 Interrupt Indication
THDLC3 Interrupt Indication
Alarm Status
Alarm Control
Alarm Indication
Alarm Criteria Control
Reserved
UPDAT
AUTOUPD PMON Control
OOFOVE
FEROVE
CRCOVE PMON Interrupt Control 0
LCVOVE PMON Interrupt Control 1
OOFOVI
FEROVI
CRCOVI PMON Interrupt Indication 0
LCVOVI PMON Interrupt Indication 1
PRBSMOD PRBSDIR
TESTEN TPLC / RPLC / PRGD Test ConE0
figuration
BUSY
TPLC Access Status
ADDRESS2 ADDRESS1 ADDRESS0 TPLC Access Control
D2
D1
D0
TPLC Access Data
GSUBST2 GSUBST1 GSUBST0 TPLC Configuration
PCCE
TPLC Control Enable
121
P 316
P 316
P 316
P 317
P 317
P 317
P 318
P 318
P 318
P 319
P 319
P 319
P 320
P 320
P 320
P 321
P 321
P 321
P 322
P 322
P 322
P 323
P 323
P 323
P 324
P 324
P 324
P 325
P 325
P 325
P 326
P 327
P 328
P 329
P 329
P 330
P 331
P 332
P 333
P 333
P 334
P 334
P 334
P 335
P 335
August 20, 2009
IDT82P2282
E1 Reg
(Hex)
XCD
XCE
XCF
XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7
XD8
XD9
Bit 7
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reference
Page
Register Name
BUSY
RPLC Access Status
RWN
ADDRESS6 ADDRESS5 ADDRESS4 ADDRESS3 ADDRESS2 ADDRESS1 ADDRESS0 RPLC Access Control
D7
D6
D5
D4
D3
D2
D1
D0
RPLC Access Data
SIGSNAP GSTRKEN
GSUBST2 GSUBST1 GSUBST0 RPLC Configuration
PCCE
RPLC Control Enable
FREEZE
DEB
SIGE
RCRB Configuration
BUSY
RCRB Access Status
RWN
ADDRESS6 ADDRESS5 ADDRESS4 ADDRESS3 ADDRESS2 ADDRESS1 ADDRESS0 RCRB Access Control
D7
D6
D5
D4
D3
D2
D1
D0
RCRB Access Data
COSI8
COSI7
COSI6
COSI5
COSI4
COSI3
COSI2
COSI1 RCRB State Change Indication
0
COSI16
COSI15
COSI14
COSI13
COSI12
COSI11
COSI10
COSI9 RCRB State Change Indication
1
COSI24
COSI23
COSI22
COSI21
COSI20
COSI19
COSI18
COSI17 RCRB State Change Indication
2
COSI30
COSI29
COSI28
COSI27
COSI26
COSI25 RCRB State Change Indication
3
Programming Information
122
P 336
P 336
P 336
P 337
P 338
P 338
P 339
P 339
P 339
P 340
P 340
P 341
P 341
August 20, 2009
IDT82P2282
5.1.2.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Indirect Register
PMON
Address (Hex)
Bit 7
Bit 6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
CRCE7
FER7
PRGD7
PRGD15
LCV7
LCV15
TCRCE7
FEBE7
TFEBE7
-
CRCE6
FER6
PRGD6
PRGD14
LCV6
LCV14
TCRCE6
FEBE6
TFEBE6
-
Bit 5
Bit 4
CRCE5 CRCE4
FER5
FER4
OOF4
PRGD5 PRGD4
PRGD13 PRGD12
LCV5
LCV4
LCV13
LCV12
TCRCE5 TCRCE4
FEBE5
FEBE4
TFEBE5 TFEBE4
-
Bit 3
Bit 2
Bit 1
Bit 0
Register
Reference Page
CRCE3
FER3
FER11
OOF3
PRGD3
PRGD11
LCV3
LCV11
TCRCE3
FEBE3
TFEBE3
-
CRCE2
FER2
FER10
COFA2
OOF2
PRGD2
PRGD10
LCV2
LCV10
TCRCE2
FEBE2
TFEBE2
-
CRCE1
CRCE9
FER1
FER9
COFA1
OOF1
PRGD1
PRGD9
LCV1
LCV9
TCRCE1
TCRCE9
FEBE1
FEBE9
TFEBE1
TFEBE9
CRCE0
CRCE8
FER0
FER8
COFA0
OOF0
PRGD0
PRGD8
LCV0
LCV8
TCRCE0
TCRCE8
FEBE0
FEBE8
TFEBE0
TFEBE8
CRCE Counter Mapping 0
CRCE Counter Mapping 1
FER Counter Mapping 0
FER Counter Mapping 1
COFA Counter Mapping
OOF Counter Mapping
PRGD Counter Mapping 0
PRGD Counter Mapping 1
LCV Counter Mapping 0
LCV Counter Mapping 1
TCRCE Counter Mapping 0
TCRCE Counter Mapping 1
FEBE Counter Mapping 0
FEBE Counter Mapping 1
TFEBE Counter Mapping 0
TFEBE Counter Mapping 1
P 342
P 342
P 343
P 343
P 344
P 344
P 345
P 345
P 346
P 346
P 347
P 347
P 348
P 348
P 349
P 349
RCRB
Address (Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
Reference Page
01 ~ 0F
-
-
-
EXTRACT
A
B
C
D
P 350
11 ~ 1F
-
-
-
EXTRACT
A
B
C
D
Extracted Signaling Data/Extract
Enable Register for TS1 ~ TS15
Extracted Signaling Data/Extract
Enable Register for TS17 ~ TS31
P 350
RPLC
Address (Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00 ~ 1F
SUBST2
SUBST1
SUBST0
SINV
OINV
EINV
G56K
GAP
20 ~ 3F
DTRK7
DTRK6
DTRK5
DTRK4
DTRK3
DTRK2
DTRK1
41 ~ 4F
-
TEST
-
STRKEN
A
B
C
51 ~ 5F
-
TEST
-
STRKEN
A
B
C
Programming Information
123
Register
Timeslot Control Register for TS0 ~
TS31
DTRK0
Data Trunk Conditioning Code
Register for TS0 ~ TS31
D
Signaling Trunk Conditioning Code
Register for TS1 ~ TS15
D
Signaling Trunk Conditioning Code
Register for TS17 ~ TS31
Reference Page
P 351
P 352
P 353
P 353
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TPLC
Address (Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SINV
OINV
EINV
G56K
GAP
00 ~ 1F
SUBST2 SUBST1 SUBST0
20 ~ 3F
DTRK7
DTRK6
DTRK5
DTRK4
DTRK3
DTRK2
DTRK1
41 ~ 4F
-
TEST
-
STRKEN
A
B
C
51 ~ 5F
-
TEST
-
STRKEN
A
B
C
Programming Information
124
Register
Timeslot Control Register for TS0
~ TS31
DTRK0
Data Trunk Conditioning Code
Register for TS0 ~ TS31
D
Signaling Trunk Conditioning Code
Register for TS1 ~ TS15
D
Signaling Trunk Conditioning Code
Register for TS17 ~ TS31
Reference Page
P 354
P 355
P 356
P 356
August 20, 2009
IDT82P2282
5.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
REGISTER DESCRIPTION
Depending on the operating mode, the registers are configured for T1/J1 or E1. Before setting any other registers, the operating mode should be
selected in registers 020H and 120H.
According to the access method, the registers can be divided into direct registers and indirect registers. In the direct registers, the registers can
be divided into global configuration registers and per-link configuration registers. The register with only one address following its name is the global
configuration register, and the register with a set of address (two addresses) following its name is the per-link configuration register.
T1/J1 Or E1 Mode (020H, 120H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
T1/J1
FM1
FM0
TEMODE
R/W
R/W
R/W
R/W
0
0
0
0
T1/J1:
This bit is valid when T1/J1 operating mode is selected by the corresponding TEMODE bit (b0, 020H,...). It selects the operating mode between
T1 and J1 for the current link.
= 0: T1 mode is selected.
= 1: J1 mode is selected.
FM[1:0]:
These two bits are valid when T1/J1 operating mode is selected by the corresponding TEMODE bit (b0, 020H,...). They select the operating format.
= 00: SF format is selected.
= 01: ESF format is selected.
= 10: T1 DM format is selected. This selection is valid in T1 operating mode only.
= 11: SLC-96 format is selected. This selection is valid in T1 operating mode only.
TEMODE:
This bit selects the operating mode for the current link.
= 0: E1 mode is selected.
= 1: T1/J1 mode is selected.
Programming Information
125
August 20, 2009
IDT82P2282
5.2.1
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 MODE
5.2.1.1
Direct Register
T1/J1 Chip ID For Dual Transceiver (000H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Type
R
R
R
R
R
R
R
R
Default
0
1
0
0
X
X
X
X
ID[7:0]:
The ID[7:0] bits are pre-set. The ID[7:4] bits represent the IDT82P2282 device. The ID[3:0] bits represent the current version number (‘0001’ is for
the first version).
T1/J1 Software Reset (004H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
Type
X
Default
A write operation to this register will generate a software reset.
The software reset can only be applied when the clock on the OSCI pin is available.
The software reset will set all the registers except the T1/J1 Or E1 Mode register (020H,...) to their default values. If the setting is changed in the
T1/J1 Or E1 Mode register (020H,...), a software reset must be applied.
Programming Information
126
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 G.772 Monitor Control (005H)
Bit No.
7
6
5
4
3
Bit Name
2
1
0
MON3
Type
Reserved
R/W
Default
MON0
Reserved
R/W
0
0
MON[3], MON[0]:
These bits determine whether the G.772 Monitor is implemented. When the G.772 Monitor is implemented, these bits select one transmitter or
receiver to be monitored by the Link 1.
MON[3], MON[0]
Monitored Path
MON[3], MON[0]
Monitored Path
00
01
No transmitter or receiver is monitored.
The receiver of the Link 2 is monitored.
10
11
No transmitter or receiver is monitored.
The transmitter of the Link 2 is monitored.
Programming Information
127
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 GPIO Control (006H)
Bit No.
7
6
5
4
Bit Name
Type
3
2
1
LEVEL0
Reserved
R/W
Default
0
0
DIR0
Reserved
R/W
1
LEVEL[0]:
When the GPIO[0] pin is defined as an output port, this bit can be read and written:
= 0: The GPIO[0] pin outputs low level.
= 1: The GPIO[0] pin outputs high level.
When the GPIO[0] pin is defined as an input port, this bit can only be read:
= 0: Low level is input on the GPIO[0] pin.
= 1: High level is input on the GPIO[0] pin.
DIR[0]:
= 0: The GPIO[0] pin is used as an output port.
= 1: The GPIO[0] pin is used as an input port.
Programming Information
128
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Reference Clock Output Select (007H)
Bit No.
7
6
5
4
Bit Name
Type
3
2
1
RO20
Reserved
R/W
Default
0
RO10
Reserved
0
R/W
0
RO20:
This bit selects the recovered clock from the line side of one link to be internally looped to the REFB_OUT output pin:
= 0: The recovered clock from the line side of Link 1 is selected to be internally looped to the REFB_OUT output pin.
= 1: The recovered clock from the line side of Link 2 is selected to be internally looped to the REFB_OUT output pin.
RO10:
This bit selects the recovered clock from the line side of one link to be internally looped to the REFA_OUT output pin:
= 0: The recovered clock from the line side of Link 1 is selected to be internally looped to the REFA_OUT output pin.
= 1: The recovered clock from the line side of Link 2 is selected to be internally looped to the REFA_OUT output pin.
Programming Information
129
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Interrupt Requisition Link ID (009H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
INT2
INT1
R
R
0
0
1
0
INTn:
= 0: No interrupt is generated in the corresponding link.
= 1: At least one interrupt is generated in the corresponding link.
T1/J1 Timer Interrupt Control (00AH)
Bit No.
7
6
5
4
3
2
Bit Name
TMOVE
Type
Reserved
R/W
Default
0
TMOVE:
= 0: Disable the interrupt on the INT pin when the TMOVI bit (b0, T1/J1-00BH) is ‘1’.
= 1: Enable the interrupt on the INT pin when the TMOVI bit (b0, T1/J1-00BH) is ‘1’.
T1/J1 Timer Interrupt Indication (00BH)
Bit No.
7
6
5
4
Bit Name
Type
3
2
1
0
TMOVI
Reserved
Default
R
0
TMOVI:
The device times every one second.
= 0: One second timer is not over.
= 1: One second timer is over.
This bit will be cleared if a ’1’ is written to it.
Programming Information
130
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 PMON Access Port (00EH)
Bit No.
7
6
5
Bit Name
4
LINKSEL0
Type
Reserved
R/W
Default
Reserved
3
2
1
0
ADDR3
ADDR2
ADDR1
ADDR0
R/W
R/W
R/W
R/W
0
0
0
0
0
LINKSEL0:
This bit selects one of the two links. One of the PMON indirect registers of the selected link can be accessed by the microprocessor.
= 0: Link 1 is selected.
= 1: Link 2 is selected.
ADDR[3:0]:
These bits select one of the PMON indirect registers of the selected link to be accessed by the microprocessor.
Address
PMON Indirect Register
Address
PMON Indirect Register
00H
01H
02H
03H
04H
05H
CRCE Counter Mapping 0
CRCE Counter Mapping 1
FER Counter Mapping 0
FER Counter Mapping 1
COFA Counter Mapping
OOF Counter Mapping
06H
07H
08H
09H
0AH
0BH
PRGD Counter Mapping 0
PRGD Counter Mapping 1
LCV Counter Mapping 0
LCV Counter Mapping 1
DDSE Counter Mapping 0
DDSE Counter Mapping 1
T1/J1 PMON Access Data (00FH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
DAT[7:0]:
These bits hold the value which is read from the selected PMON indirect register.
Programming Information
131
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Backplane Global Configuration (010H)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
RSLVCK
RMUX
R/W
R/W
1
0
2
Reserved
1
0
TSLVCK
TMUX
R/W
R/W
1
0
RSLVCK:
This bit is valid when both two links are in the Receive Clock Slave mode.
= 0: Each link uses its own clock signal on the RSCKn pin and framing pulse on the RSFSn pin.
= 1: Both two links use the clock signal on the RSCK[1] pin and the framing pulse on the RSFS[1] pin.
RMUX:
= 0: The Receive System Interface of the device is operated in the Non-multiplexed mode.
= 1: The Receive System Interface of the device is operated in the Multiplexed mode.
TSLVCK:
This bit is valid when both two links are in the Transmit Clock Slave mode.
= 0: Each link uses its own timing signal on the TSCKn pin and framing pulse on the TSFSn pin.
= 1: Both two links use the timing signal on the TSCK[1] pin and the framing pulse on the TSFS[1] pin.
TMUX:
= 0: The Transmit System Interface of the device is operated in the Non-multiplexed mode.
= 1: The Transmit System Interface of the device is operated in the Multiplexed mode.
Programming Information
132
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Transmit Jitter Attenuation Configuration (021H, 121H)
Bit No.
7
6
Bit Name
Type
5
4
3
2
1
0
TJITT_TEST
TJA_LIMT
TJA_E
TJA_DP1
TJA_DP0
TJA_BW
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Reserved
Default
TJITT_TEST:
= 0: The real time interval between the read and write pointer of the FIFO is indicated in the TJITT[6:0] bits (b6~0, T1/J1-038H,...). That is, the
current interval between the read and write pointer of the FIFO will be written into the TJITT[6:0] bits (b6~0, T1/J1-038H,...).
= 1: The peak-peak interval between the read and write pointer of the FIFO is indicated in the TJITT[6:0] bits (b6~0, T1/J1-038H,...). That is, the
current interval is compared with the old one in the TJITT[6:0] bits (b6~0, T1/J1-038H,...) and the larger one will be indicated by the TJITT[6:0] bits
(b6~0, T1/J1-038H,...); otherwise, the value in the TJITT[6:0] bits (b6~0, T1/J1-038H,...) will not be changed.
TJA_LIMT:
When the read and write pointer of the FIFO are within 2/3/4 bits (corresponding to the FIFO depth) of overflowing or underflowing, the bandwidth
of the JA can be widened to track the short term input jitter, thereby avoiding data corruption. This bit selects whether the bandwidth is normal or widened.
= 0: Normal bandwidth is selected.
= 1: Widen bandwidth is selected. In this case, the JA will not attenuate the input jitter until the read/write pointer’s position is outside the 2/3/4
bits window.
TJA_E:
= 0: Disable the Transmit Jitter Attenuator.
= 1: Enable the Transmit Jitter Attenuator.
TJA_DP[1:0]:
These two bits select the Jitter Attenuation Depth.
= 00: The Jitter Attenuation Depth is 128-bit.
= 01: The Jitter Attenuation Depth is 64-bit.
= 10 / 11: The Jitter Attenuation Depth is 32-bit.
TJA_BW:
This bit select the Jitter Transfer Function Bandwidth.
= 0: 5 Hz.
= 1: 1.26 Hz.
Programming Information
133
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Transmit Configuration 0 (022H, 122H)
Bit No.
7
6
Bit Name
Type
Default
5
4
3
2
T_OFF
Reserved
R/W
0
1
0
T_MD
Reserved
R/W
0
T_OFF:
= 0: The transmit path is power up.
= 1: The transmit path is power down. The Line Driver is in high impedance.
T_MD:
This bit selects the line code rule to encode the data stream to be transmitted.
= 0: The B8ZS encoder is selected.
= 1: The AMI encoder is selected.
Programming Information
134
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Transmit Configuration 1 (023H, 123H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
DFM_ON
T_HZ
PULS3
PULS2
PULS1
PULS0
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
0
0
0
DFM_ON:
= 0: The Driver Failure Monitor is disabled.
= 1: The Driver Failure Monitor is enabled.
T_HZ:
= 0: The Line Driver works normally.
= 1: Set the Line Driver High-Z. (The other parts of the transmit path still work normally.)
PULS[3:0]:
These bits determine the template shapes for short/long haul transmission:
PULS[3:0]
Operating Mode
Transmit Clock
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
11xx
Programming Information
Cable Impedance
Application
Reserved
DSX1
J1
DS1
DSX1
DSX1
DSX1
DSX1
100 Ω
110 Ω
100 Ω
100 Ω
100 Ω
100 Ω
100 Ω
1.544 MHz
1.544 MHz
1.544 MHz
1.544 MHz
1.544 MHz
1.544 MHz
1.544 MHz
0 - 133 ft
0 - 655 ft
0 dB LBO
133 - 266 ft
266 - 399 ft
399 - 533 ft
533 - 655 ft
Reserved
DS1
DS1
DS1
1.544 MHz
100 Ω
1.544 MHz
100 Ω
1.544 MHz
100 Ω
Arbitrary waveform setting.
135
-7.5 dB LBO
-15.0 dB LBO
-22.5 dB LBO
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Transmit Configuration 2 (024H, 124H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
SCAL5
SCAL4
SCAL3
SCAL2
SCAL1
SCAL0
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
1
SCAL[5:0]:
The following setting lists the standard values of normal amplitude in different operating modes. Each step change (one increasing or decreasing
from the standard value) will scale the amplitude of the D/A output by a certain offset. These bits are only effective when user programmable arbitrary
waveform is used.
= 000100: Normal amplitude in T1 long haul LBO/-22.5 dB operating mode. Each step change scales about 25% offset.
= 001000: Normal amplitude in T1 long haul LBO/-15 dB operating mode. Each step change scales about 12.5% offset.
= 010001: Normal amplitude in T1 long haul LBO/-7.5 dB operating mode. Each step change scales about 6.25% offset.
= 110110: Normal amplitude in T1 0~133 ft, 133~266 ft, 266~399 ft, 399~533 ft, 533~655 ft, DS1 0 dB & J1 0~655 ft operating modes. Each step
change scales about 2% offset.
Programming Information
136
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Transmit Configuration 3 (025H, 125H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DONE
RW
UI1
UI0
SAMP3
SAMP2
SAMP1
SAMP0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register is valid when the PULS[3:0] bits (b3~0, T1/J1-023H,...) are set to ‘11xx’.
DONE:
= 0: Disable the read/write operation to the pulse template RAM.
= 1: Enable the read/write operation to the pulse template RAM.
RW:
= 0: Write the data to the pulse template RAM.
= 1: Read the data to the pulse template RAM.
UI[1:0]:
These bits specify one Unit Interval (UI) address.
= 00: UI addressed 0 is specified.
= 01: UI addressed 1 is specified.
= 10: UI addressed 2 is specified.
= 11: UI addressed 3 is specified.
SAMP[3:0]:
There bits specify one sample address. There are 16 samples in each UI.
SAMP[3:0]
Specified Sample Address
SAMP[3:0]
Specified Sample Address
0000
0001
0010
0011
0100
0101
0110
0111
0
1
2
3
4
5
6
7
1000
1001
1010
1011
1100
1101
1110
1111
8
9
10
11
12
13
14
15
Programming Information
137
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Transmit Configuration 4 (026H, 126H)
Bit No.
7
Bit Name
Type
Reserved
6
5
4
3
2
1
0
WDAT6
WDAT5
WDAT4
WDAT3
WDAT2
WDAT1
WDAT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Default
WDAT[6:0]:
These bits contain the data to be stored in the pulse template RAM which is addressed by the UI[1:0] bits (b5~4, T1/J1-025H,...) and the
SAMP[3:0] bits (b3~0, T1/J1-025H,...).
T1/J1 Receive Jitter Attenuation Configuration (027H, 127H)
Bit No.
7
6
Bit Name
Type
5
4
3
2
1
0
RJITT_TEST
RJA_LIMT
RJA_E
RJA_DP1
RJA_DP0
RJA_BW
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Reserved
Default
RJITT_TEST:
= 0: The real time interval between the read and write pointer of the FIFO is indicated in the RJITT[6:0] bits (b6~0, T1/J1-039H,...). That is, the
current interval between the read and write pointer of the FIFO will be written into the RJITT[6:0] bits (b6~0, T1/J1-039H,...).
= 1: The peak-peak interval between the read and write pointer of the FIFO is indicated in the RJITT[6:0] bits (b6~0, T1/J1-039H,...). That is, the
current interval is compared with the old one in the RJITT[6:0] bits (b6~0, T1/J1-039H,...) and the larger one will be indicated by the RJITT[6:0] bits
(b6~0, T1/J1-039H,...); otherwise, the value in the RJITT[6:0] bits (b6~0, T1/J1-039H,...) will not be changed.
RJA_LIMT:
When the read and write pointer of the FIFO are within 2/3/4 bits (corresponding to the FIFO depth) of overflowing or underflowing, the bandwidth
of the JA can be widened to track the short term input jitter, thereby avoiding data corruption. This bit selects whether the bandwidth is normal or widened.
= 0: Normal bandwidth is selected.
= 1: Widen bandwidth is selected. In this case, the JA will not attenuate the input jitter until the read/write pointer’s position is outside the 2/3/4
bits window.
RJA_E:
= 0: Disable the Receive Jitter Attenuator.
= 1: Enable the Receive Jitter Attenuator.
RJA_DP[1:0]:
These two bits select the Jitter Attenuation Depth.
= 00: The Jitter Attenuation Depth is 128-bit.
= 01: The Jitter Attenuation Depth is 64-bit.
= 10 / 11: The Jitter Attenuation Depth is 32-bit.
RJA_BW:
This bit select the Jitter Transfer Function Bandwidth.
= 0: 5 Hz.
= 1: 1.26 Hz.
Programming Information
138
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Receive Configuration 0 (028H, 128H)
Bit No.
7
6
Bit Name
Type
5
4
3
2
R_OFF
Reserved
Default
R/W
0
1
0
R_MD
Reserved
R/W
0
R_OFF:
= 0: The receive path is power up.
= 1: The receive path is power down.
R_MD:
This bit selects the line code rule to decode the received data stream.
= 0: The B8ZS decoder is selected.
= 1: The AMI decoder is selected.
Programming Information
139
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Receive Configuration 1 (029H, 129H)
Bit No.
7
Bit Name
Type
6
5
EQ_ON
Reserved
Default
R/W
Reserved
0
4
3
2
1
0
LOS4
LOS3
LOS2
LOS1
LOS0
R/W
R/W
R/W
R/W
R/W
1
0
1
0
1
EQ_ON:
= 0: The Equalizer is off in short haul applications.
= 1: The Equalizer is on in long haul applications.
LOS[4:0]:
A LOS is detected when the incoming signals has “no transitions”, i.e., when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. In long haul applications, these bits select the LOS declare threshold (Q). These bits are invalid in short haul applications.
Programming Information
LOS[4:0]
LOS Declare Threshold (Q)
LOS[4:0]
LOS Declare Threshold (Q)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
-4 dB
-6 dB
-8 dB
-10 dB
-12 dB
-14 dB
-16 dB
-18 dB
-20 dB
-22 dB
-24 dB
-26 dB
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110 11111
-28 dB
-30 dB
-32 dB
-34 dB
-36 dB
-38 dB
-40 dB
-42 dB
-44 dB
-46 dB
140
-48 dB
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Receive Configuration 2 (02AH, 12AH)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
SLICE1
SLICE0
UPDW1
UPDW0
MG1
MG0
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
0
0
0
SLICE[1:0]:
These two bits define the Data Slicer threshold.
= 00: The Data Slicer generates a mark if the voltage on the RTIPn/RRINGn pins exceeds 40% of the peak amplitude.
= 01: The Data Slicer generates a mark if the voltage on the RTIPn/RRINGn pins exceeds 50% of the peak amplitude.
= 10: The Data Slicer generates a mark if the voltage on the RTIPn/RRINGn pins exceeds 60% of the peak amplitude.
= 11: The Data Slicer generates a mark if the voltage on the RTIPn/RRINGn pins exceeds 70% of the peak amplitude.
UPDW[1:0]:
These two bits select the observation period, during which the peak value of the incoming signals is measured.
= 00: The observation period is 32 bits.
= 01: The observation period is 64 bits.
= 10: The observation period is 128 bits.
= 11: The observation period is 256 bits.
MG[1:0]:
These two bits select the Monitor Gain.
= 00: The Monitor Gain is 0 dB.
= 01: The Monitor Gain is 22 dB.
= 10: Reserved.
= 11: Reserved.
Programming Information
141
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Maintenance Function Control 0 (02BH, 12BH)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
DLLP
SLLP
SRLP
R/W
R/W
R/W
0
0
0
Reserved
2
1
0
RLP
ALP
DLP
R/W
R/W
R/W
0
0
0
DLLP:
= 0: Disable the Local Digital Loopback 1.
= 1: Enable the Local Digital Loopback 1.
SLLP:
= 0: Disable the System Local Loopback.
= 1: Enable the System Local Loopback.
SRLP:
= 0: Disable the System Remote Loopback.
= 1: Enable the System Remote Loopback.
RLP:
= 0: Disable the Remote Loopback.
= 1: Enable the Remote Loopback.
ALP:
= 0: Disable the Analog Loopback.
= 1: Enable the Analog Loopback.
DLP:
= 0: Disable the Local Digital Loopback 2.
= 1: Enable the Local Digital Loopback 2.
Programming Information
142
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Maintenance Function Control 1 (02CH, 12CH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
LAC
RAISE
ATAO
R/W
R/W
R/W
0
0
0
LAC:
This bit selects the LOS criterion.
= 0: The T1.231 is selected. In short haul application, the LOS is declared when the incoming signal level is less than 800 mVpp for 175 consecutive bit intervals and is cleared when the incoming signal level is greater than 1 Vpp and has an average mark density of at least 12.5% and less than
100 consecutive zeros in 128 consecutive bit periods. In long haul application, the LOS is declared when the incoming signal level is less than Q dB
below nominal (set in the LOS[4:0] bits (b4~0, T1/J1-029H,...)) for 175 consecutive bit intervals and is cleared when the incoming signal level is
greater than (Q + 4 dB) and has an average mark density of at least 12.5% and less than 100 consecutive zeros in 128 consecutive bit periods.
= 1: The I.431 is selected. In short haul application, the LOS is declared when the incoming signal level is less than 800 mVpp for 1544 consecutive bit intervals and is cleared when the incoming signal level is greater than 1 Vpp and has an average mark density of at least 12.5% and less than
100 consecutive zeros in 128 consecutive bit periods. In long haul application, the LOS is declared when the incoming signal level is less than Q dB
below nominal (set in the LOS[4:0] bits (b4~0, T1/J1-029H,...)) for 1544 consecutive bit intervals and is cleared when the incoming signal level is
greater than (Q + 4 dB) and has an average mark density of at least 12.5% and less than 100 consecutive zeros in 128 consecutive bit periods.
RAISE:
This bit determines whether all ’One’s can be inserted in the receive path when the LOS is detected.
= 0: Disable the insertion.
= 1: Enable the insertion.
ATAO:
This bit determines whether all ’One’s can be inserted in the transmit path when the LOS is detected in the receive path.
= 0: Disable the insertion.
= 1: Enable the insertion.
Programming Information
143
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Maintenance Function Control 2 (031H, 131H)
Bit No.
7
Bit Name
Type
6
5
BPV_INS
Reserved
Default
R/W
0
Reserved
4
3
2
1
0
EXZ_DEF
EXZ_ERR1
EXZ_ERR0
CNT_MD
CNT_TRF
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BPV_INS:
A transition from ‘0’ to ‘1’ on this bit generates a single Bipolar Violation (BPV) Error to be inserted to the data stream to be transmitted.
This bit must be cleared and set again for the next BPV error insertion.
EXZ_DEF:
This bit selects the Excessive Zero (EXZ) Error criterion.
= 0: The ANSI is selected. In AMI line code rule, the EXZ error is defined as more than 15 consecutive zeros in the data stream. In B8ZS line
code rule, the EXZ error is defined as more than 7 consecutive zeros in the data stream.
= 1: The FCC is selected. In AMI line code rule, the EXZ error is defined as more than 80 consecutive zeros in the data stream. In B8ZS line code
rule, the EXZ error is defined as more than 7 consecutive zeros in the data stream.
EXZ_ERR[1:0]:
These bits must be set to ‘01’ to enable the Excessive Zero (EXZ) Error event to be counted in an internal 16-bit EXZ counter.
CNT_MD:
= 0: The Manual Report mode is selected. The internal 16-bit EXZ counter transfers its content to the EXZ Error Counter L-Byte & H-Byte registers when there is a transition from ‘0’ to ‘1’ on the CNT_TRF bit.
= 1: The Auto Report mode is selected. The internal 16-bit EXZ counter transfers its content to the EXZ Error Counter L-Byte & H-Byte registers
every one second automatically.
CNT_TRF:
This bit is valid when the CNT_MD bit is ‘0’.
A transition from ‘0’ to ‘1’ on this bit updates the content in the EXZ Error Counter L-Byte & H-Byte registers with the value in the internal 16-bit
EXZ counter.
This bit must be cleared and set again for the next updating.
Programming Information
144
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Transmit And Receive Termination Configuration (032H, 132H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
T_TERM2
T_TERM1
T_TERM0
R_TERM2
R_TERM1
R_TERM0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
1
1
1
0
T_TERM[2:0]:
These bits select the internal impedance of the transmit path to match the cable impedance:
= 000: The 75 Ω internal impedance matching is selected.
= 001: The 120 Ω internal impedance matching is selected.
= 010: The 100 Ω internal impedance matching is selected. (It is the standard value for T1 mode).
= 011: The 110 Ω internal impedance matching is selected. (It is the standard value for J1 mode).
= 1xx: Reserved.
In T1/J1 mode, the external impedance circuit is not supported in transmit path.
R_TERM[2:0]:
These bits select the internal impedance of the receive path to match the cable impedance:
= 000: The 75 Ω internal impedance matching is selected.
= 001: The 120 Ω internal impedance matching is selected.
= 010: The 100 Ω internal impedance matching is selected. (It is the standard value for T1 mode).
= 011: The 110 Ω internal impedance matching is selected. (It is the standard value for J1 mode).
= 1xx: The internal impedance matching is bypassed, and external impedance circuit should be used.
T1/J1 Interrupt Enable Control 0 (033H, 133H)
Bit No.
7
6
5
4
3
Bit Name
Type
2
DF_IE
Reserved
R/W
Default
0
LOS_IE
Reserved
R/W
0
DF_IE:
= 0: Disable the interrupt on the INT pin when the DF_IS bit (b2, T1/J1-03AH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the DF_IS bit (b2, T1/J1-03AH,...) is ‘1’.
LOS_IE:
= 0: Disable the interrupt on the INT pin when the LOS_IS bit (b0, T1/J1-03AH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the LOS_IS bit (b0, T1/J1-03AH,...) is ‘1’.
Programming Information
145
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Interrupt Enable Control 1 (034H, 134H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
DAC_IE
TJA_IE
RJA_IE
R/W
R/W
R/W
0
0
0
Reserved
2
1
0
EXZ_IE
CV_IE
CNT_IE
R/W
R/W
R/W
0
0
0
DAC_IE:
= 0: Disable the interrupt on the INT pin when the DAC_IS bit (b6, T1/J1-03BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the DAC_IS bit (b6, T1/J1-03BH,...) is ‘1’.
TJA_IE:
= 0: Disable the interrupt on the INT pin when the TJA_IS bit (b5, T1/J1-03BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the TJA_IS bit (b5, T1/J1-03BH,...) is ‘1’.
RJA_IE:
= 0: Disable the interrupt on the INT pin when the RJA_IS bit (b4, T1/J1-03BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the RJA_IS bit (b4, T1/J1-03BH,...) is ‘1’.
EXZ_IE:
= 0: Disable the interrupt on the INT pin when the EXZ_IS bit (b2, T1/J1-03BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the EXZ_IS bit (b2, T1/J1-03BH,...) is ‘1’.
CV_IE:
= 0: Disable the interrupt on the INT pin when the CV_IS bit (b1, T1/J1-03BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the CV_IS bit (b1, T1/J1-03BH,...) is ‘1’.
CNT_IE:
= 0: Disable the interrupt on the INT pin when the CNTOV_IS bit (b0, T1/J1-03BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the CNTOV_IS bit (b0, T1/J1-03BH,...) is ‘1’.
Programming Information
146
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Interrupt Trigger Edges Select (035H, 135H)
Bit No.
7
6
5
4
3
Bit Name
2
1
DF_IES
Type
Reserved
R/W
Default
0
LOS_IES
Reserved
0
R/W
0
DF_IES:
= 0: The DF_IS bit (b2, T1/J1-03AH,...) will be set to ‘1’ when there is a transition from ‘0’ to ‘1’ on the DF_S bit (b2, T1/J1-036H,...).
= 1: The DF_IS bit (b2, T1/J1-03AH,...) will be set to ‘1’ when there is any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the DF_S bit (b2, T1/J1036H,...).
LOS_IES:
= 0: The LOS_IS bit (b0, T1/J1-03AH,...) will be set to ‘1’ when there is a transition from ‘0’ to ‘1’ on the LOS_S bit (b0, T1/J1-036H,...).
= 1: The LOS_IS bit (b0, T1/J1-03AH,...) will be set to ‘1’ when there is any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the LOS_S bit (b0, T1/J1036H,...).
T1/J1 Line Status Register 0 (036H, 136H)
Bit No.
7
6
5
4
3
Bit Name
Type
2
1
DF_S
Reserved
R
Default
0
0
LOS_S
Reserved
R
0
DF_S:
= 0: No transmit driver failure is detected.
= 1: Transmit driver failure is detected.
LOS_S:
= 0: No LOS is detected.
= 1: Loss of signal (LOS) is detected.
Programming Information
147
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Line Status Register 1 (037H, 137H)
Bit No.
7
6
5
Bit Name
Type
Reserved
Default
4
3
2
1
0
LATT4
LATT3
LATT2
LATT1
LATT0
R
R
R
R
R
0
0
0
0
0
LATT[4:0]:
These bits indicate the current gain of the VGA relative to 3 V peak pulse level.
LATT[4:0]
Gain (dB)
LATT[4:0]
Gain (dB)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
0-2
2-4
4-6
6-8
8 - 10
10 - 12
12 - 14
14 - 16
16 - 18
18 - 20
20 - 22
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101 ~ 11111
22 - 24
24 - 26
26 - 28
28 - 30
30 - 32
32 - 34
34 - 36
36 - 38
38 - 40
40 - 42
42 - 44
Programming Information
148
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Transmit Jitter Measure Value Indication (038H, 138H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
TJITT6
TJITT5
TJITT4
TJITT3
TJITT2
TJITT1
TJITT0
R
R
R
R
R
R
R
0
0
0
0
0
0
0
TJITT[6:0]:
When the TJITT_TEST bit (b5, T1/J1-021H,...) is ‘0’, these bits represent the current interval between the read and write pointer of the FIFO.
When the TJITT_TEST bit (b5, T1/J1-021H,...) is ‘1’, these bits represent the P-P interval between the read and write pointer of the FIFO since
last read.
These bits will be cleared if a ’1’ is written to the register.
T1/J1 Receive Jitter Measure Value Indication (039H, 139H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
RJITT6
RJITT5
RJITT4
RJITT3
RJITT2
RJITT1
RJITT0
R
R
R
R
R
R
R
0
0
0
0
0
0
0
RJITT[6:0]:
When the RJITT_TEST bit (b5, T1/J1-027H,...) is ‘0’, these bits represent the current interval between the read and write pointer of the FIFO.
When the RJITT_TEST bit (b5, T1/J1-027H,...) is ‘1’, these bits represent the P-P interval between the read and write pointer of the FIFO since
last read.
These bits will be cleared if a ’1’ is written to the register.
Programming Information
149
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Interrupt Status 0 (03AH, 13AH)
Bit No.
7
6
5
4
3
Bit Name
Type
2
1
DF_IS
Reserved
R
Default
0
0
LOS_IS
Reserved
R
0
DF_IS:
= 0: There is no status change on the DF_S bit (b2, T1/J1-036H,...).
= 1: When the DF_IES bit (b2, T1/J1-035H,...) is ‘0’, the ‘1’ on this bit indicates there is a transition from ‘0’ to ‘1’ on the DF_S bit (b2, T1/J1036H,...); when the DF_IES bit (b2, T1/J1-035H,...) is ‘1’, the ‘1’ on this bit indicates there is a transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the DF_S bit
(b2, T1/J1-036H,...).
This bit will be cleared if a ’1’ is written to it.
LOS_IS:
= 0: There is no status change on the LOS_S bit (b0, T1/J1-036H,...).
= 1: When the LOS_IES bit (b0, T1/J1-035H,...) is ‘0’, the ‘1’ on this bit indicates there is a transition from ‘0’ to ‘1’ on the LOS_S bit (b0, T1/J1036H,...); when the LOS_IES bit (b0, T1/J1-035H,...) is ‘1’, the ‘1’ on this bit indicates there is a transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the LOS_S
bit (b0, T1/J1-036H,...).
This bit will be cleared if a ’1’ is written to it.
Programming Information
150
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Interrupt Status 1 (03BH, 13BH)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
DAC_IS
TJA_IS
RJA_IS
R
R
R
0
0
0
Reserved
2
1
0
EXZ_IS
CV_IS
CNTOV_IS
R
R
R
0
0
0
DAC_IS:
= 0: The sum of a pulse template does not exceed the D/A limitation (+63) when more than one UI is used to compose the arbitrary pulse template.
= 1: The sum of a pulse template exceeds the D/A limitation (+63) when more than one UI is used to compose the arbitrary pulse template.
This bit will be cleared if a ’1’ is written to it.
TJA_IS:
= 0: The transmit JA FIFO has not overflowed or underflowed.
= 1: The transmit JA FIFO has overflowed or underflowed.
This bit will be cleared if a ’1’ is written to it.
RJA_IS:
= 0: The receive JA FIFO has not overflowed or underflowed.
= 1: The receive JA FIFO has overflowed or underflowed.
This bit will be cleared if a ’1’ is written to it.
EXZ_IS:
= 0: No Excessive Zero (EXZ) Error is detected.
= 1: The Excessive Zero (EXZ) Error is detected.
This bit will be cleared if a ’1’ is written to it.
CV_IS:
= 0: No Bipolar Violation (BPV) Error is detected.
= 1: The Bipolar Violation (BPV) Error is detected.
This bit will be cleared if a ’1’ is written to it.
CNTOV_IS:
= 0: The internal 16-bit EXZ counter has not overflowed.
= 1: The internal 16-bit EXZ counter has overflowed.
This bit will be cleared if a ‘1’ is written to it.
Programming Information
151
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 EXZ Error Counter H-Byte (03CH, 13CH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
CNTH[7]
CNTH[6]
CNTH[5]
CNTH[4]
CNTH[3]
CNTH[2]
CNTH[1]
CNTH[0]
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
CNTH[7:0]:
These bits, together with the CNTL[7:0] bits, reflect the content in the internal 16-bit EXZ counter.
T1/J1 EXZ Error Counter L-Byte (03DH, 13DH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
CNTL[7]
CNTL[6]
CNTL[5]
CNTL[4]
CNTL[3]
CNTL[2]
CNTL[1]
CNTL[0]
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
2
1
0
CNTL[7:0]:
These bits, together with the CNTH[7:0] bits, reflect the content in the internal 16-bit EXZ counter.
T1/J1 Reference Clock Output Control (03EH, 13EH)
Bit No.
7
6
5
4
3
Bit Name
Type
REFH_LOS
Reserved
Default
R/W
0
REFH_LOS:
In case of LOS, this bit determines the outputs on the REFA_OUT and REFB_OUT pins.
= 0: Output MCLK.
= 1: Output high level.
Programming Information
152
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Interrupt Module Indication 2 (03FH, 13FH)
Bit No.
7
6
5
4
3
Bit Name
Type
2
1
0
LIU
Reserved
Default
R
0
LIU:
= 0: No interrupt is generated in the Receive / Transmit Internal Termination, Adaptive Equalizer, Data Slicer, CLK&Data Recovery, Receive /
Transmit Jitter Attenuator, B8ZS/HDB3/AMI Decoder / Encoder, Waveform Shaper / Line Build Out or Line Driver block.
= 1: Interrupt is generated in the Receive / Transmit Internal Termination, Adaptive Equalizer, Data Slicer, CLK&Data Recovery, Receive / Transmit Jitter Attenuator, B8ZS/HDB3/AMI Decoder / Encoder, Waveform Shaper / Line Build Out or Line Driver function block.
Programming Information
153
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Interrupt Module Indication 0 (040H, 140H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
IBCD
RBOC
ALARM
PMON
PRGD
RCRB
FGEN
FRMR
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
IBCD:
= 0: No interrupt is generated in the Inband Loopback Code Detector function block.
= 1: Interrupt is generated in the Inband Loopback Code Detector function block.
RBOC:
= 0: No interrupt is generated in the Bit-Oriented Message Receiver function block.
= 1: Interrupt is generated in the Bit-Oriented Message Receiver function block.
ALARM:
= 0: No interrupt is generated in the Alarm Detector function block.
= 1: Interrupt is generated in the Alarm Detector function block.
PMON:
= 0: No interrupt is generated in the Performance Monitor function block.
= 1: Interrupt is generated in the Performance Monitor function block.
PRGD:
= 0: No interrupt is generated in the PRBS Generator / Detector function block.
= 1: Interrupt is generated in the PRBS Generator / Detector function block.
RCRB:
= 0: No interrupt is generated in the Receive CAS/RBS Buffer function block.
= 1: Interrupt is generated in the Receive CAS/RBS Buffer function block.
FGEN:
= 0: No interrupt is generated in the Frame Generator function block.
= 1: Interrupt is generated in the Frame Generator function block.
FRMR:
= 0: No interrupt is generated in the Frame Processor function block.
= 1: Interrupt is generated in the Frame Processor function block.
Programming Information
154
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Interrupt Module Indication 1 (041H, 141H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
THDLC3
THDLC2
THDLC1
RHDLC3
RHDLC2
RHDLC1
ELST
TRSI/RESI
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
THDLC3:
= 0: No interrupt is generated in the HDLC Transmitter #3 function block.
= 1: Interrupt is generated in the HDLC Transmitter #3 function block.
THDLC2:
= 0: No interrupt is generated in the HDLC Transmitter #2 function block.
= 1: Interrupt is generated in the HDLC Transmitter #2 function block.
THDLC1:
= 0: No interrupt is generated in the HDLC Transmitter #1 function block.
= 1: Interrupt is generated in the HDLC Transmitter #1 function block.
RHDLC3:
= 0: No interrupt is generated in the HDLC Receiver #3 function block.
= 1: Interrupt is generated in the HDLC Receiver #3 function block.
RHDLC2:
= 0: No interrupt is generated in the HDLC Receiver #2 function block.
= 1: Interrupt is generated in the HDLC Receiver #2 function block.
RHDLC1:
= 0: No interrupt is generated in the HDLC Receiver #1 function block.
= 1: Interrupt is generated in the HDLC Receiver #1 function block.
ELST:
= 0: No interrupt is generated in the Elastic Store Buffer function block.
= 1: Interrupt is generated in the Elastic Store Buffer function block.
TRSI/RESI:
= 0: No interrupt is generated in the Transmit / Receive System Interface function block.
= 1: Interrupt is generated in the Transmit / Receive System Interface function block.
Programming Information
155
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 TBIF Option Register (042H, 142H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
FBITGAP
DE
FE
CMS
FSINV
FSTYP
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
FBITGAP:
This bit is valid in Transmit Clock Master mode.
= 0: The F-bit is not gapped.
= 1: The F-bit is gapped (no clock signal during the F-bit).
DE:
This bit selects the active edge of TSCKn to sample the data on TSDn and TSIGn and the active edge of MTSCK to sample the data on MTSD
and MTSIG.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Transmit Multiplexed mode, the bit of the two links should be set to the same value.
FE:
This bit selects the active edge of TSCKn to update/sample the pulse on TSFSn and the active edge of MTSCK to sample the pulse on MTSFS.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Transmit Multiplexed mode, the bit of the two links should be set to the same value.
CMS:
This bit is valid in Transmit Clock Slave T1/J1 mode E1 rate and Transmit Multiplexed mode.
= 0: The speed of the TSCKn / MTSCK is the same as the data rate on the system side (2.048 MHz / 8.192 MHz).
= 1: The speed of the TSCKn / MTSCK is double the data rate on the system side (4.096 MHz / 16.384 MHz).
In Transmit Clock Slave T1/J1 mode E1 rate, if both two links use the TSCK[1] and TSFS[1] to input the data (i.e., the TSLVCK bit (b, T1/J1010H) is set to ‘1’), the bit of the two links should be set to the same value.
In Transmit Multiplexed mode, the bit of the two links should be set to the same value.
FSINV:
= 0: The transmit framing pulse TSFSn is active high.
= 1: The transmit framing pulse TSFSn is active low.
In Transmit Multiplexed mode, this bit of the two links should be set to the same value.
FSTYP:
= 0: In Transmit Non-multiplexed mode, TSFSn pulses during each F-bit. In Transmit Multiplexed mode, MTSFS pulses during each F-bit of the
first link.
= 1: In Transmit Non-multiplexed mode, TSFSn pulses during the first F-bit of every SF/ESF/T1 DM/SLC-96 frame. In Transmit Multiplexed
mode, MTSFS pulses during the first F-bit of every SF/ESF/T1 DM/SLC-96 frame of the first link.
In Transmit Multiplexed mode, this bit of the two links should be set to the same value.
Programming Information
156
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 TBIF Operating Mode (043H, 143H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
2
1
0
MAP1
MAP0
TMODE
R/W
R/W
R/W
0
0
1
Default
MAP[1:0]:
In Transmit Clock Slave mode and Transmit Multiplexed mode, these 2 bits select the T1/J1 to E1 format mapping schemes.
MAP[1:0]
T1/J1 To E1 Format Mapping Schemes
00*
01
10
11
T1/J1 Rate
T1/J1 Mode E1 Rate per G.802
T1/J1 Mode E1 Rate per One Filler Every Four CHs
T1/J1 Mode E1 Rate per Continuous CHs
Note:
* These 2 bits can not be set to ‘00’ in the Transmit Multiplexed mode.
TMODE:
In Transmit Non-multiplexed mode, this bit selects the sub-mode.
= 0: The Transmit System Interface is operated in Transmit Clock Master mode. The timing signal for clocking the data and the framing pulse to
align the data input on the TSDn pin are provided from the processed data from the device.
= 1: The Transmit System Interface is operated in Transmit Clock Slave mode. The timing signal for clocking the data and the framing pulse to
align the data input on the TSDn pin are provided by the system side.
Programming Information
157
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 TBIF TS Offset (044H, 144H)
Bit No.
7
Bit Name
Type
Reserved
6
5
4
3
2
1
0
TSOFF6
TSOFF5
TSOFF4
TSOFF3
TSOFF2
TSOFF1
TSOFF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Default
TSOFF[6:0]:
These bits give a binary number to define the channel offset. The channel offset is between the framing pulse on the TSFSn/MTSFS pin and the
start of the corresponding frame input on the TSDn/MTSD pin. The signaling bits on the TSIGn/MTSIG pin are always per-channel aligned with the
data on the TSDn/MTSD pin.
In Non-multiplexed mode, the channel offset can be configured from 0 to 23 channels (0 & 23 are included). In Multiplexed mode, the channel offset can be configured from 0 to 127 channels (0 & 127 are included).
T1/J1 TBIF Bit Offset (045H, 145H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
EDGE
BOFF2
BOFF1
BOFF0
R/W
R/W
R/W
R/W
0
0
0
0
EDGE:
This bit is valid when the CMS bit (b2, T1/J1-042H,...) is ‘1’.
= 0: The first active edge of TSCKn/MTSCK is selected to sample the data on the TSDn/MTSD and TSIGn/MTSIG pins.
= 1: The second active edge of TSCKn/MTSCK is selected to sample the data on the TSDn/MTSD and TSIGn/MTSIG pins.
BOFF[2:0]:
These bits give a binary number to define the bit offset. The bit offset is between the framing pulse on the TSFSn/MTSFS pin and the start of the
corresponding frame input on the TSDn/MTSD pin. The signaling bits on the TSIGn/MTSIG pin are always per-channel aligned with the data on the
TSDn/MTSD pin.
Programming Information
158
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RBIF Option Register (046H, 146H)
Bit No.
7
6
5
Bit Name
Type
Reserved
Default
4
3
2
1
0
FBITGAP
DE
FE
CMS
TRI
R/W
R/W
R/W
R/W
R/W
0
1
1
0
1
FBITGAP:
This bit is valid in Receive Clock Master mode.
= 0: The F-bit is not gapped.
= 1: The F-bit is gapped (no clock signal during the F-bit).
DE:
This bit selects the active edge of RSCKn to update the data on RSDn and RSIGn and the active edge of MRSCK to update the data on MRSD
and MRSIG.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Receive Multiplexed mode, the bit of the two links should be set to the same value.
FE:
This bit selects the active edge of RSCKn to update/sample the pulse on RSFSn and the active edge of MRSCK to sample the pulse on MRSFS.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Receive Multiplexed mode, the bit of the two links should be set to the same value.
CMS:
This bit is valid in Receive Clock Slave T1/J1 mode E1 rate and Receive Multiplexed mode.
= 0: The speed of the RSCKn/MRSCK is the same as the data rate on the system side (2.048 MHz / 8.192 MHz).
= 1: The speed of the RSCKn/MRSCK is double the data rate on the system side (4.096 MHz / 16.384 MHz).
In Receive Clock Slave T1/J1 mode E1 rate, if both two links use the RSCK[1] and RSFS[1] to output the data (i.e., the RSLVCK bit (b, T1/J1010H) is set to ‘1’), the bit of the two links should be set to the same value.
In Receive Multiplexed mode, the bit of the two links should be set to the same value.
TRI:
= 0: The processed data and signaling bits are output on the RSDn/MRSD pins and the RSIGn/MRSIG pins respectively.
= 1: The output on the RSDn/MRSD pins and the RSIGn/MRSIG pins are in high impedance.
Programming Information
159
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RBIF Mode (047H, 147H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
2
1
0
MAP1
MAP0
RMODE
R/W
R/W
R/W
0
0
1
Default
MAP[1:0]:
In Receive Clock Slave mode and Receive Multiplexed mode, these 2 bits select the T1/J1 to E1 format mapping schemes.
MAP[1:0]
T1/J1 To E1 Format Mapping Schemes
00*
01
10
11
T1/J1 Rate
T1/J1 Mode E1 Rate per G.802
T1/J1 Mode E1 Rate per One Filler Every Four CHs
T1/J1 Mode E1 Rate per Continuous CHs
Note:
* These 2 bits can not be set to ‘00’ in the Receive Multiplexed mode.
RMODE:
In Receive Non-multiplexed mode, this bit selects the sub-mode.
= 0: The Receive System Interface is operated in Receive Clock Master mode. The timing signal for clocking the data and the framing pulse to
align the data output on the RSDn pin are received from each line side.
= 1: The Receive System Interface is operated in Receive Clock Slave mode. The timing signal for clocking the data and the framing pulse to
align the data output on the RSDn pin are provided by the system side.
Programming Information
160
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RBIF Frame Pulse (048H, 148H)
Bit No.
7
6
Bit Name
5
4
3
2
FSINV
Type
Reserved
Default
R/W
Reserved
0
1
0
CMFS
ALTFIS
R/W
R/W
0
0
FSINV:
= 0: The receive framing pulse RSFSn is active high.
= 1: The receive framing pulse RSFSn is active low.
In Receive Multiplexed mode, this bit of the two links should be set to the same value.
CMFS, ALTIFS:
In Receive Clock Master mode, these bits select what the pulse on RSFSn indicates. The ALTIFS bit is only valid in SF format.
Format
SF
ESF, T1DM,
SLC-96
CMFS
ALTIFS
0
0
1
1
0
1
0
1
0
1
X
X
Programming Information
RSFSn Indication
The RSFSn pulses during each F-bit.
The RSFSn pulses during every second F-bit.
The RSFSn pulses during the first F-bit of every SF frame.
The RSFSn pulses during the first F-bit of every second SF frame.
The RSFSn pulses during each F-bit.
The RSFSn pulses during the first F-bit of every ESF/T1 DM/SLC-96 frame.
161
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RBIF TS Offset (049H, 149H)
Bit No.
7
Bit Name
Type
Reserved
6
5
4
3
2
1
0
TSOFF6
TSOFF5
TSOFF4
TSOFF3
TSOFF2
TSOFF1
TSOFF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Default
TSOFF[6:0]:
These bits give a binary number to define the channel offset. The channel offset is between the framing pulse on the RSFSn/MRSFS pin and the
start of the corresponding frame output on the RSDn/MRSD pin. The signaling bits on the RSIGn/MRSIG pin are always per-channel aligned with the
data on the RSDn/MRSD pin.
In Non-multiplexed mode, the channel offset can be configured from 0 to 23 channels (0 & 23 are included). In Multiplexed mode, the channel offset can be configured from 0 to 127 channels (0 & 127 are included).
T1/J1 RBIF Bit Offset (04AH, 14AH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
EDGE
BOFF2
BOFF1
BOFF0
R/W
R/W
R/W
R/W
0
0
0
0
EDGE:
This bit is valid when the CMS bit (b1, T1/J1-046H,...) is ‘1’.
= 0: The first active edge of RSCKn/MRSCK is selected to update the data on the RSDn/MRSD and RSIGn/MRSIG pins.
= 1: The second active edge of RSCKn/MRSCK is selected to update the data on the RSDn/MRSD and RSIGn/MRSIG pins.
BOFF[2:0]:
These bits give a binary number to define the bit offset. The bit offset is between the framing pulse on the RSFSn/MRSFS pin and the start of the
corresponding frame output on the RSDn/MRSD pin. The signaling bits on the RSIGn/MRSIG pin are always per-channel aligned with the data on the
RSDn/MRSD pin.
Programming Information
162
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RTSFS Change Indication (04BH, 14BH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
RCOFAI
TCOFAI
R
R
0
0
1
0
RCOFAE
TCOFAE
R/W
R/W
0
0
RCOFAI:
This bit is valid in Receive Clock Slave mode and Receive Multiplexed mode.
= 0: The interval of the pulses on the RSFSn/MRSFS pin is an integer multiple of 125 µs.
= 1: The interval of the pulses on the RSFSn/MRSFS pin is not an integer multiple of 125 µs.
This bit will be cleared if a ‘1’ is written to it.
TCOFAI:
This bit is valid in Transmit Clock Slave mode and Transmit Multiplexed mode.
= 0: The interval of the pulses on the TSFSn/MTSFS pin is an integer multiple of 125 µs.
= 1: The interval of the pulses on the TSFSn/MTSFS pin is not an integer multiple of 125 µs.
This bit will be cleared if a ‘1’ is written to it.
T1/J1 RTSFS Interrupt Control (04CH, 14CH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
RCOFAE:
= 0: Disable the interrupt on the INT pin when the RCOFAI bit (b1, T1/J1-04BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the RCOFAI bit (b1, T1/J1-04BH,...) is ‘1’.
TCOFAE:
= 0: Disable the interrupt on the INT pin when the TCOFAI bit (b0, T1/J1-04BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the TCOFAI bit (b0, T1/J1-04BH,...) is ‘1’.
Programming Information
163
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 FRMR Mode 0 (04DH, 14DH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
UNFM
REFCRCE
REFEN
REFR
R/W
R/W
R/W
R/W
0
1
1
0
UNFM:
= 0: The data stream is received in framed mode and is processed by the Frame Processor.
= 1: The data stream is received in unframed mode and the Frame Processor is bypassed.
REFCRCE:
In ESF format:
= 0: Disable from re-searching for synchronization when the Excessive CRC-6 Error occurs.
= 1: Search for synchronization again when the Excessive CRC-6 Error occurs. This function can only be implemented only if the REFEN bit is
logic 1.
REFEN:
= 0: “Locked in frame”. Once the previous frame synchronization is acquired, no errors can lead to reframe except for manually setting by the
REFR bit.
= 1: Search for synchronization again when it is out of synchronization.
REFR:
A transition from logic 0 to logic 1 forces to re-search for a new SF, ESF, T1 DM frame.
Programming Information
164
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 FRMR Mode 1 (04EH, 14EH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
DDSC
MIMICC
M2O1
M2O0
R/W
R/W
R/W
R/W
0
0
0
0
DDSC:
This bit selects the synchronization criteria of T1 DM format.
= 0: If a correct DDS pattern is received before the first F-bit of a single correct Frame Alignment Pattern and there is no mimic pattern, the T1 DM
synchronization is acquired.
= 1: If a single correct Frame Alignment Pattern is received, and twelve correct DDS patterns before each F-bit of the correct Frame Alignment
Pattern are all detected, and there is no mimic pattern, the T1 DM synchronization is acquired.
MIMICC:
This bit selects the synchronization criteria in SF format and ESF format.
In SF format:
= 0: When two consecutive Frame Alignment Patterns are received error free in the data stream, the SF is synchronized. In this case, the existence of mimic patterns is ignored.
= 1: When two consecutive Frame Alignment Patterns are received error free in the data stream without mimic pattern, the SF is synchronized.
In ESF format:
= 0: When a single correct Frame Alignment Pattern and a single correct CRC-6 are found in the same frame, the ESF is synchronized. In this
case, the existence of mimic patterns is ignored.
= 1: When four consecutive Frame Alignment Patterns are detected error free in the received data stream without mimic pattern, the ESF is synchronized.
M2O[2:1]:
In SF format, these two bits define the threshold of the F Bit Error numbers in N-bit sliding F bits window. Exceeding the threshold will lead to out
of synchronization.
In ESF format, these two bits define the threshold of the Frame Alignment Bit Error numbers in N-bit sliding Frame Alignment bits window.
Exceeding the threshold will lead to out of synchronization.
In T1 DM format, these two bits define the threshold of the 7-bit pattern error numbers in N-pattern sliding 7-bit patterns window. The 7-bit pattern
consists of the 6-bit DDS pattern and its following F-bit. Exceeding the threshold will lead to out of synchronization.
In SLC-96 format, these two bits define the threshold of the Ft bit error numbers in N-bit sliding Ft bits window or the Fs bit error numbers in N-bit
sliding Fs bits in Frame (2n) (0<n<12 and n=36) window. Exceeding the threshold will lead to out of synchronization.
Programming Information
M2O[1:0]
Error Numbers
N-Bit/Pattern Sliding Window
00
01
10
11
2
2
2
4
5
6
Reserved
165
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 FRMR Status (04FH, 14FH)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
OOFV
Type
Reserved
R
Default
1
OOFV:
= 0: The SF/ESF/T1 DM/SLC-96 frame is in synchronization.
= 1: The frame is out of synchronization.
T1/J1 FRMR Interrupt Control 0 (050H, 150H)
Bit No.
7
6
5
4
3
Bit Name
Type
2
1
0
OOFE
Reserved
Default
R/W
0
OOFE:
= 0: Disable the interrupt on the INT pin when the OOFI bit (b0, T1/J1-052H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the OOFI bit (b0, T1/J1-052H,...) is ‘1’.
Programming Information
166
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 FRMR Interrupt Control 1 (051H, 151H)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
2
1
0
RMFBE
SFEE
BEEE
FERE
COFAE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
RMFBE:
= 0: Disable the interrupt on the INT pin when the RMFBI bit (b4, T1/J1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the RMFBI bit (b4, T1/J1-053H,...) is ‘1’.
SFEE:
= 0: Disable the interrupt on the INT pin when the SFEI bit (b3, T1/J1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SFEI bit (b3, T1/J1-053H,...) is ‘1’.
BEEE:
= 0: Disable the interrupt on the INT pin when the BEEI bit (b2, T1/J1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the BEEI bit (b2, T1/J1-053H,...) is ‘1’.
FERE:
= 0: Disable the interrupt on the INT pin when the FERI bit (b1, T1/J1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the FERI bit (b1, T1/J1-053H,...) is ‘1’.
COFAE:
= 0: Disable the interrupt on the INT pin when the COFAI bit (b0, T1/J1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the COFAI bit (b0, T1/J1-053H,...) is ‘1’.
Programming Information
167
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 FRMR Interrupt Indication 0 (052H, 152H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
EXCRCERI
MIMICI
R
R
0
0
2
1
0
OOFI
Reserved
R
0
EXCRCERI:
In ESF format, once the accumulated CRC-6 errors exceed 319 (>319) in a 1 second fixed window, an excessive CRC-6 error event is generated
= 0: No Excessive CRC-6 Error event is detected.
= 1: The Excessive CRC-6 Error event is detected.
This bit will be cleared if a ’1’ is written to it.
MIMICI:
This bit is valid in SF and ESF formats.
= 0: No mimic pattern is detected in the received data stream.
= 1: Mimic pattern is detected in the received data stream.
This bit will be cleared if a ’1’ is written to it.
OOFI:
= 0: There is no status change on the OOFV bit (b0, T1/J1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the OOFV bit (b0, T1/J1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
Programming Information
168
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 FRMR Interrupt Indication 1 (053H, 153H)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
2
1
0
RMFBI
SFEI
BEEI
FERI
COFAI
R
R
R
R
R
0
0
0
0
0
RMFBI:
= 0: The received bit is not the first bit of each SF/ESF/T1 DM/SLC-96 frame.
= 1: The first bit of each SF/ESF/T1 DM/SLC-96 frame is received.
This bit will be cleared if a ’1’ is written to it. This bit can not be updated during out of synchronization state.
SFEI:
In SF format, each received Ft bit is compared with the expected one (refer to Table 12). Each unmatched Ft bit leads to an Ft bit error event.
When 2 or more Ft bit errors are detected in a 6-basic-frame fixed window, the severely Ft bit error occurs
= 0: No Severely Ft Bit Error event is detected.
= 1: The Severely Ft Bit Error event is detected.
In ESF format, when 2 or more frame alignment bit errors are detected in a 1-ESF-frame fixed window, the severely frame alignment bit error
occurs.
= 0: No Severely Frame Alignment Bit Error event is detected.
= 1: The Severely Frame Alignment Bit Error event is detected.
In T1 DM format, each received Ft bit is compared with the expected one (refer to Table 14). Each unmatched Ft bit leads to an Ft bit error event.
When 2 or more Ft bit errors are detected in a 6-basic-frame fixed window, the severely Ft bit error occurs.
= 0: No Severely Ft Bit Error event is detected.
= 1: The Severely Ft Bit Error event is detected.
This bit will be cleared if a ’1’ is written to it.
BEEI:
In ESF format, when the local calculated CRC-6 of the current received ESF frame does not match the received CRC-6 of the next received ESF
frame, a single CRC-6 error event is generated
= 0: No CRC-6 Error event is detected.
= 1: The CRC-6 Error event is detected.
This bit will be cleared if a ’1’ is written to it.
FERI:
In SF format, each received F bit is compared with the expected one (refer to Table 12). Each unmatched F bit leads to an F bit error event.
= 0: No F Bit Error event is detected.
= 1: The F Bit Error event is detected.
In ESF format, each received Frame Alignment bit is compared with the expected one (refer to Table 13). Each unmatched bit leads to a frame
alignment bit error event.
= 0: No Frame Alignment Bit Error event is detected.
= 1: The Frame Alignment Bit Error event is detected.
In T1 DM format, each received F bit is compared with the expected one (refer to Table 14). Each unmatched F bit leads to an F bit error event
= 0: No F Bit Error event is detected.
= 1: The F Bit Error event is detected.
In SLC-96 format, The Ft bit in each odd frame and the Fs bit in Frame (2n) (0<n<12 and n=36) is compared with the expected one (refer to
Table 15). Each unmatched bit leads to a F-bit error event.
= 0: No F Bit Error event is detected.
= 1: The F Bit Error event is detected.
This bit will be cleared if a ’1’ is written to it.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
COFAI:
= 0: The F bit position is not changed.
= 1: The new-found F bit position differs from the previous one.
This bit will be cleared if a ’1’ is written to it.
T1/J1 RDL0 (056H, 156H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
C8
C7
C6
C5
C4
C3
C2
C1
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
C[8:1]:
In SLC-96 format, these bits together with the C[11:9] bits reflect the content in the Concentrator bits. The C[1] bit is the LSB.
In de-bounce condition, these bits are updated if the received Concentrator bits are the same for 2 consecutive SLC-96 frames; otherwise they
are updated every SLC-96 frame.
They are held during out of SLC-96 synchronization state.
T1/J1 RDL1 (057H, 157H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
M3
M2
M1
C11
C10
C9
R
R
R
R
R
R
0
0
0
0
0
0
M[3:1]:
In SLC-96 format, these bits reflect the content in the Maintenance bits. The M[1] bit is the LSB.
In de-bounce condition, these bits are updated if the received Maintenance bits are the same for 2 consecutive SLC-96 frames; otherwise they
are updated every SLC-96 frame.
They are held during out of SLC-96 synchronization state.
C[11:9]:
In SLC-96 format, these bits together with the C[8:1] bits reflect the content in the Concentrator bits. The C[11] bit is the MSB.
In de-bounce condition, these bits are updated if the received Concentrator bits are the same for 2 consecutive SLC-96 frames; otherwise they
are updated every SLC-96 frame.
They are held during out of SLC-96 synchronization state.
Programming Information
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August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RDL2 (058H, 158H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
S4
S3
S2
S1
A2
A1
R
R
R
R
R
R
0
0
0
0
0
0
S[4:1]:
In SLC-96 format, these bits reflect the content in the Switch bits. The S[1] bit is the LSB.
In de-bounce condition, these bits are updated if the received Switch bits are the same for 2 consecutive SLC-96 frames; otherwise they are
updated every SLC-96 frame.
They are held during out of SLC-96 synchronization state.
A[2:1]:
In SLC-96 format, these bits reflect the content in the Alarm bits. The A[1] bit is the LSB.
In de-bounce condition, these bits are updated if the received Alarm bits are the same for 2 consecutive SLC-96 frames; otherwise they are
updated every SLC-96 frame.
They are held during out of SLC-96 synchronization state.
Programming Information
171
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 DLB Interrupt Control (05CH, 15CH)
Bit No.
7
6
5
Bit Name
Type
Reserved
Default
4
3
2
1
0
SCDEB
SCAE
SCSE
SCME
SCCE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
SCDEB:
= 0: Disable the de-bounce function of the overhead extraction.
= 1: Enable the de-dounce function of the overhead extraction.
SCAE:
= 0: Disable the interrupt on the INT pin when the SCAI bit (b3, T1/J1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SCAI bit (b3, T1/J1-05DH,...) is ‘1’.
SCSE:
= 0: Disable the interrupt on the INT pin when the SCSI bit (b2, T1/J1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SCSI bit (b2, T1/J1-05DH,...) is ‘1’.
SCME:
= 0: Disable the interrupt on the INT pin when the SCMI bit (b1, T1/J1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SCMI bit (b1, T1/J1-05DH,...) is ‘1’.
SCCE:
= 0: Disable the interrupt on the INT pin when the SCCI bit (b0, T1/J1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SCCI bit (b0, T1/J1-05DH,...) is ‘1’.
Programming Information
172
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 DLB Interrupt Indication (05DH, 15DH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
SCAI
SCSI
SCMI
SCCI
R
R
R
R
0
0
0
0
SCAI:
= 0: The value in the A[2:1] bits is not changed.
= 1: The value in the A[2:1] bits is changed.
SCSI:
= 0: The value in the S[4:1] bits is not changed.
= 1: The value in the S[4:1] bits is changed.
SCMI:
= 0: The value in the M[3:1] bits is not changed.
= 1: The value in the M[3:1] bits is changed.
SCCI:
= 0: The value in the C[11:1] bits is not changed.
= 1: The value in the C[11:1] bits is changed.
Programming Information
173
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Mode (062H, 162H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
FDLBYP
CRCBYP
FDIS
R/W
R/W
R/W
0
0
0
FDLBYP:
In ESF format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: Enable the DL bit position to be replaced by the Bit-Oriented Code, the Automatic Performance Report Message, the HDLC data or the idle
code (‘FFFF’ for T1 / ‘FF7E’ for J1).
= 1: Disable the DL bit position to be replaced by the above codes.
In T1 DM format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: The ‘D’ bit in Bit 6 of each Channel 24 is replaced with the HDLC data.
= 1: Disable the D bit position to be replaced by the HDLC data.
In SLC-96 format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: The Concentrator (C) bit, the Maintenance (M) bit, the Alarm (A) bit and the Switch (S) bit are replaced by the contents in the C[11:1] bits
(b2~0, T1/J1-066H,... & b7~0, T1/J1-065H,...), the M[3:1] bits (b5~3, T1/J1-066H,...), the A[2:1] bits (b1~0, T1/J1-067H,...) and the S[4:1] bits (b5~2,
T1/J1-067H,...) respectively.
= 1: Disable the Concentrator (C) bit, the Maintenance (M) bit, the Alarm (A) bit and the Switch (S) bit replacement.
CRCBYP:
This bit is valid in ESF format when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: The calculated 6-bit CRC of the previous ESF frame is inserted in the current CRC-bit positions in every 4th frame starting with Frame 2 of
the current ESF frame.
= 1: Disable the CRC-6 insertion.
FDIS:
= 0: Enable the generation of the SF / ESF / T1 DM / SLC-96 frame.
= 1: Disable the generation of the SF / ESF / T1 DM / SLC-96 frame.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 XDL0 (065H, 165H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
C8
C7
C6
C5
C4
C3
C2
C1
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
C[8:1]:
These bits, together with the C[11:9] bits (b2~0, T1/J1-066H,...), are valid in SLC-96 format when the FDIS bit (b0, T1/J1-062H,...) and the FDLBYP bit (b2, T1/J1-062H,...) are both ‘0’s. They contain the data to replace the Concentrator (C) bit. The C[1] is the LSB and it is transmitted first.
T1/J1 XDL1 (066H, 166H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
M3
M2
M1
C11
C10
C9
R
R
R
R
R
R
0
0
0
0
0
0
M[3:1]:
These bits are valid in SLC-96 format when the FDIS bit (b0, T1/J1-062H,...) and the FDLBYP bit (b2, T1/J1-062H,...) are both ‘0’s. They contain
the data to replace the Maintenance (M) bit. The M[1] is transmitted first.
C[11:9]:
These bits, together with the C[8:1] bits (b7~1, T1/J1-065H,...), are valid in SLC-96 format when the FDIS bit (b0, T1/J1-062H,...) and the FDLBYP bit (b2, T1/J1-062H,...) are both ‘0’s. They contain the data to replace the Concentrator (C) bit. The C[11] is the MSB and it is transmitted last.
Programming Information
175
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 XDL2 (067H, 167H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
S4
S3
S2
S1
A2
A1
R
R
R
R
R
R
0
0
0
0
0
0
S[4:1]:
These bits are valid in SLC-96 format when the FDIS bit (b0, T1/J1-062H,...) and the FDLBYP bit (b2, T1/J1-062H,...) are both ‘0’s. They contain
the data to replace the Switch (S) bit. The S[1] is transmitted first.
A[2:1]:
These bits are valid in SLC-96 format when the FDIS bit (b0, T1/J1-062H,...) and the FDLBYP bit (b2, T1/J1-062H,...) are both ‘0’s. They contain
the data to replace the Alarm (A) bit. The A[1] is transmitted first.
T1/J1 FGEN Maintenance 0 (06BH, 16BH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
AUTOYELLOW
XYEL
R/W
R/W
0
0
AUTOYELLOW:
= 0: Disable the automatic Yellow alarm signal insertion.
= 1: The Yellow alarm signal is automatically inserted into the data stream to be transmitted when Red alarm is declared in the received data
stream.
XYEL:
= 0: Disable the manual Yellow alarm signal insertion.
= 1: The Yellow alarm signal is manually inserted into the data stream to be transmitted.
Programming Information
176
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 FGEN Maintenance 1 (06CH, 16CH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
MIMICEN
COFAEN
TXDIS
TAIS
R/W
R/W
R/W
R/W
0
0
0
0
MIMICEN:
This bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: Disable the mimic pattern insertion.
= 1: The mimic pattern is inserted into the bit right after each F-bit. The content of the mimic pattern is the same as the F-bit.
COFAEN:
Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on this bit will lead to one bit deletion or one bit repetition in the data stream to be transmitted, that
is, to change the frame alignment position. The one bit deletion or repetition occurs randomly.
TXDIS:
= 0: Normal operation.
= 1: The data stream to be transmitted are overwritten with all ‘Zero’s.
TAIS:
= 0: Normal operation.
= 1: The data stream to be transmitted are overwritten with all ’One’s.
Programming Information
177
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 FGEN Interrupt Control (06DH, 16DH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
MFE
BFE
R/W
R/W
0
0
1
0
MFI
BFI
R
R
0
0
MFE:
= 0: Disable the interrupt on the INT pin when the MFI bit (b1, T1/J1-06EH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the MFI bit (b1, T1/J1-06EH,...) is ‘1’.
BFE:
= 0: Disable the interrupt on the INT pin when the BFI bit (b0, T1/J1-06EH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the BFI bit (b0, T1/J1-06EH,...) is ‘1’.
T1/J1 FGEN Interrupt Indication (06EH, 16EH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
MFI:
= 0: The bit input to the Frame Generator is not the first bit of each SF/ESF/T1 DM/SLC-96 multiframe.
= 1: The first bit of each SF/ESF/T1 DM/SLC-96 multiframe is input to the Frame Generator.
This bit will be cleared if a ’1’ is written to it.
BFI:
= 0: The bit input to the Frame Generator is not the first bit of each basic frame.
= 1: The first bit of each basic frame is input to the Frame Generator.
This bit will be cleared if a ’1’ is written to it.
Programming Information
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August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Error Insertion (06FH, 16FH)
Bit No.
7
6
5
4
Bit Name
Type
3
2
1
0
DDSINV
CRCINV
FsINV
FtINV
R/W
R/W
R/W
R/W
0
0
0
0
Reserved
Default
DDSINV:
This bit is valid in T1 DM format when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit wil invert one 6-bit DDS pattern.
This bit is cleared when the inversion is completed.
CRCINV:
This bit is valid in ESF format when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one 6-bit CRC pattern.
This bit is cleared when the invertion is completed.
FsINV:
In SF, T1 DM formats, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one Fs bit (the F-bit in even frame).
In ESF format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one Frame Alignment bit.
In SLC-96 format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one Synchronization Fs bit.
This bit is cleared when the inversion is completed.
FtINV:
In SF, T1 DM, SLC-96 formats, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one Ft bit (the F-bit in odd frame).
This bit is cleared when the inversion is completed.
Programming Information
179
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Transmit Timing Option (070H, 170H)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
XTS
Type
Reserved
R/W
Default
0
XTS:
In Transmit Clock Master mode:
= 0: The source of the transmit clock is selected from the clock generated by the internal clock generator (1.544 MHz).
= 1: The source of the transmit clock is selected from the recovered clock from the line side.
In Transmit Clock Master mode, the Transmit Buffer is bypassed automatically.
In Transmit Clock Slave T1/J1 mode E1 rate, this bit is invalid. In the other Transmit Clock Slave modes and in Transmit Multiplexed mode:
= 0: The source of the transmit clock is selected from the clock from the backplane. The Transmit Buffer is bypassed.
= 1: The source of the transmit clock is selected from the clock generated by the internal clock generator (1.544 MHz). The Transmit Buffer is not
bypassed.
T1/J1 PRGD Control (071H, 171H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
RINV
TINV
PATS1
PATS0
R/W
R/W
R/W
R/W
0
0
0
0
RINV:
= 0: The data is not inverted before extracted to the pattern detector.
= 1: The data is inverted before extracted to the pattern detector.
TINV:
= 0: The generated pattern is not inverted.
= 1: The generated pattern is inverted.
PATS[1:0]:
These bits select the PRBS generated and detected pattern.
= 00: The 215-1 pattern per O.152 is selected.
= 01: The 220-1 pattern per O.150-4.5 is selected.
= 10: The 211-1 pattern per O.150 is selected.
= 11: Reserved.
Programming Information
180
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 PRGD Status/Error Control (072H, 172H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
BERE
INV
SYNCV
SYNCE
R/W
R/W
R
R/W
0
0
0
0
BERE:
= 0: Disable the interrupt on the INT pin when the BERI bit (b3, T1/J1-073H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the BERI bit (b3, T1/J1-073H,...) is ‘1’.
INV:
= 0: No bit error is inserted to the generated pattern.
= 1: A single bit error is inserted to the generated pattern.
This bit is cleared after the single bit error insertion is completed.
SYNCV:
= 0: The pattern is out of synchronization (the pattern detector has detected 10 or more bit errors in a fixed 48-bit window).
= 1: The pattern is in synchronization (the pattern detector has detected at least 48 consecutive error-free bit periods).
SYNCE:
= 0: Disable the interrupt on the INT pin when the SYNCI bit (b0, T1/J1-073H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SYNCI bit (b0, T1/J1-073H,...) is ‘1’.
T1/J1 PRGD Interrupt Indication (073H, 173H)
Bit No.
7
6
5
4
3
Bit Name
Type
2
1
BERI
Reserved
R
Default
0
SYNCI
Reserved
0
R
0
BERI:
= 0: No bit is mismatched with the PRGD pattern when the extracted data is in synchronization state.
= 1: At least one bit is mismatched with the PRGD pattern when the extracted data is in synchronization state.
This bit will be cleared if a ’1’ is written to it.
SYNCI:
= 0: There is no status change on the SYNCV bit (b1, T1/J1-072H,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the SYNCV bit (b1, T1/J1-072H,...).
This bit will be cleared if a ’1’ is written to it.
Programming Information
181
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 XIBC Control (074H, 174H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
IBCDEN
IBCDUNFM
CL1
CL0
R/W
R/W
R/W
R/W
0
0
0
0
IBCDEN:
= 0: Disable transmitting the inband loopback code.
= 1: Enable transmitting the inband loopback code.
IBCDUNFM:
= 0: The inband loopback code is transmitted in framed mode, that is, the bits in all 24 channels are overwritten with the inband loopback code
and the F-bit is not changed.
= 1: The inband loopback code is transmitted in unframed mode, that is, all the bits in 24 channels and the F-bit are overwritten with the inband
loopback code.
CL[1:0]:
These 2 bits define the length of the inband loopback code to be transmitted, meanwhile, they define the valid code in the IBC[7:0] bits (b7~0, T1/
J1-075H,...).
CL[1:0]
Loopback Code Length & Valid Code In The IBC[7:0]
00
01
10
11
5-bit length & the code in the IBC[7:3] is valid
6-bit length & the code in the IBC[7:2] is valid
7-bit length & the code in the IBC[7:1] is valid
8-bit length & the code in the IBC[7:0] is valid
T1/J1 XIBC Code (075H, 175H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
IBC[7:0]:
The IBC[7:X] bits define the content of the inband loopback code. The ‘X’ is one of 0 to 3 which depends on the length defined by the CL[1:0] bits
(b1~0, T1/J1-074H,...). The IBC[7] is the MSB.
Programming Information
182
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 IBCD Detector Configuration (076H, 176H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
IBCDIDLE
DSEL1
DSEL0
ASEL1
ASEL0
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
IBCDIDLE:
= 0: The F-bit is compared with the target activate/deactivate inband loopback code, but the result of the F-bit comparison is discarded.
= 1: The F-bit is skipped in the comparison process.
DSEL[1:0]:
These two bits define the length of the target deactivate inband loopback code, meanwhile, they define the valid code in the DACT[7:0] bits
(b7~0, T1/J1-079H,...).
DSEL[1:0]
Deactivate Code Length & Valid Code In The DACT[7:0]
00
01
10
11
5-bit length & the code in the DACT[7:3] is valid
6-bit or 3-bit length & the code in the DACT[7:2] is valid
7-bit length & the code in the DACT[7:1] is valid
8-bit or 4-bit length & the code in the DACT[7:0] is valid
ASEL[1:0]:
These two bits define the length of the target activate inband loopback code, meanwhile, they define the valid code in the ACT[7:0] bits (b7~0, T1/
J1-078H,...).
Programming Information
ASEL[1:0]
Activate Code Length & Valid Code In The ACT[7:0]
00
01
10
11
5-bit length & the code in the ACT[7:3] is valid
6-bit or 3-bit length & the code in the ACT[7:2] is valid
7-bit length & the code in the ACT[7:1] is valid
8-bit or 4-bit length & the code in the ACT[7:0] is valid
183
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 IBCD Detector Status (077H, 177H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
LBA
LBD
R
R
0
0
LBA:
= 0: The activate code is loss. That is, more than 600 bits are not matched with the target activate inband loopback code in a 39.8ms fixed period.
= 1: The activate code is detected. That is, in more than 126 consecutive 39.8ms fixed periods, the target activate inband loopback code is
matched with less than 600 bit errors in each 39.8ms.
LBD:
= 0: The deactivate code is loss. That is, more than 600 bits are not matched with the target deactivate inband loopback code in a 39.8ms fixed
period.
= 1: The deactivate code is detected. That is, in more than 126 consecutive 39.8ms fixed periods, the target deactivate inband loopback code is
matched with less than 600 bit errors in each 39.8ms.
T1/J1 IBCD Activate Code (078H, 178H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
ACT7
ACT6
ACT5
ACT4
ACT3
ACT2
ACT1
ACT0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
1
0
0
0
ACT[7:0]:
The ACT[7:X] bits define the content of the target activate inband loopback code. The ‘X’ is 3, 2, 1 or 0 which depends on the definition by the
ASEL[1:0] bits (b1~0, T1/J1-076H,...). The unused bits should be ignored. The ACT[7] bit is the MSB and compares with the first received code bit.
T1/J1 IBCD Deactivate Code (079H, 179H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DACT7
DACT6
DACT5
DACT4
DACT3
DACT2
DACT1
DACT0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
1
0
0
1
0
0
DACT[7:0]:
The DACT[7:X] bits define the content of the target deactivate inband loopback code. The ‘X’ is 3, 2, 1 or 0 which depends on the definition by the
DSEL[1:0] bits (b3~2, T1/J1-076H,...). The unused bits should be ignored. The DACT[7] bit is the MSB and compares with the first received code bit.
Programming Information
184
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 IBCD Interrupt Control (07AH, 17AH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
LBAE
LBDE
R/W
R/W
0
0
1
0
LBAI
LBDI
R
R
0
0
LBAE:
= 0: Disable the interrupt on the INT pin when the LBAI bit (b1, T1/J1-07BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the LBAI bit (b1, T1/J1-07BH,...) is ‘1’.
LBDE:
= 0: Disable the interrupt on the INT pin when the LBDI bit (b0, T1/J1-07BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the LBDI bit (b0, T1/J1-07BH,...) is ‘1’.
T1/J1 IBCD Interrupt Indication (07BH, 17BH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
LBAI:
= 0: There is no status change on the LBA bit (b1, T1/J1-077H,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LBA bit (b1, T1/J1-077H,...).
This bit will be cleared if a ’1’ is written to it.
LBDI:
= 0: There is no status change on the LBD bit (b0, T1/J1-077H,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LBD bit (b0, T1/J1-077H,...).
This bit will be cleared if a ’1’ is written to it.
Programming Information
185
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 ELST Configuration (07CH, 17CH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
TRKEN
SLIPD
SLIPE
R/W
R
R/W
0
0
0
TRKEN:
In Receive Clock Slave mode and Receive Multiplexed mode, if it is out of synchronization, the trunk code programmed in the TRKCODE[7:0]
bits (b7~0, T1/J1-07EH,...) can be set to replace the data or not.
= 0: Disable the replacement.
= 1: Enable the replacement.
SLIPD:
This bit makes sense only when the SLIPI bit (b0, T1/J1-07DH,...) is ‘1’.
= 0: The latest slip is due to the Elastic Store Buffer being empty.
= 1: The latest slip is due to the Elastic Store Buffer being full.
SLIPE:
= 0: Disable the interrupt on the INT pin when the SLIPI bit (b0, T1/J1-07DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SLIPI bit (b0, T1/J1-07DH,...) is ‘1’.
T1/J1 ELST Interrupt Indication (07DH, 17DH)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
SLIPI
Type
Reserved
R
Default
0
SLIPI:
= 0: No slip occurs.
= 1: A slip occurs.
This bit will be cleared if a ’1’ is written to it.
T1/J1 ELST Trunk Code (07EH, 17EH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
TRKCODE7
TRKCODE6
TRKCODE5
TRKCODE4
TRKCODE3
TRKCODE2
TRKCODE1
TRKCODE0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
1
1
1
1
1
1
1
TRKCODE[7:0]:
In Receive Clock Slave mode and Receive Multiplexed mode, if it is out of synchronization and the TRKEN bit (b2, T1/J1-07CH,...) is ‘1’, these
bits are the trunk code to replace the received data stream.
Programming Information
186
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 APRM Control (07FH, 17FH)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
LBBIT
U2BIT
U1BIT
RBIT
CRBIT
AUTOPRM
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
LBBIT:
This bit is valid in ESF format when the AUTOPRM bit (b0, T1/J1-07FH,...) is ‘1’. The value in this bit will be transmitted in the LB bit position of
the APRM.
U2BIT:
This bit is valid in ESF format when the AUTOPRM bit (b0, T1/J1-07FH,...) is ‘1’. The value in this bit will be transmitted in the U2 bit position of
the APRM.
U1BIT:
This bit is valid in ESF format when the AUTOPRM bit (b0, T1/J1-07FH,...) is ‘1’. The value in this bit will be transmitted in the U1 bit position of
the APRM.
RBIT:
This bit is valid in ESF format when the AUTOPRM bit (b0, T1/J1-07FH,...) is ‘1’. The value in this bit will be transmitted in the R bit position of the
APRM.
CRBIT:
This bit is valid in ESF format when the AUTOPRM bit (b0, T1/J1-07FH,...) is ‘1’. The value in this bit will be transmitted in the CR bit position of
the APRM.
AUTOPRM:
This bit is only valid in ESF format.
= 0: Disable the APRM transmission.
= 1: The Automatic Performance Report Message (APRM) is generated every one second and transmitted on the DL bit positions.
Programming Information
187
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 XBOC Code (080H, 180H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
XBOC5
XBOC4
XBOC3
XBOC2
XBOC1
XBOC0
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
XBOC[5:0]:
These bits are only valid in the ESF format.
When the XBOC[5:0] bits are written with any 6-bit code other than the ‘111111’, the code will be transmitted as the Bit Oriented Message (BOM).
The BOM pattern is ‘111111110XBOC[0]XBOC[1]XBOC[2]XBOC[3]XBOC[4]XBOC[5]0’ which occupies the DL of the F-bit position.
T1/J1 BOC Control (081H, 181H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
AVC
BOCE
R/W
R/W
0
0
AVC:
This bit selects the validation criteria used to declare the Bit Oriented Message (BOM) in the received data stream. It is only valid in ESF format.
= 0: The BOM is declared when the pattern is matched and the received message is identical 8 out of 10 consecutive times and differs from the
previous message.
= 1: The BOM is declared when the pattern is matched and the received message is identical 4 out of 5 consecutive times and differs from the
previous message.
BOCE:
= 0: Disable the interrupt on the INT pin when the BOCI bit (b0, T1/J1-082H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the BOCI bit (b0, T1/J1-082H,...) is ‘1’.
Programming Information
188
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 BOC Interrupt Indication (082H, 182H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
BOCI
Type
Reserved
R
Default
0
BOCI:
= 0: The BOC[5:0] bits (b5~0, T1/J1-083H,...) are not updated.
= 1: The BOC[5:0] bits (b5~0, T1/J1-083H,...) are updated.
This bit will be cleared if a ’1’ is written to it.
T1/J1 RBOC Code (083H, 183H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
BOC5
BOC4
BOC3
BOC2
BOC1
BOC0
R
R
R
R
R
R
1
1
1
1
1
1
BOC[5:0]:
When the received BOM is declared, the message is loaded into these bits. The BOC[5] bit corresponds to the LSB of the message.
Programming Information
189
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 THDLC Enable Control (084H, 184H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
TDLEN3
TDLEN2
TDLEN1
R/W
R/W
R/W
0
0
0
TDLEN3:
= 0: All the functions of the HDLC Transmitter #3 is disabled.
= 1: All the functions of the HDLC Transmitter #3 is enabled.
TDLEN2:
= 0: All the functions of the HDLC Transmitter #2 is disabled.
= 1: All the functions of the HDLC Transmitter #2 is enabled.
TDLEN1:
This bit is only valid in T1/J1 mode ESF & T1 DM formats.
= 0: All the functions of the HDLC Transmitter #1 is disabled.
= 1: All the functions of the HDLC Transmitter #1 is enabled.
Programming Information
190
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 THDLC2 Assignment (086H, 186H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
T1/J1 THDLC3 Assignment (087H, 187H)
Bit No.
7
Bit Name
Type
Reserved
Default
The function of the above two sets of registers are the same. However, they correspond to different THDLC.
EVEN:
= 0: The data is not inserted to the even frames.
= 1: The data is inserted to the even frames.
ODD:
= 0: The data is not inserted to the odd frames.
= 1: The data is inserted to the odd frames.
TS[4:0]:
These bits binary define one channel of even and/or odd frames to insert the data to. ‘00000’ corresponds to CH 1 and ‘10111’ corresponds to CH
24. The value above ‘10111’ is meanless. These bits are invalid when the EVEN bit and the ODD bit are both ‘0’.
Programming Information
191
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 THDLC2 Bit Select (089H, 189H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
T1/J1 THDLC3 Bit Select (08AH, 18AH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
The function of the above two sets of registers are the same. However, they correspond to different THDLC.
BITENn:
= 0: The data is not inserted to the corresponding bit.
= 1: The data is inserted to the corresponding bit of the assigned channel.
These bits are invalid when the EVEN bit and the ODD bit are both logic 0.
The BITEN[7] bit corresponds to the first bit (MSB) of the selected channel.
Programming Information
192
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RHDLC Enable Control (08BH, 18BH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
RDLEN3
RDLEN2
RDLEN1
R/W
R/W
R/W
0
0
0
RDLEN3:
= 0: All the functions of the HDLC Receiver #3 is disabled.
= 1: All the functions of the HDLC Receiver #3 is enabled.
RDLEN2:
= 0: All the functions of the HDLC Receiver #2 is disabled.
= 1: All the functions of the HDLC Receiver #2 is enabled.
RDLEN1:
This bit is only valid in T1/J1 mode ESF & T1 DM formats.
= 0: All the functions of the HDLC Receiver #1 is disabled.
= 1: All the functions of the HDLC Receiver #1 is enabled.
Programming Information
193
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RHDLC2 Assignment (08DH, 18DH)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
T1/J1 RHDLC3 Assignment (08EH, 18EH)
Bit No.
7
Bit Name
Type
Reserved
Default
The function of the above two sets of registers are the same. However, they correspond to different RHDLC.
EVEN:
= 0: The data is not extracted from the even frames.
= 1: The data is extracted from the even frames.
ODD:
= 0: The data is not extracted from the odd frames.
= 1: The data is extracted from the odd frames.
TS[4:0]:
These bits binary define one channel of even and/or odd frames to extract the data from. ‘00000’ corresponds to CH 1 and ‘10111’ corresponds
to CH 24. The value above ‘10111’ is meanless. These bits are invalid when the EVEN bit and the ODD bit are both ‘0’.
Programming Information
194
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RHDLC2 Bit Select (090H, 190H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
T1/J1 RHDLC3 Bit Select (091H, 191H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
The function of the above two sets of registers are the same. However, they correspond to different RHDLC.
BITENn:
= 0: The data is not extracted from the corresponding bit.
= 1: The data is extracted from the corresponding bit of the assigned channel.
These bits are invalid when the EVEN bit and the ODD bit are both logic 0.
The BITEN[7] bit corresponds to the first bit (MSB) of the selected channel.
Programming Information
195
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RHDLC1 Control Register (092H, 192H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
ADRM1
ADRM0
RHDLCM
RRST
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
ADRM1
ADRM0
RHDLCM
RRST
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
ADRM1
ADRM0
RHDLCM
RRST
R/W
R/W
R/W
R/W
0
0
0
0
T1/J1 RHDLC2 Control Register (093H, 193H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
T1/J1 RHDLC3 Control Register (094H, 194H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
ADRM[1:0]:
These two bits select the address comparison mode in HDLC mode.
= 00: No address is compared.
= 01: High byte address is compared.
= 10: Low byte address is compared.
= 11: Both high byte address and low byte address are compared.
RHDLCM:
= 0: HDLC mode is selected.
= 1: Reserved
Programming Information
196
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RRST:
A transition from ‘0’ to ‘1’ on this bit resets the corresponding HDLC Receiver. The reset will clear the FIFO, the PACK bit (b0, T1/J1-095H,... /
096H,... / 097H,...) and the EMP bit (b1, T1/J1-095H,... / 096H,... / 097H,...).
T1/J1 RHDLC1 RFIFO Access Status (095H, 195H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
EMP
PACK
R
R
1
0
1
0
EMP
PACK
R
R
1
0
1
0
EMP
PACK
R
R
1
0
T1/J1 RHDLC2 RFIFO Access Status (096H, 196H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
T1/J1 RHDLC3 RFIFO Access Status (097H, 197H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
EMP:
= 0: The FIFO is not empty.
= 1: The FIFO is empty, i.e., all the blocks are read from the FIFO.
The corresponding HDLC Receiver reset will clear this bit.
PACK:
= 0: The byte read from the FIFO is not an overhead byte.
= 1: The byte read from the FIFO is an overhead byte.
The corresponding HDLC Receiver reset will clear this bit.
Programming Information
197
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RHDLC1 Data (098H, 198H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
T1/J1 RHDLC2 Data (099H, 199H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
T1/J1 RHDLC3 Data (09AH, 19AH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
DAT[7:0]:
These bits represent the bytes read from the FIFO. The DAT[0] bit corresponds to the first bit of the serial received data from the FIFO.
Programming Information
198
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RHDLC1 Interrupt Control (09BH, 19BH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
OVFLE
RMBEE
R/W
R/W
0
0
1
0
OVFLE
RMBEE
R/W
R/W
0
0
1
0
OVFLE
RMBEE
R/W
R/W
0
0
T1/J1 RHDLC2 Interrupt Control (09CH, 19CH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
T1/J1 RHDLC3 Interrupt Control (09DH, 19DH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
OVFLE:
= 0: Disable the interrupt on the INT pin when the OVFLI bit (b1, T1/J1-09EH,... / 09FH,... / 0A0H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the OVFLI bit (b1, T1/J1-09EH,... / 09FH,... / 0A0H,...) is ‘1’.
RMBEE:
= 0: Disable the interrupt on the INT pin when the RMBEI bit (b0, T1/J1-09EH,... / 09FH,... / 0A0H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the RMBEI bit (b0, T1/J1-09EH,... / 09FH,... / 0A0H,...) is ‘1’.
Programming Information
199
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RHDLC1 Interrupt Indication (09EH, 19EH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
OVFLI
RMBEI
R
R
0
0
1
0
OVFLI
RMBEI
R
R
0
0
1
0
OVFLI
RMBEI
R
R
0
0
T1/J1 RHDLC2 Interrupt Indication (09FH, 19FH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
T1/J1 RHDLC3 Interrupt Indication (0A0H, 1A0H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
OVFLI:
The overwritten condition will occur if data is still attempted to write into the FIFO when the FIFO has already been full (128 bytes).
= 0: No overwriting occurs.
= 1: The overwriting occurs.
This bit will be cleared if a ’1’ is written to it.
RMBEI:
= 0: No block is pushed into the FIFO.
= 1: A block of the HDLC packet is pushed into the FIFO.
This bit will be cleared if a ’1’ is written to it.
Programming Information
200
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RHDLC1 High Address (0A1H, 1A1H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
HA7
HA6
HA5
HA4
HA3
HA2
HA1
HA0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
T1/J1 RHDLC2 High Address (0A2H, 1A2H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
HA7
HA6
HA5
HA4
HA3
HA2
HA1
HA0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
T1/J1 RHDLC3 High Address (0A3H, 1A3H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
HA7
HA6
HA5
HA4
HA3
HA2
HA1
HA0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
HA[7:0]:
In HDLC mode, when high byte address comparison or both bytes address comparison is required, the high byte address position (the byte following the opening flag) is compared with the value in these bits, or with ‘0xFC’ or ‘0xFE’. The HA[1] bit (the ‘C/R’ bit position) is excluded to compare.
Programming Information
201
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RHDLC1 Low Address (0A4H, 1A4H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
LA7
LA6
LA5
LA4
LA3
LA2
LA1
LA0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
T1/J1 RHDLC2 Low Address (0A5H, 1A5H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
LA7
LA6
LA5
LA4
LA3
LA2
LA1
LA0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
T1/J1 RHDLC3 Low Address (0A6H, 1A6H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
LA7
LA6
LA5
LA4
LA3
LA2
LA1
LA0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
LA[7:0]:
In HDLC mode, when low byte address comparison is required, the high byte address position (the byte following the opening flag) is compared
with the value in these bits. When both bytes address comparison is required, the low byte address position (the byte following the high byte address
position) is compared with the value in these bits.
Programming Information
202
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 THDLC1 Control (0A7H, 1A7H)
Bit No.
7
6
5
Bit Name
4
3
EOM
Type
Reserved
R/W
Default
Reserved
0
2
1
0
ABORT
THDLCM
TRST
R/W
R/W
R/W
0
0
0
2
1
0
ABORT
THDLCM
TRST
R/W
R/W
R/W
0
0
0
2
1
0
ABORT
THDLCM
TRST
R/W
R/W
R/W
0
0
0
T1/J1 THDLC2 Control (0A8H, 1A8H)
Bit No.
7
6
5
Bit Name
4
3
EOM
Type
Reserved
R/W
Default
Reserved
0
T1/J1 THDLC3 Control (0A9H, 1A9H)
Bit No.
7
6
Bit Name
Type
Default
5
4
3
EOM
Reserved
R/W
Reserved
0
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
EOM:
A transition from ‘0’ to ‘1’ on this bit indicates an entire HDLC packet is stored in the FIFO and starts the packet transmission.
ABORT:
= 0: Disable the manual abort sequence insertion.
= 1: The abort sequence (‘01111111’) is manually inserted to the current HDLC packet.
This bit is self-cleared after the abortion.
THDLCM:
= 0: HDLC mode is selected.
= 1: Reserved.
TRST:
A transition from ‘0’ to ‘1’ on the this bit resets the corresponding HDLC Transmitter. The reset will clear the FIFO.
Programming Information
203
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 TFIFO1 Threshold (0AAH, 1AAH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
LL1
LL0
HL1
HL0
R/W
R/W
R/W
R/W
0
0
0
1
3
2
1
0
LL1
LL0
HL1
HL0
R/W
R/W
R/W
R/W
0
0
0
1
3
2
1
0
LL1
LL0
HL1
HL0
R/W
R/W
R/W
R/W
0
0
0
1
T1/J1 TFIFO2 Threshold (0ABH, 1ABH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
T1/J1 TFIFO3 Threshold (0ACH, 1ACH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
LL[1:0]:
These 2 bits set the lower threshold of the FIFO. If the fill level is below the lower threshold, an interrupt may be generated.
= 00: 16 bytes
= 01: 32 bytes
= 10: 64 bytes
= 11: 96 bytes
HL[1:0]:
These 2 bits set the upper threshold of the FIFO. Once the fill level exceeds the upper threshold, the data stored in the FIFO will start to be transmitted.
= 00: 16 bytes
= 01: 32 bytes
= 10: 64 bytes
= 11: 128 bytes
Programming Information
204
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 THDLC1 Data (0ADH, 1ADH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
T1/J1 THDLC2 Data (0AEH, 1AEH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
T1/J1 THDLC3 Data (0AFH, 1AFH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
DAT[7:0]:
The bytes to be stored in the FIFO. The DAT[0] bit corresponds to the first bit of the serial data in the FIFO to be transmitted.
Programming Information
205
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 TFIFO1 Status (0B0H, 1B0H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
FUL
EMP
RDY
R
R
R
0
1
1
2
1
0
FUL
EMP
RDY
R
R
R
0
1
1
2
1
0
FUL
EMP
RDY
R
R
R
0
1
1
T1/J1 TFIFO2 Status (0B1H, 1B1H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
T1/J1 TFIFO3 Status (0B2H, 1B2H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
FUL:
= 0: The FIFO is not full.
= 1: The FIFO is full of 128 bytes.
EMP:
= 0: The FIFO is not empty.
= 1: The FIFO is empty.
RDY:
= 0: The fill level of the FIFO is not below the lower threshold set by the LL[1:0] bits (b3~2, T1/J1-0AAH,... / 0ABH,... / 0ACH,...).
= 1: The fill level of the FIFO is below the lower threshold set by the LL[1:0] bits (b3~2, T1/J1-0AAH,... / 0ABH,... / 0ACH,...).
Programming Information
206
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 THDLC1 Interrupt Control (0B3H, 1B3H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
UDRUNE
RDYE
R/W
R/W
0
0
1
0
UDRUNE
RDYE
R/W
R/W
0
0
1
0
UDRUNE
RDYE
R/W
R/W
0
0
T1/J1 THDLC2 Interrupt Control (0B4H, 1B4H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
T1/J1 THDLC3 Interrupt Control (0B5H, 1B5H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
UDRUNE:
= 0: Disable the interrupt on the INT pin when the UDRUNI bit (b1, T1/J1-0B6H,... / 0B7H,... / 0B8H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the UDRUNI bit (b1, T1/J1-0B6H,... / 0B7H,... / 0B8H,...) is ‘1’.
RDYE:
= 0: Disable the interrupt on the INT pin when the RDYI bit (b0, T1/J1-0B6H,... / 0B7H,... / 0B8H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the RDYI bit (b0, T1/J1-0B6H,... / 0B7H,... / 0B8H,...) is ‘1’.
Programming Information
207
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 THDLC1 Interrupt Indication (0B6H, 1B6H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
UDRUNI
RDYI
R
R
0
0
1
0
UDRUNI
RDYI
R
R
0
0
1
0
UDRUNI
RDYI
R
R
0
0
T1/J1 THDLC2 Interrupt Indication (0B7H, 1B7H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
T1/J1 THDLC3 Interrupt Indication (0B8H, 1B8H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
UDRUNI:
When the FIFO is empty and the last transmitted byte is not the end of the current HDLC packet, the under-run occurs. This bit indicates whether
the under-run occurs.
= 0: No under-run occurs.
= 1: Under-run occurs.
This bit will be cleared if a ’1’ is written to it.
RDYI:
= 0: There is no status change on the RDY bit (b0, T1/J1-0B0H,... / 0B1H,... / 0B2H,...).
= 1: There is a transition (from ‘0’ to ‘1’) on the RDY bit (b0, T1/J1-0B0H,... / 0B1H,... / 0B2H,...).
This bit will be cleared if a ’1’ is written to it.
Programming Information
208
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Alarm Status (0B9H, 1B9H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
AIS
YEL
RED
R
R
R
0
0
0
AIS:
= 0: More than 60 zeros are detected in a 40ms fixed window and this status persists for Mx40ms. Here ‘M’ is decided by the AISCTH[7:0] bits
(b7~0, T1/J1-0C1H,...).
= 1: Less than 61 zeros are detected in a 40ms fixed window and this status persists for Nx40ms. Here ‘N’ is decided by the AISDTH[7:0] bits
(b7~0, T1/J1-0C0H,...).
YEL:
The Yellow Alarm is detected when the frame is synchronized.
In T1 SF / SLC-96 format:
= 0: More than 76 ’One’s are detected on the Bit 2 of each channel during a 40ms fixed window and this status persists for Mx40ms. Here ‘M’ is
decided by the YELCTH[7:0] bits (b7~0, T1/J1-0BFH,...).
= 1: Less than 77 ’One’s are detected on the Bit 2 of each channel during a 40ms fixed window and this status persists for Nx40ms. Here ‘N’ is
decided by the YELDTH[7:0] bits (b7~0, T1/J1-0BEH,...).
In T1 ESF format:
= 0: Less than 8 ‘0xFF00’ (MSB first) are detected on the DL bits during a 40ms fixed window and this status persists for Mx40ms. Here ‘M’ is
decided by the YELCTH[7:0] bits (b7~0, T1/J1-0BFH,...).
= 1: More than 7 ‘0xFF00’ (MSB first) are detected on the DL bits during a 40ms fixed window and this status persists for Nx40ms. Here ‘N’ is
decided by the YELDTH[7:0] bits (b7~0, T1/J1-0BEH,...).
In T1 DM format:
= 0: More than 3 ’One’s are detected on the Y bit (Bit 6 in each CH 24) during a 40ms fixed window and this status persists for Mx40ms. Here ‘M’
is decided by the YELCTH[7:0] bits (b7~0, T1/J1-0BFH,...).
= 1: Less than 4 ’One’s are detected on the Y bit (Bit 6 in each CH 24) during a 40ms fixed window and this status persists for Nx40ms. Here ‘N’
is decided by the YELDTH[7:0] bits (b7~0, T1/J1-0BEH,...).
In J1 SF format:
= 0: More than 3 zeros are detected on the F-bit of the 12nd frame during a 40ms fixed window and this status persists for Mx40ms. Here ‘M’ is
decided by the YELCTH[7:0] bits (b7~0, T1/J1-0BFH,...).
= 1: Less than 4 zeros are detected on the F-bit of the 12nd frame during a 40ms fixed window and this status persists for Nx40ms. Here ‘N’ is
decided by the YELDTH[7:0] bits (b7~0, T1/J1-0BEH,...).
In J1 ESF format:
= 0: More than 2 zeros are detected on the DL bits during a 40 ms fixed window and this status persists for Mx40 ms. Here ‘M’ is decided by the
YELCTH[7:0] bits (b7~0, T1/J1-0BFH,...).
= 1: Less than 3 zeros are detected on the DL bits during a 40 ms fixed window and this status persists for Nx40 ms. Here ‘N’ is decided by the
YELDTH[7:0] bits (b7~0, T1/J1-0BEH,...).
RED:
= 0: The in SF / ESF / T1 DM / SLC-96 synchronization status persists for Mx120ms. Here ‘M’ is decided by the REDCTH[7:0] bits (b7~0, T1/J10BDH,...).
= 1: The out of SF / ESF / T1 DM / SLC-96 synchronization status persists for Nx40ms. Here ‘N’ is decided by the REDDTH[7:0] bits (b7~0, T1/
J1-0BCH,...).
Programming Information
209
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Alarm Control (0BAH, 1BAH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
AISE
YELE
REDE
R/W
R/W
R/W
0
0
0
2
1
0
AISI
YELI
REDI
R
R
R
0
0
0
AISE:
= 0: Disable the interrupt on the INT pin when the AISI bit (b3, T1/J1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the AISI bit (b3, T1/J1-05DH,...) is ‘1’.
YELE:
= 0: Disable the interrupt on the INT pin when the YELI bit (b3, T1/J1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the YELI bit (b3, T1/J1-05DH,...) is ‘1’.
REDE:
= 0: Disable the interrupt on the INT pin when the REDI bit (b3, T1/J1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the REDI bit (b3, T1/J1-05DH,...) is ‘1’.
T1/J1 Alarm Indication (0BBH, 1BBH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
AISI:
= 0: There is no status change on the AIS bit (b1, T1/J1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the AIS bit (b1, T1/J1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
YELI:
= 0: There is no status change on the YEL bit (b1, T1/J1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the YEL bit (b1, T1/J1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
REDI:
= 0: There is no status change on the RED bit (b1, T1/J1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the RED bit (b1, T1/J1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
Programming Information
210
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RED Declare Threshold (0BCH, 1BCH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
REDDTH7
REDDTH6
REDDTH5
REDDTH4
REDDTH3
REDDTH2
REDDTH1
REDDTH0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
1
1
1
1
1
1
REDDTH[7:0]:
The RED alarm is declared when the out of SF/ESF/T1 DM/SLC-96 synchronization status persists for Nx40ms. The value of the ‘N’ is decided
by these bits.
T1/J1 RED Clear Threshold (0BDH, 1BDH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
REDCTH7
REDCTH6
REDCTH5
REDCTH4
REDCTH3
REDCTH2
REDCTH1
REDCTH0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
1
1
1
1
1
1
1
REDCTH[7:0]:
The RED alarm is cleared when the in SF/ESF/T1 DM/SLC-96 synchronization status persists for Mx120ms. The value of the ‘M’ is decided by
these bits.
Programming Information
211
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Yellow Declare Threshold (0BEH, 1BEH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
YELDTH7
YELDTH6
YELDTH5
YELDTH4
YELDTH3
YELDTH2
YELDTH1
YELDTH0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
1
0
1
0
YELDTH[7:0]:
In T1 SF/SLC-96 format, the Yellow alarm is declared when less than 77 ’One’s are detected on the Bit 2 of each channel during a 40ms fixed
window and this status persists for Nx40ms; in T1 ESF format, the Yellow alarm is declared when more than 7 ‘0xFF00’ (MSB first) are detected on the
sliding DL bits during a 40ms fixed window and this status persists for Nx40ms; in T1 DM format, the Yellow alarm is declared when less than 77
’One’s are detected on the Y bit (Bit 6 in each CH 24) during a 40ms fixed window and this status persists for Nx40ms; in J1 SF format, the Yellow
alarm is declared when less than 4 ’One’s are detected on the F-bit of the 12nd frame during a 40ms fixed window and this status persists for Nx40ms;
in J1 ESF format, the Yellow alarm is declared when less than 3 zeros are detected on the DL bits during a 40ms fixed window and this status persists
for Nx40ms. The value of the ‘N’ are all decided by these bits.
T1/J1 Yellow Clear Threshold (0BFH, 1BFH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
YELCTH7
YELCTH6
YELCTH5
YELCTH4
YELCTH3
YELCTH2
YELCTH1
YELCTH0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
1
0
1
0
YELCTH[7:0]:
In T1 SF/SLC-96 format, the Yellow alarm is cleared when more than 76 ’One’s are detected on the Bit 2 of each channel during a 40ms fixed
window and this status persists for Mx40ms; in T1 ESF format, the Yellow alarm is cleared when less than 8 ‘0xFF00’ (MSB first) are detected on the
sliding DL bits during a 40ms fixed window and this status persists for Mx40ms; in T1 DM format, the Yellow alarm is cleared when more than 76
’One’s are detected on the Y bit (Bit 6 in each CH 24) during a 40ms fixed window and this status persists for Mx40ms; in J1 SF format, the Yellow
alarm is cleared when more than 3 ’One’s are detected on the F-bit of the 12nd frame during a 40ms fixed window and this status persists for Mx40ms;
in J1 ESF format, the Yellow alarm is cleared when more than 2 zeros are detected on the DL bits during a 40ms fixed window and this status persists
for Mx40ms. The value of the ‘M’ are all decided by these bits.
Programming Information
212
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 AIS Declare Threshold (0C0H, 1C0H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
AISDTH7
AISDTH6
AISDTH5
AISDTH4
AISDTH3
AISDTH2
AISDTH1
AISDTH0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
1
1
1
1
1
1
AISDTH[7:0]:
The Blue alarm is declared when less than 61 zeros are detected in a 40ms fixed window and this status persists for Nx40ms. The value of the
‘N’ is decided by these bits.
T1/J1 AIS Clear Threshold (0C1H, 1C1H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
AISCTH7
AISCTH6
AISCTH5
AISCTH4
AISCTH3
AISCTH2
AISCTH1
AISCTH0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
1
1
1
1
1
1
AISCTH[7:0]:
The Blue alarm is cleared when more than 60 zeros are detected in a 40ms fixed window and this status persists for Mx40ms. The value of the
‘M’ is decided by these bits.
Programming Information
213
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 PMON Control (0C2H, 1C2H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
UPDAT
AUTOUPD
R/W
R/W
0
0
UPDAT:
A transition from ‘0’ to ‘1’ on this bit updates all the PMON indirect registers.
AUTOUPD:
= 0: Disable the automatic update function of the PMON indirect registers.
= 1: All the PMON indirect registers are updated every one second automatically.
Programming Information
214
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 PMON Interrupt Control 0 (0C3H, 1C3H)
Bit No.
7
Bit Name
PRDGOVE
Type
R/W
Default
0
6
5
Reserved
4
3
2
1
0
DDSOVE
COFAOVE
OOFOVE
FEROVE
CRCOVE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
2
1
0
PRDGOVE:
= 0: Disable the interrupt on the INT pin when the PRDGOVI bit (b7, T1/J1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the PRDGOVI bit (b7, T1/J1-0C5H,...) is ‘1’.
DDSOVE:
= 0: Disable the interrupt on the INT pin when the DDSOVI bit (b4, T1/J1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the DDSOVI bit (b4, T1/J1-0C5H,...) is ‘1’.
COFAOVE:
= 0: Disable the interrupt on the INT pin when the COFAOVI bit (b3, T1/J1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the COFAOVI bit (b3, T1/J1-0C5H,...) is ‘1’.
OOFOVE:
= 0: Disable the interrupt on the INT pin when the OOFOVI bit (b2, T1/J1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the OOFOVI bit (b2, T1/J1-0C5H,...) is ‘1’.
FEROVE:
= 0: Disable the interrupt on the INT pin when the FEROVI bit (b1, T1/J1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the FEROVI bit (b1, T1/J1-0C5H,...) is ‘1’.
CRCOVE:
= 0: Disable the interrupt on the INT pin when the CRCOVI bit (b0, T1/J1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the CRCOVI bit (b0, T1/J1-0C5H,...) is ‘1’.
T1/J1 PMON Interrupt Control 1 (0C4H, 1C4H)
Bit No.
7
6
5
4
3
Bit Name
Type
LCVOVE
Reserved
Default
R/W
0
LCVOVE:
= 0: Disable the interrupt on the INT pin when the LCVOVI bit (b0, T1/J1-0C6H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the LCVOVI bit (b0, T1/J1-0C6H,...) is ‘1’.
Programming Information
215
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 PMON Interrupt Indication 0 (0C5H, 1C5H)
Bit No.
7
Bit Name
PRDGOVI
Type
R
Default
0
6
5
Reserved
4
3
2
1
0
DDSOVI
COFAOVI
OOFOVI
FEROVI
CRCOVI
R
R
R
R
R
0
0
0
0
0
3
2
1
0
PRDGOVI:
= 0: The PMON indirect PRGD Counter Mapping registers have not overflowed.
= 1: The PMON indirect PRGD Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
DDSOVI:
= 0: The PMON indirect DDSE Counter Mapping registers have not overflowed.
= 1: The PMON indirect DDSE Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
COFAOVI:
= 0: The PMON indirect COFA Counter Mapping register has not overflowed.
= 1: The PMON indirect COFA Counter Mapping register has overflowed.
This bit will be cleared if a ’1’ is written to it.
OOFOVI:
= 0: The PMON indirect OOF Counter Mapping register has not overflowed.
= 1: The PMON indirect OOF Counter Mapping register has overflowed.
This bit will be cleared if a ’1’ is written to it.
FEROVI:
= 0: The PMON indirect FER Counter Mapping registers have not overflowed.
= 1: The PMON indirect FER Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
CRCOVI:
= 0: The PMON indirect CRCE Counter Mapping registers have not overflowed.
= 1: The PMON indirect CRCE Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
T1/J1 PMON Interrupt Indication 1 (0C6H, 1C6H)
Bit No.
7
6
5
4
Bit Name
Type
LCVOVI
Reserved
Default
R
0
LCVOVI:
= 0: The PMON indirect LCV Counter Mapping registers have not overflowed.
= 1: The PMON indirect LCV Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
Programming Information
216
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 TPLC / RPLC / PRGD Test Configuration (0C7H, 1C7H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
PRBSMODE1
PRBSMODE0
PRBSDIR
TESTEN
R/W
R/W
R/W
R/W
0
0
0
0
PRBSMODE[1:0]:
These two bits select one mode to extract/replace the data for the PRBS Generator/Detector.
= 00: The unframed mode is selected. All 24 channels are extracted/replaced and the per-channel configuration in the TEST bit (b6, T1/J1-ID41~58H) is ignored.
= 01: The 8-bit-based mode is selected. The received data will only be extracted/replaced on the channel configured by the TEST bit (b6, T1/J1ID-41~58H).
= 10: The 7-bit-based mode is selected. The received data will only be extracted/replaced on the 7 MSB of the channel configured by the TEST
bit (b6, T1/J1-ID-41~58H).
= 11: Reserved.
PRBSDIR:
= 0: The pattern in the PRBS Generator/Detector is generated in the transmit path and is detected in the receive path.
= 1: The pattern in the PRBS Generator/Detector is generated in the receive path and is detected in the transmit path.
TESTEN:
A transition from ‘0’ to ‘1’ on this bit initiates the PRBS Generator/Detector.
Programming Information
217
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 TPLC Access Status (0C8H, 1C8H)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
BUSY
Type
Reserved
R
Default
0
BUSY:
= 0: No reading or writing operation on the indirect registers.
= 1: An internal indirect register is being accessed. Any new operation on the internal indirect register is not allowed.
T1/J1 TPLC Access Control (0C9H, 1C9H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
RWN
ADDRESS6
ADDRESS5
ADDRESS4
ADDRESS3
ADDRESS2
ADDRESS1
ADDRESS0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
RWN:
= 0: Write the data to the specified indirect register.
= 1: Read the data to the specified indirect register.
ADDRESS[6:0]:
These bits specify the address of the indirect register (from 01H to 18H & from 21H to 38H & from 41H to 58H) for the microprocessor access.
T1/J1 TPLC Access Data (0CAH, 1CAH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
D7
D6
D5
D4
D3
D2
D1
D0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
D[7:0]:
This register holds the value which will be read from or written into the indirect registers (from 01H to 18H & from 21H to 38H & from 41H to 58H).
If data is to be written into the indirect register, this register must be written before the target indirect register’s address and RWN=0 is written into the
TPLC Access Control register. If data is to be read from the indirect register, the target indirect register’s address and RWN=1 must be written into the
TPLC Access Control register first, then this register will contain the requested data byte.
Programming Information
218
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 TPLC Configuration (0CBH, 1CBH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
SIGSNAP
GSTRKEN
ZCS2
ZCS1
ZCS0
GSUBST2
GSUBST1
GSUBST0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
0
0
0
0
0
0
0
SIGSNAP:
This bit is valid in SF, ESF or SLC-96 format.
= 0: Disable the signaling snapshot.
= 1: Enable the signaling snapshot. That is, the signaling bits of the first frame are locked and input on the TSIGn/MTSIG pin as the signaling bits
of the current whole SF, ESF or SLC-96 frame.
GSTRKEN:
= 0: The replacement is performed on a per-channel basis by setting the STRKEN bit (b4, T1/J1-ID-41~58H) in the corresponding channel.
= 1: The signaling bits (ABCD) of all channels are replaced by the signaling trunk conditioning code in the A,B,C,D bits (b3~0, T1/J1-ID-41~58H).
ZCS[2:0]:
These bits select one type of Zero Code Suppression. (Bit 1 is the MSB in the following table).
ZCS[2:0]
000
001
010
011
100
others
Zero Code Suppression
No Zero Code Suppression.
GTE Zero Code Suppression. Bit 8 of an all-zero channel is replaced by a ‘1’, except in signaling frames where Bit 7 is forced to be a ‘1’.
Jammed Bit 8 Zero Code Suppression. Bit 8 of all channels are replaced by a ‘1’.
Bell Zero Code Suppression. Bit 7 of an all-zero channel is replaced by a ‘1’.
DDS Zero Code Suppression. An all-zero channel is replaced with ‘10011000’.
Reserved.
GSUBST[2:0]:
These bits select the replacement of all the channels.
GSUBST[2:0]
000
001
010
011
100
others
Replacement Selection
The replacement is performed on a per-channel basis by setting the SUBST[2:0] bits (b7~5, T1/J1-ID-01~18H) in the corresponding channel.
The data of all channels is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, T1/J1-ID-21~38H).
The data of all channels is replaced by the A-Law digital milliwatt pattern.
The data of all channels is replaced by the µ-Law digital milliwatt pattern.
The data of all channels is replaced by the payload loopback code extracted from the Elastic Store Buffer in the receive path.
Reserved.
Programming Information
219
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 TPLC Control Enable (0CCH, 1CCH)
Bit No.
7
6
5
4
3
Bit Name
Type
2
1
ABXX
Reserved
R/W
Default
0
0
PCCE
Reserved
R/W
0
ABXX:
This bit is valid in ESF & SLC-96 format.
= 0: The signaling bits are valid in the lower nibble of each channel.
= 1: The signaling bits are valid in the upper 2-bit positions of the lower nibble of each channel. The other bits of the channel are Don’t Care conditions.
PCCE:
= 0: Disable all the functions in the Transmit Payload Control.
= 1: Enable all the functions in the Transmit Payload Control.
Programming Information
220
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RPLC Access Status (0CDH, 1CDH)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
BUSY
Type
Reserved
R
Default
0
BUSY:
= 0: No reading or writing operation on the indirect registers.
= 1: An internal indirect register is being accessed. Any new operation on the internal indirect register is not allowed.
T1/J1 RPLC Access Control (0CEH, 1CEH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
RWN
ADDRESS6
ADDRESS5
ADDRESS4
ADDRESS3
ADDRESS2
ADDRESS1
ADDRESS0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
RWN:
= 0: Write the data to the specified indirect register.
= 1: Read the data to the specified indirect register.
ADDRESS[6:0]:
These bits specify the address of the indirect register (from 01H to 18H & from 21H to 38H & from 41H to 58H) for the microprocessor access.
T1/J1 RPLC Access Data (0CFH, 1CFH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
D7
D6
D5
D4
D3
D2
D1
D0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
D[7:0]:
This register holds the value which will be read from or written into the indirect registers (from 01H to 18H & from 21H to 38H & from 41H to 58H).
If data is to be written into the indirect register, this register must be written before the target indirect register’s address and RWN=0 is written into the
RPLC Access Control register. If data is to be read from the indirect register, the target indirect register’s address and RWN=1 must be written into the
RPLC Access Control register first, then this register will contain the requested data byte.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RPLC Configuration (0D0H, 1D0H)
Bit No.
7
6
Bit Name
SIGSNAP
GSTRKEN
Type
R/W
R/W
Default
1
0
5
4
3
Reserved
2
1
0
GSUBST2
GSUBST1
GSUBST0
R/W
R/W
R/W
0
0
0
SIGSNAP:
This bit is valid when SF, ESF or SLC-96 frame is in synchronization.
= 0: Disable the signaling snapshot.
= 1: Enable the signaling snapshot. That is, the signaling bits of the first frame are locked and output on the RSIGn/MRSIG pin as the signaling
bits of the current whole SF, ESF or SLC-96 frame.
GSTRKEN:
= 0: The replacement is performed on a per-channel basis by setting the STRKEN bit (b4, T1/J1-ID-41~58H) in the corresponding channel.
= 1: The signaling bits (ABCD) of all channels are replaced by the signaling trunk conditioning code in the A,B,C,D bits (b3~0, T1/J1-ID-41~58H).
GSUBST[2:0]:
These bits select the replacement of all the channels.
GSUBST[2:0]
000
001
010
011
the others
Replacement Selection
The replacement is performed on a per-channel basis by setting the SUBST[2:0] bits (b7~5, T1/J1-ID-01~18H) in the corresponding channel.
The data of all channels is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, T1/J1-ID-21~38H).
The data of all channels is replaced by the A-Law digital milliwatt pattern.
The data of all channels is replaced by the µ-Law digital milliwatt pattern.
Reserved.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RPLC Control Enable (0D1H, 1D1H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
ABXX
SIGFIX
POL
PCCE
R/W
R/W
R/W
R/W
0
0
0
0
ABXX:
This bit is valid in ESF & SLC-96 format.
= 0: The signaling bits are valid in the lower nibble of each channel.
= 1: The signaling bits are valid in the upper 2-bit positions of the lower nibble of each channel. The other bits of the channel are Don’t Care conditions.
SIGFIX:
This bit is only valid in the SF, ESF and SLC-96 formats.
= 0: Disable the signaling bits fixing function.
= 1: The signaling bits (ABCD) are fixed to the value set in the POL bit (b1, T1/J1-0D1H,...).
POL:
This bit is only valid when the SIGFIX bit is ‘1’.
= 0: The signaling bits (ABCD) are fixed to logic 0.
= 1: The signaling bits (ABCD) are fixed to logic 1.
PCCE:
= 0: Disable all the functions in the Receive Payload Control.
= 1: Enable all the functions in the Receive Payload Control.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RCRB Configuration (0D2H, 1D2H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
FREEZE
DEB
SIGE
SIGF
R/W
R/W
R/W
R/W
0
0
0
1
FREEZE:
= 0: Disable the manual signaling freezing.
= 1: Manually freeze the signaling data in the A,B,C,D bits (b3~0, T1/J1-ID-01~18H) as the previous valid value.
DEB:
= 0: Disable the signaling de-bounce.
= 1: Enable the signaling de-bounce. That is, the A,B,C,D bits (b3~0, T1/J1-ID-01~18H) are updated only if 2 consecutive received AB/ABCD
codewords of the same channel are identical.
SIGE:
= 0: Disable the interrupt on the INT pin when any of the COSI bits (T1/J1-0D8H,... & T1/J1-0D7H,... & T1/J1-0D6H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when any of the COSI bits (T1/J1-0D8H,... & T1/J1-0D7H,... & T1/J1-0D6H,...) is ‘1’.
SIGF:
This bit is valid only in the ESF and SLC-96 format.
= 0: The extracted signaling bits are in 4 states signaling, i.e., the signaling bits on Framer 6 & 18 of a signaling multi-frame are recognized as ‘A’
and the signaling bits on Framer 12 & 24 are recognized as ‘B’. Only the signaling bits A & B are saved in the Extracted Signaling Data/Extract Enable
register. The C & D bits in the Extracted Signaling Data/Extract Enable register are not cared.
= 1: The extracted signaling bits are in 16 states signaling, i.e., four signaling bits A, B, C & D are all saved in the Extracted Signaling Data/
Extract Enable register.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RCRB Access Status (0D3H, 1D3H)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
BUSY
Type
Reserved
R
Default
0
BUSY:
= 0: No reading or writing operation on the indirect registers.
= 1: An internal indirect register is being accessed. Any new operation on the internal indirect register is not allowed.
T1/J1 RCRB Access Control (0D4H, 1D4H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
RWN
ADDRESS6
ADDRESS5
ADDRESS4
ADDRESS3
ADDRESS2
ADDRESS1
ADDRESS0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
RWN:
= 0: Write the data to the specified indirect register.
= 1: Read the data to the specified indirect register.
ADDRESS[6:0]:
These bits specify the address of the indirect register (from 01H to 18H) for the microprocessor access.
T1/J1 RCRB Access Data (0D5H, 1D5H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
D7
D6
D5
D4
D3
D2
D1
D1
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
D[7:0]:
This register holds the value which will be read from or written into the indirect registers (from 01H to 18H). If data is to be written into the indirect
register, this register must be written before the target indirect register’s address and RWN=0 is written into the RCRB Access Control register. If data
is to be read from the indirect register, the target indirect register’s address and RWN=1 must be written into the RCRB Access Control register first,
then this register will contain the requested data byte.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 RCRB State Change Indication 0 (0D6H, 1D6H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
COSI8
COSI7
COSI6
COSI5
COSI4
COSI3
COSI2
COSI1
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
COSI[X]:
= 0: The signaling bits in its corresponding channel is not changed.
= 1: The signaling bits in its corresponding channel is changed.
The corresponding bit will be cleared if a ‘1’ is written to it. The COSI[8:1] bits correspond to channel 8 ~ 1 respectively.
T1/J1 RCRB State Change Indication 1 (0D7H, 1D7H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
COSI16
COSI15
COSI14
COSI13
COSI12
COSI11
COSI10
COSI9
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
COSI[X]:
= 0: The signaling bits in its corresponding channel is not changed.
= 1: The signaling bits in its corresponding channel is changed.
The corresponding bit will be cleared if a ‘1’ is written to it. The COSI[16:9] bits correspond to channel 16 ~ 9 respectively.
T1/J1 RCRB State Change Indication 2 (0D8H, 1D8H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
COSI24
COSI23
COSI22
COSI21
COSI20
COSI19
COSI18
COSI17
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
COSI[X]:
= 0: The signaling bits in its corresponding channel is not changed.
= 1: The signaling bits in its corresponding channel is changed.
The corresponding bit will be cleared if a ‘1’ is written to it. The COSI[24:17] bits correspond to channel 24 ~ 17 respectively.
Programming Information
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IDT82P2282
5.2.1.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Indirect Register
PMON:
The PMON Counter Mapping Registers (00H ~ 0BH) of a link are updated as a group in the following three ways:
1. A transition from ‘0’ to ‘1’ on the UPDAT bit (b1, T1/J1-0C2H,...) updates all the registers;
2. If the AUTOUPD bit (b0, T1/J1-0C2H,...) is set to ‘1’, the registers will be updated every one second;
T1/J1 CRCE Counter Mapping 0 (00H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
CRCE7
CRCE6
CRCE5
CRCE4
CRCE3
CRCE2
CRCE1
CRCE0
Type
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
CRCE[7:0]:
In ESF format, these bits together with the CRCE[9:8] bits count the CRC-6 Error numbers. The CRCE[0] bit is the LSB.
T1/J1 CRCE Counter Mapping 1 (01H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
CRCE9
CRCE8
R
R
0
0
CRCE[9:8]:
In ESF format, these bits together with the CRCE[7:0] bits count the CRC-6 Error numbers. The CRCE[9] bit is the MSB.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 FER Counter Mapping 0 (02H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
FER7
FER6
FER5
FER4
FER3
FER2
FER1
FER0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
FER[7:0]:
In SF / T1 DM / SLC-96 format, these bits together with the FER[11:8] bits count the F Bit Error numbers. The FER[0] bit is the LSB.
In ESF format, these bits together with the FER[11:8] bits count the Frame Alignment Bit Error numbers. The FER[0] bit is the LSB.
T1/J1 FER Counter Mapping 1 (03H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
FER11
FER10
FER9
FER8
R
R
R
R
0
0
0
0
FER[11:8]:
In SF / T1 DM / SLC-96 format, these bits together with the FER[7:0] bits count the F Bit Error numbers. The FER[11] bit is the MSB.
In ESF format, these bits together with the FER[7:0] bits count the Frame Alignment Bit Error numbers. The FER[11] bit is the MSB.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 COFA Counter Mapping (04H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
COFA2
COFA1
COFA0
R
R
R
0
0
0
COFA[2:0]:
These bits count the times of the new-found F bit position being different from the previous one events.
T1/J1 OOF Counter Mapping (05H)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
2
1
0
OOF4
OOF3
OOF2
OOF1
OOF0
R
R
R
R
R
0
0
0
0
0
OOF[4:0]:
In SF / ESF / T1 DM / SLC-96 format, these bits count the times of out of SF / ESF / T1 DM / SLC-96 synchronization events.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 PRGD Counter Mapping 0 (06H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
PRGD7
PRGD6
PRGD5
PRGD4
PRGD3
PRGD2
PRGD1
PRGD0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
PRGD[7:0]:
These bits together with the PRGD[15:8] bits count the PRGD Bit Error numbers. The PRGD[0] bit is the LSB.
T1/J1 PRGD Counter Mapping 1 (07H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
PRGD15
PRGD14
PRGD13
PRGD12
PRGD11
PRGD10
PRGD9
PRGD8
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
PRGD[15:8]:
These bits together with the PRGD[7:0] bits count the PRGD Bit Error numbers. The PRGD[15] bit is the MSB.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 LCV Counter Mapping 0 (08H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
LCV7
LCV6
LCV5
LCV4
LCV3
LCV2
LCV1
LCV0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
LCV[7:0]:
These bits together with the LCV[15:8] bits count the Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code Violation (CV) Error (in B8ZS
decoding) numbers. The LCV[0] bit is the LSB.
T1/J1 LCV Counter Mapping 1 (09H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
LCV15
LCV14
LCV13
LCV12
LCV11
LCV10
LCV9
LCV8
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
LCV[15:8]:
These bits together with the LCV[7:0] bits count the Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code Violation (CV) Error (in B8ZS
decoding) numbers. The LCV[15] bit is the MSB.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 DDSE Counter Mapping 0 (0AH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DDSE7
DDSE6
DDSE5
DDSE4
DDSE3
DDSE2
DDSE1
DDSE0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
DDSE[7:0]:
In T1 DM format, these bits together with the DDSE[9:8] bits count the DDS Pattern Error numbers. The DDSE[0] bit is the LSB.
T1/J1 DDSE Counter Mapping 1 (0BH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
DDSE9
DDSE8
R
R
0
0
DDSE[9:8]:
In T1 DM format, these bits together with the DDSE[7:0] bits count the DDS Pattern Error numbers. The DDSE[9] bit is the MSB
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RCRB:
The indirect registers of RCRB addressed from 01H to 18H are the Extracted Signaling Data / Extract Enable Registers for CH1 to CH24. Each
address corresponds to one channel.
T1/J1 Extracted Signaling Data/Extract Enable Register (01H ~ 18H)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
2
1
0
EXTRACT
A
B
C
D
R/W
R
R
R
R
1
0
0
0
0
EXTRACT:
This bit is valid when the SF/ESF/SLC-96 frame is synchronized.
= 0: Disable the signaling bits extraction.
= 1: The signaling bits are extracted to the A,B,C,D bits (b3~0, T1/J1-ID-01~18H).
In T1-DM format, there is no signaling bits. The EXTRACT bit of all the channels should be set to ‘0’.
A, B, C, D:
These bits are valid when the EXTRACT bit (b4, T1/J1-ID-01~18H) is enabled.
These bits are the extracted signaling bits. In SF format, the C, D bits are the repetition of the signaling bits A & B.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RPLC:
The indirect registers of RPLC addressed from 01H to 18H are the Channel Control Registers for CH1 to CH24. Each address corresponds to
one channel.
The indirect registers of RPLC addressed from 21H to 38H are the Data Trunk Conditioning Code Registers for CH1 to CH24. Each address corresponds to one channel.
The indirect registers of RPLC addressed from 41H to 58H are the Signaling Trunk Conditioning Code Registers for CH1 to CH24. Each address
corresponds to one channel.
T1/J1 Channel Control Register (01H ~ 18H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
SUBST2
SUBST1
SUBST0
SINV
OINV
EINV
G56K
GAP
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
SUBST[2:0]:
When the GSUBST[2:0] bits (b2~0, T1/J1-0D0H,...) are ‘000’, these bits select the replacement on a per-channel basis.
SUBST[2:0]
000
001
010
011
the others
Replacement Selection
No operation.
The data of the corresponding channel is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, T1/J1-ID-21~38H).
The data of the corresponding channel is replaced by the A-Law digital milliwatt pattern.
The data of the corresponding channel is replaced by the µ-Law digital milliwatt pattern.
Reserved.
SINV, OINV, EINV:
These three bits select how to invert the bits in the corresponding channel.
SINV
OINV
EINV
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Programming Information
Bit Inversion
No inversion.
Invert the even bits (bit 2, 4, 6, 8) of the corresponding channel (bit 1 is the MSB).
Invert the odd bits (bit 3, 5, 7) except the MSB of the corresponding channel (bit 1 is the MSB).
Invert the bits from bit 2 to bit 8 of the corresponding channel (bit 1 is the MSB).
Invert the MSB (bit 1) of the corresponding channel.
Invert the MSB (bit 1) and the even bits (bit 2, 4, 6, 8) of the corresponding channel.
Invert all the odd bits (bit 1, 3, 5, 7) of the corresponding channel (bit 1 is the MSB).
Invert all the bits (bit 1 ~ bit 8) of the corresponding channel (bit 1 is the MSB).
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G56K, GAP:
These bits are valid in Receive Clock Master mode when the PCCE bit (b0, T1/J1-0D1H,...) is ‘1’.
G56K
GAP
0
1
X
0
0
1
Gap Mode
The corresponding channel is not gapped.
Bit 8 (LSB) of the corresponding channel is gapped (no clock signal during the Bit 8).
The corresponding channel is gapped (no clock signal during the channel).
T1/J1 Data Trunk Conditioning Code Register (21H ~ 38H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DTRK7
DTRK6
DTRK5
DTRK4
DTRK3
DTRK2
DTRK1
DTRK0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
DTRK[7:0]:
These bits are the data trunk code that can replace the data of the channel selected by the GSUBST[2:0] bits (b2~0, T1/J1-0D0H,...) or the
SUBST[2:0] bits (b7~5, T1/J1-ID-01~18H).
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Signaling Trunk Conditioning Code Register (41H ~ 58H)
Bit No.
7
Bit Name
Type
6
5
TEST
Reserved
Default
R/W
0
Reserved
4
3
2
1
0
STRKEN
A
B
C
D
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
TEST:
This bit is valid in 8-bit-based mode or in 7-bit-based mode selected by the PRBSMODE[1:0] bits (b3~2, T1/J1-0C7H,...).
= 0: Disable the data in the corresponding channel to be tested by the PRBS Generator/Detector.
= 1: Enable the data in the corresponding channel to be extracted to the PRBS Generator/Detector for test (when the PRBSDIR bit (b1, T1/J10C7H,...) is ‘0’); or enable the test pattern from the PRBS Generator/Detector to replace the data in the corresponding channel for test (when the PRBSDIR bit (b1, T1/J1-0C7H,...) is ‘1’). In 8-bit-based mode, the data refers to all 8 bits. In 7-bit-based mode, the data refers to the 7 MSB.
All the channels that are extracted to the PRBS Generator/Detector are concatenated and treated as a continuous stream in which pseudo random are searched for. Similarly, all the channels set to be replaced with the PRBS Generator/Detector test pattern data are concatenated replaced by
the PRBS.
STRKEN:
= 0: No operation.
= 1: The data of the corresponding channel is replaced by the signaling trunk code set in the A, B, C, D bits (b3~0, T1/J1-ID-41~58H).
A, B, C, D:
These bits are the signaling trunk code that can replace the signaling bits of the channel selected by the GSTRKEN bit (b6, T1/J1-0D0H,...) or the
STRKEN bit (b4, T1/J1-ID-41~58H).
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TPLC:
The indirect registers of TPLC addressed from 01H to 18H are the Channel Control Registers for CH1 to CH24. Each address corresponds to
one channel.
The indirect registers of TPLC addressed from 21H to 38H are the Data Trunk Conditioning Code Registers for CH1 to CH24. Each address corresponds to one channel.
The indirect registers of TPLC addressed from 41H to 58H are the Signaling Trunk Conditioning Code Registers for CH1 to CH24. Each address
corresponds to one channel.
T1/J1 Channel Control Register (01H ~ 18H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
SUBST2
SUBST1
SUBST0
SINV
OINV
EINV
G56K
GAP
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
SUBST[2:0]:
When the GSUBST[2:0] bits (b2~0, T1/J1-0CBH,...) are ‘000’, these bits select the replacement on a per-channel basis.
SUBST[2:0]
000
001
010
011
100
others
Replacement Selection
No operation.
The data of the corresponding channel is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, T1/J1-ID-21~38H).
The data of the corresponding channel is replaced by the A-Law digital milliwatt pattern.
The data of the corresponding channel is replaced by the µ-Law digital milliwatt pattern.
The data of the corresponding channel is replaced by the payload loopback code extracted from the Elastic Store Buffer in the receive path.
Reserved.
SINV, OINV, EINV:
These three bits select how to invert the bits in the corresponding channel.
SINV
OINV
EINV
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Programming Information
Bit Inversion
No inversion.
Invert the even bits (bit 2, 4, 6, 8) of the corresponding channel (bit 1 is the MSB).
Invert the odd bits (bit 3, 5, 7) except the MSB of the corresponding channel (bit 1 is the MSB).
Invert the bits from bit 2 to bit 8 of the corresponding channel (bit 1 is the MSB).
Invert the MSB (bit 1) of the corresponding channel.
Invert the MSB (bit 1) and the even bits (bit 2, 4, 6, 8) of the corresponding channel.
Invert all the odd bits (bit 1, 3, 5, 7) of the corresponding channel (bit 1 is the MSB).
Invert all the bits (bit 1 ~ bit 8) of the corresponding channel (bit 1 is the MSB).
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
G56K, GAP:
These bits are valid in Transmit Clock Master mode when the PCCE bit (b0, T1/J1-0CCH,...) is ‘1’.
G56K
GAP
0
1
X
0
0
1
Gap Mode
The corresponding channel is not gapped.
Bit 8 (LSB) of the corresponding channel is gapped (no clock signal during the Bit 8).
The corresponding channel is gapped (no clock signal during the channel).
T1/J1 Data Trunk Conditioning Code Register (21H ~ 38H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DTRK7
DTRK6
DTRK5
DTRK4
DTRK3
DTRK2
DTRK1
DTRK0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
DTRK[7:0]:
These bits are the data trunk code that can replace the data of the channel selected by the GSUBST[2:0] bits (b2~0, T1/J1-0CBH,...) or the
SUBST[2:0] bits (b7~5, T1/J1-ID-01~18H).
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 Signaling Trunk Conditioning Code Register (41H ~ 58H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
TEST
SIGINS
STRKEN
A
B
C
D
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
TEST:
This bit is valid in 8-bit-based mode or in 7-bit-based mode selected by the PRBSMODE[1:0] bits (b3~2, T1/J1-0C7H,...).
= 0: Disable the data in the corresponding channel to be tested by the PRBS Generator/Detector.
= 1: Enable the data in the corresponding channel to be extracted to the PRBS Generator/Detector for test (when the PRBSDIR bit (b1, T1/J10C7H,...) is ‘1’); or enable the test pattern from the PRBS Generator/Detector to replace the data in the corresponding channel for test (when the PRBSDIR bit (b1, T1/J1-0C7H,...) is ‘0’). In 8-bit-based mode, the data refers to all 8 bits. In 7-bit-based mode, the data refers to the 7 MSB.
All the channels that are extracted to the PRBS Generator/Detector are concatenated and treated as a continuous stream in which pseudo random are searched for. Similarly, all the channels set to be replaced with the PRBS Generator/Detector test pattern data are concatenated replaced by
the PRBS.
SIGINS:
= 0: The signaling insertion is not allowed.
= 1: The signaling bits are inserted into the data stream to be transmitted. The signaling source is selected by the STRKEN bit (b4, T1/J1-ID41~58H).
STRKEN:
= 0: No operation.
= 1: The data of the corresponding channel is replaced by the signaling trunk code set in the A, B, C, D bits (b3~0, T1/J1-ID-41~58H).
A, B, C, D:
These bits are the signaling trunk code that can replace the signaling bits of the channel selected by the GSTRKEN bit (b6, T1/J1-0CBH,...) or
the STRKEN bit (b4, T1/J1-ID-41~58H).
Programming Information
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IDT82P2282
5.2.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 MODE
5.2.2.1
Direct Register
E1 Chip ID For Dual Transceiver (000H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Type
R
R
R
R
R
R
R
R
Default
0
1
0
0
X
X
X
X
ID[7:0]:
The ID[7:0] bits are pre-set. The ID[7:4] bits represent the IDT82P2282 device. The ID[3:0] bits represent the current version number (‘0001’ is for
the first version).
E1 Software Reset (004H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
Type
X
Default
A write operation to this register will generate a software reset.
The software reset can only be applied when the clock on the OSCI pin is available.
The software reset will set all the registers except the T1/J1 Or E1 Mode register (020H,...) to their default values. If the setting is changed in the
T1/J1 Or E1 Mode register (020H,...), a software reset must be applied.
Programming Information
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August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 G.772 Monitor Control (005H)
Bit No.
7
6
5
4
3
Bit Name
2
1
0
MON3
Type
Reserved
R/W
Default
MON0
Reserved
R/W
0
0
MON[3], MON[0]:
These bits determine whether the G.772 Monitor is implemented. When the G.772 Monitor is implemented, these bits select one transmitter or
receiver to be monitored by the Link 1.
MON[3], MON[0]
Monitored Path
MON[3], MON[0]
Monitored Path
00
01
No transmitter or receiver is monitored.
The receiver of the Link 2 is monitored.
10
11
No transmitter or receiver is monitored.
The transmitter of the Link 2 is monitored.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 GPIO Control (006H)
Bit No.
7
6
5
4
Bit Name
Type
3
2
1
LEVEL0
Reserved
R/W
Default
0
0
DIR0
Reserved
R/W
1
LEVEL[0]:
When the GPIO[0] pin is defined as an output port, this bit can be read and written:
= 0: The GPIO[0] pin outputs low level.
= 1: The GPIO[0] pin outputs high level.
When the GPIO[0] pin is defined as an input port, this bit can only be read:
= 0: Low level is input on the GPIO[0] pin.
= 1: High level is input on the GPIO[0] pin.
DIR[0]:
= 0: The GPIO[0] pin is used as an output port.
= 1: The GPIO[0] pin is used as an input port.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Reference Clock Output Select (007H)
Bit No.
7
6
5
4
Bit Name
Type
3
2
1
RO20
Reserved
R/W
Default
0
0
RO10
Reserved
R/W
0
RO20:
This bit selects the link to be internally looped to the REFB_OUT output pin:
= 0: The Link 1 is selected.
= 1: The Link 2 is selected.
When no LOS of the selected link is detected, the REFB_OUT pin outputs the recovered clock of the selected link from the Clock and Data
Recovery function block.
When LOS of the selected link is detected, the REFB_OUT pin outputs MCLK or high level, as selected by the REFH_LOS bit (b0, E1-03EH,...).
(This feature is available in ZB revision only).
RO10:
This bit selects the link to be internally looped to the REFA_OUT output pin:
= 0: The Link 1 is selected.
= 1: The Link 2 is selected.
When no LOS of the selected link is detected, the REFA_OUT pin outputs the recovered clock of the selected link from the Clock and Data
Recovery function block.
When LOS of the selected link is detected, the REFA_OUT pin outputs MCLK or high level, as selected by the REFH_LOS bit (b0, E1-03EH,...).
(This feature is available in ZB revision only).
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Interrupt Requisition Link ID (009H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
INT2
INT1
R
R
0
0
1
0
INTn:
= 0: No interrupt is generated in the corresponding link.
= 1: At least one interrupt is generated in the corresponding link.
E1 Timer Interrupt Control (00AH)
Bit No.
7
6
5
4
3
2
Bit Name
TMOVE
Type
Reserved
R/W
Default
0
TMOVE:
= 0: Disable the interrupt on the INT pin when the TMOVI bit (b0, E1-00BH) is ‘1’.
= 1: Enable the interrupt on the INT pin when the TMOVI bit (b0, E1-00BH) is ‘1’.
E1 Timer Interrupt Indication (00BH)
Bit No.
7
6
5
4
Bit Name
Type
3
2
1
0
TMOVI
Reserved
Default
R
0
TMOVI:
The device times every one second.
= 0: One second timer is not over.
= 1: One second timer is over.
This bit will be cleared if a ’1’ is written to it.
Programming Information
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August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 PMON Access Port (00EH)
Bit No.
7
6
5
Bit Name
4
LINKSEL0
Type
Reserved
R/W
Default
Reserved
3
2
1
0
ADDR3
ADDR2
ADDR1
ADDR0
R/W
R/W
R/W
R/W
0
0
0
0
0
LINKSEL0:
This bit selects one of the two links. One of the PMON indirect registers of the selected link can be accessed by the microprocessor.
= 0: Link 1 is selected.
= 1: Link 2 is selected.
ADDR[3:0]:
These bits select one of the PMON indirect registers of the selected link to be accessed by the microprocessor.
Address
PMON Indirect Register
Address
PMON Indirect Register
00H
01H
02H
03H
04H
05H
06H
07H
CRCE Counter Mapping 0
CRCE Counter Mapping 1
FER Counter Mapping 0
FER Counter Mapping 1
COFA Counter Mapping
OOF Counter Mapping
PRGD Counter Mapping 0
PRGD Counter Mapping 1
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
LCV Counter Mapping 0
LCV Counter Mapping 1
TCRCE Counter Mapping 0
TCRCE Counter Mapping 1
FEBE Counter Mapping 0
FEBE Counter Mapping 1
TFEBE Counter Mapping 0
TFEBE Counter Mapping 1
E1 PMON Access Data (00FH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
DAT[7:0]:
These bits hold the value which is read from the selected PMON indirect register.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Backplane Global Configuration (010H)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
RSLVCK
RMUX
R/W
R/W
1
0
2
Reserved
1
0
TSLVCK
TMUX
R/W
R/W
1
0
RSLVCK:
This bit is valid when both two links are in the Receive Clock Slave mode.
= 0: Each link uses its own clock signal on the RSCKn pin and framing pulse on the RSFSn pin.
= 1: Both two links use the clock signal on the RSCK[1] pin and the framing pulse on the RSFS[1] pin.
RMUX:
= 0: The Receive System Interface of the device is operated in the Non-multiplexed mode.
= 1: The Receive System Interface of the device is operated in the Multiplexed mode.
TSLVCK:
This bit is valid when both two links are in the Transmit Clock Slave mode.
= 0: Each link uses its own timing signal on the TSCKn pin and framing pulse on the TSFSn pin.
= 1: Both two links use the timing signal on the TSCK[1] pin and the framing pulse on the TSFS[1] pin.
TMUX:
= 0: The Transmit System Interface of the device is operated in the Non-multiplexed mode.
= 1: The Transmit System Interface of the device is operated in the Multiplexed mode.
Programming Information
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August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Transmit Jitter Attenuation Configuration (021H, 121H)
Bit No.
7
6
Bit Name
Type
5
4
3
2
1
0
TJITT_TEST
TJA_LIMT
TJA_E
TJA_DP1
TJA_DP0
TJA_BW
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Reserved
Default
TJITT_TEST:
= 0: The real time interval between the read and write pointer of the FIFO is indicated in the TJITT[6:0] bits (b6~0, E1-038H,...). That is, the current interval between the read and write pointer of the FIFO will be written into the TJITT[6:0] bits (b6~0, E1-038H,...).
= 1: The peak-peak interval between the read and write pointer of the FIFO is indicated in the TJITT[6:0] bits (b6~0, E1-038H,...). That is, the current interval is compared with the old one in the TJITT[6:0] bits (b6~0, E1-038H,...) and the larger one will be indicated by the TJITT[6:0] bits (b6~0,
E1-038H,...); otherwise, the value in the TJITT[6:0] bits (b6~0, E1-038H,...) is not changed.
TJA_LIMT:
When the read and write pointer of the FIFO are within 2/3/4 bits (corresponding to the FIFO depth) of overflowing or underflowing, the bandwidth
of the JA can be widened to track the short term input jitter, thereby avoiding data corruption. This bit selects whether the bandwidth is normal or widened.
= 0: Normal bandwidth is selected.
= 1: Widen bandwidth is selected. In this case, the JA will not attenuate the input jitter until the read/write pointer’s position is outside the 2/3/4
bits window.
TJA_E:
= 0: Disable the Transmit Jitter Attenuator.
= 1: Enable the Transmit Jitter Attenuator.
TJA_DP[1:0]:
These two bits select the Jitter Attenuation Depth.
= 00: The Jitter Attenuation Depth is 128-bit.
= 01: The Jitter Attenuation Depth is 64-bit.
= 10 / 11: The Jitter Attenuation Depth is 32-bit.
TJA_BW:
This bit select the Jitter Transfer Function Bandwidth.
= 0: 6.77 Hz.
= 1: 0.87 Hz.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Transmit Configuration 0 (022H, 122H)
Bit No.
7
6
Bit Name
Type
Default
5
4
3
2
T_OFF
Reserved
R/W
0
1
0
T_MD
Reserved
R/W
0
T_OFF:
= 0: The transmit path is power up.
= 1: The transmit path is power down. The Line Driver is in high impedance.
T_MD:
This bit selects the line code rule to encode the data stream to be transmitted.
= 0: The HDB3 encoder is selected.
= 1: The AMI encoder is selected.
Programming Information
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August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Transmit Configuration 1 (023H, 123H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
DFM_ON
T_HZ
PULS3
PULS2
PULS1
PULS0
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
0
0
0
DFM_ON:
= 0: The Driver Failure Monitor is disabled.
= 1: The Driver Failure Monitor is enabled.
T_HZ:
= 0: The Line Driver works normally.
= 1: Set the Line Driver High-Z. (The other parts of the transmit path still work normally.)
PULS[3:0]:
These bits determine the template shapes for short/long haul transmission:
PULS[3:0]
Transmit Clock
Cable Impedance
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
11xx
2.048 MHz
2.048 MHz
75 Ω (in internal impedance matching mode) / Reserved (in external impedance matching mode)
120 Ω (in internal impedance matching mode) / 75 Ω & 120 Ω (in external impedance matching mode)
Programming Information
Reserved
Arbitrary waveform setting.
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Transmit Configuration 2 (024H, 124H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
SCAL5
SCAL4
SCAL3
SCAL2
SCAL1
SCAL0
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
1
SCAL[5:0]:
The following setting lists the standard value of normal amplitude in different operating modes. Each step change (one increasing or decreasing
from the standard value) will scale the amplitude of the D/A output by a certain offset. These bits are only effective when user programmable arbitrary
waveform is used.
= 100001: Normal amplitude in E1 - 75 Ω & 120 Ω operating modes. Each step change scales about 3% offset.
Programming Information
250
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Transmit Configuration 3 (025H, 125H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DONE
RW
UI1
UI0
SAMP3
SAMP2
SAMP1
SAMP0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register is valid when the PULS[3:0] bits (b3~0, E1-023H,...) are set to ‘11xx’.
DONE:
= 0: Disable the read/write operation to the pulse template RAM.
= 1: Enable the read/write operation to the pulse template RAM.
RW:
= 0: Write the data to the pulse template RAM.
= 1: Read the data to the pulse template RAM.
UI[1:0]:
These bits specify one Unit Interval (UI) address.
= 00: UI addressed 0 is specified.
= 01: UI addressed 1 is specified.
= 10: UI addressed 2 is specified.
= 11: UI addressed 3 is specified.
SAMP[3:0]:
There bits specify one sample address. There are 16 samples in each UI.
SAMP[3:0]
Specified Sample Address
SAMP[3:0]
Specified Sample Address
0000
0001
0010
0011
0100
0101
0110
0111
0
1
2
3
4
5
6
7
1000
1001
1010
1011
1100
1101
1110
1111
8
9
10
11
12
13
14
15
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Transmit Configuration 4 (026H, 126H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
WDAT6
WDAT5
WDAT4
WDAT3
WDAT2
WDAT1
WDAT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
WDAT[6:0]:
These bits contain the data to be stored in the pulse template RAM which is addressed by the UI[1:0] bits (b5~4, E1-025H,...) and the SAMP[3:0]
bits (b3~0, E1-025H,...).
Programming Information
252
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Receive Jitter Attenuation Configuration (027H, 127H)
Bit No.
7
6
Bit Name
Type
5
4
3
2
1
0
RJITT_TEST
RJA_LIMT
RJA_E
RJA_DP1
RJA_DP0
RJA_BW
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Reserved
Default
RJITT_TEST:
= 0: The real time interval between the read and write pointer of the FIFO is indicated in the RJITT[6:0] bits (b6~0, E1-039H,...). That is, the current interval between the read and write pointer of the FIFO will be written into the RJITT[6:0] bits (b6~0, E1-039H,...).
= 1: The peak-peak interval between the read and write pointer of the FIFO is indicated in the RJITT[6:0] bits (b6~0, E1-039H,...). That is, the current interval is compared with the old one in the RJITT[6:0] bits (b6~0, E1-039H,...) and the larger one will be indicated by the RJITT[6:0] bits (b6~0,
E1-039H,...); otherwise, the value in the RJITT[6:0] bits (b6~0, E1-039H,...) is not changed.
RJA_LIMT:
When the read and write pointer of the FIFO are within 2/3/4 bits (corresponding to the FIFO depth) of overflowing or underflowing, the bandwidth
of the JA can be widened to track the short term input jitter, thereby avoiding data corruption. This bit selects whether the bandwidth is normal or widened.
= 0: Normal bandwidth is selected.
= 1: Widen bandwidth is selected. In this case, the JA will not attenuate the input jitter until the read/write pointer’s position is outside the 2/3/4
bits window.
RJA_E:
= 0: Disable the Receive Jitter Attenuator.
= 1: Enable the Receive Jitter Attenuator.
RJA_DP[1:0]:
These two bits select the Jitter Attenuation Depth.
= 00: The Jitter Attenuation Depth is 128-bit.
= 01: The Jitter Attenuation Depth is 64-bit.
= 10 / 11: The Jitter Attenuation Depth is 32-bit.
RJA_BW:
This bit select the Jitter Transfer Function Bandwidth.
= 0: 6.77 Hz.
= 1: 0.87 Hz.
Programming Information
253
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Receive Configuration 0 (028H, 128H)
Bit No.
7
6
Bit Name
Type
5
4
3
2
R_OFF
Reserved
Default
R/W
0
1
0
R_MD
Reserved
R/W
0
R_OFF:
= 0: The receive path is power up.
= 1: The receive path is power down.
R_MD:
This bit selects the line code rule to decode the received data stream.
= 0: The HDB3 decoder is selected.
= 1: The AMI decoder is selected.
Programming Information
254
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Receive Configuration 1 (029H, 129H)
Bit No.
7
Bit Name
Type
6
5
EQ_ON
Reserved
Default
R/W
Reserved
0
4
3
2
1
0
LOS4
LOS3
LOS2
LOS1
LOS0
R/W
R/W
R/W
R/W
R/W
1
0
1
0
1
EQ_ON:
= 0: The Equalizer is off in short haul applications.
= 1: The Equalizer is on in long haul applications.
LOS[4:0]:
A LOS is detected when the incoming signals has “no transitions”, i.e., when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. In long haul applications, these bits select the LOS declare threshold (Q). These bits are invalid in short haul applications.
Programming Information
LOS[4:0]
LOS Declare Threshold (Q)
LOS[4:0]
LOS Declare Threshold (Q)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
-4 dB
-6 dB
-8 dB
-10 dB
-12 dB
-14 dB
-16 dB
-18 dB
-20 dB
-22 dB
-24 dB
-26 dB
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110 11111
-28 dB
-30 dB
-32 dB
-34 dB
-36 dB
-38 dB
-40 dB
-42 dB
-44 dB
-46 dB
255
-48 dB
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Receive Configuration 2 (02AH, 12AH)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
SLICE1
SLICE0
UPDW1
UPDW0
MG1
MG0
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
0
0
0
SLICE[1:0]:
These two bits define the Data Slicer threshold.
= 00: The Data Slicer generates a mark if the voltage on the RTIPn/RRINGn pins exceeds 40% of the peak amplitude.
= 01: The Data Slicer generates a mark if the voltage on the RTIPn/RRINGn pins exceeds 50% of the peak amplitude.
= 10: The Data Slicer generates a mark if the voltage on the RTIPn/RRINGn pins exceeds 60% of the peak amplitude.
= 11: The Data Slicer generates a mark if the voltage on the RTIPn/RRINGn pins exceeds 70% of the peak amplitude.
UPDW[1:0]:
These two bits select the observation period, during which the peak value of the incoming signals are measured.
= 00: The observation period is 32 bits.
= 01: The observation period is 64 bits.
= 10: The observation period is 128 bits.
= 11: The observation period is 256 bits.
MG[1:0]:
These two bits select the Monitor Gain.
= 00: The Monitor Gain is 0 dB.
= 01: The Monitor Gain is 22 dB.
= 10: Reserved.
= 11: Reserved.
Programming Information
256
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Maintenance Function Control 0 (02BH, 12BH)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
DLLP
SLLP
SRLP
R/W
R/W
R/W
0
0
0
Reserved
2
1
0
RLP
ALP
DLP
R/W
R/W
R/W
0
0
0
DLLP:
= 0: Disable the Local Digital Loopback 1.
= 1: Enable the Local Digital Loopback 1.
SLLP:
= 0: Disable the System Local Loopback.
= 1: Enable the System Local Loopback.
SRLP:
= 0: Disable the System Remote Loopback.
= 1: Enable the System Remote Loopback.
RLP:
= 0: Disable the Remote Loopback.
= 1: Enable the Remote Loopback.
ALP:
= 0: Disable the Analog Loopback.
= 1: Enable the Analog Loopback.
DLP:
= 0: Disable the Local Digital Loopback 2.
= 1: Enable the Local Digital Loopback 2.
Programming Information
257
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Maintenance Function Control 1 (02CH, 12CH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
LAC
RAISE
ATAO
R/W
R/W
R/W
0
0
0
LAC:
This bit selects the LOS criteria.
= 0: The G.775 is selected. In short haul application, the LOS is declared when the incoming signal level is less than 800 mVpp for 32 consecutive bit intervals and is cleared when the incoming signal level is greater than 1 Vpp and has an average mark density of at least 12.5% and less than
16 consecutive zeros in 32 consecutive bit periods. In long haul application, the LOS is declared when the incoming signal level is less than Q dB
below nominal (set in the LOS[4:0] bits (b4~0, E1-029H,...)) for 32 consecutive bit intervals and is cleared when the incoming signal level is greater
than (Q + 4 dB) and has an average mark density of at least 12.5% and less than 16 consecutive zeros in 32 consecutive bit periods.
= 1: The I.431/ETSI is selected. In short haul application, the LOS is declared when the incoming signal level is less than 800 mVpp for 2048 consecutive bit intervals and is cleared when the incoming signal level is greater than 1 Vpp and has an average mark density of at least 12.5% and less
than 16 consecutive zeros in 32 consecutive bit periods. In long haul application, the LOS is declared when the incoming signal level is less than Q dB
below nominal (set in the LOS[4:0] bits (b4~0, E1-029H,...)) for 2048 consecutive bit intervals and is cleared when the incoming signal level is greater
than (Q + 4 dB) and has an average mark density of at least 12.5% and less than 16 consecutive zeros in 32 consecutive bit periods.
RAISE:
This bit determines whether all ‘One’s can be inserted in the receive path when the LOS is detected.
= 0: Disable the insertion.
= 1: Enable the insertion.
ATAO:
This bit determines whether all ‘One’s can be inserted in the transmit path when the LOS is detected in the receive path.
= 0: Disable the insertion.
= 1: Enable the insertion.
Programming Information
258
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Maintenance Function Control 2 (031H, 131H)
Bit No.
7
Bit Name
Type
6
5
BPV_INS
Reserved
Default
R/W
0
Reserved
4
3
2
1
0
EXZ_DEF
EXZ_ERR1
EXZ_ERR0
CNT_MD
CNT_TRF
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BPV_INS:
A transition from ‘0’ to ‘1’ on this bit generates a single Bipolar Violation (BPV) Error to be inserted to the data stream to be transmitted.
This bit must be cleared and set again for the next BPV error insertion.
EXZ_DEF:
This bit selects the Excessive Zero (EXZ) Error criteria.
= 0: The ANSI is selected. In AMI line code rule, the EXZ error is defined as more than 15 consecutive zeros in the data stream. In HDB3 line
code rule, the EXZ error is defined as more than 3 consecutive zeros in the data stream.
= 1: The FCC is selected. In AMI line code rule, the EXZ error is defined as more than 80 consecutive zeros in the data stream. In HDB3 line
code rule, the EXZ error is defined as more than 3 consecutive zeros in the data stream.
EXZ_ERR[1:0]:
These bits must be set to ‘01’ to enable the Excessive Zero (EXZ) Error event to be counted in an internal 16-bit EXZ counter.
CNT_MD:
= 0: The Manual Report mode is selected. The internal 16-bit EXZ counter transfers its content to the EXZ Error Counter L-Byte & H-Byte registers when there is a transition from ‘0’ to ‘1’ on the CNT_TRF bit.
= 1: The Auto Report mode is selected. The internal 16-bit EXZ counter transfers its content to the EXZ Error Counter L-Byte & H-Byte registers
every one second automatically.
CNT_TRF:
This bit is valid when the CNT_MD bit is ‘0’.
A transition from ‘0’ to ‘1’ on this bit updates the content in the EXZ Error Counter L-Byte & H-Byte registers with the value in the internal 16-bit
EXZ counter.
This bit must be cleared and set again for the next updating.
Programming Information
259
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Transmit And Receive Termination Configuration (032H, 132H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
T_TERM2
T_TERM1
T_TERM0
R_TERM2
R_TERM1
R_TERM0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
1
1
1
0
T_TERM[2:0]:
These bits select the internal impedance of the transmit path to match the cable impedance:
= 000: The 75 Ω internal impedance matching is selected.
= 001: The 120 Ω internal impedance matching is selected.
(The above two values are the standard value for E1 mode).
= 010: The 100 Ω internal impedance matching is selected.
= 011: The 110 Ω internal impedance matching is selected.
= 1xx: The internal impedance matching is bypassed, and external impedance circuit should be used.
R_TERM[2:0]:
These bits select the internal impedance of the receive path to match the cable impedance:
= 000: The 75 Ω internal impedance matching is selected.
= 001: The 120 Ω internal impedance matching is selected.
(The above two values are the standard values for E1 mode).
= 010: The 100 Ω internal impedance matching is selected.
= 011: The 110 Ω internal impedance matching is selected.
= 1xx: The internal impedance matching is bypassed, and external impedance circuit should be used.
E1 Interrupt Enable Control 0 (033H, 133H)
Bit No.
7
6
5
4
3
Bit Name
Type
2
DF_IE
Reserved
R/W
Default
0
LOS_IE
Reserved
R/W
0
DF_IE:
= 0: Disable the interrupt on the INT pin when the DF_IS bit (b2, E1-03AH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the DF_IS bit (b2, E1-03AH,...) is ‘1’.
LOS_IE:
= 0: Disable the interrupt on the INT pin when the LOS_IS bit (b0, E1-03AH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the LOS_IS bit (b0, E1-03AH,...) is ‘1’.
Programming Information
260
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Interrupt Enable Control 1 (034H, 134H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
DAC_IE
TJA_IE
RJA_IE
R/W
R/W
R/W
0
0
0
Reserved
2
1
0
EXZ_IE
CV_IE
CNT_IE
R/W
R/W
R/W
0
0
0
DAC_IE:
= 0: Disable the interrupt on the INT pin when the DAC_IS bit (b6, E1-03BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the DAC_IS bit (b6, E1-03BH,...) is ‘1’.
TJA_IE:
= 0: Disable the interrupt on the INT pin when the TJA_IS bit (b5, E1-03BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the TJA_IS bit (b5, E1-03BH,...) is ‘1’.
RJA_IE:
= 0: Disable the interrupt on the INT pin when the RJA_IS bit (b4, E1-03BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the RJA_IS bit (b4, E1-03BH,...) is ‘1’.
EXZ_IE:
= 0: Disable the interrupt on the INT pin when the EXZ_IS bit (b2, E1-03BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the EXZ_IS bit (b2, E1-03BH,...) is ‘1’.
CV_IE:
= 0: Disable the interrupt on the INT pin when the CV_IS bit (b1, E1-03BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the CV_IS bit (b1, E1-03BH,...) is ‘1’.
CNT_IE:
= 0: Disable the interrupt on the INT pin when the CNTOV_IS bit (b0, E1-03BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the CNTOV_IS bit (b0, E1-03BH,...) is ‘1’.
Programming Information
261
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Interrupt Trigger Edges Select (035H, 135H)
Bit No.
7
6
5
4
3
Bit Name
2
1
DF_IES
Type
Reserved
R/W
Default
0
LOS_IES
Reserved
0
R/W
0
DF_IES:
= 0: The DF_IS bit (b2, E1-03AH,...) will be set to ‘1’ when there is a transition from ‘0’ to ‘1’ on the DF_S bit (b2, E1-036H,...).
= 1: The DF_IS bit (b2, E1-03AH,...) will be set to ‘1’ when there is any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the DF_S bit (b2, E1-036H,...).
LOS_IES:
= 0: The LOS_IS bit (b0, E1-03AH,...) will be set to ‘1’ when there is a transition from ‘0’ to ‘1’ on the LOS_S bit (b0, E1-036H,...).
= 1: The LOS_IS bit (b0, E1-03AH,...) will be set to ‘1’ when there is any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the LOS_S bit (b0, E1036H,...).
E1 Line Status Register 0 (036H, 136H)
Bit No.
7
6
5
4
3
Bit Name
Type
2
1
DF_S
Reserved
R
Default
0
0
LOS_S
Reserved
R
0
DF_S:
= 0: No transmit driver failure is detected.
= 1: Transmit driver failure is detected.
LOS_S:
= 0: No LOS is detected.
= 1: Loss of signal (LOS) is detected.
Programming Information
262
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Line Status Register 1 (037H, 137H)
Bit No.
7
6
5
Bit Name
Type
Reserved
Default
4
3
2
1
0
LATT4
LATT3
LATT2
LATT1
LATT0
R
R
R
R
R
0
0
0
0
0
LATT[4:0]:
These bits indicate the current gain of the VGA relative to 3 V peak pulse level.
LATT[4:0]
Gain (dB)
LATT[4:0]
Gain (dB)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
0-2
2-4
4-6
6-8
8 - 10
10 - 12
12 - 14
14 - 16
16 - 18
18 - 20
20 - 22
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101 ~ 11111
22 - 24
24 - 26
26 - 28
28 - 30
30 - 32
32 - 34
34 - 36
36 - 38
38 - 40
40 - 42
42 - 44
Programming Information
263
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Transmit Jitter Measure Value Indication (038H, 138H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
TJITT6
TJITT5
TJITT4
TJITT3
TJITT2
TJITT1
TJITT0
R
R
R
R
R
R
R
0
0
0
0
0
0
0
TJITT[6:0]:
When the TJITT_TEST bit (b5, E1-021H,...) is ‘0’, these bits represent the current interval between the read and write pointer of the FIFO.
When the TJITT_TEST bit (b5, E1-021H,...) is ‘1’, these bits represent the P-P interval between the read and write pointer of the FIFO since last
read.
These bits will be cleared if a ’1’ is written to the register.
E1 Receive Jitter Measure Value Indication (039H, 139H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
RJITT6
RJITT5
RJITT4
RJITT3
RJITT2
RJITT1
RJITT0
R
R
R
R
R
R
R
0
0
0
0
0
0
0
RJITT[6:0]:
When the RJITT_TEST bit (b5, E1-027H,...) is ‘0’, these bits represent the current interval between the read and write pointer of the FIFO.
When the RJITT_TEST bit (b5, E1-027H,...) is ‘1’, these bits represent the P-P interval between the read and write pointer of the FIFO since last
read.
These bits will be cleared if a ’1’ is written to the register.
Programming Information
264
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Interrupt Status 0 (03AH, 13AH)
Bit No.
7
6
5
4
3
Bit Name
Type
2
1
DF_IS
Reserved
R
Default
0
0
LOS_IS
Reserved
R
0
DF_IS:
= 0: There is no status change on the DF_S bit (b2, E1-036H,...).
= 1: When the DF_IES bit (b2, E1-035H,...) is ‘0’, the ‘1’ on this bit indicates there is a transition from ‘0’ to ‘1’ on the DF_S bit (b2, E1-036H,...);
when the DF_IES bit (b2, E1-035H,...) is ‘1’, the ‘1’ on this bit indicates there is a transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the DF_S bit (b2, E1036H,...).
This bit will be cleared if a ’1’ is written to it.
LOS_IS:
= 0: There is no status change on the LOS_S bit (b0, E1-036H,...).
= 1: When the LOS_IES bit (b0, E1-035H,...) is ‘0’, the ‘1’ on this bit indicates there is a transition from ‘0’ to ‘1’ on the LOS_S bit (b0, E1036H,...); when the LOS_IES bit (b0, E1-035H,...) is ‘1’, the ‘1’ on this bit indicates there is a transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the LOS_S bit
(b0, E1-036H,...).
This bit will be cleared if a ’1’ is written to it.
Programming Information
265
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Interrupt Status 1 (03BH, 13BH)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
DAC_IS
TJA_IS
RJA_IS
R
R
R
0
0
0
Reserved
2
1
0
EXZ_IS
CV_IS
CNTOV_IS
R
R
R
0
0
0
DAC_IS:
= 0: The sum of a pulse template does not exceed the D/A limitation (+63) when more than one UI is used to compose the arbitrary pulse template.
= 1: The sum of a pulse template exceeds the D/A limitation (+63) when more than one UI is used to compose the arbitrary pulse template.
This bit will be cleared if a ’1’ is written to it.
TJA_IS:
= 0: The transmit JA FIFO has not overflowed or underflowed.
= 1: The transmit JA FIFO has overflowed or underflowed.
This bit will be cleared if a ’1’ is written to it.
RJA_IS:
= 0: The receive JA FIFO has not overflowed or underflowed.
= 1: The receive JA FIFO has overflowed or underflowed.
This bit will be cleared if a ’1’ is written to it.
EXZ_IS:
= 0: No Excessive Zero (EXZ) Error is detected.
= 1: The Excessive Zero (EXZ) Error is detected.
This bit will be cleared if a ’1’ is written to it.
CV_IS:
= 0: No Bipolar Violation (BPV) Error or HDB3 Code Violation (CV) Error is detected.
= 1: The Bipolar Violation (BPV) Error or HDB3 Code Violation (CV) Error is detected.
This bit will be cleared if a ’1’ is written to it.
CNTOV_IS:
= 0: The internal 16-bit EXZ counter has not overflowed.
= 1: The internal 16-bit EXZ counter has overflowed.
This bit will be cleared if a ‘1’ is written to it.
Programming Information
266
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 EXZ Error Counter H-Byte (03CH, 13CH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
CNTH[7]
CNTH[6]
CNTH[5]
CNTH[4]
CNTH[3]
CNTH[2]
CNTH[1]
CNTH[0]
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
CNTH[7:0]:
These bits, together with the CNTL[7:0] bits, reflect the content in the internal 16-bit EXZ counter.
E1 EXZ Error Counter L-Byte (03DH, 13DH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
CNTL[7]
CNTL[6]
CNTL[5]
CNTL[4]
CNTL[3]
CNTL[2]
CNTL[1]
CNTL[0]
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
2
1
0
CNTL[7:0]:
These bits, together with the CNTH[7:0] bits, reflect the content in the internal 16-bit EXZ counter.
E1 Reference Clock Output Control (03EH, 13EH)
Bit No.
7
6
5
4
3
Bit Name
Type
REFH_LOS
Reserved
Default
R/W
0
REFH_LOS:
In case of LOS, this bit determines the outputs on the REFA_OUT and REFB_OUT pins.
= 0: Output MCLK.
= 1: Output high level.
Programming Information
267
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Interrupt Module Indication 2 (03FH, 13FH)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
LIU
Type
Reserved
R
Default
0
LIU:
= 0: No interrupt is generated in the Receive / Transmit Internal Termination, Adaptive Equalizer, Data Slicer, CLK&Data Recovery, Receive /
Transmit Jitter Attenuator, B8ZS/HDB3/AMI Decoder / Encoder, Waveform Shaper / Line Build Out or Line Driver block.
= 1: Interrupt is generated in the Receive / Transmit Internal Termination, Adaptive Equalizer, Data Slicer, CLK&Data Recovery, Receive / Transmit Jitter Attenuator, B8ZS/HDB3/AMI Decoder / Encoder, Waveform Shaper / Line Build Out or Line Driver function block.
E1 Interrupt Module Indication 0 (040H, 140H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
ALARM
PMON
PRGD
RCRB
FGEN
FRMR
R
R
R
R
R
R
0
0
0
0
0
0
ALARM:
= 0: No interrupt is generated in the Alarm Detector function block.
= 1: Interrupt is generated in the Alarm Detector function block.
PMON:
= 0: No interrupt is generated in the Performance Monitor function block.
= 1: Interrupt is generated in the Performance Monitor function block.
PRGD:
= 0: No interrupt is generated in the PRBS Generator / Detector function block.
= 1: Interrupt is generated in the PRBS Generator / Detector function block.
RCRB:
= 0: No interrupt is generated in the Receive CAS/RBS Buffer function block.
= 1: Interrupt is generated in the Receive CAS/RBS Buffer function block.
FGEN:
= 0: No interrupt is generated in the Frame Generator function block.
= 1: Interrupt is generated in the Frame Generator function block.
FRMR:
= 0: No interrupt is generated in the Frame Processor function block.
= 1: Interrupt is generated in the Frame Processor function block.
Programming Information
268
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Interrupt Module Indication 1 (041H, 141H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
THDLC3
THDLC2
THDLC1
RHDLC3
RHDLC2
RHDLC1
ELST
TRSI/RESI
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
THDLC3:
= 0: No interrupt is generated in the HDLC Transmitter #3 function block.
= 1: Interrupt is generated in the HDLC Transmitter #3 function block.
THDLC2:
= 0: No interrupt is generated in the HDLC Transmitter #2 function block.
= 1: Interrupt is generated in the HDLC Transmitter #2 function block.
THDLC1:
= 0: No interrupt is generated in the HDLC Transmitter #1 function block.
= 1: Interrupt is generated in the HDLC Transmitter #1 function block.
RHDLC3:
= 0: No interrupt is generated in the HDLC Receiver #3 function block.
= 1: Interrupt is generated in the HDLC Receiver #3 function block.
RHDLC2:
= 0: No interrupt is generated in the HDLC Receiver #2 function block.
= 1: Interrupt is generated in the HDLC Receiver #2 function block.
RHDLC1:
= 0: No interrupt is generated in the HDLC Receiver #1 function block.
= 1: Interrupt is generated in the HDLC Receiver #1 function block.
ELST:
= 0: No interrupt is generated in the Elastic Store Buffer function block.
= 1: Interrupt is generated in the Elastic Store Buffer function block.
TRSI/RESI:
= 0: No interrupt is generated in the Transmit / Receive System Interface function block.
= 1: Interrupt is generated in the Transmit / Receive System Interface function block.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 TBIF Option Register (042H, 142H)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
2
1
0
DE
FE
CMS
FSINV
FSTYP
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
DE:
This bit selects the active edge of TSCKn to sample the data on TSDn and TSIGn and the active edge of MTSCK to sample the data on MTSD
and MTSIG.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Transmit Multiplexed mode, the bit of the two links should be set to the same value.
FE:
This bit selects the active edge of TSCKn to update/sample the pulse on TSFSn and the active edge of MTSCK to sample the pulse on MTSFS.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Transmit Multiplexed mode, the bit of the two links should be set to the same value.
CMS:
This bit is valid in Transmit Clock Slave mode and Transmit Multiplexed mode.
= 0: The speed of TSCKn/MTSCK is the same as the data rate on the system side (2.048 Mb/s / 8.192 Mb/s).
= 1: The speed of TSCKn/MTSCK is double the data rate on the system side (4.096 Mb/s / 16.384 Mb/s).
In Transmit Clock Slave mode, if both two links use TSCK[1] and TSFS[1] to input the data (i.e., the TSLVCK bit (b, T1/J1-01H) is set to ‘1’), the
bit of the two links should be set to the same value.
In Transmit Multiplexed mode, the bit of the two links should be set to the same value.
FSINV:
= 0: The transmit framing pulse TSFSn is active high.
= 1: The transmit framing pulse TSFSn is active low.
In Transmit Multiplexed mode, this bit of the two links should be set to the same value.
FSTYP:
= 0: In Transmit Non-multiplexed mode, TSFSn pulses during the first bit of each Basic frame. In Transmit Multiplexed mode, MTSFS pulses during the first bit of each Basic frame of the first link.
= 1: In Transmit Non-multiplexed mode, if the CRC Multi-frame is to be generated, TSFSn pulses during the first bit of each CRC Multi-frame; if
the Signaling Multi-frame is to be generated, TSFSn pulses during the first bit of each Signaling Multi-frame; if both the CRC Multi-frame and the Signaling Multi-frame are to be generated, TSFSn goes high/low during the first bit of each Signaling Multi-frame and goes the opposite during the second bit of each CRC Multi-frame. In Transmit Multiplexed mode, if the CRC Multi-frame is to be generated, MTSFS pulses during the first bit of each
CRC Multi-frame of the first link; if the Signaling Multi-frame is to be generated, MTSFS pulses during the first bit of each Signaling Multi-frame of the
first link; if both the CRC Multi-frame and the Signaling Multi-frame are to be generated, MTSFS goes high/low during the first bit of each Signaling
Multi-frame and goes the opposite during the second bit of each CRC Multi-frame of the first link.
In Transmit Multiplexed mode, this bit of the two links should be set to the same value.
Programming Information
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August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 TBIF Operating Mode (043H, 143H)
Bit No.
7
6
5
4
3
Bit Name
Type
2
1
0
TMODE
Reserved
Default
R/W
1
TMODE:
In Transmit Non-multiplexed mode, this bit selects the sub-mode.
= 0: The Transmit System Interface is operated in Transmit Clock Master mode. The timing signal for clocking the data and the framing pulse to
align the data input on the TSDn pin are provided from the processed data from the device.
= 1: The Transmit System Interface is operated in Transmit Clock Slave mode. The timing signal for clocking the data and the framing pulse to
align the data input on the TSDn pin are provided by the system side.
Programming Information
271
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 TBIF TS Offset (044H, 144H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
TSOFF6
TSOFF5
TSOFF4
TSOFF3
TSOFF2
TSOFF1
TSOFF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
TSOFF[6:0]:
These bits give a binary number to define the timeslot offset. The timeslot offset is between the framing pulse on the TSFSn/MTSFS pin and the
start of the corresponding frame input on the TSDn/MTSD pin. The signaling bits on the TSIGn/MTSIG pin are always per-timeslot aligned with the
data on the TSDn/MTSD pin.
In Non-multiplexed mode, the timeslot offset can be configured from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the timeslot offset can be configured from 0 to 127 timeslots (0 & 127 are included).
E1 TBIF Bit Offset (045H, 145H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
EDGE
BOFF2
BOFF1
BOFF0
R/W
R/W
R/W
R/W
0
0
0
0
EDGE:
This bit is valid when the CMS bit (b2, E1-042H,...) is ‘1’.
= 0: The first active edge of TSCKn/MTSCK is selected to sample the data on the TSDn/MTSD and TSIGn/MTSIG pins.
= 1: The second active edge of TSCKn/MTSCK is selected to sample the data on the TSDn/MTSD and TSIGn/MTSIG pins.
BOFF[2:0]:
These bits give a binary number to define the bit offset. The bit offset is between the framing pulse on the TSFSn/MTSFS pin and the start of the
corresponding frame input on the TSDn/MTSD pin. The signaling bits on the TSIGn/MTSIG pin are always per-timeslot aligned with the data on the
TSDn/MTSD pin.
Programming Information
272
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RBIF Option Register (046H, 146H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
DE
FE
CMS
TRI
R/W
R/W
R/W
R/W
1
1
0
1
DE:
This bit selects the active edge of RSCKn to update the data on RSDn and RSIGn and the active edge of MRSCK to update the data on MRSD
and MRSIG.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Receive Multiplexed mode, the bit of the two links should be set to the same value.
FE:
This bit selects the active edge of RSCKn to update/sample the pulse on RSFSn and the active edge of MRSCK to sample the pulse on MRSFS.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Receive Multiplexed mode, the bit of the two links should be set to the same value.
CMS:
This bit is valid in Receive Clock Slave mode and Receive Multiplexed mode.
= 0: The speed of RSCKn/MRSCK is the same as the data rate on the system side (2.048 Mb/s / 8.192 Mb/s).
= 1: The speed of RSCKn/MRSCK is double the data rate on the system side (4.096 Mb/s / 16.384 Mb/s).
In Receive Clock Slave mode, if both two links use the RSCK[1] and RSFS[1] to output the data (i.e., the RSLVCK bit (b, E1-01H) is set to ‘1’), the
bit of the two links should be set to the same value.
In Receive Multiplexed mode, the bit of the two links should be set to the same value.
TRI:
= 0: The processed data and signaling bits are output on the RSDn/MRSD and RSIGn/MRSIG pins respectively.
= 1: The output on the RSDn/MRSD and RSIGn/MRSIG pins are in high impedance.
Programming Information
273
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RBIF Mode (047H, 147H)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
RMODE
Type
Reserved
R/W
Default
1
RMODE:
In Receive Non-multiplexed mode, this bit selects the sub-mode.
= 0: The Receive System Interface is operated in Receive Clock Master mode. The timing signal for clocking the data and the framing pulse to
align the data output on the RSDn pin are received from each line side.
= 1: The Receive System Interface is operated in Receive Clock Slave mode. The timing signal for clocking the data and the framing pulse to
align the data output on the RSDn pin are provided by the system side.
E1 RBIF Frame Pulse (048H, 148H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
FSINV
OHD
SMFS
CMFS
R/W
R/W
R/W
R/W
0
0
0
0
0
Reserved
FSINV:
= 0: The receive framing pulse RSFSn is active high.
= 1: The receive framing pulse RSFSn is active low.
In Receive Multiplexed mode, this bit of the two links should be set to the same value.
OHD, SMFS, CMFS:
In Receive Clock Master mode, these bits select what the pulse on RSFSn indicates.
OHD
SMFS
CMFS
RSFSn Indication
0
0
0
0
0
0
1
1
0
1
0
1
1
0
0
The RSFSn pulses during the first bit of each Basic frame.
The RSFSn pulses during the first bit of each CRC Multi-frame.
The RSFSn pulses during the first bit of each Signaling Multi-frame.
The RSFSn goes high/low during the first bit of each Signaling Multi-frame and goes the opposite during the second bit of each CRC Multi-frame.
The RSFSn pulses during the TS0 and TS16.
Programming Information
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August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RBIF TS Offset (049H, 149H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
TSOFF6
TSOFF5
TSOFF4
TSOFF3
TSOFF2
TSOFF1
TSOFF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
TSOFF[6:0]:
Except that in the Receive Master mode, when the OHD bit (b3, E1-048H,...), the SMFS bit (b2, E1-048H,...) and the CMFS bit (b1, E1-048H,...)
are set to TS1 and TS16 overhead indication, the timeslot offset is supported in all the other conditions.
These bits give a binary number to define the timeslot offset. The timeslot offset is between the framing pulse on the RSFSn/MRSFS pin and the
start of the corresponding frame output on the RSDn/MRSD pin. The signaling bits on the RSIGn/MRSIG pin are always per-timeslot aligned with the
data on the RSDn/MRSD pin.
In Non-multiplexed mode, the timeslot offset can be configured from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the timeslot offset can be configured from 0 to 127 timeslots (0 & 127 are included).
E1 RBIF Bit Offset (04AH, 14AH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
EDGE
BOFF2
BOFF1
BOFF0
R/W
R/W
R/W
R/W
0
0
0
0
EDGE:
This bit is valid when the CMS bit (b1, E1-046H,...) is ‘1’.
= 0: The first active edge of RSCKn/MRSCK is selected to update the data on the RSDn/MRSD and RSIGn/MRSIG pins.
= 1: The second active edge of RSCKn/MRSCK is selected to update the data on the RSDn/MRSD and RSIGn/MRSIG pins.
BOFF[2:0]:
Except that in the Receive Master mode, when the OHD bit (b3, E1-048H,...), the SMFS bit (b2, E1-048H,...) and the CMFS bit (b1, E1-048H,...)
are set to TS1 and TS16 overhead indication, the bit offset is supported in all the other conditions.
These bits give a binary number to define the bit offset. The bit offset is between the framing pulse on the RSFSn/MRSFS pin and the start of the
corresponding frame output on the RSDn/MRSD pin. The signaling bits on the RSIGn/MRSIG pin are always per-channel aligned with the data on the
RSDn/MRSD pin.
Programming Information
275
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RTSFS Change Indication (04BH, 14BH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
RCOFAI
TCOFAI
R
R
0
0
1
0
RCOFAE
TCOFAE
R/W
R/W
0
0
RCOFAI:
This bit is valid in Receive Clock Slave mode and Receive Multiplexed mode.
= 0: The interval of the pulses on the RSFSn/MRSFS pin is an integer multiple of 125 µs.
= 1: The interval of the pulses on the RSFSn/MRSFS pin is not an integer multiple of 125 µs.
This bit will be cleared if a ’1’ is written to it.
TCOFAI:
This bit is valid in Transmit Clock Slave mode and Transmit Multiplexed mode.
= 0: The pulse on the TSFSn/MTSFS pin is an integer multiple of 125 µs.
= 1: The pulse on the TSFSn/MTSFS pin is not an integer multiple of 125 µs.
This bit will be cleared if a ’1’ is written to it.
E1 RTSFS Interrupt Control (04CH, 14CH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
RCOFAE:
= 0: Disable the interrupt on the INT pin when the RCOFAI bit (b1, E1-04BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the RCOFAI bit (b1, E1-04BH,...) is ‘1’.
TCOFAE:
= 0: Disable the interrupt on the INT pin when the TCOFAI bit (b0, E1-04BH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the TCOFAI bit (b0, E1-04BH,...) is ‘1’.
Programming Information
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August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FRMR Mode 0 (04DH, 14DH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
UNFM
REFCRCE
REFEN
REFR
R/W
R/W
R/W
R/W
0
1
1
0
UNFM:
= 0: The data stream is received in framed mode and is processed by the Frame Processor.
= 1: The data stream is received in unframed mode and the Frame Processor is bypassed.
REFCRCE:
= 0: disable from re-searching for synchronization when the Excessive CRC-4 Error occurs.
= 1: Search for synchronization again when the Excessive CRC-4 Error occurs. This function can only be implemented only if the REFEN bit is
logic 1.
REFEN:
= 0: “Locked in frame”. Once the previous Basic frame synchronization is acquired, and no errors can lead to reframe except for manually setting
by the REFR bit.
= 1: Search for Basic frame synchronization again when it is out of synchronization.
REFR:
A transition from logic 0 to logic 1 forces to re-search for a new Basic frame synchronization.
Programming Information
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August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FRMR Mode 1 (04EH, 14EH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
BIT2C
CASEN
CRCEN
CNTNFAS
WORDERR
TS16C
SMFASC
C2NCIWCK
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
1
1
0
0
0
0
0
BIT2C:
This bit determines the criteria of out of Basic frame synchronization.
= 0: 3 consecutive FAS pattern errors lead to out of Basic frame synchronization.
= 1: 3 consecutive FAS pattern errors or 3 consecutive NFAS errors lead to out of Basic frame synchronization.
CASEN:
= 0: Disable searching for the Channel Associated Signaling (CAS) Multi-Frame.
= 1: Enable searching for the Channel Associated Signaling (CAS) Multi-Frame after the Basic frame synchronization is acquired.
CRCEN:
= 0: Disable searching for the CRC Multi-Frame.
= 1: Enable searching for the CRC Multi-Frame after the Basic frame synchronization is acquired.
CNTNFAS & WORDERR:
These two bits determine the criteria of FAS/NFAS Bit/Pattern Error generation:
WORDERR
CNTNFAS
0
1
0
1
0
0
1
1
Error Generation
Each bit error in FAS is counted as an error event.
A FAS pattern error is counted as an error event.
Each bit error in FAS or NFAS error is counted as an error event.
A FAS pattern error or NFAS error is counted as an error event.
TS16C & SMFASC:
These two bits determine the criteria of out of CAS Signaling Multi-Frame synchronization:
TS16C
SMFASC
Out Of CAS Signaling Multi-Frame Synchronization Criteria
X
0
0
1
1
1
2 consecutive CAS Signaling Multi-Frame Alignment Pattern Errors occur.
2 consecutive CAS Signaling Multi-Frame Alignment Pattern Errors occur or all the contents in TS16 are zeros for one
Signaling Multi-Frame.
2 consecutive CAS Signaling Multi-Frame Alignment Pattern Errors occur or all the contents in TS16 are zeros for two
consecutive Signaling Multi-Frames.
C2NCIWCK:
= 0: Stop searching for CRC Multi-Frame alignment pattern in CRC to non-CRC interworking mode.
= 1: Enable searching for CRC Multi-Frame alignment pattern even if CRC to non-CRC interworking has been declared.
Programming Information
278
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FRMR Status (04FH, 14FH)
Bit No.
7
6
5
Bit Name
Type
Reserved
Default
4
3
2
1
0
C2NCIWV
OOSMFV
OOCMFV
OOOFV
OOFV
R
R
R
R
R
0
1
1
0
1
C2NCIWV:
= 0: The Frame Processor does not operate in CRC to non-CRC interworking mode.
= 1: The Frame Processor operates in CRC to non-CRC interworking mode.
OOSMFV:
= 0: The CAS Signaling Multi-Frame is in synchronization.
= 1: The CAS Signaling Multi-Frame is out of synchronization.
OOCMFV:
= 0: The CRC Multi-Frame is in synchronization.
= 1: The CRC Multi-Frame is out of synchronization.
OOOFV:
= 0: The offline Basic frame is in synchronization.
= 1: The offline Basic frame is out of synchronization.
OOFV:
= 0: The Basic frame is in synchronization.
= 1: The Basic frame is out of synchronization.
Programming Information
279
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FRMR Interrupt Control 0 (050H, 150H)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
2
1
0
C2NCIWE
OOSMFE
OOCMFE
OOOFE
OOFE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
C2NCIWE:
= 0: Disable the interrupt on the INT pin when the C2NCIWI bit (b4, E1-052H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the C2NCIWI bit (b4, E1-052H,...) is ‘1’.
OOSMFE:
= 0: Disable the interrupt on the INT pin when the OOSMFI bit (b3, E1-052H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the OOSMFI bit (b3, E1-052H,...) is ‘1’.
OOCMFE:
= 0: Disable the interrupt on the INT pin when the OOCMFI bit (b2, E1-052H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the OOCMFI bit (b2, E1-052H,...) is ‘1’.
OOOFE:
= 0: Disable the interrupt on the INT pin when the OOOFI bit (b1, E1-052H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the OOOFI bit (b1, E1-052H,...) is ‘1’.
OOFE:
= 0: Disable the interrupt on the INT pin when the OOFI bit (b0, E1-052H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the OOFI bit (b0, E1-052H,...) is ‘1’.
Programming Information
280
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FRMR Interrupt Control 1 (051H, 151H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
ISMFPE
ICSMFPE
SMFERE
ICMFPE
CMFERE
CRCEE
FERE
COFAE
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
ISMFPE:
= 0: Disable the interrupt on the INT pin when the ISMFPI bit (b4, T1/J1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the ISMFPI bit (b4, T1/J1-053H,...) is ‘1’.
ICSMFPE:
= 0: Disable the interrupt on the INT pin when the ICSMFPI bit (b3, T1/J1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the ICSMFPI bit (b3, T1/J1-053H,...) is ‘1’.
SMFERE:
= 0: Disable the interrupt on the INT pin when the SMFERI bit (b2, E1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SMFERI bit (b2, E1-053H,...) is ‘1’.
ICMFPE:
= 0: Disable the interrupt on the INT pin when the ICMFPI bit (b2, T1/J1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the ICMFPI bit (b2, T1/J1-053H,...) is ‘1’.
CMFERE:
= 0: Disable the interrupt on the INT pin when the CMFERI bit (b2, E1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the CMFERI bit (b2, E1-053H,...) is ‘1’.
CRCEE:
= 0: Disable the interrupt on the INT pin when the CRCEI bit (b2, T1/J1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the CRCEI bit (b2, T1/J1-053H,...) is ‘1’.
FERE:
= 0: Disable the interrupt on the INT pin when the FERI bit (b1, E1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the FERI bit (b1, E1-053H,...) is ‘1’.
COFAE:
= 0: Disable the interrupt on the INT pin when the COFAI bit (b0, E1-053H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the COFAI bit (b0, E1-053H,...) is ‘1’.
Programming Information
281
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FRMR Interrupt Indication 0 (052H, 152H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
EXCRCERI
C2NCIWI
OOSMFI
OOCMFI
OOOFI
OOFI
R
R
R
R
R
R
0
0
0
0
0
0
EXCRCERI:
When CRC Multi-Frame is synchronized, once the accumulated CRC-4 errors are not less than 915 (≥915) in a 1 second fixed window, an
excessive CRC-4 error event is generated. During out of CRC Multi-Frame synchronization state, the Excessive CRC-4 Error detection is suspended.
= 0: No Excessive CRC-4 Error event is detected.
= 1: The Excessive CRC-4 Error event is detected.
This bit will be cleared if a ’1’ is written to it.
C2NCIWI:
= 0: There is no status change on the C2NCIWV bit (b4, E1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the C2NCIWV bit (b4, E1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
OOSMFI:
= 0: There is no status change on the OOSMFV bit (b3, E1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the OOSMFV bit (b3, E1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
OOCMFI:
= 0: There is no status change on the OOCMFV bit (b2, E1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the OOCMFV bit (b2, E1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
OOOFI:
= 0: There is no status change on the OOOFV bit (b1, E1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the OOOFV bit (b1, E1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
OOFI:
= 0: There is no status change on the OOFV bit (b0, E1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the OOFV bit (b0, E1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FRMR Interrupt Indication 1 (053H, 153H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
ISMFPI
ICSMFPI
SMFERI
ICMFPI
CMFERI
CRCEI
FERI
COFAI
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
ISMFPI:
= 0: The received bit is not the first bit of each CAS Signaling Multi-Frame.
= 1: The first bit of each CAS Signaling Multi-Frame is received.
This bit will be cleared if a ’1’ is written to it. It can not be updated during out of CAS Signaling Multi-Frame synchronization state
ICSMFPI:
= 0: The received bit is not the first bit of each CRC Sub Multi-Frame.
= 1: The first bit of each CRC Sub Multi-Frame is received.
This bit will be cleared if a ’1’ is written to it. It can not be updated during out of CRC Multi-Frame synchronization state.
SMFERI:
When Signaling Multi-Frame is synchronized, the received Signaling Multi-Frame alignment signals are compared with the expected one (‘0000’).
When one or more bits do not match, a single CAS Signaling Multi-Frame alignment pattern error event is generated. During out of CAS Signaling
Multi-Frame synchronization state, the CAS Signaling Multi-Frame Alignment Pattern Error detection is suspended.
= 0: No CAS Signaling Multi-Frame Alignment Pattern Error event is detected.
= 1: The CAS Signaling Multi-Frame Alignment Pattern Error event is detected.
This bit will be cleared if a ’1’ is written to it.
ICMFPI:
= 0: The received bit is not the first bit of each CRC Multi-Frame.
= 1: The first bit of each CRC Multi-Frame is received.
This bit will be cleared if a ’1’ is written to it. It can not be updated during out of CRC Multi-Frame synchronization state.
CMFERI:
When CRC Multi-Frame is synchronized, the received CRC Multi-Frame alignment signals are compared with the expected one (‘001011’). If one
or more bits do not match, a single CRC Multi-Frame alignment pattern error event is generated. During out of CRC Multi-Frame synchronization
state, the CRC Multi-Frame Alignment Pattern Error detection is suspended.
= 0: No CRC Multi-Frame Alignment Pattern Error event is detected.
= 1: The CRC Multi-Frame Alignment Pattern Error event is detected.
This bit will be cleared if a ’1’ is written to it.
CRCEI:
When CRC Multi-Frame is synchronized and the local calculated CRC-4 of the current received CRC Sub Multi-Frame does not match the
received CRC-4 of the next received CRC Sub Multi-Frame, a single CRC-4 error event is generated. During out of CRC Multi-Frame synchronization
state, the CRC-4 Error detection is suspended.
= 0: No CRC-4 Error event is detected.
= 1: The CRC-4 Error event is detected.
This bit will be cleared if a ’1’ is written to it.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
FERI:
When Basic frame is synchronized and the criteria set by the WORDERR bit (b3, E1-04EH,...) and the CNTNFAS bit (b4, E1-04EH,...) are met, a
FAS/NFAS Bit/Pattern Error event is generated. During out of Basic frame synchronization state, the FAS/NFAS Bit/Pattern Error detection is suspended.
= 0: No FAS/NFAS Bit/Pattern Error event is detected.
= 1: The FAS/NFAS Bit/Pattern Error event is detected.
This bit will be cleared if a ’1’ is written to it.
COFAI:
= 0: The Basic frame alignment pattern position is not changed.
= 1: The new-found Basic frame alignment pattern position differs from the previous one.
This bit will be cleared if a ’1’ is written to it.
E1 TS0 International / National (054H, 154H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
Si0
Si1
A
Sa4
Sa5
Sa6
Sa7
Sa8
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Si0:
This bit reflects the content in the International bit of the latest received NFAS frame. It is updated on the boundary of the associated NFAS frame
and is held during out of Basic frame state.
Si1:
This bit reflects the content in the International bit of the latest received FAS frame. It is updated on the boundary of the associated FAS frame
and is held during out of Basic frame state.
A:
This bit reflects the content in the Remote Alarm Indication bit of the latest received NFAS frame. It is updated on the boundary of the associated
NFAS frame and is held during out of Basic frame state.
Sa[4:8]:
These bits reflect the content in the National bit of the latest received NFAS frame. They are updated on the boundary of the associated NFAS
frame and are held during out of Basic frame state.
Programming Information
284
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 TS16 Spare (055H, 155H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
X0
Y
X1
X2
R
R
R
R
0
0
0
0
X[0:2]:
These bits reflect the content in the Extra bits. They are updated at the first bit of the next CAS Signaling Multi-Frame and are held during out of
CAS Signaling Multi-Frame state.
Y:
This bit reflects the content in the Remote Signaling Multi-Frame Alarm Indication bit. It is updated at the first bit of the next CAS Signaling MultiFrame and is held during out of CAS Signaling Multi-Frame state.
E1 Sa4 Codeword (056H, 156H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
Sa41
Sa42
Sa43
Sa44
R
R
R
R
0
0
0
0
Sa4[1:4]:
These bits reflect the content in the Sa4 National Bit codeword.
If de-bounce is enabled by the SaDEB bit (b6, E1-05CH,...), they are updated when the received Sa4 National Bit codeword is the same for 2
consecutive CRC Sub Multi-Frames. If de-bounce is disabled, they are updated every CRC Sub Multi-Frame. These bits are held during out of CRC
Multi-Frame synchronization state.
Programming Information
285
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Sa5 Codewo3rd (057H, 157H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
Sa51
Sa52
Sa53
Sa54
R
R
R
R
0
0
0
0
Sa5[1:4]:
These bits reflect the content in the Sa5 National Bit codeword.
If de-bounce is enabled by the SaDEB bit (b6, E1-05CH,...), they are updated when the received Sa5 National Bit codeword is the same for 2
consecutive CRC Sub Multi-Frames. If de-bounce is disabled, they are updated every CRC Sub Multi-Frame. These bits are held during out of CRC
Multi-Frame synchronization state.
E1 Sa6 Codeword (058H, 158H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
Sa61
Sa62
Sa63
Sa64
R
R
R
R
0
0
0
0
Sa6[1:4]:
These bits reflect the content in the Sa6 National Bit codeword.
If de-bounce is enabled by the SaDEB bit (b6, E1-05CH,...), they are updated when the received Sa6 National Bit codeword is the same for 2
consecutive CRC Sub Multi-Frames. If de-bounce is disabled, they are updated every CRC Sub Multi-Frame. These bits are held during out of CRC
Multi-Frame synchronization state.
Programming Information
286
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Sa7 Codeword (059H, 159H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
Sa71
Sa72
Sa73
Sa74
R
R
R
R
0
0
0
0
Sa7[1:4]:
These bits reflect the content in the Sa7 National Bit codeword.
If de-bounce is enabled by the SaDEB bit (b6, E1-05CH,...), they are updated when the received Sa7 National Bit codeword is the same for 2
consecutive CRC Sub Multi-Frames. If de-bounce is disabled, they are updated every CRC Sub Multi-Frame. These bits are held during out of CRC
Multi-Frame synchronization state.
E1 Sa8 Codeword (05AH, 15AH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
Sa81
Sa82
Sa83
Sa84
R
R
R
R
0
0
0
0
Sa8[1:4]:
These bits reflect the content in the Sa8 National Bit codeword.
If de-bounce is enabled by the SaDEB bit (b6, E1-05CH,...), they are updated when the received Sa8 National Bit codeword is the same for 2
consecutive CRC Sub Multi-Frames. If de-bounce is disabled, they are updated every CRC Sub Multi-Frame. These bits are held during out of CRC
Multi-Frame synchronization state.
Programming Information
287
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Sa6 Codeword Indication (05BH, 15BH)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
2
1
0
Sa6-FI
Sa6-EI
Sa6-CI
Sa6-AI
Sa6-8I
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Sa6-FI:
= 0: Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are not matched with 0xFFF.
= 1: Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are matched with 0xFFF.
Sa6-EI:
= 0: Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are not matched with 0xEEE.
= 1: Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are matched with 0xEEE.
Sa6-CI:
= 0: Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are not matched with 0xCCC.
= 1: Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are matched with 0xCCC.
Sa6-AI:
= 0: Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are not matched with 0xAAA.
= 1: Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are matched with 0xAAA.
Sa6-8I:
= 0: Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are not matched with 0x888.
= 1: Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are matched with 0x888.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Sa Codeword Interrupt Control (05CH, 15CH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
Sa6SYN
SaDEB
Sa6SCE
Sa4E
Sa5E
Sa6E
Sa7E
Sa8E
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Sa6SYN:
= 0: Any 12 consecutive Sa6 bits are compared with 0x888, 0xAAA, 0xCCC, 0xEEE and 0xFFF when CRC Multi-Frame is synchronized.
= 1: Any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are compared with 0x888, 0xAAA, 0xCCC, 0xEEE and 0xFFF when
CRC Multi-Frame is synchronized.
SaDEB:
= 0: Disable the de-bounce function of the National Bit codeword extraction.
= 1: Enable the de-dounce function of the National Bit codeword extraction.
Sa6SCE:
= 0: Disable the interrupt on the INT pin when the SCAI bit (b3, T1/J1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SCAI bit (b3, T1/J1-05DH,...) is ‘1’.
Sa4E:
= 0: Disable the interrupt on the INT pin when the Sa4I bit (b2, E1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the Sa4I bit (b2, E1-05DH,...) is ‘1’.
Sa5E:
= 0: Disable the interrupt on the INT pin when the Sa5I bit (b2, E1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the Sa5I bit (b2, E1-05DH,...) is ‘1’.
Sa6E:
= 0: Disable the interrupt on the INT pin when the Sa6I bit (b2, E1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the Sa6I bit (b2, E1-05DH,...) is ‘1’.
Sa7E:
= 0: Disable the interrupt on the INT pin when the Sa7I bit (b2, E1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the Sa7I bit (b2, E1-05DH,...) is ‘1’.
Sa8E:
= 0: Disable the interrupt on the INT pin when the Sa8I bit (b2, E1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the Sa8I bit (b2, E1-05DH,...) is ‘1’.
Programming Information
289
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Sa Codeword Interrupt Indication (05DH, 15DH)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
Sa6SCI
Sa4I
Sa5I
Sa6I
Sa7I
Sa8I
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Sa6SCI:
= 0: Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are not matched with 0x888, 0xAAA,
0xCCC, 0xEEE or 0xFFF.
= 1: Any 12 consecutive Sa6 bits or any 3 consecutive 4-bit Sa6 codewords in the CRC Sub Multi-Frame are matched with 0x888, 0xAAA,
0xCCC, 0xEEE or 0xFFF.
Sa4I:
= 0: The value in the Sa4[1:4] bits is not changed.
= 1: The value in the Sa4[1:4] bits is changed.
Sa5I:
= 0: The value in the Sa5[1:4] bits is not changed.
= 1: The value in the Sa5[1:4] bits is changed.
Sa6I:
= 0: The value in the Sa6[1:4] bits is not changed.
= 1: The value in the Sa6[1:4] bits is changed.
Sa7I:
= 0: The value in the Sa7[1:4] bits is not changed.
= 1: The value in the Sa7[1:4] bits is changed.
Sa8I:
= 0: The value in the Sa8[1:4] bits is not changed.
= 1: The value in the Sa8[1:4] bits is changed.
Programming Information
290
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Overhead Error Status (05FH, 15FH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
RAICRCV
CFEBEV
V52LINKV
R
R
R
0
0
0
RAICRCV:
The Continuous RAI & FEBE Error event is detected on the base of CRC Multi-Frame synchronization.
= 0: No Continuous RAI & FEBE Error event is detected.
= 1: The Continuous RAI & FEBE Error event is detected, i.e., a logic 1 is received in the A bit and a logic 0 is received in any of the E1 and E2
bits for 10ms.
CFEBEV:
The Continuous FEBE Error event is detected on the base of CRC Multi-Frame synchronization.
= 0: No Continuous FEBE Error event is detected.
= 1: The Continuous FEBE Error event is detected, i.e., a logic 0 is received in any of the E1 or E2 bit on ≥ 990 occasions per second for the latest 5 consecutive seconds.
V52LINKV:
The V5.2 link ID signal can be received on the base of Basic Frame synchronization.
= 0: The V5.2 link ID signal is not received.
= 1: The V5.2 link ID signal is received, i.e., 2 out of 3 sliding Sa7 bits are logic 0s.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Overhead Interrupt Control (060H, 160H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
TCRCEE
TFEBEE
FEBEE
RAICRCE
CFEBEE
V52LINKE
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
TCRCEE:
= 0: Disable the interrupt on the INT pin when the TCRCEI bit (b3, E1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the TCRCEI bit (b3, E1-05DH,...) is ‘1’.
TFEBEE:
= 0: Disable the interrupt on the INT pin when the TFEBEI bit (b3, E1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the TFEBEI bit (b3, E1-05DH,...) is ‘1’.
FEBEE:
= 0: Disable the interrupt on the INT pin when the FEBEI bit (b3, E1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the FEBEI bit (b3, E1-05DH,...) is ‘1’.
RAICRCE:
= 0: Disable the interrupt on the INT pin when the RAICRCI bit (b3, E1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the RAICRCI bit (b3, E1-05DH,...) is ‘1’.
CFEBEE:
= 0: Disable the interrupt on the INT pin when the CFEBEI bit (b3, E1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the CFEBEI bit (b3, E1-05DH,...) is ‘1’.
V52LINKE:
= 0: Disable the interrupt on the INT pin when the V52LINKI bit (b0, E1-05DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the V52LINKI bit (b0, E1-05DH,...) is ‘1’.
Programming Information
292
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Overhead Interrupt Indication (061H, 161H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
TCRCEI
TFEBEI
FEBEI
RAICRCI
CFEBEI
V52LINKI
R
R
R
R
R
R
0
0
0
0
0
0
TCRCEI:
If the 4-bit Sa6 codeword of a CRC Sub Multi-Frame is matched with ‘0010’ or ‘0011’, the Network Terminal CRC Error event is generated.
= 0: No NT CRC Error event is detected.
= 1: The NT CRC Error event is detected.
This bit will be cleared if a ’1’ is written to it.
TFEBEI:
If the 4-bit Sa6 codeword of a CRC Sub Multi-Frame is matched with ‘0001’ or ‘0011’, the Network Terminal Far End Block Error event is generated.
= 0: No NT FEBE Error event is detected.
= 1: The NT FEBE Error event is detected.
This bit will be cleared if a ’1’ is written to it.
FEBEI:
When CRC Multi-Frame is synchronized and any of the CRC error indication (E1 or E2) bits is received as a logic 0, a far end block error event is
generated. During out of CRC Multi-Frame synchronization state, the Far End Block Error (FEBE) detection is suspended.
= 0: No Far End Block Error (FEBE) event is detected.
= 1: The Far End Block Error (FEBE) event is detected.
This bit will be cleared if a ’1’ is written to it.
RAICRCI:
= 0: There is no status change on the RAICRCV bit (b, E1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the RAICRCV bit (b2, E1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
CFEBEI:
= 0: There is no status change on the CFEBEV bit (b, E1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the CFEBEV bit (b, E1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
V52LINKI:
= 0: There is no status change on the V52LINKV bit (b, E1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the V52LINKV bit (b, E1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
Programming Information
293
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Mode (062H, 162H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
XDIS
SiDIS
FEBEDIS
CRCM
SIGEN
GENCRC
FDIS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
1
0
XDIS:
This bit is valid when the Signaling Multi-frame is generated.
= 0: The Extra bits (the Bit 5, 7 & 8 of TS16 of Frame 0 of the Signaling Multi-Frame) are replaced by the value set in the X[0:2] bits (b3 & b1~0,
E1-06AH,...).
= 1: Disable the Extra bits to be replaced by the value set in the X[0:2] bits (b3 & b1~0, E1-06AH,...).
SiDIS:
When the Basic frame is generated, this bit determines how to replace the International bit.
= 0: The International bit (Bit 1) of FAS frame and NFAS frame are replaced by the value set in the Si[1] (b0, E1-063H,...) and Si[0] bits (b1, E1063H,...) respectively.
= 1: Disable the International bit (Bit 1) of FAS frame and NFAS frame to be replaced by the value set in the Si[1] (b0, E1-063H,...) and Si[0] bits
(b1, E1-063H,...) respectively.
When the CRC Multi-frame is generated, this bit, together with the FEBEDIS bit (b4, E1-062H,...) and the OOCMFV bit (b2, E1-04FH,...), determines how to replace the E bit (refer to the description of the FEBEDIS bit).
.
FEBEDIS:
When the CRC Multi-frame is generated, this bit, together with the SiDIS bit (b5, E1-062H,...) and the OOCMFV bit (b2, E1-04FH,...), determines
how to replace the E bit.
FEBEDIS (b4, E1-062H,...)
OOCMFV (b2, E1-04FH,...)
SiDIS (b5, E1-062H,...)
0
0
X
0
1
X
1
X
0
1
X
1
E Bits Insertion
A single zero is inserted into the E bit when a CRC-4 Error event is
detected in the receive path. (the E1 bit corresponds to SMFI and the E2
bit corresponds to SMFII)
The value in the Si[1] bit (b0, E1-063H,...) is inserted into the E1 bit position. The value in the Si[0] bit (b1, E1-063H,...) is inserted into the E2 bit
position.
The value in the Si[1] bit (b0, E1-063H,...) is inserted into the E1 bit position. The value in the Si[0] bit (b1, E1-063H,...) is inserted into the E2 bit
position.
The E bit positions are unchanged.
CRCM, SIGEN, GENCRC:
These bits are valid when the FDIS bit (b0, E1-062H,...) is 0. They control what kind of frame is generated:
SIGEN =1: signaling multiframe enable
GENCRC=1: CRC multiframe enable
CRCM=1: Modified CRC multiframe. This bit is only valid when GENCRC=1.
FDIS:
= 0: Enable the generation of the Basic frame, CRC Multi-Frame and Channel Associated Signaling (CAS) Multi-Frame.
= 1: Disable the generation of the Basic frame, CRC Multi-Frame and Channel Associated Signaling (CAS) Multi-Frame.
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FGEN International Bit (063H, 163H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
Si0
Si1
R/W
R/W
1
1
Si0:
When the Basic frame is generated and the SiDIS bit (b5, E1-062H,...) is ‘0’, it contains the value to replace the International bit (Bit 1) of the
NFAS frame.
When the CRC Multi-frame is generated, controlled by the FEBEDIS bit (b4, E1-062H,...), the OOCMFV bit (b2, E1-04FH,...) bit and the SiDIS bit
(b5, E1-062H,...), it contains the value to replace the E2 bit.
Si1:
When the Basic frame is generated and the SiDIS bit (b5, E1-062H,...) is ‘0’, it contains the value to replace the International bit (Bit 1) of the FAS
frame.
When the CRC Multi-frame is generated, controlled by the FEBEDIS bit (b4, E1-062H,...), the OOCMFV bit (b2, E1-04FH,...) bit and the SiDIS bit
(b5, E1-062H,...), it contains the value to replace the E1 bit.
Programming Information
295
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FGEN Sa Control (064H, 164H)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
2
1
0
Sa4EN
Sa5EN
Sa6EN
Sa7EN
Sa8EN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Sa4EN:
This bit is valid when the Basic frame is generated.
= 0: Disable the Sa4[1:4] bits to be replaced by the value set in the Sa4[1:4] bits (b3~0, E1-065H,...).
= 1: The Sa4[1:4] bits are replaced by the value set in the Sa4[1:4] bits (b3~0, E1-065H,...).
Sa5EN:
This bit is valid when the Basic frame is generated.
= 0: Disable the Sa5[1:4] bits to be replaced by the value set in the Sa5[1:4] bits (b3~0, E1-066H,...).
= 1: The Sa5[1:4] bits are replaced by the value set in the Sa5[1:4] bits (b3~0, E1-066H,...).
Sa6EN:
This bit is valid when the Basic frame is generated.
= 0: Disable the Sa6[1:4] bits to be replaced by the value set in the Sa6[1:4] bits (b3~0, E1-067H,...).
= 1: The Sa6[1:4] bits are replaced by the value set in the Sa6[1:4] bits (b3~0, E1-067H,...).
Sa7EN:
This bit is valid when the Basic frame is generated.
= 0: Disable the Sa7[1:4] bits to be replaced by the value set in the Sa7[1:4] bits (b3~0, E1-068H,...).
= 1: The Sa7[1:4] bits are replaced by the value set in the Sa7[1:4] bits (b3~0, E1-068H,...).
Sa8EN:
This bit is valid when the Basic frame is generated.
= 0: Disable the Sa8[1:4] bits to be replaced by the value set in the Sa8[1:4] bits (b3~0, E1-069H,...).
= 1: The Sa8[1:4] bits are replaced by the value set in the Sa8[1:4] bits (b3~0, E1-069H,...).
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Sa4 Code-word (065H, 165H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
Sa41
Sa42
Sa43
Sa44
R/W
R/W
R/W
R/W
1
1
1
1
Sa4[1:4]:
These bits are valid when the Basic frame is generated and the Sa4EN bit (b4, E1-064H,...) is ‘1’. When only the Basic frame is generated, the
value in the Sa4[1] bit replaces the Sa4 bit. When the CRC Multi-frame is generated, they contain the value to replace the Sa4[1:4] bits.
E1 Sa5 Code-word (066H, 166H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
Sa51
Sa52
Sa53
Sa54
R/W
R/W
R/W
R/W
1
1
1
1
Sa5[1:4]:
These bits are valid when the Basic frame is generated and the Sa5EN bit (b3, E1-064H,...) is ‘1’. When only the Basic frame is generated, the
value in the Sa5[1] bit replaces the Sa5 bit. When the CRC Multi-frame is generated, they contain the value to replace the Sa5[1:4] bits.
E1 Sa6 Code-word (067H, 167H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
Sa61
Sa62
Sa63
Sa64
R/W
R/W
R/W
R/W
1
1
1
1
Sa6[1:4]:
These bits are valid when the Basic frame is generated and the Sa6EN bit (b2, E1-064H,...) is ‘1’. When only the Basic frame is generated, the
value in the Sa6[1] bit replaces the Sa6 bit. When the CRC Multi-frame is generated, they contain the value to replace the Sa6[1:4] bits.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Sa7 Code-word (068H, 168H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
Sa71
Sa72
Sa73
Sa74
R/W
R/W
R/W
R/W
1
1
1
1
Sa7[1:4]:
These bits are valid when the Basic frame is generated and the Sa7EN bit (b1, E1-064H,...) is ‘1’. When only the Basic frame is generated, the
value in the Sa7[1] bit replaces the Sa7 bit. When the CRC Multi-frame is generated, they contain the value to replace the Sa7[1:4] bits.
E1 Sa8 Code-word (069H, 169H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
Sa81
Sa82
Sa83
Sa84
R/W
R/W
R/W
R/W
1
1
1
1
Sa8[1:4]:
These bits are valid when the Basic frame is generated and the Sa8EN bit (b0, E1-064H,...) is ‘1’. When only the Basic frame is generated, the
value in the Sa8[1] bit replaces the Sa8 bit. When the CRC Multi-frame is generated, they contain the value to replace the Sa8[1:4] bits.
E1 FGEN Extra (06AH, 16AH)
Bit No.
7
6
5
4
3
Bit Name
Type
2
X0
Reserved
R/W
Default
1
Reserved
1
0
X1
X2
R/W
R/W
1
1
X[0:2]:
These bits are valid when the Signaling Multi-frame is generated and the XDIS bit (b6, E1-062H,...) is ‘0’. They contain the value to replace the
Extra bits (the Bit 5, 7 & 8 of TS16 of Frame 0 of the Signaling Multi-Frame).
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FGEN Maintenance 0 (06BH, 16BH)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
TS16LOS
TS16AIS
MFAIS
G706RAI
AUTOYELLOW
REMAIS
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
TS16LOS:
= 0: Normal operation.
= 1: The data stream to be transmitted on TS16 is overwritten with all zeros.
TS16AIS:
= 0: Normal operation.
= 1: The data stream to be transmitted on TS16 is overwritten with all ‘One’s.
MFAIS:
This bit is valid when the Signaling Multi-Frame is generated. The value in this bit will be continuously transmitted in the Y bit position (the Bit 6 of
TS16 of Frame 0 of the Signaling Multi-Frame).
G706RAI:
This bit is valid when the Basic frame is generated. It selects the criteria for automatic RAI transmission.
= 0: The RAI is transmitted automatically when: 1). out of Basic frame sync is declared in the receive path; 2). the receive path is operated in
CRC-4 to non-CRC-4 inter-working mode; 3). the offline searching in the receive path is out of Basic Frame sync; 4). the REMAIS bit (b0, E1-06BH,...)
is 1.
= 1: The RAI is transmitted automatically when: 1). out of Basic frame sync is declared in the receive path; 2). the REMAIS bit (b0, E1-06BH,...)
is 1.
AUTOYELLOW:
This bit is valid when the Basic frame is generated.
= 0: Disable the automatic RAI transmission.
= 1: The Remote Alarm Indication (RAI) is automatically transmitted as logic 1 in the A bit position when conditions meet the criteria selected by
the G706RAI bit (b2, E1-06BH,...).
REMAIS:
This bit is valid when the Basic frame is generated.
= 0: Disable the manual RAI transmission.
= 1: The Remote Alarm Indication (RAI) is manually transmitted as logic 1 in the A bit position.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FGEN Maintenance 1 (06CH, 16CH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
COFAEN
TXDIS
TAIS
R/W
R/W
R/W
0
0
0
COFAEN:
Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on this bit will lead to one bit deletion or one bit repetition in the data stream to be transmitted, that
is, to change the frame alignment position. The one bit deletion or repetition occurs randomly.
TXDIS:
= 0: Normal operation.
= 1: The data stream to be transmitted is overwritten with all ‘Zero’s.
TAIS:
= 0: Normal operation.
= 1: The data stream to be transmitted is overwritten with all ‘One’s.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FGEN Interrupt Control (06DH, 16DH)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
2
1
0
SMFE
FASE
SIGMFE
MFE
BFE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
SMFE:
= 0: Disable the interrupt on the INT pin when the SMFI bit (b4, E1-06EH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SMFI bit (b4, E1-06EH,...) is ‘1’.
FASE:
= 0: Disable the interrupt on the INT pin when the FASI bit (b3, E1-06EH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the FASI bit (b3, E1-06EH,...) is ‘1’.
SIGMFE:
= 0: Disable the interrupt on the INT pin when the SIGMFI bit (b2, E1-06EH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SIGMFI bit (b2, E1-06EH,...) is ‘1’.
MFE:
= 0: Disable the interrupt on the INT pin when the MFI bit (b1, E1-06EH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the MFI bit (b1, E1-06EH,...) is ‘1’.
BFE:
= 0: Disable the interrupt on the INT pin when the BFI bit (b0, E1-06EH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the BFI bit (b0, E1-06EH,...) is ‘1’.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 FGEN Interrupt Indication (06EH, 16EH)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
2
1
0
SMFI
FASI
SIGMFI
MFI
BFI
R
R
R
R
R
0
0
0
0
0
SMFI:
= 0: The bit input to the Frame Generator is not the first bit of each CRC Sub Multi-Frame.
= 1: The first bit of each CRC Sub Multi-Frame is input to the Frame Generator.
This bit will be cleared if a ’1’ is written to it.
FASI:
= 0: The bit input to the Frame Generator is not the first bit of each FAS.
= 1: The first bit of each FAS is input to the Frame Generator.
This bit will be cleared if a ’1’ is written to it.
SIGMFI:
= 0: The bit input to the Frame Generator is not the first bit of each Signaling Multi-Frame.
= 1: The first bit of each Signaling Multi-Frame is input to the Frame Generator.
This bit will be cleared if a ’1’ is written to it.
MFI:
= 0: The bit input to the Frame Generator is not the first bit of each CRC Multi-Frame.
= 1: The first bit of each CRC Multi-Frame is input to the Frame Generator.
This bit will be cleared if a ’1’ is written to it.
BFI:
= 0: The bit input to the Frame Generator is not the first bit of each Basic frame.
= 1: The first bit of each Basic frame is input to the Frame Generator.
This bit will be cleared if a ’1’ is written to it.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Error Insertion (06FH, 16FH)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
CRCINV
CRCPINV
CASPINV
NFASINV
FASALLINV
FAS1INV
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
CRCINV:
This bit is valid when the CRC Multi-frame or the Modified CRC Multi-frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert all 4 calculated CRC bits in one Sub-Multi-Frame.
This bit is cleared when the inversion is completed.
CRCPINV:
This bit is valid when the CRC Multi-frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one 6-bit CRC Multi-Frame alignment pattern (‘001011’).
This bit is cleared when the inversion is completed.
CASPINV:
This bit is valid when the CAS Multi-frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one 4-bit Signaling Multi-Frame alignment pattern (‘0000’).
This bit is cleared when the inversion is completed.
NFASINV:
This bit is valid when the Basic frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one NFAS bit (the Bit 2 of TS0 of each odd frame).
This bit is cleared when the inversion is completed.
FASALLINV:
This bit is valid when the Basic frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one 7-bit FAS pattern (the Bit 2 ~ Bit 8 of TS0 of each even frame).
This bit is cleared when the inversion is completed.
FAS1INV:
This bit is valid when the Basic frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one FAS bit (the Bit 2 ~ Bit 8 of TS0 of each even frame).
This bit is cleared when the inversion is completed.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Transmit Timing Option (070H, 170H)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
XTS
Type
Reserved
R/W
Default
0
XTS:
In Transmit Clock Master mode:
= 0: The source of the transmit clock is selected from the clock generated by the internal clock generator (2.048 MHz).
= 1: The source of the transmit clock is selected from the recovered clock from the line side.
In Transmit Clock Master mode, the Transmit Buffer is bypassed automatically.
In Transmit Clock Slave mode and in Transmit Multiplexed mode:
= 0: The source of the transmit clock is selected from the clock from the backplane. The Transmit Buffer is bypassed.
= 1: The source of the transmit clock is selected from the clock generated by the internal clock generator (2.048 MHz). The Transmit Buffer is not
bypassed.
E1 PRGD Control (071H, 171H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
RINV
TINV
PATS1
PATS0
R/W
R/W
R/W
R/W
0
0
0
0
RINV:
= 0: The data is not inverted before extracted to the pattern detector.
= 1: The data is inverted before extracted to the pattern detector.
TINV:
= 0: The generated pattern is not inverted.
= 1: The generated pattern is inverted.
PATS[1:0]:
These bits select the PRBS generated and detected pattern.
= 00: The 215-1 pattern per O.152 is selected.
= 01: The 220-1 pattern per O.150-4.5 is selected.
= 10: The 211-1 pattern per O.150 is selected.
= 11: Reserved.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 PRGD Status/Error Control (072H, 172H)
Bit No.
7
6
5
4
Bit Name
Type
3
2
1
0
BERE
INV
SYNCV
SYNCE
R/W
R/W
R
R/W
0
0
0
0
Reserved
Default
BERE:
= 0: Disable the interrupt on the INT pin when the BERI bit (b3, E1-073H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the BERI bit (b3, E1-073H,...) is ‘1’.
INV:
= 0: No bit error is inserted to the generated pattern.
= 1: A single bit error is inserted to the generated pattern.
This bit is cleared after the single bit error insertion is completed.
SYNCV:
= 0: The pattern is out of synchronization (the pattern detector has detected 10 or more bit errors in a fixed 48-bit window).
= 1: The pattern is in synchronization (the pattern detector has detected at least 48 consecutive error-free bit periods).
SYNCE:
= 0: Disable the interrupt on the INT pin when the SYNCI bit (b0, E1-073H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SYNCI bit (b0, E1-073H,...) is ‘1’.
E1 PRGD Interrupt Indication (073H, 173H)
Bit No.
7
6
5
4
3
Bit Name
Type
2
1
BERI
Reserved
R
Default
0
SYNCI
Reserved
0
R
0
BERI:
= 0: No bit is mismatched with the PRGD pattern when the extracted data is in synchronization state.
= 1: At least one bit is mismatched with the PRGD pattern when the extracted data is in synchronization state.
This bit will be cleared if a ’1’ is written to it.
SYNCI:
= 0: There is no status change on the SYNCV bit (b1, E1-072H,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the SYNCV bit (b1, E1-072H,...).
This bit will be cleared if a ’1’ is written to it.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 ELST Configuration (07CH, 17CH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
TRKEN
SLIPD
SLIPE
R/W
R
R/W
0
0
0
TRKEN:
In Receive Clock Slave mode and Receive Multiplexed mode, if it is out of synchronization, the trunk code programmed in the TRKCODE[7:0]
bits (b7~0, E1-07EH,...) can be set to replace the data or not.
= 0: Disable the replacement.
= 1: Enable the replacement.
SLIPD:
This bit makes sense only when the SLIPI bit (b0, E1-07DH,...) is ‘1’.
= 0: The latest slip is due to the Elastic Store Buffer being empty.
= 1: The latest slip is due to the Elastic Store Buffer being full.
SLIPE:
= 0: Disable the interrupt on the INT pin when the SLIPI bit (b0, E1-07DH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SLIPI bit (b0, E1-07DH,...) is ‘1’.
E1 ELST Interrupt Indication (07DH, 17DH)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
SLIPI
Type
Reserved
R
Default
0
SLIPI:
= 0: No slip occurs.
= 1: A slip occurs.
This bit will be cleared if a ’1’ is written to it.
E1 ELST Trunk Code (07EH, 17EH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
TRKCODE7
TRKCODE6
TRKCODE5
TRKCODE4
TRKCODE3
TRKCODE2
TRKCODE1
TRKCODE0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
1
1
1
1
1
1
1
TRKCODE[7:0]:
In Receive Clock Slave mode and Receive Multiplexed mode, if it is out of synchronization and the TRKEN bit (b2, E1-07CH,...) is ‘1’, these bits
are the trunk codes to replace the received data stream.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 THDLC Enable Control (084H, 184H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
TDLEN3
TDLEN2
TDLEN1
R/W
R/W
R/W
0
0
0
TDLEN3:
= 0: All the functions of the HDLC Transmitter #3 is disabled.
= 1: All the functions of the HDLC Transmitter #3 is enabled.
TDLEN2:
= 0: All the functions of the HDLC Transmitter #2 is disabled.
= 1: All the functions of the HDLC Transmitter #2 is enabled.
TDLEN1:
= 0: All the functions of the HDLC Transmitter #1 is disabled.
= 1: All the functions of the HDLC Transmitter #1 is enabled.
Programming Information
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E1 THDLC1 Assignment (085H, 185H)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
E1 THDLC2 Assignment (086H, 186H)
Bit No.
7
Bit Name
Type
Reserved
Default
E1 THDLC3 Assignment (087H, 187H)
Bit No.
7
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
EVEN:
= 0: The data is not inserted to the even frames.
= 1: The data is inserted to the even frames.
ODD:
= 0: The data is not inserted to the odd frames.
= 1: The data is inserted to the odd frames.
TS[4:0]:
These bits binary define one timeslot of even and/or odd frames to insert the data to. They are invalid when the EVEN bit and the ODD bit are
both ‘0’.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 THDLC1 Bit Select (088H, 188H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
E1 THDLC2 Bit Select (089H, 189H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
E1 THDLC3 Bit Select (08AH, 18AH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
BITENn:
= 0: The data is not inserted to the corresponding bit.
= 1: The data is inserted to the corresponding bit of the assigned timeslot.
These bits are invalid when the EVEN bit and the ODD bit are both logic 0.
The BITEN[7] bit corresponds to the first bit (MSB) of the selected timeslot.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RHDLC Enable Control (08BH, 18BH)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
RDLEN3
RDLEN2
RDLEN1
R/W
R/W
R/W
0
0
0
RDLEN3:
= 0: All the functions of the HDLC Receiver #3 is disabled.
= 1: All the functions of the HDLC Receiver #3 is enabled.
RDLEN2:
= 0: All the functions of the HDLC Receiver #2 is disabled.
= 1: All the functions of the HDLC Receiver #2 is enabled.
RDLEN1:
= 0: All the functions of the HDLC Receiver #1 is disabled.
= 1: All the functions of the HDLC Receiver #1 is enabled.
Programming Information
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E1 RHDLC1 Assignment (08CH, 18CH)
Bit No.
7
Bit Name
Type
Reserved
Default
6
5
4
3
2
1
0
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
EVEN
ODD
TS4
TS3
TS2
TS1
TS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
E1 RHDLC2 Assignment (08DH, 18DH)
Bit No.
7
Bit Name
Type
Reserved
Default
E1 RHDLC3 Assignment (08EH, 18EH)
Bit No.
7
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
EVEN:
= 0: The FIFO is not empty.
= 1: The data is extracted from the even frames.
The even frames are FAS frames.
ODD:
= 0: The data is not extracted from the odd frames.
= 1: The data is extracted from the odd frames.
The odd frames are NFAS frames.
TS[4:0]:
These bits binary define one timeslot of even and/or odd frames to extract the data from. They are invalid when the EVEN bit and the ODD bit are
both ‘0’.
Programming Information
311
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RHDLC1 Bit Select (08FH, 18FH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
E1 RHDLC2 Bit Select (090H, 190H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
E1 RHDLC3 Bit Select (091H, 191H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
BITEN7
BITEN6
BITEN5
BITEN4
BITEN3
BITEN2
BITEN1
BITEN0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
BITENn:
= 0: The data is not extracted from the corresponding bit.
= 1: The data is extracted from the corresponding bit of the assigned channel.
These bits are invalid when the EVEN bit and the ODD bit are both logic 0.
The BITEN[7] bit corresponds to the first bit (MSB) of the selected channel.
Programming Information
312
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RHDLC1 Control Register (092H, 192H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
ADRM1
ADRM0
RHDLCM
RRST
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
ADRM1
ADRM0
RHDLCM
RRST
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
ADRM1
ADRM0
RHDLCM
RRST
R/W
R/W
R/W
R/W
0
0
0
0
E1 RHDLC2 Control Register (093H, 193H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
E1 RHDLC3 Control Register (094H, 194H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
ADRM[1:0]:
These two bits select the address comparison mode in HDLC mode.
= 00: No address is compared.
= 01: High byte address is compared.
= 10: Low byte address is compared.
= 11: Both high byte address and low byte address are compared.
RHDLCM:
= 0: HDLC mode is selected.
= 1: Reserved.
RRST:
A transition from ‘0’ to ‘1’ on the this bit will reset the corresponding HDLC Receiver. The reset will clear the FIFO, the PACK bit (b0, E1-095H,...
/ 096H,... / 097H,...) and the EMP bit (b1, E1-095H,... / 096H,... / 097H,...).
E1 RHDLC1 RFIFO Access Status (095H, 195H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
Programming Information
313
2
1
0
EMP
PACK
R
R
1
0
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RHDLC2 RFIFO Access Status (096H, 196H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
EMP
PACK
R
R
1
0
1
0
EMP
PACK
R
R
1
0
E1 RHDLC3 RFIFO Access Status (097H, 197H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
EMP:
= 0: All valid HDLC blocks are pushed into the FIFO.
= 1: The FIFO is empty, i.e., all the blocks are read from the FIFO.
The corresponding HDLC Receiver reset will clear this bit.
PACK:
= 0: The byte read from the FIFO is not an overhead byte.
= 1: The byte read from the FIFO is an overhead byte.
The corresponding HDLC Receiver reset will clear this bit.
Programming Information
314
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RHDLC1 Data (098H, 198H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
E1 RHDLC2 Data (099H, 199H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
E1 RHDLC3 Data (09AH, 19AH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
DAT[7:0]:
These bits represent the bytes read from the FIFO. The DAT[0] bit corresponds to the first bit of the serial received data from the FIFO.
Programming Information
315
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RHDLC1 Interrupt Control (09BH, 19BH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
OVFLE
RMBEE
R/W
R/W
0
0
1
0
OVFLE
RMBEE
R/W
R/W
0
0
1
0
OVFLE
RMBEE
R/W
R/W
0
0
E1 RHDLC2 Interrupt Control (09CH, 19CH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
E1 RHDLC3 Interrupt Control (09DH, 19DH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
OVFLE:
= 0: Disable the interrupt on the INT pin when the OVFLI bit (b1, E1-09EH,... / 09FH,... / 0A0H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the OVFLI bit (b1, E1-09EH,... / 09FH,... / 0A0H,...) is ‘1’.
RMBEE:
= 0: Disable the interrupt on the INT pin when the RMBEI bit (b0, E1-09EH,... / 09FH,... / 0A0H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the RMBEI bit (b0, E1-09EH,... / 09FH,... / 0A0H,...) is ‘1’.
Programming Information
316
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RHDLC1 Interrupt Indication (09EH, 19EH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
OVFLI
RMBEI
R
R
0
0
1
0
OVFLI
RMBEI
R
R
0
0
1
0
OVFLI
RMBEI
R
R
0
0
E1 RHDLC2 Interrupt Indication (09FH, 19FH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
E1 RHDLC3 Interrupt Indication (0A0H, 1A0H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
OVFLI:
The overwritten condition will occur if data is still attempted to write into the FIFO when the FIFO has already been full (128 bytes).
= 0: No overwriting occurs.
= 1: The overwriting occurs.
This bit will be cleared if a ’1’ is written to it.
RMBEI:
= 0: No block is pushed into the FIFO.
= 1: A block of the HDLC packet is pushed into the FIFO.
This bit will be cleared if a ’1’ is written to it.
Programming Information
317
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RHDLC1 High Address (0A1H, 1A1H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
HA7
HA6
HA5
HA4
HA3
HA2
HA1
HA0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
E1 RHDLC2 High Address (0A2H, 1A2H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
HA7
HA6
HA5
HA4
HA3
HA2
HA1
HA0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
E1 RHDLC3 High Address (0A3H, 1A3H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
HA7
HA6
HA5
HA4
HA3
HA2
HA1
HA0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
HA[7:0]:
In HDLC mode, when high byte address comparison or both bytes address comparison is required, the high byte address position (the byte following the opening flag) is compared with the value in these bits, or with ‘0xFC’ or ‘0xFE’. The HA[1] bit (the ‘C/R’ bit position) is excluded to compare.
Programming Information
318
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RHDLC1 Low Address (0A4H, 1A4H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
LA7
LA6
LA5
LA4
LA3
LA2
LA1
LA0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
E1 RHDLC2 Low Address (0A5H, 1A5H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
LA7
LA6
LA5
LA4
LA3
LA2
LA1
LA0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
E1 RHDLC3 Low Address (0A6H, 1A6H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
LA7
LA6
LA5
LA4
LA3
LA2
LA1
LA0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
LA[7:0]:
In HDLC mode, when low byte address comparison is required, the high byte address position (the byte following the opening flag) is compared
with the value in these bits. When both bytes address comparison is required, the low byte address position (the byte following the high byte address
position) is compared with the value in these bits.
Programming Information
319
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 THDLC1 Control (0A7H, 1A7H)
Bit No.
7
6
5
Bit Name
4
3
EOM
Type
Reserved
R/W
Default
Reserved
0
2
1
0
ABORT
THDLCM
TRST
R/W
R/W
R/W
0
0
0
2
1
0
ABORT
THDLCM
TRST
R/W
R/W
R/W
0
0
0
2
1
0
ABORT
THDLCM
TRST
R/W
R/W
R/W
0
0
0
E1 THDLC2 Control (0A8H, 1A8H)
Bit No.
7
6
5
Bit Name
4
3
EOM
Type
Reserved
R/W
Default
Reserved
0
E1 THDLC3 Control (0A9H, 1A9H)
Bit No.
7
6
Bit Name
Type
Default
5
4
3
EOM
Reserved
R/W
Reserved
0
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
EOM:
A transition from ‘0’ to ‘1’ on this bit indicates an entire HDLC packet is stored in the FIFO and starts the packet transmission.
ABORT:
= 0: Disable the manual abort sequence insertion.
= 1: The abort sequence (‘01111111’) is manually inserted to the current HDLC packet.
This bit is self-cleared after the abortion.
THDLCM:
= 0: HDLC mode is selected.
= 1: Reserved.
TRST:
A transition from ‘0’ to ‘1’ on the this bit resets the corresponding HDLC Transmitter. The reset will clear the FIFO.
Programming Information
320
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 TFIFO1 Threshold (0AAH, 1AAH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
LL1
LL0
HL1
HL0
R/W
R/W
R/W
R/W
0
0
0
1
3
2
1
0
LL1
LL0
HL1
HL0
R/W
R/W
R/W
R/W
0
0
0
1
3
2
1
0
LL1
LL0
HL1
HL0
R/W
R/W
R/W
R/W
0
0
0
1
E1 TFIFO2 Threshold (0ABH, 1ABH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
E1 TFIFO3 Threshold (0ACH, 1ACH)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
LL[1:0]:
These 2 bits set the lower threshold of the FIFO. If the fill level is below the lower threshold, an interrupt may be generated.
= 00: 16 bytes
= 01: 32 bytes
= 10: 64 bytes
= 11: 96 bytes
HL[1:0]:
These 2 bits set the upper threshold of the FIFO. Once the fill level exceeds the upper threshold, the data stored in the FIFO will start to be transmitted.
= 00: 16 bytes
= 01: 32 bytes
= 10: 64 bytes
= 11: 128 bytes
Programming Information
321
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 THDLC1 Data (0ADH, 1ADH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
E1 THDLC2 Data (0AEH, 1AEH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
E1 THDLC3 Data (0AFH, 1AFH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
DAT[7:0]:
The bytes are to be stored in the FIFO. The DAT[0] bit corresponds to the first bit of the serial data in the FIFO to be transmitted.
Programming Information
322
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 TFIFO1 Status (0B0H, 1B0H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
FUL
EMP
RDY
R
R
R
0
1
1
2
1
0
FUL
EMP
RDY
R
R
R
0
1
1
2
1
0
FUL
EMP
RDY
R
R
R
0
1
1
E1 TFIFO2 Status (0B1H, 1B1H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
E1 TFIFO3 Status (0B2H, 1B2H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
FUL:
= 0: The FIFO is not full.
= 1: The FIFO is full of 128 bytes.
EMP:
= 0: The FIFO is not empty.
= 1: The FIFO is empty.
RDY:
= 0: The fill level of the FIFO is not below the lower threshold set by the LL[1:0] bits (b3~2, E1-0AAH,... / 0AB,... / 0ACH,...).
= 1: The fill level of the FIFO is below the lower threshold set by the LL[1:0] bits (b3~2, E1-0AAH,... / 0ABH,... / 0ACH,...).
Programming Information
323
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 THDLC1 Interrupt Control (0B3H, 1B3H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
UDRUNE
RDYE
R/W
R/W
0
0
1
0
UDRUNE
RDYE
R/W
R/W
0
0
1
0
UDRUNE
RDYE
R/W
R/W
0
0
E1 THDLC2 Interrupt Control (0B4H, 1B4H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
E1 THDLC3 Interrupt Control (0B5H, 1B5H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
UDRUNE:
= 0: Disable the interrupt on the INT pin when the UDRUNI bit (b1, E1-0B6H,... / 0B7H,... / 0B8H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the UDRUNI bit (b1, E1-0B6H,... / 0B7H,... / 0B8H,...) is ‘1’.
RDYE:
= 0: Disable the interrupt on the INT pin when the RDYI bit (b0, E1-0B6H,... / 0B7H,... / 0B8H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the RDYI bit (b0, E1-0B6H,... / 0B7H,... / 0B8H,...) is ‘1’.
Programming Information
324
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 THDLC1 Interrupt Indication (0B6H, 1B6H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
UDRUNI
RDYI
R
R
0
0
1
0
UDRUNI
RDYI
R
R
0
0
1
0
UDRUNI
RDYI
R
R
0
0
E1 THDLC2 Interrupt Indication (0B7H, 1B7H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
E1 THDLC3 Interrupt Indication (0B8H, 1B8H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
The function of the above three sets of registers are the same. However, they correspond to different THDLC.
UDRUNI:
When the FIFO is empty and the last transmitted byte is not the end of the current HDLC packet, the under-run occurs. This bit indicates whether
the under-run occurs.
= 0: No under-run occurs.
= 1: Under-run occurs.
This bit will be cleared if a ’1’ is written to it.
RDYI:
= 0: There is no status change on the RDY bit (b0, E1-0B0H,... / 0B1H,... / 0B2H,...).
= 1: There is a transition (from ‘0’ to ‘1’) on the RDY bit (b0, E1-0B0H,... / 0B1H,... / 0B2H,...).
This bit will be cleared if a ’1’ is written to it.
Programming Information
325
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Alarm Status (0B9H, 1B9H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
TS16LOSV
TS16AISV
RMAIV
AIS
RAIV
RED
R
R
R
R
R
R
0
0
0
0
0
0
TS16LOSV:
The LOS in TS16 is detected on the base of Basic frame synchronization.
= 0: The LOS in TS16 is cleared when 16 consecutive TS16 are not all received as ‘0’.
= 1: The LOS in TS16 is detected when 16 consecutive TS16 are all received as ‘0’.
TS16AISV:
The AIS in TS16 is detected on the base of Basic frame synchronization.
= 0: The AIS in TS16 is cleared when TS16 contains more than 3 zeros in a 16-consecutive-Basic-frame period.
= 1: The AIS in TS16 is detected when TS16 contains less than 4 zeros in each of two 16-consecutive-Basic-frame periods.
RMAIV:
The Remote Signaling Multi-Frame alarm is detected on the base of CAS Signaling Multi-Frame synchronization.
= 0: The Remote Signaling Multi-Frame alarm is cleared when a single Y bit is received as ‘0’.
= 1: The Remote Signaling Multi-Frame alarm is detected when 3 consecutive Y bits are received as ‘1’.
AIS:
= 0: The AIS alarm is cleared. That is, when the AISC bit (b1, E1-0BCH,...) is ‘0’, more than 2 zeros are detected in a 512-bit fixed window; when
the AISC bit (b1, E1-0BCH,...) is ‘1’, more than 2 zeros are detected in each of 2 consecutive 512-bit fixed window.
= 1: The AIS alarm is detected. That is, when the AISC bit (b1, E1-0BCH,...) is ‘0’, less than 3 zeros are detected in a 512-bit fixed window and it
is out of Basic frame synchronization; when the AISC bit (b1, E1-0BCH,...) is ‘1’, less than 3 zeros are detected in each of 2 consecutive 512-bit fixed
window.
RAIV:
The Remote alarm is detected on the base of Basic frame synchronization.
= 0: The Remote alarm is cleared. That is, when the RAIC bit (b0, E1-0BCH,...) is ‘0’, a single A bit is received as ‘0’; when the RAIC bit (b0, E10BCH,...) is ‘1’, a single A bit is received as ‘0’.
= 1: The Remote alarm is detected. That is, when the RAIC bit (b0, E1-0BCH,...) is ‘0’, 4 consecutive A bits are received as ‘1’; when the RAIC bit
(b0, E1-0BCH,...) is ‘1’, a single A bit is received as ‘1’.
RED:
= 0: The RED alarm is cleared when in Basic frame synchronization persists for 100ms.
= 1: The RED alarm is detected when out of Basic frame synchronization persists for 100ms.
Programming Information
326
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Alarm Control (0BAH, 1BAH)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
TS16LOSE
TS16AISE
RMAIE
AISE
RAIE
REDE
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
TS16LOSE:
= 0: Disable the interrupt on the INT pin when the TS16LOSI bit (b5, E1-0BBH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the TS16LOSI bit (b5, E1-0BBH,...) is ‘1’.
TS16AISE:
= 0: Disable the interrupt on the INT pin when the TS16AISI bit (b4, E1-0BBH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the TS16AISI bit (b4, E1-0BBH,...) is ‘1’.
RMAIE:
= 0: Disable the interrupt on the INT pin when the RMAII bit (b3, E1-0BBH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the RMAII bit (b3, E1-0BBH,...) is ‘1’.
AISE:
= 0: Disable the interrupt on the INT pin when the AISI bit (b2, E1-0BBH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the AISI bit (b2, E1-0BBH,...) is ‘1’.
RAIE:
= 0: Disable the interrupt on the INT pin when the RAII bit (b1, E1-0BBH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the RAII bit (b1, E1-0BBH,...) is ‘1’.
REDE:
= 0: Disable the interrupt on the INT pin when the REDI bit (b0, E1-0BBH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the REDI bit (b0, E1-0BBH,...) is ‘1’.
Programming Information
327
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Alarm Indication (0BBH, 1BBH)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
TS16LOSI
TS16AISI
RMAII
AISI
RAII
REDI
R
R
R
R
R
R
0
0
0
0
0
0
TS16LOSI:
= 0: There is no status change on the TS16LOSV bit (b5, E1-0B9H,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the TS16LOSV bit (b5, E1-0B9H,...).
This bit will be cleared if a ’1’ is written to it.
TS16AISI:
= 0: There is no status change on the TS16AISV bit (b4, E1-0B9H,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the TS16AISV bit (b4, E1-0B9H,...).
This bit will be cleared if a ’1’ is written to it.
RMAII:
= 0: There is no status change on the RMAIV bit (b3, E1-0B9H,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the RMAIV bit (b3, E1-0B9H,...).
This bit will be cleared if a ’1’ is written to it.
AISI:
= 0: There is no status change on the AIS bit (b2, E1-0B9H,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the AIS bit (b2, E1-0B9H,...).
This bit will be cleared if a ’1’ is written to it.
RAII:
= 0: There is no status change on the RAIV bit (b1, E1-0B9H,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the RAIV bit (b1, E1-0B9H,...).
This bit will be cleared if a ’1’ is written to it.
REDI:
= 0: There is no status change on the RED bit (b0, E1-0B9H,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the RED bit (b0, E1-0B9H,...).
This bit will be cleared if a ’1’ is written to it.
Programming Information
328
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Alarm Criteria Control (0BCH, 1BCH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
1
0
AISC
RAIC
R/W
R/W
0
0
AISC:
This bit selects the AIS alarm detection criteria.
= 0: The criterion meets I.431. The AIS alarm will be declared when less than 3 zeros are detected in a 512-bit fixed window and it is out of Basic
frame synchronization, and the AIS alarm will be cleared when more than 2 zeros are detected in a 512-bit fixed window.
= 1: The criterion meets G.775. The AIS alarm will be declared when less than 3 zeros are detected in each of 2 consecutive 512-bit fixed window, and the AIS alarm will be cleared when more than 2 zeros are detected in each of 2 consecutive 512-bit fixed window.
RAIC:
This bit selects the Remote alarm detection criterion.
= 0: The Remote alarm will be declared when 4 consecutive A bits are received as ‘1’, and the Remote alarm will be cleared when a single A bit
is received as ‘0’.
= 1: The Remote alarm will be declared when a single A bit is received as ‘1’, and the Remote alarm will be cleared when a single A bit is
received as ‘0’.
E1 PMON Control (0C2H, 1C2H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
UPDAT
AUTOUPD
R/W
R/W
0
0
UPDAT:
A transition from ‘0’ to ‘1’ on this bit updates all the PMON indirect registers.
AUTOUPD:
= 0: Disable the automatic update function of the PMON indirect registers.
= 1: All the PMON indirect registers are updated every one second automatically.
Programming Information
329
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 PMON Interrupt Control 0 (0C3H, 1C3H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
PRDGOVE
TFEBEOVE
FEBEOVE
TCRCOVE
COFAOVE
OOFOVE
FEROVE
CRCOVE
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
PRDGOVE:
= 0: Disable the interrupt on the INT pin when the PRDGOVI bit (b7, E1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the PRDGOVI bit (b7, E1-0C5H,...) is ‘1’.
TFEBEOVE:
= 0: Disable the interrupt on the INT pin when the TFEBEOVI bit (b6, E1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the TFEBEOVI bit (b6, E1-0C5H,...) is ‘1’.
FEBEOVE:
= 0: Disable the interrupt on the INT pin when the FEBEOVI bit (b5, E1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the FEBEOVI bit (b5, E1-0C5H,...) is ‘1’.
TCRCOVE:
= 0: Disable the interrupt on the INT pin when the TCRCOVI bit (b4, E1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the TCRCOVI bit (b4, E1-0C5H,...) is ‘1’.
COFAOVE:
= 0: Disable the interrupt on the INT pin when the COFAOVI bit (b3, E1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the COFAOVI bit (b3, E1-0C5H,...) is ‘1’.
OOFOVE:
= 0: Disable the interrupt on the INT pin when the OOFOVI bit (b2, E1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the OOFOVI bit (b2, E1-0C5H,...) is ‘1’.
FEROVE:
= 0: Disable the interrupt on the INT pin when the FEROVI bit (b1, E1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the FEROVI bit (b1, E1-0C5H,...) is ‘1’.
CRCOVE:
= 0: Disable the interrupt on the INT pin when the CRCOVI bit (b0, E1-0C5H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the CRCOVI bit (b0, E1-0C5H,...) is ‘1’.
Programming Information
330
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 PMON Interrupt Control 1 (0C4H, 1C4H)
Bit No.
7
6
5
4
3
Bit Name
Type
2
1
0
LCVOVE
Reserved
Default
R/W
0
LCVOVE:
= 0: Disable the interrupt on the INT pin when the LCVOVI bit (b0, E1-0C6H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the LCVOVI bit (b0, E1-0C6H,...) is ‘1’.
Programming Information
331
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 PMON Interrupt Indication 0 (0C5H, 1C5H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
PRDGOVI
TFEBEOVI
FEBEOVI
TCRCOVI
COFAOVI
OOFOVI
FEROVI
CRCOVI
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
PRDGOVI:
= 0: The PMON indirect PRGD Counter Mapping registers have not overflowed.
= 1: The PMON indirect PRGD Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
TFEBEOVI:
= 0: The PMON indirect TFEBE Counter Mapping registers have not overflowed.
= 1: The PMON indirect TFEBE Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
FEBEOVI:
= 0: The PMON indirect FEBE Counter Mapping registers have not overflowed.
= 1: The PMON indirect FEBE Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
TCRCOVI:
= 0: The PMON indirect DDSE Counter Mapping registers have not overflowed.
= 1: The PMON indirect DDSE Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
COFAOVI:
= 0: The PMON indirect COFA Counter Mapping register has not overflowed.
= 1: The PMON indirect COFA Counter Mapping register has overflowed.
This bit will be cleared if a ’1’ is written to it.
OOFOVI:
= 0: The PMON indirect OOF Counter Mapping register has not overflowed.
= 1: The PMON indirect OOF Counter Mapping register has overflowed.
This bit will be cleared if a ’1’ is written to it.
FEROVI:
= 0: The PMON indirect FER Counter Mapping registers have not overflowed.
= 1: The PMON indirect FER Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
CRCOVI:
= 0: The PMON indirect CRCE Counter Mapping registers have not overflowed.
= 1: The PMON indirect CRCE Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
Programming Information
332
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 PMON Interrupt Indication 1 (0C6H, 1C6H)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
LCVOVI
Type
Reserved
R
Default
0
LCVOVI:
= 0: The PMON indirect LCV Counter Mapping registers have not overflowed.
= 1: The PMON indirect LCV Counter Mapping registers have overflowed.
This bit will be cleared if a ’1’ is written to it.
E1 TPLC / RPLC / PRGD Test Configuration (0C7H, 1C7H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
PRBSMODE1
PRBSMODE0
PRBSDIR
TESTEN
R/W
R/W
R/W
R/W
0
0
0
0
PRBSMODE[1:0]:
These two bits select one mode to extract/replace the data for the PRBS Generator/Detector.
= 00: The unframed mode is selected. All 32 timeslots are extracted/replaced and the per-timeslot configuration in the TEST bit (b6, E1-ID41~4FH & 51~5FH) is ignored.
= 01: The 8-bit-based mode is selected. The received data will only be extracted/replaced on the timeslot configured by the TEST bit (b6, E1-ID41~4FH & 51~5FH).
= 10: The 7-bit-based mode is selected. The received data will only be extracted/replaced on the 7 MSB of the timeslot configured by the TEST
bit (b6, E1-ID-41~4FH & 51~5FH).
= 11: Reserved.
PRBSDIR:
= 0: The pattern in the PRBS Generator/Detector is generated in the transmit path and is detected in the receive path.
= 1: The pattern in the PRBS Generator/Detector is generated in the receive path and is detected in the transmit path.
TESTEN:
A transition from ‘0’ to ‘1’ on this bit initiates the PRBS Generator/Detector.
Programming Information
333
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 TPLC Access Status (0C8H, 1C8H)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
BUSY
Type
Reserved
R
Default
0
BUSY:
= 0: No reading or writing operation on the indirect registers.
= 1: An internal indirect register is being accessed. Any new operation on the internal indirect register is not allowed.
E1 TPLC Access Control (0C9H, 1C9H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
RWN
ADDRESS6
ADDRESS5
ADDRESS4
ADDRESS3
ADDRESS2
ADDRESS1
ADDRESS0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
RWN:
= 0: Write the data to the specified indirect register.
= 1: Read the data to the specified indirect register.
ADDRESS[6:0]:
These bits specify the address of the indirect register (from 00H to 3FH & from 41H to 4FH & from 51H to 5FH) for the microprocessor access.
E1 TPLC Access Data (0CAH, 1CAH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
D7
D6
D5
D4
D3
D2
D1
D0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
D[7:0]:
This register holds the value which will be read from or written into the indirect registers (from 00H to 3FH & from 41H to 4FH & from 51H to 5FH).
If data is to be written into the indirect register, this register must be written before the target indirect register’s address and RWN=0 is written into the
TPLC Access Control register. If data is to be read from the indirect register, the target indirect register’s address and RWN=1 must be written into the
TPLC Access Control register first, then this register will contain the requested data byte.
Programming Information
334
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 TPLC Configuration (0CBH, 1CBH)
Bit No.
7
6
Bit Name
SIGSNAP
GSTRKEN
Type
R/W
R/W
Default
1
0
5
4
3
Reserved
2
1
0
GSUBST2
GSUBST1
GSUBST0
R/W
R/W
R/W
0
0
0
SIGSNAP:
This bit is valid when the Signaling Multi-frame is generated.
= 0: Disable the signaling snapshot.
= 1: Enable the signaling snapshot. That is, the signaling bits of the first Basic frame are locked and input on the TSIGn/MTSIG pin as the signaling bits of the current whole Signaling Multi-frame.
GSTRKEN:
= 0: The replacement is performed on a per-timeslot basis by setting the STRKEN bit (b4, E1-ID-41~4FH & 51~5FH) in the corresponding
timeslot.
= 1: The signaling bits (ABCD) of all timeslots are replaced by the signaling trunk conditioning code in the A,B,C,D bits (b3~0, E1-ID-41~4FH &
51~5FH).
GSUBST[2:0]:
These bits select the replacement of all the channels.
GSUBST[2:0]
000
001
010
011
100
others
Replacement Selection
The replacement is performed on a per-timeslot basis by setting the SUBST[2:0] bits (b7~5, E1-ID-00~1FH) in the corresponding timeslot.
The data of all timeslots is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, E1-ID-20~3FH).
The data of all timeslots is replaced by the A-Law digital milliwatt pattern.
The data of all timeslots is replaced by the µ-Law digital milliwatt pattern.
The data of all timeslots is replaced by the payload loopback code extracted from the Elastic Store Buffer in the receive path.
Reserved.
E1 TPLC Control Enable (0CCH, 1CCH)
Bit No.
7
6
5
4
3
Bit Name
Type
2
1
0
PCCE
Reserved
Default
R/W
0
PCCE:
= 0: Disable all the functions in the Transmit Payload Control.
= 1: Enable all the functions in the Transmit Payload Control.
Programming Information
335
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RPLC Access Status (0CDH, 1CDH)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
BUSY
Type
Reserved
R
Default
0
BUSY:
= 0: No reading or writing operation on the indirect registers.
= 1: An internal indirect register is being accessed. Any new operation on the internal indirect register is not allowed.
E1 RPLC Access Control (0CEH, 1CEH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
RWN
ADDRESS6
ADDRESS5
ADDRESS4
ADDRESS3
ADDRESS2
ADDRESS1
ADDRESS0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
RWN:
= 0: Write the data to the specified indirect register.
= 1: Read the data to the specified indirect register.
ADDRESS[6:0]:
These bits specify the address of the indirect register (from 00H to 3FH & from 41H to 4FH & from 51H to 5FH) for the microprocessor access.
E1 RPLC Access Data (0CFH, 1CFH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
D7
D6
D5
D4
D3
D2
D1
D0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
D[7:0]:
This register holds the value which will be read from or written into the indirect registers (from 00H to 3FH & from 41H to 4FH & from 51H to 5FH).
If data is to be written into the indirect register, this register must be written before the target indirect register’s address and RWN=0 is written into the
RPLC Access Control register. If data is to be read from the indirect register, the target indirect register’s address and RWN=1 must be written into the
RPLC Access Control register first, then this register will contain the requested data byte.
Programming Information
336
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RPLC Configuration (0D0H, 1D0H)
Bit No.
7
6
Bit Name
SIGSNAP
GSTRKEN
Type
R/W
R/W
Default
0
0
5
4
3
Reserved
2
1
0
GSUBST2
GSUBST1
GSUBST0
R/W
R/W
R/W
0
0
0
SIGSNAP:
This bit is valid when Signaling Multi-frame is in synchronization.
= 0: Disable the signaling snapshot.
= 1: Enable the signaling snapshot. That is, the signaling bits of the first Basic frame are locked and output on the RSIGn/MRSIG pin as the signaling bits of the current whole Signaling Multi-frame.
GSTRKEN:
= 0: The replacement is performed on a per-timeslot basis by setting the STRKEN bit (b4, E1-ID-41~4FH & 51~5FH) in the corresponding
timeslot.
= 1: The signaling bits (ABCD) of all timeslots are replaced by the signaling trunk conditioning code in the A,B,C,D bits (b3~0, E1-ID-41~4FH &
51~5FH).
GSUBST[2:0]:
These bits select the replacement of all the timeslots.
GSUBST[2:0]
000
001
010
011
the others
Replacement Selection
The replacement is performed on a per-timeslot basis by setting the SUBST[2:0] bits (b7~5, E1-ID-00~1FH) in the corresponding timeslot.
The data of all timeslots is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, E1-ID-20~3FH).
The data of all timeslots is replaced by the A-Law digital milliwatt pattern.
The data of all timeslots is replaced by the µ-Law digital milliwatt pattern.
Reserved.
Programming Information
337
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RPLC Control Enable (0D1H, 1D1H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
PCCE
Type
Reserved
R/W
Default
0
PCCE:
= 0: Disable all the functions in the Receive Payload Control.
= 1: Enable all the functions in the Receive Payload Control.
E1 RCRB Configuration (0D2H, 1D2H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
FREEZE
DEB
SIGE
R/W
R/W
R/W
0
0
0
0
Reserved
FREEZE:
= 0: Disable the manual signaling freezing.
= 1: Manually freeze the signaling data in the A,B,C,D bits (b3~0, E1-ID-01~0FH & 11~1FH) as the previous valid value.
DEB:
= 0: Disable the signaling de-bounce.
= 1: Enable the signaling de-bounce. That is, the A,B,C,D bits (b3~0, E1-ID-01~0FH & 11~1FH) are updated only if 2 consecutive received ABCD
codeword of the same timeslot are identical.
SIGE:
= 0: Disable the interrupt on the INT pin when any of the COSI bits (E1-0D9H,... & E1-0D8H,... & E1-0D7H,... & E1-0D6H,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when any of the COSI bits (E1-0D9H,... & E1-0D8H,... & E1-0D7H,... & E1-0D6H,...) is ‘1’.
Programming Information
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E1 RCRB Access Status (0D3H, 1D3H)
Bit No.
7
6
5
4
3
2
1
Bit Name
0
BUSY
Type
Reserved
R
Default
0
BUSY:
= 0: No reading or writing operation on the indirect registers.
= 1: An internal indirect register is being accessed. Any new operation on the internal indirect register is not allowed.
E1 RCRB Access Control (0D4H, 1D4H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
RWN
ADDRESS6
ADDRESS5
ADDRESS4
ADDRESS3
ADDRESS2
ADDRESS1
ADDRESS0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
RWN:
= 0: Write the data to the specified indirect register.
= 1: Read the data to the specified indirect register.
ADDRESS[6:0]:
These bits specify the address of the indirect register (from 01H to 0FH & from 11H to 1FH) for the microprocessor access.
E1 RCRB Access Data (0D5H, 1D5H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DAT7
DAT6
DAT5
DAT4
DAT3
DAT2
DAT1
DAT0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
DAT[7:0]:
This register holds the value which will be read from or written into the indirect registers (from 01H to 0FH & from 11H to 1FH). If data is to be written into the indirect register, this register must be written before the target indirect register’s address and RWN=0 is written into the RCRB Access
Control register. If data is to be read from the indirect register, the target indirect register’s address and RWN=1 must be written into the RCRB Access
Control register first, then this register will contain the requested data byte.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RCRB State Change Indication 0 (0D6H, 1D6H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
COSI8
COSI7
COSI6
COSI5
COSI4
COSI3
COSI2
COSI1
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
COSI[X]:
= 0: The signaling bits in its corresponding timeslot is not changed.
= 1: The signaling bits in its corresponding timeslot is changed.
The corresponding bit will be cleared if a ‘1’ is written to it. The COSI[8:1] bits correspond to timeslot 8 ~ 1 respectively.
E1 RCRB State Change Indication 1 (0D7H, 1D7H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
COSI16
COSI15
COSI14
COSI13
COSI12
COSI11
COSI10
COSI9
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
COSI[X]:
= 0: The signaling bits in its corresponding timeslot is not changed.
= 1: The signaling bits in its corresponding timeslot is changed.
The corresponding bit will be cleared if a ‘1’ is written to it. The COSI[16] bit corresponds to timeslot 17. The COSI[15:9] bits correspond to
timeslot 15 ~ 9 respectively.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RCRB State Change Indication 2 (0D8H, 1D8H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
COSI24
COSI23
COSI22
COSI21
COSI20
COSI19
COSI18
COSI17
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
COSI[X]:
= 0: The signaling bits in its corresponding timeslot is not changed.
= 1: The signaling bits in its corresponding timeslot is changed.
The corresponding bit will be cleared if a ‘1’ is written to it. The COSI[24:17] bits correspond to timeslot 25 ~ 18 respectively.
E1 RCRB State Change Indication 3 (0D9H, 1D9H)
Bit No.
7
6
Bit Name
Type
Reserved
Default
5
4
3
2
1
0
COSI30
COSI29
COSI28
COSI27
COSI26
COSI25
R
R
R
R
R
R
0
0
0
0
0
0
COSI[X]:
= 0: The signaling bits in its corresponding timeslot is not changed.
= 1: The signaling bits in its corresponding timeslot is changed.
The corresponding bit will be cleared if a ‘1’ is written to it. The COSI[30:25] bits correspond to timeslot 31 ~ 26 respectively.
Programming Information
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5.2.2.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Indirect Register
PMON:
The PMON Counter Mapping Registers (00H ~ 0FH) of a link are updated as a group in the following three ways:
1. A transition from ‘0’ to ‘1’ on the UPDAT bit (b1, E1-0C2H,...) updates all the registers;
2. If the AUTOUPD bit (b0, E1-0C2H,...) is set to ‘1’, the registers will be updated every one second;
E1 CRCE Counter Mapping 0 (00H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
CRCE7
CRCE6
CRCE5
CRCE4
CRCE3
CRCE2
CRCE1
CRCE0
Type
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
1
0
CRCE9
CRCE8
R
R
0
0
CRCE[7:0]:
These bits together with the CRCE[9:8] bits count the CRC-4 Error numbers. The CRCE[0] bit is the LSB.
E1 CRCE Counter Mapping 1 (01H)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
CRCE[9:8]:
These bits together with the CRCE[7:0] bits count the CRC-4 Error numbers. The CRCE[9] bit is the MSB.
Programming Information
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E1 FER Counter Mapping 0 (02H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
FER7
FER6
FER5
FER4
FER3
FER2
FER1
FER0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
FER[7:0]:
These bits together with the FER[11:8] bits count the FAS/NFAS Bit/Pattern Error numbers. The FER[0] bit is the LSB.
E1 FER Counter Mapping 1 (03H)
Bit No.
7
6
5
4
Bit Name
Type
Reserved
Default
3
2
1
0
FER11
FER10
FER9
FER8
R
R
R
R
0
0
0
0
FER[11:8]:
These bits together with the FER[7:0] bits count the FAS/NFAS Bit/Pattern Error numbers. The FER[11] bit is the MSB.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 COFA Counter Mapping (04H)
Bit No.
7
6
5
4
3
Bit Name
Type
Reserved
Default
2
1
0
COFA2
COFA1
COFA0
R
R
R
0
0
0
COFA[2:0]:
These bits count the times of the new-found Basic frame alignment pattern position being different from the previous one events.
E1 OOF Counter Mapping (05H)
Bit No.
7
6
Bit Name
Type
Default
Reserved
5
4
3
2
1
0
OOF4
OOF3
OOF2
OOF1
OOF0
R
R
R
R
R
0
0
0
0
0
OOF[4:0]:
These bits count the times of out of Basic frame synchronization events.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 PRGD Counter Mapping 0 (06H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
PRGD7
PRGD6
PRGD5
PRGD4
PRGD3
PRGD2
PRGD1
PRGD0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
PRGD[7:0]:
These bits together with the PRGD[15:8] bits count the PRGD Bit Error numbers. The PRGD[0] bit is the LSB.
E1 PRGD Counter Mapping 1 (07H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
PRGD15
PRGD14
PRGD13
PRGD12
PRGD11
PRGD10
PRGD9
PRGD8
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
PRGD[15:8]:
These bits together with the PRGD[7:0] bits count the PRGD Bit Error numbers. The PRGD[15] bit is the MSB.
Programming Information
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E1 LCV Counter Mapping 0 (08H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
LCV7
LCV6
LCV5
LCV4
LCV3
LCV2
LCV1
LCV0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
LCV[7:0]:
These bits together with the LCV[15:8] bits count the Bipolar Violation (BPV) Error (in AMI decoding) or HDB3 Code Violation (CV) Error (in HDB3
decoding) numbers. The LCV[0] bit is the LSB.
E1 LCV Counter Mapping 1 (09H)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
LCV15
LCV14
LCV13
LCV12
LCV11
LCV10
LCV9
LCV8
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
LCV[15:8]:
These bits together with the LCV[7:0] bits count the Bipolar Violation (BPV) Error (in AMI decoding) or HDB3 Code Violation (CV) Error (in HDB3
decoding) numbers. The LCV[15] bit is the MSB.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 TCRCE Counter Mapping 0 (0AH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
TCRCE7
TCRCE6
TCRCE5
TCRCE4
TCRCE3
TCRCE2
TCRCE1
TCRCE0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
1
0
TCRCE9
TCRCE8
R
R
0
0
TCRCE[7:0]:
These bits together with the TCRCE[9:8] bits count the NT CRC Error numbers. The TCRCE[0] bit is the LSB.
E1 TCRCE Counter Mapping 1 (0BH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
TCRCE[9:8]:
These bits together with the TCRCE[7:0] bits count the NT CRC Error numbers. The TCRCE[9] bit is the MSB
Programming Information
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E1 FEBE Counter Mapping 0 (0CH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
FEBE7
FEBE6
FEBE5
FEBE4
FEBE3
FEBE2
FEBE1
FEBE0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
1
0
FEBE9
FEBE8
R
R
0
0
FEBE[7:0]:
These bits together with the FEBE[9:8] bits count the Far End Block Error numbers. The FEBE[0] bit is the LSB.
E1 FEBE Counter Mapping 1 (0DH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
FEBE[9:8]:
These bits together with the FEBE[7:0] bits count the Far End Block Error numbers. The FEBE[9] bit is the MSB
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 TFEBE Counter Mapping 0 (0EH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
TFEBE7
TFEBE6
TFEBE5
TFEBE4
TFEBE3
TFEBE2
TFEBE1
TFEBE0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
1
0
TFEBE9
TFEBE8
R
R
0
0
TFEBE[7:0]:
These bits together with the TFEBE[9:8] bits count the NT FEBE Error numbers. The TFEBE[0] bit is the LSB.
E1 TFEBE Counter Mapping 1 (0FH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
TFEBE[9:8]:
These bits together with the TFEBE[7:0] bits count the NT FEBE Error numbers. The TFEBE[9] bit is the MSB
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RCRB:
The indirect registers of RCRB addressed from 01H to 0FH & from 11H to 1FH are the Extracted Signaling Data / Extract Enable Registers for
TS1 to TS15 & TS17 to TS31. Each address corresponds to one timeslot.
E1 Extracted Signaling Data/Extract Enable Register (01H ~ 0FH & 11H ~ 1FH)
Bit No.
7
6
5
Bit Name
Type
Reserved
Default
4
3
2
1
0
EXTRACT
A
B
C
D
R/W
R
R
R
R
1
0
0
0
0
EXTRACT:
This bit is valid when the Signaling Multi-Frame is synchronized.
= 0: Disable the signaling bits extraction.
= 1: The signaling bits are extracted to the A,B,C,D bits (b3~0, E1-ID-01~0FH & 11~1FH).
A, B, C, D:
These bits are valid when the EXTRACT bit is enabled.
These bits are the extracted signaling bits.
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RPLC:
The indirect registers of RPLC addressed from 00H to 1FH are the Timeslot Control Registers for TS0 to TS31. Each address corresponds to one
timeslot.
The indirect registers of RPLC addressed from 20H to 3FH are the Data Trunk Conditioning Code Registers for TS0 to TS31. Each address corresponds to one timeslot.
The indirect registers of RPLC addressed from 41H to 4FH and from 51H to 5FH are the Signaling Trunk Conditioning Code Registers for TS1 to
TS15 and TS17 to TS31 respectively. Each address corresponds to one timeslot.
E1 Timeslot Control Register (00H ~ 1FH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
SUBST2
SUBST1
SUBST0
SINV
OINV
EINV
G56K
GAP
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
SUBST[2:0]:
When the GSUBST[2:0] bits (b2~0, E1-0D0H,...) are ‘000’, these bits select the replacement on a per-timeslot basis.
SUBST[2:0]
000
001
010
011
the others
Replacement Selection
No operation.
The data of the corresponding timeslot is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, E1-ID-20~3FH).
The data of the corresponding timeslot is replaced by the A-Law digital milliwatt pattern.
The data of the corresponding timeslot is replaced by the µ-Law digital milliwatt pattern.
Reserved.
SINV, OINV, EINV:
These three bits select how to invert the bits in the corresponding timeslot.
SINV
OINV
EINV
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Programming Information
Bit Inversion
No inversion.
Invert the even bits (bit 2, 4, 6, 8) of the corresponding timeslot (bit 1 is the MSB).
Invert the odd bits (bit 3, 5, 7) except the MSB of the corresponding timeslot (bit 1 is the MSB).
Invert the bits from bit 2 to bit 8 of the corresponding timeslot (bit 1 is the MSB).
Invert the MSB (bit 1) of the corresponding timeslot.
Invert the MSB (bit 1) and the even bits (bit 2, 4, 6, 8) of the corresponding timeslot.
Invert all the odd bits (bit 1, 3, 5, 7) of the corresponding timeslot (bit 1 is the MSB).
Invert all the bits (bit 1 ~ bit 8) of the corresponding timeslot (bit 1 is the MSB).
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G56K, GAP:
These bits are valid in Receive Clock Master mode when the PCCE bit (b0, E1-0D1H,...) is ‘1’.
G56K
GAP
0
1
X
0
0
1
Gap Mode
The corresponding timeslot is not gapped.
Bit 8 (LSB) of the corresponding timeslot is gapped (no clock signal during the Bit 8).
The corresponding timeslot is gapped (no clock signal during the timeslot).
E1 Data Trunk Conditioning Code Register (20H ~ 3FH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DTRK7
DTRK6
DTRK5
DTRK4
DTRK3
DTRK2
DTRK1
DTRK0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
DTRK[7:0]:
These bits are the data trunk codes that can replace the data of the timeslot selected by the GSUBST[2:0] bits (b2~0, E1-0D0H,...) or the
SUBST[2:0] bits (b7~5, E1-ID-00~1FH).
Programming Information
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 Signaling Trunk Conditioning Code Register (41H ~ 4FH & 51H ~ 5FH)
Bit No.
7
Bit Name
Type
6
5
TEST
Reserved
Default
R/W
0
Reserved
4
3
2
1
0
STRKEN
A
B
C
D
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
TEST:
This bit is valid in 8-bit-based mode or in 7-bit-based mode selected by the PRBSMODE[1:0] bits (b3~2, E1-0C7H,...).
= 0: Disable the data in the corresponding timeslot to be tested by the PRBS Generator/Detector.
= 1: Enable the data in the corresponding timeslot to be extracted to the PRBS Generator/Detector for test (when the PRBSDIR bit (b1, E10C7H,...) is ‘0’); or enable the test pattern from the PRBS Generator/Detector to replace the data in the corresponding timeslot for test (when the PRBSDIR bit (b1, E1-0C7H,...) is ‘1’). In 8-bit-based mode, the data refers to all 8 bits. In 7-bit-based mode, the data refers to the 7 MSB.
All the timeslots that are extracted to the PRBS Generator/Detector are concatenated and treated as a continuous stream in which pseudo random are searched for. Similarly, all the timeslots set to be replaced with the PRBS Generator/Detector test pattern data are concatenated replaced by
the PRBS.
STRKEN:
= 0: No operation.
= 1: The data of the corresponding timeslot is replaced by the signaling trunk code set in the A, B, C, D bits (b3~0, E1-ID-41~4FH & 51~5FH).
A, B, C, D:
These bits are the signaling trunk codes that can replace the signaling bits of the timeslot selected by the GSTRKEN bit (b6, E1-0D0H,...) or the
STRKEN bit (b4, E1-ID-41~4FH & 51~5FH).
Programming Information
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TPLC:
The indirect registers of TPLC addressed from 00H to 1FH are the Timeslot Control Registers for TS0 to TS31. Each address corresponds to one
timeslot.
The indirect registers of TPLC addressed from 20H to 3FH are the Data Trunk Conditioning Code Registers for TS0 to TS31. Each address corresponds to one timeslot.
The indirect registers of TPLC addressed from 41H to 4FH and from 51H to 5FH are the Signaling Trunk Conditioning Code Registers for TS1 to
TS15 and TS17 to TS31 respectively. Each address corresponds to one timeslot.
E1 Timeslot Control Register (00H ~ 1FH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
SUBST2
SUBST1
SUBST0
SINV
OINV
EINV
G56K
GAP
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
SUBST[2:0]:
When the GSUBST[2:0] bits(b2~0, E1-0CBH,...) are ‘000’, these bits select the replacement on a per-channel basis.
SUBST[2:0]
000
001
010
011
100
others
Replacement Selection
No operation.
The data of the corresponding timeslot is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, T1/J1-ID-21~38H).
The data of the corresponding timeslot is replaced by the A-Law digital milliwatt pattern.
The data of the corresponding timeslot is replaced by the µ-Law digital milliwatt pattern.
The data of the corresponding timeslot is replaced by the payload loopback code extracted from the Elastic Store Buffer in the receive path.
Reserved.
SINV, OINV, EINV:
These three bits select how to invert the bits in the corresponding channel.
SINV
OINV
EINV
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Programming Information
Bit Inversion
No inversion.
Invert the even bits (bit 2, 4, 6, 8) of the corresponding channel (bit 1 is the MSB).
Invert the odd bits (bit 3, 5, 7) except the MSB of the corresponding channel (bit 1 is the MSB).
Invert the bits from bit 2 to bit 8 of the corresponding channel (bit 1 is the MSB).
Invert the MSB (bit 1) of the corresponding channel.
Invert the MSB (bit 1) and the even bits (bit 2, 4, 6, 8) of the corresponding channel.
Invert all the odd bits (bit 1, 3, 5, 7) of the corresponding channel (bit 1 is the MSB).
Invert all the bits (bit 1 ~ bit 8) of the corresponding channel (bit 1 is the MSB).
354
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
G56K, GAP:
These bits are valid in Transmit Clock Master mode when the PCCE bit (b0, E1-0CCH,...) is ‘1’.
G56K
GAP
0
1
X
0
0
1
Gap Mode
The corresponding timeslot is not gapped.
Bit 8 (LSB) of the corresponding timeslot is gapped (no clock signal during the Bit 8).
The corresponding timeslot is gapped (no clock signal during the timeslot).
E1 Data Trunk Conditioning Code Register (20H ~ 3FH)
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DTRK7
DTRK6
DTRK5
DTRK4
DTRK3
DTRK2
DTRK1
DTRK0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
DTRK[7:0]:
These bits are the data trunk codes that can replace the data of the channel selected by the GSUBST[2:0] bits (b2~0, T1/J1-0CBH,...) or the
SUBST[2:0] bits (b7~5, T1/J1-ID-01~18H).
Programming Information
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E1 Signaling Trunk Conditioning Code Register (41H ~ 4FH & 51H ~ 5FH)
Bit No.
7
Bit Name
Type
6
5
TEST
Reserved
Default
R/W
0
Reserved
4
3
2
1
0
STRKEN
A
B
C
D
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
TEST:
This bit is valid in 8-bit-based mode or in 7-bit-based mode selected by the PRBSMODE[1:0] bits (b3~2, T1/J1-0C7H,...).
= 0: Disable the data in the corresponding channel to be tested by the PRBS Generator/Detector.
= 1: Enable the data in the corresponding channel to be extracted to the PRBS Generator/Detector for test (when the PRBSDIR bit (b1, E10C7H,...) is ‘0’); or enable the test pattern from the PRBS Generator/Detector to replace the data in the corresponding channel for test (when the PRBSDIR bit (b1, E1-0C7H,...) is ‘1’). In 8-bit-based mode, the data refers to all 8 bits. In 7-bit-based mode, the data refers to the 7 MSB.
All the channels that are extracted to the PRBS Generator/Detector are concatenated and treated as a continuous stream in which pseudo random are searched for. Similarly, all the channels set to be replaced with the PRBS Generator/Detector test pattern data are concatenated replaced by
the PRBS.
STRKEN:
= 0: No operation.
= 1: The data of the corresponding channel is replaced by the signaling trunk code set in the A, B, C, D bits (b3~0, T1/J1-ID-41~58H).
A, B, C, D:
These bits are the signaling trunk codes that can replace the signaling bits of the channel selected by the GSTRKEN bit (b6, T1/J1-0CBH,...) or
the STRKEN bit (b4, T1/J1-ID-41~58H).
Programming Information
356
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
6
IEEE STD 1149.1 JTAG TEST
ACCESS PORT
Data Input (TDI) pin, and shifted out of the registers via the Test Data
Output (TDO) pin. Both TDI and TDO are clocked at a rate determined
by TCK.
The JTAG boundary scan registers include BSR (Boundary Scan
Register), DIR (Device Identification Register), BR (Bypass Register)
and IR (Instruction Register). These will be described in the following
pages. Refer to Figure - 41 for architecture.
The IDT82P2282 supports the digital Boundary Scan Specification
as described in the IEEE 1149.1 standards.
The boundary scan architecture consists of data and instruction
registers plus a Test Access Port (TAP) controller. Control of the TAP is
achieved through signals applied to the Test Mode Select (TMS) and
Test Clock (TCK) input pins. Data is shifted into the registers via the Test
BSR (Boundary Scan Register)
DIR (Device Identification Register)
MUX
TDI
MUX
BR (Bypass Register)
IR (Instruction Register)
TDO
Control<6:0>
TMS
TRST
TAP
(Test Access Port)
Controller
Select
Output Enable
TCK
Figure 41. JTAG Architecture
IEEE STD 1149.1 JTAG Test Access Port
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August 20, 2009
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
6.1
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR)
The instructions are shifted in LSB first to this 3-bit register. See
Table 82 for details of the codes and the instructions related.
The IR (Instruction Register) with instruction decode block is used
to select the test to be executed or the data register to be accessed or
both.
Table 82: IR Code
IR Code
Instruction
Comment
000
EXTEST
010
SAMPLE /
PRELOAD
001
IDCODE
111
BYPASS
011
CLAMP
010
HIGHZ
101
-
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction,
the boundary scan register is placed between TDI and TDO. The signal on the input pins can be sampled by loading the boundary scan
register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR
state. The signal on the output pins can be controlled by loading patterns shifted in through input TDI into the boundary scan register using
the Update-DR state.
The sample/preload instruction is used to allow scanning of the boundary-scan register without causing interference to the normal operation of the on-chip system logic. Data received at system input pins is supplied without modification to the on-chip system logic; data from
the on-chip system logic is driven without modification through the system output pins. SAMPLE allows a snapshot to be taken of the data
flowing from the system pins to the on-chip system logic or vice versa, without interfering with the normal operation of the assembled
board. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of boundary-scan register cells prior to selection
of another boundary-scan test operation.
The identification instruction is used to connect the identification register between TDI and TDO. The device’s identification code can then
be shifted out using the Shift-DR state.
The BYPASS instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to bypass the
device.
This instruction allows the state of the signals driven from device pins to be determined from the boundary-scan register while the bypass
register is selected as the serial path between TDI and TDO. The signals driven from the device pins will not change while the CLAMP
instruction is selected.
Use of the HIGHZ instruction places the device in a state in which all of its system logic outputs are placed in an inactive drive state (e.g.,
high impedance). In this state, and in-circuit test system may drive signals onto the connections normally driven by a device output without
incurring the risk of damage to the device.
(for IC manufactory test)
IEEE STD 1149.1 JTAG Test Access Port
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August 20, 2009
IDT82P2282
6.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
JTAG DATA REGISTER
6.2.3
BOUNDARY SCAN REGISTER (BSR)
The bidirectional ports interface to 2 boundary scan cells:
- In cell: The Input cell is observable only (BC_4).
- Out cell: The output cell is controllable and observable (BC_1).
The Boundary Scan (BS) sequence is illustrated in Table 84.
6.2.1
DEVICE IDENTIFICATION REGISTER (IDR)
The IDR can be set to define the Vision, the Part Number, the Manufacturer Identity and a fixed bit. The IDR is 32 bits long and is partitioned as in Table 83. Data from the IDR is shifted out to the TDO LSB
first.
Table 84: Boundary Scan (BS) Sequence
Table 83: IDR
Bit No.
Comments
0
1 ~ 11
12 ~ 27
28 ~ 31
Set to ‘1’
Manufacturer Identity (033H)
Part Number (04BAH)
Version Number
6.2.2
BYPASS REGISTER (BYP)
The BYR consists of a single bit. It can provide a serial path
between the TDI input and TDO output, bypassing the BYR to reduce
test access times.
IEEE STD 1149.1 JTAG Test Access Port
359
BS-Cell Name
BS No.
BS-Cell Type
GPIO_OUT
GPIO_IN
THZ
GPIO_OE
MPM
SPIEN
D0_OUT
D0_IN
D1_OUT
D1_IN
D2_OUT
D2_IN
D3_OUT
D3_IN
D4_OUT
D4_IN
D5_OUT
D5_IN
D6_OUT
D6_IN
D7_OUT
D7_IN
D_OEN
DS/RD/SCLK
WR/RW/SDI
CS
INT_OUT
INT_OE
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
TSFS2_OUT
TSFS2_IN
TSIG[2]
TSD[2]
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
OUT-CELL
IN-CELL
IN-CELL
OUT-CELL
IN-CELL
IN-CELL
OUT-CELL
IN-CELL
OUT-CELL
IN-CELL
OUT-CELL
IN-CELL
OUT-CELL
IN-CELL
OUT-CELL
IN-CELL
OUT-CELL
IN-CELL
OUT-CELL
IN-CELL
OUT-CELL
IN-CELL
OUT-CELL
IN-CELL
IN-CELL
IN-CELL
OUT-CELL
OUT-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
OUT-CELL
IN-CELL
IN-CELL
IN-CELL
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 84: Boundary Scan (BS) Sequence (Continued)
BS-Cell Name
BS No.
BS-Cell Type
TSCK2_OUT
TSCK2_IN
TSCK_FS2_OE
RSFS2_OUT
RSFS2_IN
RSIG[2]
RSD[2]
RSD_RSIG2_EN
RSCK2_OUT
RSCK2_IN
RSCK_FS2_EN
TSFS1_OUT
TSFS1_IN
TSIG[1]
TSD[1]
TSCK1_OUT
TSCK1_IN
TSCK_FS1_OE
RSFS1_OUT
RSFS1_IN
RSIG[1]
RSD[1]
RSD_RSIG1_EN
RSCK1_OUT
RSCK1_IN
RSCK_FS1_EN
CLK_GEN
IC
IC
RESET
CLK_SEL[0]
CLK_SEL[1]
CLK_SEL[2]
REFA_OUT
REFB_OUT
OSCI
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
OUT-CELL
IN-CELL
OUT-CELL
OUT-CELL
IN-CELL
OUT-CELL
OUT-CELL
OUT-CELL
OUT-CELL
IN-CELL
OUT-CELL
OUT-CELL
IN-CELL
IN-CELL
IN-CELL
OUT-CELL
IN-CELL
OUT-CELL
OUT-CELL
IN-CELL
OUT-CELL
OUT-CELL
OUT-CELL
OUT-CELL
IN-CELL
OUT-CELL
OUT-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
OUT-CELL
OUT-CELL
IN-CELL
IEEE STD 1149.1 JTAG Test Access Port
360
August 20, 2009
IDT82P2282
6.3
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TEST ACCESS PORT CONTROLLER
either the data or instruction registers. The value shown next to each
state transition in this figure states the value present at TMS at each rising edge of TCK.
The TAP controller is a 16-state synchronous state machine.
Figure - 42 shows its state diagram. A description of each state is listed
in Table 85. Note that the figure contains two main branches to access
Table 85: TAP Controller State Description
State
Description
Test Logic In this state, the test logic is disabled to continue normal operation of the device. During initialization, the device initializes the instruction register with the
Reset IDCODE instruction.
Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input is held high for at least 5 rising
edges of TCK. The controller remains in this state while TMS is high.
Run-Test/ This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The instruction regIdle
ister and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the controller moves to the Select-DR
state.
Select-DR- This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction retains its
Scan
previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-DR state and a scan
sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the controller moves to the Select-IR-Scan
state.
Capture- In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruction does not
DR
change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in this state and a rising
edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
Shift-DR In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage toward its serial
output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising edge is applied to
TCK, the controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if TMS is low.
Exit1-DR This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state, which
terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-DR state. The test data register
selected by the current instruction retains its previous value and the instruction does not change during this state.
Pause-DR The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO.
For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test sequence. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this
state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-DR state.
Exit2-DR This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state, which
terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-DR state. The test data register
selected by the current instruction retains its previous value and the instruction does not change during this state.
Update-DR The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched into the parallel output
of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output changes only in this state. All shift-register stages in the test data register selected by the current instruction retain their previous value and the instruction does not change during this state.
Select-IR- This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low and a rising
Scan
edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a scan sequence for the instruction register is initiated. If
TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-Reset state. The instruction does not change during this
state.
Capture-IR In this controller state, the shift register contained in the instruction register loads a fixed value of '100' on the rising edge of TCK. This supports fault-isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the instruction does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or the
Shift-IR state if TMS is held low.
Shift-IR In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its serial output
on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or
remains in the Shift-IR state if TMS is held low.
Exit1-IR This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which
terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-IR state. The test data register
selected by the current instruction retains its previous value and the instruction does not change during this state.
IEEE STD 1149.1 JTAG Test Access Port
361
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 85: TAP Controller State Description (Continued)
State
Description
Pause-IR The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as long as TMS is low.
When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-IR state.
Exit2-IR This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which
terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-IR state. The test data register
selected by the current instruction retains its previous value and the instruction does not change during this state.
Update-IR The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK. When the new
instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction retain their previous value.
IEEE STD 1149.1 JTAG Test Access Port
362
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
1
Test-logic Reset
0
0
1
Run Test/Idle
1
Select-DR
0
1
1
Select-IR
0
1
Capture-DR
Capture-IR
0
0
0
0
Shift-DR
Shift-IR
1
1
1
1
Exit1-DR
Exit1-IR
0
0
0
0
Pause-DR
Pause-IR
1
0
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
Update-IR
0
1
1
0
Figure 42. JTAG State Diagram
IEEE STD 1149.1 JTAG Test Access Port
363
August 20, 2009
IDT82P2282
7
7.1
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
PHYSICAL AND ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Voltage on VDDAR/VDDAT/VDDAX/VDDAB/VDDAP w.r.t. GND
Voltage on VDDDIO w.r.t. GND
Voltage on VDDDC w.r.t. GND
Voltage on Any Input Pin
ESD Performance (HBM)
Latch-up Current on Any Pin
Maximum Lead Temperature
Maximum Junction Temperature
Maximum Allowed Power Dissipation (Package)
Min
Max
-65 °C
-0.3 V
-0.3 V
-0.3 V
-0.3 V
2000 V
1.5 x Inormal *
250 °C
150 °C
+150 °C
4.6 V
4.6 V
2.2 V
6V
1.64W
Note:
* Inormal is the total current in normal operation mode.
Caution: Long-term exposure to absolute maximum ratings may affect the device’s reliability, and permanent damage may occur if the rating is
exceeded during operation. Functional operation under these conditions is not implied. The device should be operated under recommended operating
conditions.
7.2
RECOMMENDED OPERATING CONDITIONS
Parameter
Description
Min.
Typ.
Max
Unit
Top
VDDDIO
VDDAR/VDDAT/VDDAX/VDDAB/VDDAP
VDDDC
VIL
VIH
Operating Temperature Range
Digital IO Power Supply
Analog IO Power Supply
Digital Core Power
Input Low Voltage
Input High Voltage
-40
3.0
3.13
1.68
0
2.0
25
3.3
3.3
1.8
85
3.6
3.47
1.98
0.8
3.3
°C
V
V
V
V
V
Physical And Electrical Specifications
364
August 20, 2009
IDT82P2282
7.3
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
D.C. CHARACTERISTICS
@ TA = -40 to +85 °C, VDDDIO = 3.3 V + 0.3 V, VDDDC = 1.8 + 10%
Parameter
Description
Min.
Typ.
Max
Unit
VDDAR/VDDAT/VDDAX/VDDAB/
VDDAP, VDDDIO
VDDDC
VIL
VIH
VOL
VOH
VT+
VTIILPU
IIL
IIH
IOLD
Analog/IO Power Supply
3.0
3.3
3.6
V
Digital Core Ground
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Reset Input High Voltage
Reset Input Low Voltage
Input Low Current with Pull-up
Input Low Current
Input High Current
Output Low Current
1.68
1.8
1.98
0.8
V
V
V
V
V
V
V
µA
µA
µA
mA
IOHD
Output High Current
8
mA
VO = VOH, D7 - D0
IOL
IOH
CIN
Output Low Current
Output High Current
Maximum Input Capacitance at any Input Pins
4
4
10
mA
mA
pF
VO = VOL, except D7 - D0
VO = VOH, except D7 - D0
2.0
0.40
2.4
1.35
-1
-1
8
0
0
1.0
-100
+1
+1
10
Ivdddc
DC Current on VDDDC
20
mA
Ivdda
DC Current on VDDAR/VDDAT/VDDAX/VDDAB/
VDDAP
Power Dissipation
100
mA
270
mW
P
Physical And Electrical Specifications
365
Test Conditions
VDDDIO = min, IOL = 4 mA, 8 mA
VDDDIO = min, IOH = 4 mA, 8 mA
VIL = GND
VIL = GND
VO = VOL, D7 - D0
with the PRBS pattern, excluding
Loading Dissipation
August 20, 2009
IDT82P2282
7.4
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
DIGITAL I/O TIMING CHARACTERISTICS
The capacitive loading for timing measurement is:
100 pF for BUS: D[7:0],
50 pF for other pins.
The timing can be applied to both clock edges as defined by active clock edge selection.
Delays are measured according to the cross of 50% of the rising/falling edge.
The duty cycle for TSCKn/MTSCK & RSCKn/MRSCK is from 40% to 60%.
7.4.1
IN NON-MULTIPLEXED MODE
The system Input / Output timing in Non-Multiplexed mode is listed as below:
Symbol
Parameter
Min.
Typ.
Tprop
Ts
Thold
Propagation Delay
Set Up Time
Hold Time
-10 / 0 *
10
10
Max
Unit
20
ns
ns
ns
Note:
* The ‘-10’ applies to the case that the clock is input and the ‘0’ applies to the case that the clock is output.
TSCK
RSCK
Tprop
Outputs
Ts
Thold
Inputs
Figure 43. I/O Timing in Non-Multiplexed Mode
Physical And Electrical Specifications
366
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IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
7.4.2
IN MULTIPLEXED MODE
The system Input / Output timing in Multiplexed mode is listed as below:
Symbol
Parameter
Min.
Tprop
Ts
Thold
Propagation Delay
Set Up Time
Hold Time
-10
10
10
Typ.
Max
Unit
20
ns
ns
ns
MTCSK
MRCSK
Tprop
HighZ
valid data
Outputs
Ts
Valid data
Thold
Inputs
Figure 44. I/O Timing in Multiplexed Mode
7.5
CLOCK FREQUENCY REQUIREMENT
- Relative to nominal rate
TSCK
RSCK
OSCI
Physical And Electrical Specifications
Min
Max
Unit
-100
-100
-32
+100
+100
+32
ppm
ppm
ppm
367
August 20, 2009
IDT82P2282
7.6
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 LINE RECEIVER ELECTRICAL CHARACTERISTICS
Parameter
Receiver Sensitivity
Short haul with cable loss @ 772 kHz:
Long haul with cable loss @ 772 kHz:
Analog LOS level
Short haul:
Long haul:
Allowable consecutive zeros before LOS
T1.231 - 1993:
I.431:
LOS reset
Receive Intrinsic Jitter
10 Hz - 8 KHz
10 Hz - 40 KHz
8 KHz - 40 KHz
Wide Band
Input Jitter Tolerance
0.1 Hz - 1 Hz:
4.9 Hz - 300 Hz:
10 KHz - 100 KHz:
Receiver Differential Input Impedance
Input Termination Resistor Tolerance
Receive Return Loss
39 KHz - 77 KHz:
77 KHz - 1.544 MHz:
1.544 MHz - 2.316 MHz
Physical And Electrical Specifications
Min.
Typ.
Max
Unit
Test Conditions
10
36
dB
with nominal pulse amplitude of 3.0 V for 100 Ω termination
800
4
48
mVp-p
dB
A LOS level is programmable for long haul.
175
1544
12.5
0.02
0.025
0.025
0.05
138.0
28.0
0.4
20
% ‘One’s G.775, ETSI 300233
JA is enabled
U.I.
U.I.
U.I.
U.I.
U.I.
U.I.
U.I.
KΩ
AT&T62411
±1%
20
20
20
dB
dB
dB
368
G.703
Internal Termination
August 20, 2009
IDT82P2282
7.7
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 LINE RECEIVER ELECTRICAL CHARACTERISTICS
Parameter
Receiver Sensitivity
Short haul with cable loss @ 1024 kHz:
Long haul with cable loss @ 1024 kHz:
Analog LOS level
Short haul:
Long haul:
Allowable consecutive zeros before LOS
G.775:
I.431 / ETSI300233:
LOS reset
Receive Intrinsic Jitter
Input Jitter Tolerance
1 Hz - 20 Hz:
20 Hz - 2.4 KHz:
18 KHz - 100 KHz:
Receiver Differential Input Impedance
Input Termination Resistor Tolerance
Receive Return Loss
51 KHz - 102 KHz:
102 KHz - 2.048 MHz:
2.048 MHz - 3.072 MHz
Physical And Electrical Specifications
Min.
Typ.
Max
Unit
Test Conditions
10
43
dB
with nominal pulse amplitude of 3.0 V for 120 Ω and 2.37 V for
75 Ω termination
800
4
48
mVp-p
dB
A LOS level is programmable for long haul.
32
2048
12.5
0.05
37
5
2
20
% ‘One’s G.775, ETSI 300233
U.I.
JA is enabled; wide band
U.I.
U.I.
U.I.
KΩ
G.823, with 6 dB cable attenuation
±1%
20
20
20
dB
dB
dB
369
G.703
Internal Termination
August 20, 2009
IDT82P2282
7.8
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
T1/J1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS
Parameter
Output pulse amplitudes
Zero (space) level
Transmit amplitude variation with supply
Difference between pulse sequences for 17 consecutive pulses (T1.102)
Output pulse width at 50% of nominal amplitude
Pulse width variation at the half amplitude (T1.102)
Imbalance between Positive and Negative Pulses amplitude (T1.102)
Transmit Return Loss
39 KHz - 77 KHz:
77 KHz - 1.544 MHz:
1.544 MHz - 2.316 MHz:
Intrinsic Transmit Jitter (TSCK is jitter free)
10 Hz - 8 KHz:
8 KHz - 40 KHz:
10 Hz - 40 KHz:
wide band:
Line short circuit current
Physical And Electrical Specifications
Min.
Typ.
Max
Unit
2.4
-0.15
-1
3.0
338
350
3.6
0.15
+1
200
362
20
1.05
V
V
%
mV
ns
ns
0.95
20
15
12
dB
dB
dB
0.020
0.025
0.025
0.050
110
370
U.I.p-p
U.I.p-p
U.I.p-p
U.I.p-p
mA
Ip-p
August 20, 2009
IDT82P2282
7.9
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS
Parameter
Output pulse amplitudes
E1, 75Ω load:
E1, 120Ω load:
Zero (space) level
E1, 75Ω load:
E1, 120Ω load:
Transmit amplitude variation with supply
Difference between pulse sequences for 17 consecutive pulses (T1.102)
Output pulse width at 50% of nominal amplitude
Ratio of the amplitudes of Positive and Negative pulses at the center of the pulse interval (G.703)
Ratio of the width of Positive and Negative pulses at the center of the pulse interval (G.703)
Transmit Return Loss (G.703)
E1, 75 Ω / 120 Ω
51 KHz - 102 KHz:
102 KHz - 2.048 MHz:
2.048 MHz - 3.072 MHz:
Intrinsic Transmit Jitter (TSCK is jitter free)
20 Hz - 100 KHz
Line short circuit current
Physical And Electrical Specifications
371
Min.
Typ.
Max
Unit
2.14
2.7
2.37
3.0
2.60
3.3
V
V
0.237
0.3
+1
200
256
1.05
1.05
V
V
%
mV
ns
-0.237
-0.3
-1
232
0.95
0.95
244
20
15
12
dB
dB
dB
0.050
110
U.I.
mA
Ip-p
August 20, 2009
IDT82P2282
7.10
7.10.1
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
JITTER TOLERANCE
T1/J1 MODE
Jitter Tolerance
Min.
1 Hz
4.9 Hz - 300 Hz
10 KHz - 100 KHz
138.0
28.0
0.4
Typ.
Max
Unit
Standard
U.I.
U.I.
U.I.
AT&T 62411
Figure 45. T1/J1 Jitter Tolerance Performance Requirement
Physical And Electrical Specifications
372
August 20, 2009
IDT82P2282
7.10.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 MODE
Jitter Tolerance
Min.
1 Hz
20 Hz - 2.4 KHz
18 KHz - 100 KHz
37
1.5
0.2
Typ.
Max
Unit
Standard
U.I.
U.I.
U.I.
G.823
Cable attenuation is 6 dB
Figure 46. E1 Jitter Tolerance Performance Requirement
Physical And Electrical Specifications
373
August 20, 2009
IDT82P2282
7.11
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
JITTER TRANSFER
Parameter
Min.
Typ.
Jitter Attenuator Latency Delay
32-bit FIFO:
64-bit FIFO:
128-bit FIFO:
Input jitter tolerance before FIFO overflow or underflow
32-bit FIFO:
64-bit FIFO:
128-bit FIFO:
Max
Unit
16
32
64
U.I.
U.I.
U.I.
28
58
120
U.I.
U.I.
U.I.
7.11.1
T1/J1 MODE
T1/J1 Jitter Transfer performance is required by AT&T pub.62411.
Parameter
Min.
@ 1 Hz
@ 20 Hz
@ 1 kHz
@ 1.4 kHz
@ 70 kHz
0
0
+33.3
40
40
Typ.
Max
Unit
dB
Figure 47. T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-000009)
Physical And Electrical Specifications
374
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
7.11.2
E1 MODE
E1 Jitter Transfer performance is required by G.736.
Parameter
Min.
@ 3 Hz
@ 40 Hz
@ 400 Hz
@ 100 kHz
-0.5
-0.5
+19.5
+19.5
Typ.
Max
Unit
dB
Figure 48. E1 Jitter Transfer Performance Requirement (G.736)
Physical And Electrical Specifications
375
August 20, 2009
IDT82P2282
7.12
7.12.1
7.12.1.1
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
MICROPROCESSOR TIMING SPECIFICATION
MOTOROLA NON-MULTIPLEXED MODE
Read Cycle Specification
Symbol
Parameter
Min
Max
Units
tRC
Read Cycle Time
237
ns
tDW
Valid DS Width
232
ns
tRWV
Delay from DS to Valid Read Signal
tRWH
RW to DS Hold Time
tAV
21
134
21
Address to DS Hold Time
tPRD
DS to Valid Read Data Propagation Delay
tDAZ
Delay from Read Data Active to High Z
5
Recovery Time from Read Cycle
5
tRecovery
ns
Delay from DS to Valid Address
tADH
ns
134
ns
ns
206
ns
20
ns
ns
tRC
tRecovery
tDW
DS+CS
tRWH
tRWV
RW
tADH
tAV
A[X:0]
Valid
Address
tDAZ
tPRD
READ D[7:0]
Valid Data
Figure 49. Motorola Non-Multiplexed Mode Read Cycle
Physical And Electrical Specifications
376
August 20, 2009
IDT82P2282
7.12.1.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Write Cycle Specification
Symbol
Parameter
Min
Max
Units
tWC
Write Cycle Time
237
ns
tDW
Valid DS width
232
ns
tRWV
Delay from DS to valid write signal
tRWH
RW to DS Hold Time
tAV
Delay from DS to Valid Address
tAH
Address to DS Hold Time
tDV
Delay from DS to valid write data
tDHW
tRecovery
21
165
ns
21
165
Recovery Time from Write Cycle
ns
ns
83
Write Data to DS Hold Time
ns
ns
165
ns
5
ns
tRecovery
tWC
DS+CS
tDW
tRWH
tRWV
RW
tAV
A[x:0]
tAH
Valid Address
tDV
tDHW
Valid Data
Write D[7:0]
Figure 50. Motorola Non-Multiplexed Mode Write Cycle
Physical And Electrical Specifications
377
August 20, 2009
IDT82P2282
7.12.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
INTEL NON-MULTIPLEXED MODE
7.12.2.1
Read Cycle Specification
Symbol
tRC
tRDW
Parameter
Min
Units
Read Cycle Time
237
ns
Valid RD Width
232
ns
tAV
Delay from RD to Valid Address
tAH
Address to RD Hold Time
tPRD
RD to Valid Read Data Propagation Delay
tDAZ
Delay from Read Data Active to High Z
5
Recovery Time from Read Cycle
5
tRecovery
Max
21
134
ns
ns
206
ns
20
ns
ns
tRC
tRecovery
tRDW
CS+RD
tAV
A[x:0]
Valid
tAH
Address
tDAZ
tPRD
READ D[7:0]
Valid Data
Note: The WR pin should be tied to high.
Figure 51. Intel Non-Multiplexed Mode Read Cycle
Physical And Electrical Specifications
378
August 20, 2009
IDT82P2282
7.12.2.2
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Write Cycle Specification
Symbol
tWC
tWRW
Parameter
Units
237
ns
Valid WR width
232
ns
Delay from WR to Valid Address
tAH
Address to WR Hold Time
tDV
Delay from WR to valid write data
tRecovery
Max
Write Cycle Time
tAV
tDHW
Min
21
165
ns
83
Write Data to WR Hold Time
ns
165
ns
5
ns
Recovery Time from Write Cycle
tRecovery
tWC
WR+CS
ns
tWRW
tAH
tAV
A[x:0]
Valid Address
tDHW
tDV
Valid Data
Write D[7:0]
Note: The RD pin should be tied to high.
Figure 52. Intel Non-Multiplexed Mode Write Cycle
Physical And Electrical Specifications
379
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
7.12.3
SPI MODE
The maximum SPI data transfer clock is 2 MHz.
Symbol
Description
fOP
SCLK Frequency
tCSH
Min. CS High Time
Min.
Max
Units
2.0
MHz
100
ns
tCSS
CS Setup Time
50
ns
tCSD
CS Hold Time
100
ns
tCLD
Clock Disable Time
50
ns
tCLH
Clock High Time
205
ns
tCLL
Clock Low Time
205
ns
tDIS
Data Setup Time
50
ns
tDIH
Data Hold Time
150
tPD
Output Delay
150
ns
tDF
Output Disable Time
50
ns
ns
tCSH
CS
tCSS
tCLH
tCLL
tCLD
tCSD
SCLK
tDIS
SDI
tDIH
Valid Input
tPD
SDO
tDF
High Impedance
Valid Output
High Impedance
Figure 53. SPI Timing Diagram
Physical And Electrical Specifications
380
August 20, 2009
IDT82P2282
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
ORDERING INFORMATION
IDT
XXXXXXX
Device Type
XX
Package
X
Process/Temperature Range
BLANK
Industrial (-40 °C to +85 °C)
PF
PFG
Thin Quad Flat Pack (TQFP, PK100)
Green Thin Quad Flat Pack (TQFP, PKG100)
82P2282
Dual T1/E1/J1 Long / Short Haul Transceiver
DOCUMENT HISTORY
08/20/2009
10/28/2008
02/26/2008
04/06/2007
08/01/2006
04/12/2006
09/01/2004
pgs. 12, 59
pgs. 12, 59
pgs. 68, 69, 76, 77
pgs. 18, 24, 25, 26, 27, 54, 65, 70, 72, 84, 102, 107, 193, 199, 201, 293, 309, 316
pg. 381
pgs. 18, 48, 50, 150, 382
pgs. 69, 71, 166, 291
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1-800-345-7015 or 408-284-8200
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IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
381
for Tech Support:
408-360 -1552
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