NJU7042 INPUT/OUTPUT FULL-SWING TINY SINGLE C-MOS OPERATIONAL AMPLIFIER ■GENERAL DESCRIPTION The NJU7042 is a single C-MOS operational amplifier permitting input and output in full swing. The operating voltage is 2.7V to 5.5V and the input and output stage permits signal to swing between both of the supply rails. The input offset voltage is lower than 5mV, and the input bias current is as low as than 1pA, consequently very small signal around the ground level can be amplified. Furthermore, The NJU7042 is packaged with very small MTP-5, therefore it can be especially applied to portable items. ■PACKAGE INFORMATION ■FEATURES ●Input Full-Swing VIN=VSS to VDD ●Output Full-Swing VOM≥2.7V min ●Low Input Offset Voltage VIO=5mV max ●Single-Power-Supply VDD=2.7 to 5.5V ●Low Operating Current IDD=15uA typ ●High Load Current IOH/IOL=200uA typ ●Low Bias Current IIB=1pA typ ●Compensation Capacitor Incorporated ●Package Outline MTP-5 ●C-MOS Technology ■PIN CONFIGURATION (Top View) NJU7042F IN+ 1 5 VDD VSS 2 IN- 3 4 OUT ■EQUIVALENT CIRCUIT VDD IN - IN + OUT VSS 01/06/01 ( 1 / 3 ) NJU7042 ■ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL RATING UNIT Supply Voltage VDD 7.0 V Differential Input Voltage VID V ±7.0 (Note1) Common Mode Input Voltage VIC -0.3~7.0 V Power Dissipation PD 200 mW Operating Temperature Topr -40~+85 °C Storage Temperature Tstg -55~+125 °C Note1) If the supply voltage (VDD) is less than 7.0V, the input voltage must not over the VDD level though 7.0V is limit specified. Note2) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for the circuit. ■ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL CONDITIONS Operating Voltage VDD Input Offset Voltage VIO VIN=VDD/2 Input Offset Current IIO Input Bias Current IIB Input Impedance RIN Large Signal Voltage Gain AVD Input Common Mode VICM Voltage Range VOM1 Maximum Output RL=30kΩ Swing Voltage VOM2 RL=30kΩ Output Source Current IOH VOH=VDD-0.3 Output Sink Current IOH VOL=VDD+0.3 Common Mode CMR VIN=VDD/2 Rejection Ratio Supply Voltage SVR VDD=2.7~5.5V Rejection Ratio Operating Current IDD Slew Rate SR Unity Gain Bandwidth Ft AV=40dB,CL=10pF Note3) The load capacitance (CL) should be used less than 200pF MIN 2.7 60 VSS to VDD VDD-0.3 100 100 (VDD=3.0V,RL=∞,Ta=25°C) TYP MAX UNIT 5.5 V 5 mV 1 pA 1 pA 1 TΩ 70 dB - - V 200 200 VSS+0.3 - 60 70 - dB 60 70 - dB - 15 0.03 47 30 - uA V/us kHz V uA [CAUTION] The specifications on this data book are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this data book are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. 01/06/01 ( 2 / 3 )