ICS9248-66 Integrated Circuit Systems, Inc. Advance Information Frequency Timing Generator for PENTIUM II Systems Features Key Specification Generates the following system clocks: - 3 CPU clocks ( 2.5V, 100/133MHz) - 8 PCI clocks, including 1 free-running (3.3V, 33MHz) - 1 CPU/2 clocks (2.5V, 50/66MHz) - 1 IOAPIC clocks (2.5V, 16.67MHz) - 3 Fixed frequency 66MHz clocks(3.3V, 66MHz) - 2 REF clocks(3.3V, 14.318MHz) - 1 USB clock (3.3V, 48MHz) Efficient power management through PD#, CPU_STOP# and PCI_STOP#. 0 to -0.5% typical down spread modulation on CPU, PCI, IOAPIC, 3V66 and CPU/2 output clocks. Uses external 14.318MHz crystal. Block Diagram CPU Output Jitter: <250ps CPU/2 Output Jitter. <250ps IOAPIC Output Jitter: <500ps 48MHz, 3V66, PCI Output Jitter: <500ps Ref Output Jitter. <1000ps CPU Output Skew: <175ps PCI Output Skew: <500ps 3V66 Output Skew <250ps CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads) 3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads) CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads) Pin Configuration 48-pin SSOP 9248-66 Rev - 7/28/99 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. ICS9248-66 Advance Information General Description Power Groups: The ICS9248-66 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the ICS9211-01. VDDREF, GNDREF = REF, X1, X2 GNDPCI, VDDPCI = PCICLK VDD66, GND66 = 3V66 VDD48, GND48 = 48MHz VDDCOR, GNDCOR = PLL Core VDDLCPU/2 , GNDLCPU/2 = CPU/2 VDDLIOAPIC, GNDIOAPIC = IOAPIC Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-66 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. The CPU/2 clocks are inputs to the DRCG. Pin Descriptions Pin number 1, 7, 13, 19, 23, 26, 35 2, 3 Pin name Type GND PWR Ground pins REF(0:1) OUT 14.318MHz reference clock outputs at 3.3V 4, 10, 16, 22, 28, 36 VDD PWR Power pins 3.3V 5 6 X1 X2 IN OUT 8 PCICLK_F OUT XTAL_IN 14.318MHz crystal input XTAL_OUT Crystal output Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not affected by the PCI_STOP# input. PCICLK[1:7] OUT PCI clock outputs at 3.3V. Synchronous to CPU clocks. 3V66[0:2] OUT 25 SEL 133/100# IN 27 29, 30 48MHz SEL[0:1] OUT IN 31 SPREAD# IN 32 PD# IN 33 CPU_STOP# IN 34 PCI_STOP# IN 40 GNDLCPU PWR 37, 38, 41 CPUCLK[0:3] OUT 39, 42 43 VDDLCPU GNDLCPU/2 PWR PWR 44 CPU/2 OUT 45 46 47 VDDLCPU/2 GNDLIOAPIC IOAPIC PWR PWR OUT 66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is driven active.. This selects the frequency for the CPU and CPU/2 outputs. High = 133MHz, Low=100MHz Fixed 48MHz clock output. 3.3V Function select pins. See truth table for details. Enables spread spectrum when active(Low). modulates all the CPU, PCI, IOAPIC, 3V66 and CPU/2 clocks. Does not affect the REF and 48MHz clocks. 0.5% down spread modulation. This asynchronous input powers down the chip when drive active(Low). The internal PLLs are disabled and all the output clocks are held at a Low state. This asychronous input halts the CPUCLK[0:3] and the 3V66[0:3] clocks at logic "0" when driven active(Low). Does not affect the CPU/2 clocks. This asynchronous input halts the PCICLK[1:7] at logic"0" when driven active(Low). PCICLK_F is not affected by this input. Ground pin for the CPUCLKs Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state of the SEL 133/100MHz. Power pin for the CPUCLKs. 2.5V Ground pin for the CPU/2 clocks. 2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz depending on the state of the SEL 133/100# input pin. Power pin for the CPU/2 clocks. 2.5V Ground pin for the IOAPIC outputs. IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at 16.67MHz. 48 VDDLIOAPIC PWR Power pin for the IOAPIC outputs. 2.5V. 9, 11, 12, 14, 15, 17, 18 20, 21, 24 Description 2 ICS9248-66 Advance Information Frequency Select: SEL 133/100- SEL1 SEL0 # 0 0 0 0 0 1 CPU MHz CPU/2 MHz 3V66 MHz PCI MHz 48 MHz REF MHz IOAPIC MHz Hi-Z N/A Hi-Z N/A Hi-Z N/A Hi-Z N/A Hi-Z N/A Hi-Z N/A Hi-Z N/A Hi-Z 14.318 16.67 14.318 16.67 0 1 0 100 50 66.6 33.3 0 1 1 100 50 66.6 33.3 1 0 0 1 1 1 0 1 1 1 0 1 48 TCLK/TCLK/2 TCLK/4 TCLK/4 TCLK/8 2 N/A N/A N/A N/ A N/A 133.3 66. 6 66.6 33.3 Hi-Z 133.3 66.6 66.6 33.3 48 TCLK TCLK/16 N/A 14.318 14.318 N/ A 16.67 16.67 Comments Tri-state Reserved 48MHz PLL disabled Test mode (1) Reserved Note: 1. TCLK is a test clock driven on the x1 input during test mode. ICS9248-66 Power Management Features: 3V66 PCI PCI_F REF. 48MHz Osc VCOs LOW LOW LOW LOW LOW OFF OFF ON ON LOW LOW ON ON ON ON LOW ON ON LOW ON ON ON ON ON 0 ON ON ON ON LOW ON ON ON ON 1 ON ON ON ON ON ON ON ON ON CPU_STOP# PD # PCI_STOP# CPUCLK CPU/2 IOAPIC X 0 X LOW LOW 0 1 0 LOW 0 1 1 1 1 1 1 Note: 1. LOW means outputs held static LOW as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs. 4. All 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled LOW. 5. CPU/2, IOAPIC, REF, 48 MHz signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions except PD# = LOW 3 ICS9248-66 Advance Information Power Management Requirements: Latency Singal CPU_STOP PCI_STOP# PD# Singal State No. of rising edges of PCICLK 0 (disabled) 1 1 (enabled) 1 0 (disabled) 1 1 (enabled) 1 (normal operation) 0 (power down) 1 3mS 2max. Note: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/ high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device. CPU_STOP# Timing Diagram CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU and 3V66 clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU clock) and must be internally synchronized to the external output. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse. ONLY one rising edge of PCICLK_F is allowed after the clock control logic switched for both the CPU and 3V66 outputs to become enabled/disabled. Notes: 1. All timing is referenced to the internal CPUCLK. 2. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed. 3. CPU_STOP# signal is an input singal that must be made synchronous to free running PCICLK_F 4. 3V66 clocks also stop/start before 5. PD# and PCI_STOP# are shown in a high state. 6. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz 4 ICS9248-66 Advance Information PCI_STOP# Timing Diagram PCI_STOP# is an input to the clock synthesizer and must be made synchronous to the clock driver PCICLK_F output. It is used to turn off the PCI clocks for low power operation. PCI clocks are required to be stopped in a low state and started such that a full high pulse width is guaranteed. ONLY one rising edge of PCICLK_F is allowed after the clock control logic switched for the PCI outputs to become enabled/disabled. Notes: 1. All timing is referenced to CPUCLK. 2. PCI_STOP# signal is an input signal which must be made synchronous to PCICLK_F output. 3. Internal means inside the chip. 4. All other clocks continue to run undisturbed. 5. PD# and CPU_STOP# are shown in a high state. 6. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 5 ICS9248-66 Advance Information PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device). 2. Internal means inside the chip 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 6 ICS9248-66 Advance Information Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Group Offset Group CPU to 3V66 3V66 to PCI CPU to IOAPIC Offset 0.0-1.5ns CPU leads 1.5-4.0ns 3V66 leads 1.5-4.0ns CPU leads Measurement Loads CPU @ 20pF, 3V66 @ 30pF 3V66 @ 30pF, PCI @ 30pF CPU @ 20pF, IOAPIC @ 20pF Measure Points CPU @1.25V, 3V66 @ 1.5V 3V66 @ 1.5V, PCI @ 1.5V CPU @1.25V, IOAPIC @ 1.5V No te: 1 . All o ffsets are to be meas u red at ris in g edg es. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER SYMBOL Input High Voltage VIH 2 Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance VIL IIH IIL1 IIL2 VSS-0.3 -5 Input Capacitance 1 1 Transition Time Settling Time1 Clk Stabilization 1 Delay 1 CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors MIN TYP MAX VDD+0. 3 0.8 5 UNITS V V µA µA µA IDD3.3OP CL = 0 pF; Select mA IDD3.3PD CL = 0 pF; With input address to Vdd or GND µA Fi Lpin CIN C out CINX Ttrans Ts TSTAB tPZH,tPZH tPLZ,tPZH VDD = 3.3 V; Logic Inputs Out put pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs) Guarenteed by design, not 100% tested in production. 7 14.318 7 5 6 27 1 1 45 3 3 10 10 MHz nH pF pF pF mS mS mS nS nS ICS9248-66 Advance Information Electrical Characteristics - CPU TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL RDSP2B1 VOH2B VOL2B IOH2B IOL2B Rise Time tr2B1 VOL = 0.4 V, VOH = 2.0 V 0.4 1.6 ns 1 1.6 ns 1 CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V MIN 13.5 2 TYP -27 27 Fall Time tf2B VOH = 0.4 V, VOL = 2.0 V 0.4 Duty Cycle d t2B1 VT = 1.25 V 45 Skew tsk2B1 Jitter tjcyc-cyc1 VT = 1.25 V VT = 1.25 V MAX UNITS 45 Ω V 0.4 V -27 mA 30 mA 55 ns 175 ps 250 ps Guarenteed by design, not 100% tested in production. Electrical Characteristics - CPU/2 TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL RDSP2B1 VOH2B VOL2B IOH2B IOL2B Rise Time tr2B1 VOL = 0.4 V, VOH = 2.0 V 0.4 1.6 ns Fall Time VOH = 0.4 V, VOL = 2.0 V 0.4 1.6 ns Duty Cycle tf2B1 d t2B1 55 ns Jitter VT = 1.25 V VT = 1.25 V 45 tjcyc-cyc1 250 ps 1 CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V Guarenteed by design, not 100% tested in production. 8 MIN 13.5 2 -27 27 TYP MAX UNITS 45 Ω V 0.4 V -27 mA 30 mA ICS9248-66 Advance Information Electrical Characteristics - 3V66 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance SYMBOL CONDITIONS 1 VO = VDD*(0.5) RDSP1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN11 VOH1 VOL1 IOH1 IOL1 Rise Time Fall Time Duty Cycle Skew Jitter 1 -33 30 VOL = 0.4 V, VOH = 2.4 V 0.5 2.0 ns VOH = 2.4 V, VOL = 0.4 V 0.5 2.0 ns VT = 1.5 V 45 55 % 250 500 ps ps 1 1 1 VT = 1.5 V VT = 1.5 V tsk1 tjcyc-cyc MAX UNITS 55 Ω 0.55 -33 38 tr11 dt1 TYP Ω V V mA mA VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 tf1 MIN 12 12 2.4 55 Guarenteed by design, not 100% tested in production. Electrical Characteristics - PCI TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance SYMBOL CONDITIONS RDSP11 VO = VDD*(0.5) Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN11 VOH1 VOL1 IOH1 IOL1 Rise Time Fall Time Duty Cycle Skew Jitter 1 -29 29 VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns VT = 1.5 V 45 55 % 500 500 ps ps 1 1 1 VT = 1.5 V VT = 1.5 V tsk1 tjcyc-cyc MAX UNITS 55 Ω 0.55 -23 27 tr11 dt1 TYP Ω V V mA mA VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 tf1 MIN 12 Guarenteed by design, not 100% tested in production. 9 12 2.4 55 ICS9248-66 Advance Information Electrical Characteristics - 48M, REF TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Duty Cycle Jitter Skew 1 SYMBOL 1 RDSP5 RDSN51 VOH5 VOL5 IOH5 IOL5 dt51 tjcyc-cyc1 tjcyc-cyc1 Tsk CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = 1 mA IOL = -1 mA VOH @MIN=1 V, VOH@MAX= 3.135 V VOL@MIN=1.95 V, VOL@MIN=0.4 V VT = 1.5 V VT = 1.5 V; Fixed Clocks VT = 1.5 V; Ref Clocks VT = 1.5 V,Fixed Clocks MIN 20 20 2.4 TYP MAX UNITS 60 Ω 60 Ω V 0.4 V -23 mA 27 mA 55 % 500 ps 1000 ps N/A ps TYP MAX UNITS 45 Ω V 0.4 V -27 mA 30 mA 1.6 ns 1.6 ns 55 ns NA ps 500 ps -29 29 45 Guarenteed by design, not 100% tested in production. Electrical Characteristics - IOAPIC TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter 1 SYMBOL RDSP2B1 VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B1 dt2B1 tsk2B1 tjcyc-cyc1 CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V VOL = 0.4 V, VOH = 2.0 V VOH = 0.4 V, VOL = 2.0 V VT = 1.25 V VT = 1.25 V VT = 1.25 V Guarenteed by design, not 100% tested in production. 10 MIN 13.5 2 -27 27 0.4 0.4 45 ICS9248-66 Advance Information SYMBOL A A1 A2 B C D E e H h L N ∝ X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0° 5° 8° .085 .093 .100 VARIATIONS AD MIN. .720 D NOM. .725 N MAX. .730 56 56 Pin SSOP Package Ordering Information ICS9248yF-66 Example: ICS XXXX y F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 11 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.