Intersil ISL28236FBZ 5mhz, dual precision rail-to-rail input-output (rrio) op amp Datasheet

ISL28236
®
Data Sheet
June 18, 2009
5MHz, Dual Precision Rail-to-Rail
Input-Output (RRIO) Op Amp
FN6921.0
Features
• 5MHz Gain Bandwidth Product @ AV = 100
The ISL28236 is a low-power dual operational amplifier
optimized for single supply operation from 2.4V to 5.5V,
allowing operation from one lithium cell or two Ni-Cd
batteries. The device features a gain-bandwidth product of
5MHz.
The ISL28236 features an Input Range Enhancement Circuit
(IREC), which enables the amplifier to maintain CMRR
performance for input voltages greater than the positive
supply. The input signal is capable of swinging 0.25V above
the positive supply and to the negative supply with only a
slight degradation of the CMRR performance. The output
operation is rail-to-rail.
The part typically draw less than 1mA supply current per
amplifier while meeting excellent DC accuracy, AC
performance, noise and output drive specifications.
Operation is guaranteed over -40°C to +125°C temperature
range.
• 2mA Typical Supply Current
• 240µV Maximum Offset Voltage
• 6nA Typical Input Bias Current
• Down to 2.4V Single Supply Voltage Range
• Rail-to-rail Input and Output
• -40°C to +125°C Operation
• Pb-Free (RoHS compliant)
Applications
• Low-end Audio
• 4mA to 20mA Current Loops
• Medical Devices
• Sensor Amplifiers
• ADC Buffers
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
• DAC Output Amplifiers
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28236FBZ
28236 FBZ
8 Ld SOIC
MDP0027
ISL28236FBZ-T7*
28236 FBZ
8 Ld SOIC
MDP0027
Coming Soon
ISL28236FUZ
8236Z
8 Ld MSOP
MDP0043
Coming Soon
ISL28236FUZ-T7*
8236Z
Pinouts
OUT_A 1
IN-_A 2
8 Ld MSOP
MDP0043
ISL28236
(8 LD MSOP)
TOP VIEW
ISL28236
(8 LD SOIC)
TOP VIEW
IN+_A 3
V- 4
8 V+
- +
+ -
OUT_A 1
7 OUT_B
IN-_A 2
6 IN-_B
IN+_A 3
5 IN+_B
V- 4
8 V+
7 OUT_B
- +
+ -
6 IN-_B
5 IN+_B
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL28236
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn-on Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/µs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . .
120
8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . .
160
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization.
DESCRIPTION
CONDITIONS
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
DC SPECIFICATIONS
VOS
Input Offset Voltage
ΔV OS
--------------ΔT
Input Offset Voltage vs Temperature
IOS
Input Offset Current
IB
8 Ld SOIC
-240
-250
20
240
250
0.4
µV
µV/°C
-10
-30
2
10
30
nA
TA = -40°C to +125°C
-40
-50
6
40
50
nA
TA = -40°C to +125°C
5
V
Input Bias Current
VCM
Common-Mode Voltage Range
Guaranteed by CMRR
0
CMRR
Common-Mode Rejection Ratio
VCM = 0V to 5V
90
90
115
dB
PSRR
Power Supply Rejection Ratio
V+ = 2.4V to 5.5V
90
90
100
dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4V, RL = 100kΩ to VCM
600
500
1600
V/mV
100
V/mV
VO = 0.5V to 4V, RL = 1kΩ to VCM
VOUT
IS
Maximum Output Voltage Swing
Supply Current
Output low, RL = 100kΩ to VCM
1
10
10
mV
Output low, RL = 1kΩ to VCM
47
70
90
mV
Output high, RL = 100kΩ to VCM
4.99
4.99
4.997
V
Output high, RL = 1kΩ to VCM
4.93
4.91
4.952
V
2
2
2.5
2.6
mA
FN6921.0
June 18, 2009
ISL28236
Electrical Specifications
PARAMETER
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
DESCRIPTION
CONDITIONS
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
IO+
Short-Circuit Output Source Current
RL = 10Ω to VCM
50
40
70
mA
IO-
Short-Circuit Output Sink Current
RL = 10Ω to VCM
50
40
70
mA
VSUPPLY
Supply Operating Range
V+ to V-
2.4
5.5
V
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
AV = 100, RF = 100kΩ, RG = RL = 10kΩ to
VCM
eN
Input Noise Voltage Peak-to-Peak
5
MHz
f = 0.1Hz to 10Hz, RL = 10kΩ to VCM
0.4
µVP-P
Input Noise Voltage Density
fO = 1kHz, RL = 10kΩ to VCM
15
nV/√Hz
iN
Input Noise Current Density
fO = 10kHz, RL = 10kΩ to VCM
0.35
pA/√Hz
CMRR
at 120Hz
Input Common Mode Rejection Ratio
VCM = 0.1VP-P, RL = 10kΩ to VCM
90
dB
PSRR+
at 120Hz
Power Supply Rejection Ratio (V+)
V+, V- = ±1.2V and ±2.5V,
VSOURCE = 0.1VP-P, RL = 10kΩ to VCM
88
dB
PSRRat 120Hz
Power Supply Rejection Ratio (V-)
V+, V- = ±1.2V and ±2.5V
VSOURCE = 0.1VP-P, RL = 10kΩ to VCM
105
dB
Crosstalk at
10kHz
Channel A to Channel B
V+, V- = ±2.5V; AV = 1
VSOURCE = 0.4VP-P, RL = 10kΩ to VCM
140
dB
TRANSIENT RESPONSE
SR
Slew Rate
VOUT = ±1.5V; Rf = 50kΩ, RG = 50kΩ to
VCM
±1.8
V/µs
tr, tf, Large
Signal
Rise Time, 10% to 90%, VOUT
AV = -1, VOUT = 4VP-P, RL = 10kΩ to VCM
2.1
µs
Fall Time, 90% to 10%, VOUT
AV = -1, VOUT = 4VP-P, RL = 10kΩ to VCM
2
µs
tr, tf, Small
Signal
Rise Time, 10% to 90%, VOUT
AV = +1, VOUT = 100mVP-P,
RL = 10kΩ to VCM
60
ns
Fall Time, 90% to 10%, VOUT
AV = +1 VOUT = 100mVP-P,
RL = 10kΩ to VCM
50
ns
Settling Time to 0.01%; 4V Step
VOUT = 4VP-P; RL = 10kΩ to VCM
5.1
µs
ts,
NOTE:
2. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
3
FN6921.0
June 18, 2009
ISL28236
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open
8
60
6
40
4
GAIN (dB)
10
80
VOS (µV)
100
20
0
-20
V+ = 5V
RL = OPEN
Rf = 100k, Rg = 100
AV = +1000
-40
-60
-80
-1
0
1
2
3
VCM (V)
VS = 5V
CL = 4pF
AV = +2
VOUT = 10mVP-P
-10
100
6
1k
10k
NORMALIZED GAIN (dB)
-2
VOUT = 100mV
-3
-4
VOUT = 10mV
-5
-6 VS = 5V
RL = 10k
-7
CL = 4pF
-8 A = +1
V
-9
10k
VOUT = 50mV
VOUT = 1V
100k
1M
10M
100M
RL = 10k
-1
-2
RL = 100k
-3
-4
-5
-6 V+ = 5V
CL = 4pF
-7
AV = +1
-8 V
OUT = 10mVP-P
-9
10k
100k
FIGURE 3. GAIN vs FREQUENCY vs VOUT, RL = 10k
1M
10M
100M
FIGURE 4. GAIN vs FREQUENCY vs RL
70
1
AV = 1001
AV = 1001, Rg = 1k, Rf = 1M
AV = 101, Rg = 1k, Rf = 100k
AV = 101
V+ = 5V
CL = 16.3pF
RL = 10k
VOUT = 10mVP-P
30
AV = 10
AV = 10, Rg = 1k, Rf = 9.09k
10
AV = 1
-10
100
AV = 1, Rg = INF, Rf = 0
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 5. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
4
NORMALIZED GAIN (dB)
0
50
GAIN (dB)
RL = 1k
FREQUENCY (Hz)
FREQUENCY (Hz)
0
100M
0
-1
20
10M
1
0
40
1M
FIGURE 2. GAIN vs FREQUENCY vs FEEDBACK RESISTOR
VALUES Rf/Rg
1
60
100k
FREQUENCY (Hz)
FIGURE 1. INPUT OFFSET VOLTAGE vs COMMON-MODE
INPUT VOLTAGE
NORMALIZED GAIN (dB)
-2
-8
5
Rf = Ri = 1k
0
-6
4
Rf = Ri = 10k
2
-4
-100
Rf = Ri = 100k
-1
-2
-3
-4
VS = 2.4V
-5
-6 RL = 10k
CL = 4pF
-7
AV = +1
-8 V
OUT = 10mVP-P
-9
10k
100k
VS = 5V
1M
10M
100M
FREQUENCY (Hz)
FIGURE 6. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FN6921.0
June 18, 2009
ISL28236
8
7
6
5
4
3
2
1
0
-1
-2
-3 V = 5V
S
-4 R = 10k
-5 L
-6 AV = +1
-7 VOUT = 10mVP-P
-8
10k
100k
120
CL = 37pF
100
CL = 26pF
80
CMRR (dB)
NORMALIZED GAIN (dB)
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)
CL = 16pF
VS = 2.4V
60
40
20
CL = 4pF
0
1M
10M
-20
0.1
100M
VS = 5V
RL = 10k
CL = 4pF
AV = +1
VCM = 100mVP-P
10
1
FREQUENCY (Hz)
FIGURE 7. GAIN vs FREQUENCY vs CL
120
100
100
PSRR (dB)
PSRR (dB)
PSRRV+, V- = ±1.2V
RL = 10k
CL = 4pF
AV = +1
VSOURCE = 100mVP-P
0
-20
0.1
1
10
10k
100k
1M
-20
0.1
10M
V+, V- = ±2.5V
RL = 10k
CL = 4pF
AV = +1
VSOURCE = 100mVP-P
1
10
FREQUENCY (Hz)
160
100
20
0
10
1M
10M
V+, V- = ±2.5V
RL = OPEN TRANSMIT CHANNEL
RL = 10k RECEIVING CHANNEL
CL = 4pF
AV = +1
VSOURCE = 400mVP-P
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 11. CROSSTALK vs FREQUENCY, V+, V- = ±2.5V
5
V+ = 5V
RL = 1k
CL = 16.3pF
AV = +1
INPUT NOISE VOLTAGE (nV√Hz)
CROSSTALK (dB)
120
40
100k
100
140
60
100
1k
10k
FREQUENCY (Hz)
FIGURE 10. PSRR vs FREQUENCY, V+, V- = ±2.5V
FIGURE 9. PSRR vs FREQUENCY, V+, V- = ±1.2V
80
10M
PSRR40
0
1k
1M
60
20
100
100k
80
60
20
10k
PSRR+
PSRR+
40
1k
FIGURE 8. CMRR vs FREQUENCY; V+ = 2.4V AND 5V
120
80
100
FREQUENCY (Hz)
10
1
10
100
1k
FREQUENCY (Hz)
10k
100k
FIGURE 12. INPUT NOISE VOLTAGE DENSITY vs FREQUENCY
FN6921.0
June 18, 2009
ISL28236
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)
10
0.5
0.3
1
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0.1
1
10
100
1k
FREQUENCY (Hz)
10k
-0.5
100k
2.0
SMALL SIGNAL (V)
1.5
1.0
V+, V- = ±2.5V
RL = 1k and 10k
CL = 4pF
AV = 2
VOUT = 4VP-P
0
-0.5
-1.0
-1.5
-2.0
-2.5
0
10
20
30
40
50
TIME (µs)
1
2
3
4
5
6
7
8
9
10
FIGURE 14. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz
2.5
0.5
0
TIME (s)
FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY
LARGE SIGNAL (V)
V+ = 5V
RL = 10k
CL = 16.3pF
Rg = 10, Rf = 100k
AV = 10000
0.4
INPUT NOISE (µV)
INPUT CURRENT NOISE (pA√Hz)
V+ = 5V
RL = 1k
CL = 16.3pF
AV = +1
60
70
80
FIGURE 15. LARGE SIGNAL STEP RESPONSE
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
V+, V- = ±1.2V AND ±2.5V
RL = 1k and 10k
CL = 4pF
AV = 1
VOUT = 100mVP-P
0
0.1
0.2
0.3
0.4 0.5 0.6
TIME (µs)
0.7
0.8
0.9
1.0
FIGURE 16. SMALL SIGNAL STEP RESPONSE
2.6
-1.5
2.4
MAX
VS = ±2.875V
2
VS = ±2.5V
1.8
1.6
VS = ±1.5V
CURRENT (mA)
CURRENT (mA)
2.2
-1.7
-1.9
MEDIAN
-2.1
1.4
-2.3
1.2
1
-40
MIN
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 17. SUPPLY CURRENT vs TEMPERATURE vs
SUPPLY VOLTAGE
6
120
-2.5
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 18. NEGATIVE SUPPLY CURRENT vs
TEMPERATURE, V+, V- = ±2.5V
FN6921.0
June 18, 2009
ISL28236
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)
200
200
150
150
MAX
MAX
100
50
VOS (µV)
VOS (µV)
100
MEDIAN
0
-50
MEDIAN
0
-50
MIN
-100
-150
-40
50
-20
0
20
40
MIN
-100
60
80
100
120
-150
-40
-20
0
20
40
FIGURE 19. VOS vs TEMPERATURE, V+, V- = ±1.2V,
MAX
5
0
0
-5
IBIAS- (nA)
IBIAS+ (nA)
120
10
MAX
5
MEDIAN
-10
-15
-20
-5
-10
MEDIAN
-15
MIN
-20
MIN
-25
-25
-20
0
20
40
60
80
TEMPERATURE (°C)
100
-30
-40
120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 21. IBIAS+ vs TEMPERATURE, V+, V- = ±2.5V
FIGURE 22. IBIAS- vs TEMPERATURE, V+, V- = ±2.5V
30
30
25
25
MAX
MAX
20
20
15
15
IBIAS- (nA)
IBIAS- (nA)
100
15
10
10
5
MEDIAN
0
10
5
MEDIAN
0
MIN
-5
-10
-40
80
FIGURE 20. VOS vs TEMPERATURE, V+, V- = ±2.5V,
15
-30
-40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
MIN
-5
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 23. IBIAS+ vs TEMPERATURE, V+, V- = ±1.2V
7
-10
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 24. IBIAS- vs TEMPERATURE, V+, V- = ±1.2V
FN6921.0
June 18, 2009
ISL28236
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)
12
12
10
10
MAX
8
6
4
2
IOS (nA)
IOS (nA)
4
MEDIAN
0
-2
-4
-6
MIN
-8
-20
0
20
40
60
80
TEMPERATURE (°C)
100
MEDIAN
0
-4
-6
MIN
-8
-10
-40
120
-20
0
100
120
FIGURE 26. IOS vs TEMPERATURE, V+, V- = ±1.2V
170
160
150
MAX
150
140
PSRR (dB)
140
130
120
MEDIAN
130
MAX
120
110
110
MIN
90
-40
-20
0
20
40
MEDIAN
100
100
60
80
100
90
-40
120
MIN
-20
0
TEMPERATURE (°C)
40
60
80
100
120
FIGURE 28. PSRR vs TEMPERATURE, V+, V- = ±1.2V
4060
220
200
3560
MAX
MAX
180
AVOL (V/mV)
3060
2560
2060
MEDIAN
1560
1060
160
140
MEDIAN
120
MIN
100
MIN
80
560
60
-40
20
TEMPERATURE (°C)
FIGURE 27. CMRR vs TEMPERATURE, V+, V- = ±2.5V
AVOL (V/mV)
20
40
60
80
TEMPERATURE (°C)
FIGURE 25. IOS vs TEMPERATURE, V+, V- = ±2.5V
160
CMRR (dB)
2
-2
-10
-40
MAX
8
6
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 29. AVOL vs TEMPERATURE, V+, V- = ±2.5V, VO = -2V
TO +2V, RL = 100k
8
60
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 30. AVOL vs TEMPERATURE, V+, V- = ±2.5V, VO = -2V
TO +2V, RL = 1k
FN6921.0
June 18, 2009
ISL28236
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open (Continued)
70
4.965
65
4.960
MAX
VOUT (mV)
VOUT (V)
MEDIAN
4.950
55
MIN
45
MIN
4.940
40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
35
-40
120
FIGURE 31. VOUT HIGH vs TEMPERATURE, V+, V- = ±2.5V,
RL = 1k
1.75
4.9980
1.55
0
20
40
60
80
TEMPERATURE (°C)
100
120
MAX
MAX
1.35
4.9970
MIN
VOUT (mV)
4.9975
VOUT (V)
-20
FIGURE 32. VOUT LOW vs TEMPERATURE, V+, V- = ±2.5V,
RL = 1k
4.9985
MEDIAN
4.9965
1.15
0.95
0.75
4.9960
4.9955
-40
MEDIAN
50
4.945
4.935
-40
MAX
60
4.955
MIN
MEDIAN
0.55
-20
0
20
40
60
80
TEMPERATURE (°C)
100
0.35
-40
120
FIGURE 33. VOUT HIGH vs TEMPERATURE, V+, V- = ±2.5V,
RL = 100k
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
FIGURE 34. VOUT LOW vs TEMPERATURE, V+, V- = ±2.5V,
RL = 100k
2.9
SLEW RATE RISE (V/uS)
2.7
MAX
2.5
2.3
2.1
1.9
MEDIAN
1.7
MIN
1.5
1.3
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 35. SLEW RATE RISE vs TEMPERATURE,
VOUT = ±1.5V, VP-PV+, V- = ±2.5V, RL = 100k
9
FN6921.0
June 18, 2009
ISL28236
Pin Descriptions
ISL28236
(8 Ld SOIC)
(8 Ld MSOP)
PIN NAME
2 (A)
6 (B)
ININ-_A
IN-_B
FUNCTION
EQUIVALENT CIRCUIT
inverting input
V+
IN-
IN+
VCircuit 1
3 (A)
5 (B)
IN+
IN+_A
IN+_B
4
V-
Non-inverting input
Negative supply
See Circuit 1
V+
CAPACITIVELY
COUPLED
ESD CLAMP
VCircuit 2
1 (A)
7 (B)
OUT
OUT_A
OUT_B
Output
V+
OUT
VCircuit 3
8
V+
Positive supply
Applications Information
Introduction
The ISL28236 is a dual channel Bi-CMOS rail-to-rail input,
output (RRIO) micropower precision operational amplifier.
The part is designed to operate from single supply (2.4V to
5.5V) or dual supply (±1.2V to ±2.75V). The ISL28236 has
an input common mode range that extends 0.25V above the
positive rail and down to the negative supply rail. The output
operation can swing within about 3mV of the supply rails with
a 100kΩ load.
Rail-to-Rail Input
Many rail-to-rail input stages use two differential input pairs,
a long-tail PNP (or PFET) and an NPN (or NFET). Severe
penalties have to be paid for this circuit topology. As the
input signal moves from one supply rail to another, the
operational amplifier switches from one input pair to the
other. Thus causing drastic changes in input offset voltage
and an undesired change in magnitude and polarity of input
offset current.
The ISL28236 solves this problem using an internal
charge-pump to provide a voltage boost to the V+ supply rail
driving the input differential pair. This results in extending the
input common voltage rails to 0.25V beyond the V+ positive
10
See Circuit 2
rail. The input offset voltage exhibits a smooth behavior
throughout the extended common-mode input range. The
input bias current versus the common-mode voltage range
gives an undistorted behavior from the negative rail to 0.25V
higher than the positive rail.
Power Supply Decoupling
The internal charge pump operates at approximately 27MHz
and oscillator ripple doesn’t show up in the 5MHz bandwidth
of the amplifier. Good power supply decoupling with 0.01µF
capacitors at each device power supply pin, is the most
effective way to reduce oscillator ripple at the amplifier
output. Figure 36 shows the electrical connection of these
capacitors using split power supplies. For single supply
operation with V- tied to a ground plane, only a single 0.01µF
capacitor from V+ is needed. When multiple ISL28236
op amps are used on a single PC board, each op amp will
require a 0.01µF decoupling capacitor at each supply pin
Rail-to-Rail Output
The rail-rail output stage uses CMOS devices that typically
swing to within 3mV of the supply rails with a 100kΩ load.
The NMOS sinks current to swing the output in the negative
direction. The PMOS sources current to swing the output in the
positive direction.
FN6921.0
June 18, 2009
ISL28236
Current Limiting
These devices have no internal current-limiting circuitry. If
the output is shorted, it is possible to exceed the Absolute
Maximum Rating for output current or power dissipation,
potentially resulting in the destruction of the device.
Results of Overdriving the Output
Caution should be used when overdriving the output for long
periods of time. Overdriving the output can occur in two ways.
1. The input voltage times the gain of the amplifier exceeds the
supply voltage by a large value or,
2. The output current required is higher than the output stage
can deliver.
These conditions can result in a shift in the Input Offset Voltage
(VOS) (as much as 1µV/hr. of exposure under these
conditions).
IN+ and IN- Input Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. They also contain
back-to-back diodes across the input terminals (see “Pin
Descriptions” on page 10 - Circuit 1). For applications where
the input differential voltage is expected to exceed 0.5V, an
external series resistor must be used to ensure the input
currents never exceed 5mA (Figure 36).
V+
0.01µF
DECOUPLING
CAPACITORS
VIN
VOUT
RIN
RL
+
0.01µF
V-
FIGURE 36. LOCAL POWER SUPPLY DECOUPLING AND
INPUT CURRENT LIMITING
Limitations of the Differential Input Protection
If the input differential voltage is expected to exceed 0.5V, an
external current limiting resistor must be used to ensure the
input current never exceeds 5mA. For non-inverting unity gain
applications, the current limiting can be via a series IN+ resistor,
or via a feedback resistor of appropriate value. For other gain
configurations, the series IN+ resistor is the best choice, unless
the feedback (RF) and gain setting (RG) resistors are both
sufficiently large to limit the input current to 5mA.
Large differential input voltages can arise from several
sources:
1. During open loop (comparator) operation. Used this way,
the IN+ and IN- voltages don’t track, so differentials arise.
2. When the amplifier is disabled but an input signal is still
present. An RL or RG to GND keeps the IN- at GND, while
the varying IN+ signal creates a differential voltage. Mux
11
Amp applications are similar, except that the active
channel VOUT determines the voltage on the IN- terminal.
3. When the slew rate of the input pulse is considerably
faster than the op amp’s slew rate. If the VOUT can’t keep
up with the IN+ signal, a differential voltage results, and
visible distortion occurs on the input and output signals.
To avoid this issue, keep the input slew rate below
1.9V/µs, or use appropriate current limiting resistors.
Large (>2V) differential input voltages can also cause an
increase in disabled ICC.
Using Only One Channel
If the application only requires one channel, the user must
configure the unused channel to prevent it from oscillating.
The unused channel will oscillate if the input and output pins
are floating. This will result in higher than expected supply
currents and possible noise injection into the channel being
used. The proper way to prevent this oscillation is to short
the output to the negative input and ground the positive input
(as shown in Figure 37).
+
FIGURE 37. PREVENTING OSCILLATIONS IN UNUSED
CHANNELS
Power Dissipation
It is possible to exceed the +125°C maximum junction
temperatures under certain load and power supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all applications
to determine if power supply voltages, load conditions, or
package type need to be modified to remain in the safe
operating area. These parameters are related in Equation 1:
T JMAX = T MAX + ( θ JA xPD MAXTOTAL )
(EQ. 1)
where:
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
• PDMAX for each amplifier can be calculated using
Equation 2:
V OUTMAX
PD MAX = V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------R
L
(EQ. 2)
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
• IMAX = Maximum supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
FN6921.0
June 18, 2009
ISL28236
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
12
FN6921.0
June 18, 2009
ISL28236
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
MILLIMETERS
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
0.10 C
N LEADS
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
-
0.08 M C A B
b
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3° ±3°
DETAIL X
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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13
FN6921.0
June 18, 2009
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