PRELIMINARY ICS8520 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8520 is a low skew, high performance 1-to-16 Differential-to-3.3V LVHSTL Fanout Buffer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8520 has 1 clock input pair. The CLK, nCLK pair can accept most standard differential input levels. • 16 differential 3.3V LVHSTL outputs each with the ability to drive 50Ω to ground Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the ICS8520 ideal for interfacing to today’s most advanced microprocessor and static RAMs. • Maximum output frequency up to 500MHz ,&6 • 1 differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Translates single ended input levels to LVHSTL levels with resistor bias nCLK input • Output skew: 50ps (maximum) • Part-to-part skew: 250ps (maximum) • Propagation delay: 1.6ns (maximum) • VOH: 1.2V (maximum) • 40% of VOH ≤ Vcrossover ≤ 60% of VOH • 3.3V core, 1.8V output operating supply voltages • 0°C to 70°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT nCLK VCCO Q15 nQ15 Q14 nQ14 GND Q13 nQ13 Q12 nQ12 VCCO CLK nCLK Q15 nQ15 Q1 nQ1 Q14 nQ14 Q2 nQ2 Q13 nQ13 Q3 nQ3 Q12 nQ12 Q4 nQ4 Q11 nQ11 Q5 nQ5 Q10 nQ10 Q6 nQ6 Q9 nQ9 Q7 nQ7 Q8 nQ8 VCCO Q11 nQ11 Q10 nQ10 GND Q9 nQ9 Q8 nQ8 VCCO VCC 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 ICS8520 CLK VCCO nQ0 Q0 nQ1 Q1 GND nQ2 Q2 nQ3 Q3 VCCO VCCO nQ4 Q4 nQ5 Q5 GND nQ6 Q6 nQ7 Q7 VCCO VCC Q0 nQ0 48-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. ICS8520DY www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001 1 PRELIMINARY ICS8520 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number 1, 11, 14, 24, 25, 35, 38, 48 2, 3 Name Type Description VCCO Power Output supply pins. Connect to 1.8V. Q11, nQ11 Output Differential output pair. LVHSTL interface levels. 4, 5 6, 19, 30, 43 7, 8 Q10, nQ10 Output Differential output pair. LVHSTL interface levels. VEE Power Negative supply pins. Connect to ground. Q9, nQ9 Output Differential output pair. LVHSTL interface levels. 9, 10 Q8, nQ8 Output Differential output pair. LVHSTL interface levels. 12, 13 VCC Power Positive supply pins. Connect to 3.3V. 15, 16 Q7, nQ7 Output Differential output pair. LVHSTL interface levels. 17, 18 Q6, nQ6 Output Differential output pair. LVHSTL interface levels. 20, 21 Q5, nQ5 Output Differential output pair. LVHSTL interface levels. 22, 23 Q4, nQ4 Output Differential output pair. LVHSTL interface levels. 26, 27 Q3, nQ3 Output Differential output pair. LVHSTL interface levels. 28, 29 Q2, nQ2 Output 36 CLK Input 37 nCLK Input 39, 40 Q15, nQ15 Output Differential output pair. LVHSTL interface levels. 41, 42 Q14, nQ14 Output Differential output pair. LVHSTL interface levels. 44, 45 Q13, nQ13 Output Differential output pair. LVHSTL interface levels. 46, 47 Q12, nQ12 Output Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Pulldown Non inver ting differential clock input. Pullup Inver ting differential clock input. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. ICS8520DY www.icst.com/products/hiperclocks.html 2 REV. B JULY 5, 2001 PRELIMINARY ICS8520 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical CLK, nCLK 51 51 Maximum 4 Units pF KΩ KΩ TABLE 3. FUNCTION TABLE Inputs Outputs CLK nCLK Q0 thru Q15 nQ0 thru nQ15 0 1 LOW HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Single ended use requires that one of the differential inputs be biased. The voltage at the biased input sets the switch point for the single ended input. For LVCMOS and LVTTL levels the recommended input bias network is a resistor to VCC, a resistor of equal value to ground and a 0.1µF capacitor from the input to ground. The resulting switch point is approximately VCC/2 ± 300mV. ICS8520DY www.icst.com/products/hiperclocks.html 3 REV. B JULY 5, 2001 PRELIMINARY ICS8520 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCCx Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG 4.6V -0.5V to VCC+0.5 V -0.5V to VCC+0.5V 46°C/W (no air flow) -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol VCC VCCO IEE Parameter Positive Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 1.6 Typical 3.3 1.8 Maximum 3.465 2.0 120 Units V V mA Maximum Units 150 µA 1 µA TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions CLK Minimum Typical VIN = VCC = 3.465V nCLK VIN = VCC = 3.465V CLK VIN = 0V, VCC = 3.465V -1 nCLK VIN = 0V, VCC = 3.465V -150 µA µA VPP Peak-to-Peak Input Voltage 0.15 Common Mode Voltage Range; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. 1.3 V VCC - 0.85 V TABLE 4C. LVHSTL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Output VOH High Voltage; NOTE 1 Output VOL Low Voltage; NOTE 1 Output VOX Crossover Voltage NOTE 1:Outputs terminated with 50Ω to ground. ICS8520DY Minimum Typical Maximum Units 1.0 1.2 V 0 0.4 V 40% x (VOH - VOL) + VOL 60% x (VOH - VOL) + VOL V www.icst.com/products/hiperclocks.html 4 REV. B JULY 5, 2001 PRELIMINARY ICS8520 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol fMAX Parameter Maximum Input Frequency tPD Propagation Delay, Low-to-High; NOTE 1 tsk(o) Output Skew; NOTE 2, 4 Test Conditions Minimum 0 < f ≤ 250MHz 1 Typical Maximum 500 Units MHz 1.6 ns 50 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 250 ps tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps odc Output Duty Cycle 47 53 % All parameters measured at 250MHz unless noted otherwise NOTE 1: Measured from the differential input crossing point to the differential ouput crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ICS8520DY www.icst.com/products/hiperclocks.html 5 REV. B JULY 5, 2001 PRELIMINARY ICS8520 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER FIGURE 1A, 1B, 1C - INPUT CLOCK WAVEFORMS VCC CLK CROSS POINTS VPP VCMR nCLK GND FIGURE 1A - LVDS, HSTL, SSTL DIFFERENTIAL INPUT LEVELS VCC CLK CROSS POINTS VPP VCMR nCLK GND FIGURE 1B - LVPECL DIFFERENTIAL INPUT LEVEL VCC CLK or nCLK GND FIGURE 1C- LVCMOS AND LVTTL SINGLE ENDED INPUT LEVEL ICS8520DY www.icst.com/products/hiperclocks.html 6 REV. B JULY 5, 2001 PRELIMINARY ICS8520 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX TABLE 6. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL MAXIMUM 48 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. 0.50 BASIC e L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 ICS8520DY www.icst.com/products/hiperclocks.html 7 REV. B JULY 5, 2001 PRELIMINARY ICS8520 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVHSTL FANOUT BUFFER ORDERING INFORMATION Part/Order Number ICS8520DY ICS8520DYT Marking ICS8520DY ICS8520DY Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0°C to 70°C 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS8520DY www.icst.com/products/hiperclocks.html 8 REV. B JULY 5, 2001