DS90LV049Q www.ti.com SNLS300D – MAY 2008 – REVISED APRIL 2013 DS90LV049Q Automotive LVDS Dual Line Driver and Receiver Pair Check for Samples: DS90LV049Q FEATURES DESCRIPTION • • • • • The DS90LV049Q is a dual CMOS flow-through differential line driver-receiver pair designed for applications requiring ultra low power dissipation, exceptional noise immunity, and high data throughput. The device is designed to support data rates in excess of 400 Mbps utilizing Low Voltage Differential Signaling (LVDS) technology. 1 2 • • • • • • • AECQ-100 Grade 1 Up to 400 Mbps Switching Rates Flow-Through Pinout Simplifies PCB Layout 50 ps Typical Driver Channel-to-Channel Skew 50 ps Typical Receiver Channel-to-Channel Skew 3.3 V Single Power Supply Design TRI-STATE Output Control Internal Fail-Safe Biasing of Receiver Inputs Low Power Dissipation (70 mW at 3.3 V Static) High Impedance on LVDS Outputs on Power Down Conforms to TIA/EIA-644-A LVDS Standard Available in Low Profile 16 Pin TSSOP Package Connection Diagram The DS90LV049Q drivers accept LVTTL/LVCMOS signals and translate them to LVDS signals. The receivers accept LVDS signals and translate them to 3 V CMOS signals. The LVDS input buffers have internal failsafe biasing that places the outputs to a known H (high) state for floating receiver inputs. In addition, the DS90LV049Q supports a TRI-STATE function for a low idle power state when the device is not in use. The EN and EN inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four gates. Functional Diagram RIN1- 1 16 EN RIN1+ 2 15 ROUT1 RIN1- RIN2+ 3 14 ROUT2 RIN1+ RIN2- 4 13 GND DOUT2- 5 12 VDD RIN2+ DOUT2+ 6 11 DIN2 RIN2- DOUT1+ 7 10 DIN1 DOUT1- 8 9 EN DOUT2DOUT2+ Figure 1. TSSOP Package See Package Number PW0016A DOUT1+ DOUT1- R1 ROUT1 R2 ROUT2 D2 DIN2 D1 DIN1 EN AND EN 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated DS90LV049Q SNLS300D – MAY 2008 – REVISED APRIL 2013 www.ti.com Truth Table EN EN LVDS Out LVCMOS Out L or Open L or Open OFF OFF H L or Open ON ON L or Open H OFF OFF H H OFF OFF These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3 V to +4 V Supply Voltage (VDD) −0.3 V to (VDD + 0.3 V) LVCMOS Input Voltage (DIN) LVDS Input Voltage (RIN+, RIN-) −0.3 V to +3.9 V Enable Input Voltage (EN, EN) −0.3 V to (VDD + 0.3 V) LVCMOS Output Voltage (ROUT) −0.3 V to (VDD + 0.3 V) −0.3 V to +3.9 V LVDS Output Voltage (DOUT+, DOUT-) LVCMOS Output Short Circuit Current (ROUT) 100 mA LVDS Output Short Circuit Current (DOUT+, DOUT−) 24 mA LVDS Output Short Circuit Current Duration (DOUT+, DOUT−) Continuous −65°C to +150°C Storage Temperature Range Lead Temperature Range Soldering (4 sec.) +260°C Maximum Junction Temperature +135°C Maximum Package Power Dissipation @ +25°C PW0016A Package 1146 mW Derate PW0016A Package 10.4 mW/°C above +25°C Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC) θJA 96.0°C/W θJC 30.0°C/W ESD Rating HBM MM CDM (1) (2) (3) (4) (5) (3) ≥ 8 kV (4) ≥ 250 V (5) ≥ 1250 V Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. JESD22-A114C Machine Model, applicable std. JESD22-A115-A Field Induced Charge Device Model, applicable std. JESD22-C101-C Recommended Operating Conditions Min Typ Max Supply Voltage (VDD) +3.0 +3.3 +3.6 V Operating Free Air Temperature (TA) −40 +25 +125 °C 2 Submit Documentation Feedback Units Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LV049Q DS90LV049Q www.ti.com SNLS300D – MAY 2008 – REVISED APRIL 2013 Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. Parameter Test Conditions (1) (2) (3) Pin Min Typ Max Units V LVCMOS Input DC Specifications (Driver Inputs, ENABLE Pins) VIH Input High Voltage 2.0 VDD VIL Input Low Voltage GND 0.8 V IIH Input High Current VIN = VDD IIL Input Low Current VIN = GND VCL Input Clamp Voltage ICL = −18 mA DIN EN EN −10 1 +10 μA +10 μA −10 −0.1 −1.5 −0.6 250 350 450 mV 1 35 |mV| 1.23 1.375 V 1 25 |mV| −5.8 −9.0 mA −5.8 −9.0 mA V LVDS Output DC Specifications (Driver Outputs) | VOD | Differential Output Voltage ΔVOD Change in Magnitude of VOD for Complementary Output States VOS Offset Voltage ΔVOS Change in Magnitude of VOS for Complementary Output States IOS Output Short Circuit Current IOSD Differential Output Short Circuit Current (4) IOFF Power-off Leakage VOUT = 0 V or 3.6 V VDD = 0 V or Open −20 ±1 +20 μA IOZ Output TRI-STATE Current EN = 0 V and EN = VDD VOUT = 0 V or VDD −10 ±1 +10 μA −15 35 mV (4) RL = 100 Ω (Figure 2) ENABLED, DIN = VDD, DOUT+ = 0 V or DIN = GND, DOUT− = 0 V 1.125 DOUT− DOUT+ ENABLED, VOD = 0 V LVDS Input DC Specifications (Receiver Inputs) VTH Differential Input High Threshold VTL Differential Input Low Threshold VCMR Common-Mode Voltage Range IIN VCM = 1.2 V, 0.05 V, 2.35 V VID = 100 mV, VDD=3.3 V VDD=3.6 V VIN =0 V or 2.8 V Input Current -100 RIN+ RIN- VDD=0 V VIN =0 V or 2.8 V or 3.6 V −15 0.05 mV 3 V −12 ±4 +12 μA −10 ±1 +10 μA 2.7 3.3 LVCMOS Output DC Specifications (Receiver Outputs) VOH Output High Voltage IOH = -0.4 mA, VID= 200 mV VOL Output Low Voltage IOL = 2 mA, VID = 200 mV IOZ Output TRI-STATE Current Disabled, VOUT =0 V or VDD ROUT -10 V 0.05 0.25 V ±1 +10 μA 21 35 mA 15 25 mA General DC Specifications (5) IDD Power Supply Current IDDZ TRI-State Supply Current (1) (2) (3) (4) (5) EN = 3.3 V EN = 0 V VDD Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: VTH, VTL, VOD and ΔVOD. All typical values are given for: VDD = +3.3 V, TA = +25°C. The DS90LV049Q drivers are current mode devices and only function within datasheet specifications when a resistive load is applied to their outputs. The typical range of the resistor values is 90 Ω to 110 Ω. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Both driver and receiver inputs are static. All LVDS outputs have 100 Ω load. All LVCMOS outputs are floating. None of the outputs have any lumped capacitive load. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LV049Q 3 DS90LV049Q SNLS300D – MAY 2008 – REVISED APRIL 2013 www.ti.com Switching Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. Parameter Test Conditions (1) (2) Min Typ Max Units LVDS Outputs (Driver Outputs) tPHLD Differential Propagation Delay High to Low 0.7 2 ns tPLHD Differential Propagation Delay Low to High 0.7 2 ns tSKD1 Differential Pulse Skew |tPHLD − tPLHD| (3) (4) 0 0.05 0.4 ns tSKD2 Differential Channel-to-Channel Skew (3) (5) 0 0.05 0.5 ns tSKD3 Differential Part-to-Part Skew 1.0 ns tTLH Rise Time (3) (6) RL = 100 Ω (Figure 3 and Figure 4) 0 (3) (3) 0.2 0.4 1 ns 0.2 tTHL Fall Time 0.4 1 ns tPHZ Disable Time High to Z 1.5 3 ns tPLZ Disable Time Low to Z 1.5 3 ns tPZH Enable Time Z to High 1 3 6 ns tPZL Enable Time Z to Low 1 3 6 fMAX Maximum Operating Frequency RL = 100 Ω (Figure 5 and Figure 6) (7) 250 ns MHz LVCMOS Outputs (Receiver Outputs) tPHL Propagation Delay High to Low 0.5 2 3.5 ns tPLH Propagation Delay Low to High 0.5 2 3.5 ns tSK1 Pulse Skew |tPHL − tPLH| 0 0.05 0.4 ns 0 0.05 0.5 ns 1.0 ns (8) tSK2 Channel-to-Channel Skew tSK3 Part-to-Part Skew tTLH Rise Time (3) (9) (Figure 7 and Figure 8) (10) 0 (3) 0.3 0.9 1.4 ns tTHL Fall Time 0.3 0.75 1.4 ns tPHZ Disable Time High to Z 3 5.6 8 ns tPLZ Disable Time Low to Z 3 5.4 8 ns tPZH Enable Time Z to High 2.5 4.6 7 ns tPZL Enable Time Z to Low 4.6 7 fMAX Maximum Operating Frequency (Figure 9 and Figure 10) 2.5 (11) 250 ns MHz (1) (2) (3) All typical values are given for: VDD = +3.3 V, TA = +25°C. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns. These parameters are ensured by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage, temperature) ranges. (4) tSKD1 or differential pulse skew is defined as |tPHLD − tPLHD|. It is the magnitude difference in the differential propagation delays between the positive going edge and the negative going edge of the same driver channel. (5) tSKD2 or differential channel-to-channel skew is defined as the magnitude difference in the differential propagation delays between two driver channels on the same device. (6) tSKD3 or differential part-to-part skew is defined as |tPLHD Max − tPLHD Min| or |tPHLD Max − tPHLD Min|. It is the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range. (7) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output Criteria: duty cycle = 45%/55%, VOD > 250 mV, all channels switching. (8) tSK1 or pulse skew is defined as |tPHL − tPLH|. It is the magnitude difference in the propagation delays between the positive going edge and the negative going edge of the same receiver channel. (9) tSK2 or channel-to-channel skew is defined as the magnitude difference in the propagation delays between two receiver channels on the same device. (10) tSK3 or part-to-part skew is defined as |tPLH Max − tPLH Min| or |tPHL Max − tPHL Min|. It is the difference between the minimum and maximum specified propagation delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range. (11) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, VID = 200 mV, VCM = 1.2 V . Output Criteria: duty cycle = 45%/55%, VOH > 2.7 V, VOL < 0.25 V, all channels switching. 4 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LV049Q DS90LV049Q www.ti.com SNLS300D – MAY 2008 – REVISED APRIL 2013 Parameter Measurement Information Power Supply VDD EN DOUT+ SMU DIN D SMU 100 : SMU DOUT- Figure 2. Driver VOD and VOS Test Circuit Power Supply Oscilloscope Z0 = 50 : C = 15 pF Distributed Signal Generator VDD EN DOUT+ DIN Transmission Line 50 : D Transmission Line DC Block Transmission Line DC Block 100 : DOUT- 50 : 50 : Z0 = 50 : C = 15 pF Distributed Figure 3. Driver Propagation Delay and Transition Time Test Circuit Figure 4. Driver Propagation Delay and Transition Time Waveforms Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LV049Q 5 DS90LV049Q SNLS300D – MAY 2008 – REVISED APRIL 2013 www.ti.com Parameter Measurement Information (continued) Power Supplies 2.4 V Oscilloscope VDD 1 k: DOUT+ DIN 3.3 V 950 : Transmission Line D 100 : 50 : Transmission Line DOUT- 1 k: EN 950 : 2.4 V Z0 = 50 : C = 15 pF Distributed Signal Generator 50 : Z0 = 50 : C = 15 pF Distributed 50 : Transmission Line Figure 5. Driver TRI-STATE Delay Test Circuit Figure 6. Driver TRI-STATE Delay Waveform Power Supply Z0 = 50 : C = 15 pF Distributed RIN+ ROUT Transmission Line Signal Generator Oscilloscope VDD R 100 : Transmission Line 950 : Transmission Line 50 : Z0 = 50 : C = 15 pF Distributed RINEN Power Supply Figure 7. Receiver Propagation Delay and Transition Time Test Circuit 6 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LV049Q DS90LV049Q www.ti.com SNLS300D – MAY 2008 – REVISED APRIL 2013 Parameter Measurement Information (continued) Figure 8. Receiver Propagation Delay and Transition Time Waveforms Power Supplies VDD 1 k: Oscilloscope 2.5 V RIN+ ROUT 1.4 V 100 : 950 : R Transmission Line 1.0 V 50 : RIN- Z0 = 50 : C = 15 pF Distributed Signal Generator Z0 = 50 : C = 15 pF Distributed EN 50 : Transmission Line Figure 9. Receiver TRI-STATE Delay Test Circuit Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LV049Q 7 DS90LV049Q SNLS300D – MAY 2008 – REVISED APRIL 2013 www.ti.com Parameter Measurement Information (continued) 3V EN 1.5 V 1.5 V 0V 3V 1.5 V 1.5 V 0V EN tPHZ OUT tPZH VOH 0.5 V 50% VDD / 2 tPZL VDD / 2 tPLZ 50% 0.5 V OUT VOL Figure 10. Receiver TRI-STATE Delay Waveforms Typical Application Figure 11. Point-to-Point Application APPLICATION INFORMATION General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (lit #550062-003), AN-805 (SNOA233), AN-808 (SNLA028), AN-903 (SNLA034), AN-916 (SNLA219, AN-971(SNLA165), AN-977 (SNLA166). LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 11. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media is in the range of 100 Ω. A termination resistor of 100 Ω (selected to match the media), and is located as close to the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The TRI-STATE function allows the device outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. 8 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LV049Q DS90LV049Q www.ti.com SNLS300D – MAY 2008 – REVISED APRIL 2013 The DS90LV049Q has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side. POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1 μF and 0.001 μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10 μF (35 V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground. PC BOARD CONSIDERATIONS Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. DIFFERENTIAL TRACES Use controlled impedance traces which match the differential impedance of your transmission medium (that is, cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10 mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than traces 3 mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997 mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number or vias and other discontinuities on the line. Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. TERMINATION Use a termination resistor which best matches the differential impedance or your transmission line. The resistor should be between 90 Ω and 130 Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connecting a single resistor across the pair at the receiver end will suffice. Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10 mm (12 mm MAX). PROBING LVDS TRANSMISSION LINES Always use high impedance (> 100 kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LV049Q 9 DS90LV049Q SNLS300D – MAY 2008 – REVISED APRIL 2013 www.ti.com CABLES AND CONNECTORS, GENERAL COMMENTS When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100 Ω. They should not introduce major impedance discontinuities. Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. FAIL-SAFE FEATURE An LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20 mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating receiver inputs. The DS90LV049Q has two receivers, and if an application requires a single receiver, the unused receiver inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down current sources to set the output to a HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs. External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors should be in the 5 kΩ to 15 kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point should be set to approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry. For more information on failsafe biasing of LVDS interfaces, please refer to AN-1194 (SNLA051). PIN DESCRIPTIONS 10 Pin No. Name 10, 11 DIN Description 6, 7 DOUT+ Non-inverting driver output pins, LVDS levels. 5, 8 DOUT− Inverting driver output pins, LVDS levels. 2, 3 RIN+ Non-inverting receiver input pins, LVDS levels. There is a pull-up current source present. 1, 4 RIN- Inverting receiver input pins, LVDS levels. There is a pull-down current source present. 14, 15 ROUT 9, 16 EN, EN 12 VDD Power supply pin. 13 GND Ground pin. Driver input pins, LVCMOS levels. There is a pull-down current source present. Receiver output pins, LVCMOS levels. Enable and Disable pins. There are pull-down current sources present at both pins. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LV049Q DS90LV049Q www.ti.com SNLS300D – MAY 2008 – REVISED APRIL 2013 Typical Performance Curves Differential Output Voltage vs Load Resistor Power Supply Current vs Frequency 90 VDD = 3.3 V TA = 25o C Power Supply Current - IDD [mA] Differential Output Voltage - VOD [V] 0.45 0.40 0.35 0.30 0.25 40 60 80 100 120 140 160 75 60 VDD = 3.3 V TA = 25o C RL = 100 : CL = 15 pF VID = 0.4 V VIN = 3.3 V All Switching 45 Single Receiver Switching 30 Single Driver Switching 15 0 0.1 Resistor Load - RL [:] 1 10 100 1000 Frequency - f [MHz] Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LV049Q 11 DS90LV049Q SNLS300D – MAY 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D • 12 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LV049Q PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DS90LV049QMT/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 90LV049 QMT DS90LV049QMTX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 90LV049 QMT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS90LV049QMTX/NOPB TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90LV049QMTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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