ICST ICS85211BMI-03LNT Low skew, 1-to-2 differential-to-lvhstl fanout buffer Datasheet

ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85211BI-03 is a low skew, high perforICS
mance 1-to-2 Differential-to-LVHSTL Fanout
HiPerClockS™
Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The CLK, nCLK pair can accept most
standard differential input levels.The ICS85211BI-03 is characterized to operate from a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics
make the ICS85211BI-03 ideal for those clock distribution applications demanding well defined performance
and repeatability.
• Two differential LVHSTL compatible outputs
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Translates any single-ended input signal to
LVHSTL levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.3ns (maximum)
• Output duty cycle: 49% - 51% up to 266.6MHz
• VOH = 1.15V (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
CLK
nCLK
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
VDD
CLK
nCLK
GND
ICS85211BI-03
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
85211BMI-03
www.icst.com/products/hiperclocks.html
1
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
Q0, nQ0
Output
Differential output pair. LVHSTL interface levels.
3, 4
Q1, nQ1
Output
Differential output pair. LVHSTL interface levels.
5
GND
Power
6
nCLK
Input
7
CLK
Input
8
VDD
Power
Power supply ground.
Pullup/
Pulldown
Pullup
Inver ting differential clock input. VDD/2 default when left floating.
Non-inver ting differential clock input.
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
RPULLUP
Input Pullup Resistor
51
KΩ
RPULLDOWN
Input Pulldown Resistor
51
KΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
CLK
nCLK
0
1
Input to Output Mode
Polarity
Q0, Q1
nQ0, nQ1
0
LOW
HIGH
Differential to Differential
Non Inver ting
1
HIGH
LOW
Differential to Differential
Non Inver ting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential
Non Inver ting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential
Non Inver ting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
85211BMI-03
www.icst.com/products/hiperclocks.html
2
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Inputs, VI
-0.5V to VDD + 0.5 V
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
operation of product at these conditions or any conditions be-
Package Thermal Impedance, θJA
112.7°C/W (0 lfpm)
istics is not implied. Exposure to absolute maximum rating
Storage Temperature, TSTG
-65°C to 150°C
conditions for extended periods may affect product reliability.
yond those listed in the DC Characteristics or AC Character-
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Power Supply Voltage
Test Conditions
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
55
mA
Maximum
Units
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C
Symbol
Parameter
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
nCLK
VDD = VIN = 3.465V
150
µA
CLK
VDD = VIN = 3.465V
150
µA
nCLK
VDD = 3.465V, VIN = 0V
-150
CLK
VDD = 3.465V, VIN = 0V
-5
µA
µA
VPP
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
0.5
VCMR
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
1.3
V
VDD - 0.85
V
TABLE 4C. LVHSTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage
0.7
1.15
V
VOL
Output Low Voltage
0
0.4
V
VSWING
Peak-to-Peak Output Voltage Swing
1.15
V
85211BMI-03
0.3
www.icst.com/products/hiperclocks.html
3
0.65
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
Test Conditions
Maximum
Units
700
MHz
tPD
Propagation Delay; NOTE 1
1.3
ns
Output Skew; NOTE 2, 4
30
ps
t sk(pp)
Par t-to-Par t Skew; NOTE 3, 4
250
ps
tR / tF
Output Rise/Fall Time
185
450
ps
47
53
%
20% to 80%
Output Duty Cycle
0.9
Typical
t sk(o)
o dc
IJ 600MHz
Minimum
IJ 266.6MHz
49
51
%
All parameters measured at 600MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85211BMI-03
www.icst.com/products/hiperclocks.html
4
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V±5%
V DD
Qx
V DD
SCOPE
nCLK
LVHSTL
V
Cross Points
PP
V
CMR
CLK
nQx
GND
GND
0V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
PART 1
nQx
Qx
Qy
PART 2
nQy
nQy
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK
80%
80%
CLK
VSW I N G
Clock
Outputs
20%
20%
nQ0, nQ1
tF
tR
Q0, Q1
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0, nQ1
Q0, Q1
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH PERIOD
85211BMI-03
www.icst.com/products/hiperclocks.html
5
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
LVHSTL OUTPUT
All unused LVHSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
85211BMI-03
www.icst.com/products/hiperclocks.html
6
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 2A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
85211BMI-03
www.icst.com/products/hiperclocks.html
7
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of ICS85211BI-03. In
this example, the input is driven by an ICS HiPerClockS
LVHSTL driver. The decoupling capacitors should be physically located near the power pin.
Zo = 50 Ohm
1.8V
-
U1
Zo = 50 Ohm
5
6
7
8
Zo = 50 Ohm
nQ1
Q1
nQ0
Q0
VDD=3.3V
LVHSTL
ICS
HiPerClockS
LVHSTL Driv er
GND
nCLK
CLK
VDD
R6
50
R5
50
4
3
2
1
Zo = 50 Ohm
+
R1
50
R2
50
LVHSTL Input
ICS85211BMI-03
C1
0.1u
Zo = 50 Ohm
Zo = 50 Ohm
+
Unused Output
Can Be Floated
R3
50
R4
50
LVHSTL Input
FIGURE 3. ICS85211BI-03 LVHSTL BUFFER SCHEMATIC EXAMPLE
85211BMI-03
www.icst.com/products/hiperclocks.html
8
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85211BI-03.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85211BI-03 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 55mA = 190.6mW
Power (outputs)MAX = 77.76mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 77.76mW = 155.52mW
Total Power_MAX (3.465V, with all outputs switching) = 190.6mW + 155.52mW = 346.12mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.346W * 103.3°C/W = 120.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85211BMI-03
www.icst.com/products/hiperclocks.html
9
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in Figure 4.
VDD
Q1
VOUT
RL
50Ω
FIGURE 4. LVHSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /R ) * (VDD_MAX - V
L
)
OH_MAX
Pd_L = (VOL_MAX /R ) * (VDD_MAX - VOL_MAX)
L
Pd_H = (1.15V/50Ω) * (3.465V - 1.15V) = 53.24mW
Pd_L = (0.4V (50Ω) * (3.465V - 0.4V) = 24.52mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 77.76mW
85211BMI-03
www.icst.com/products/hiperclocks.html
10
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85211BI-03 is: 472
85211BMI-03
www.icst.com/products/hiperclocks.html
11
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - M SUFFIX
FOR
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
8 LEAD SOIC
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
MINIMUN
N
MAXIMUM
8
A
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
e
4.00
1.27 BASIC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-012
85211BMI-03
www.icst.com/products/hiperclocks.html
12
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS85211BMI-03
211BMI03
8 lead SOIC
tube
-40°C to 85°C
ICS85211BMI-03T
211BMI03
8 lead SOIC
2500 tape & reel
-40°C to 85°C
ICS85211BMI-03LN
211BI03L
8 lead "Lead-Free" SOIC
tube
-40°C to 85°C
ICS85211BMI-03LNT
211BI03L
8 lead "Lead-Free" SOIC
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
85211BMI-03
www.icst.com/products/hiperclocks.html
13
REV. B NOVEMBER 15, 2005
ICS85211BI-03
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table
T4A
B
B
B
T8
T8
B
T8
B
T9
85211BMI-03
Page
3
8
1
7
12
12
12
6
9-10
13
Description of Change
Power Supply Table - changed IDD max. from 50mA to 55mA.
Power Considerations - changed the IDD limit from 50mA to 55mA to reflect
Table 4A. Recalculated Power Dissipation and Junction Temperature formulas.
Features Section - add Lead-Free bullet.
Updated Differential Clock Input Interface section.
Added Lead-Free par t number to Ordering Information table.
Ordering Information Table - corrected Lead-Free P/N from "LF" to "LN".
Ordering Information Table - corrected marking to read 211BMI02".
Added Recommendations for Unused Input and Output Pins.
Corrected Power Considerations, Power Dissipation calculation.
Ordering Information Table - added lead-free note.
www.icst.com/products/hiperclocks.html
14
Date
10/15/03
9/14/04
10/11/04
10/18/04
11/15/05
REV. B NOVEMBER 15, 2005
Similar pages