IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A 1Mb x 36 and 2Mb x 18 36Mb, PIPELINE 'NO WAIT' STATE BUS SRAM SEPTEMBER 2007 FEATURES DESCRIPTION • 100 percent bus utilization The 36 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricated with ISSI's advanced CMOS technology. • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP and 165-ball PBGA packages Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. • Power supply: NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. • Industrial temperature available A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. • Lead-free available FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -200 3.1 5 200 -166 3.5 6 166 Units ns ns MHz Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. Rev. A 09/13/07 1 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A BLOCK DIAGRAM x 36: A [0:19] or x 18: A [0:20] ADDRESS REGISTER A2-A19 or A2-A20 MODE A0-A1 CLK CONTROL LOGIC K CKE WRITE ADDRESS REGISTER 1Mx36; 2Mx18 MEMORY ARRAY BURST ADDRESS COUNTER A'0-A'1 WRITE ADDRESS REGISTER K DATA-IN REGISTER K DATA-IN REGISTER CE CE2 CE2 ADV WE BWŸX } CONTROL REGISTER K CONTROL LOGIC (X=a,b,c,d or a,b) OUTPUT REGISTER BUFFER OE ZZ 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A PIN CONFIGURATION — 1M X 36, 165-Ball PBGA (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWc BWb CE2 CKE ADV A A NC B NC A CE2 BWd BWa CLK WE OE A A NC C DQPc NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPb D DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb E DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb F DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb G DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb H NC NC NC VDD VSS VSS VSS VDD NC NC ZZ J DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa K DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa L DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa M DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa N DQPd NC VDDQ VSS NC NC NC VSS VDDQ NC DQPa P NC NC A A NC A1* NC A A A NC R MODE A A A NC A0* NC A A A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. (Under Evaluation) PIN DESCRIPTIONS Symbol Pin Name MODE Burst Sequence Selection A Address Inputs VDD 3.3V/2.5V Power Supply A0, A1 Synchronous Burst Address Inputs NC No Connect ADV Synchronous Burst Address Advance/ Load DQx Data Inputs/Outputs DQPx Parity Data I/O WE Synchronous Read/Write Control Input VDDQ Isolated output Power Supply 3.3V/2.5V CLK Synchronous Clock VSS Ground CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a-d) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 3 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A 165-PIN PBGA PACKAGE CONFIGURATION 2M x 18 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A BWb NC CE2 CKE ADV A NC A NC NC VDDQ BWa Vss CLK Vss WE Vss VDDQ NC NC DQPa D NC DQb VDDQ VDD Vss Vss Vss OE Vss VDD A C NC Vss A A A B CE CE2 VDDQ NC DQa E NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa F NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa G NC DQb VDDQ Vss NC NC NC ZZ J DQb NC VDDQ VDD Vss Vss VDD VDD DQa NC Vss Vss NC NC Vss Vss VDDQ H VDD VDD Vss Vss VDD VDDQ DQa NC K DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa L DQb NC VDDQ VDD Vss Vss VDD VDDQ DQa M DQb NC VDDQ VDD Vss Vss Vss NC NC Vss VDD VDDQ DQa NC N DQPb NC Vss NC NC NC NC NC NC NC Vss A NC P VDDQ A A NC R MODE A A A NC A A A1* A0* NC A VDDQ A NC A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. (Under Evaluation) PIN DESCRIPTIONS Symbol Pin Name MODE Burst Sequence Selection A Address Inputs VDD 3.3V/2.5V Power Supply A0, A1 Synchronous Burst Address Inputs NC No Connect ADV Synchronous Burst Address Advance/ Load DQx Data Inputs/Outputs DQPx Parity Data I/O WE Synchronous Read/Write Control Input VDDQ Isolated output Power Supply 3.3V/2.5V CLK Synchronous Clock VSS Ground CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable 4 BWx (x=a,b) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A PIN CONFIGURATION DQa DQb DQa DQb VDDQ VDDQ Vss DQa NC Vss Vss DQb DQa DQb DQa DQa Vss DQPb NC VDDQ VDDQ DQa DQa DQPa NC NC NC Vss A ADV A OE CKE CLK WE CE2 VDD Vss BWa NC BWb NC CE2 CE A A A NC NC VDDQ Vss NC DQPa DQa DQa Vss VDDQ DQa DQa Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa NC NC Vss VDDQ NC NC NC A A DQb VDD VDD A DQb DQb Vss NC VDD ZZ A DQb A VDDQ A Vss VDDQ NC A A DQb VDD Vss DQb Vss DQb NC NC NC NC MODE DQd DQd DQPd DQb Vss A1 A0 VDDQ DQb DQb VDDQ A DQd DQd Vss Vss NC A DQd VDDQ NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A Vss DQd DQb NC A VDDQ DQb MODE DQd DQPb A A DQd A NC Vss A DQc VDD VDD A DQc A VDDQ NC A A Vss VDD DQc Vss DQc NC NC DQc DQc A1 A0 Vss A VDDQ A DQc A DQc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A DQPc A A A A A ADV A OE CKE CLK WE CE2 VDD Vss BWa BWc BWb BWd CE2 CE A A 100-Pin TQFP 2M x 18 1M x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs CLK Synchronous Clock ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable WE Write Enable CKE Clock Enable Vss Ground for Core NC Not Connected Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 CE, CE2, CE2 Synchronous Chip Enable OE Output Enable DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data I/O MODE Burst Sequence Selection VDD +3.3V/2.5V Power Supply VSS Ground for output Buffer VDDQ Isolated Output Buffer Supply: +3.3V/2.5V ZZ Snooze Enable 5 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A STATE DIAGRAM READ READ READ BURST WRITE BEGIN READ DS READ WRITE DESELECT BURST BURST READ BEGIN WRITE DS BURST DS BURST DS DS WRITE BURST WRITE READ WRITE WRITE BURST SYNCHRONOUS TRUTH TABLE(1) Operation Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read Continue Burst Read NOP/Dummy Read Dummy Read Begin Burst Write Continue Burst Write NOP/Write Abort Write Abort Ignore Clock Notes: Address Used CE CE2 CE CE2 ADV WE BW BWx OE CKE CLK N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address H X X X L X L X L X L X X X L X X H X H X H X H X X X X H X L X L X L X L X X L L L H L H L H L H L H X X X X X H X H X L X L X X X X X X X X X X L L H H X X X X X L L H H X X X X X L L L L L L L L L L L L H ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1. 2. 3. 4. "X" means don't care. The rising edge of clock is symbolized by ↑ A continue deselect cycle can only be entered if a deselect cycle is executed first. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A ASYNCHRONOUS TRUTH TABLE(1) Operation ZZ OE I/O STATUS Sleep Mode H L L L L X L H X X High-Z DQ High-Z Din, High-Z High-Z Read Write Deselected Notes: 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE BW BWa BW BWb H L L L L X L H L H X H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. WRITE TRUTH TABLE (x36) Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE BW BWa BW BWb BW BWc BW BWd H L L L L L L X L H H H L H X H L H H L H X H H L H L H X H H H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC) External Address A1 A0 1st Burst Address A1 A0 2nd Burst Address A1 A0 3rd Burst Address A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 7 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A LINEAR BURST ADDRESS TABLE (MODE = VSS) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TSTG PD IOUT VIN, VOUT VIN Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to VSS for I/O Pins Voltage Relative to VSS for for Address and Control Inputs Value –65 to +150 1.6 100 –0.5 to VDDQ + 0.3 –0.3 to 4.6 Unit °C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE (IS61NLPx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C VDD 3.3V ± 5% 3.3V ± 5% VDDQ 3.3V / 2.5V ± 5% 3.3V / 2.5V ± 5% VDD 2.5V ± 5% 2.5V ± 5% VDDQ 2.5V ± 5% 2.5V ± 5% OPERATING RANGE (IS61NVPx) Range Commercial Industrial 8 Ambient Temperature 0°C to +70°C -40°C to +85°C Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 3.3V 2.5V Symbol Parameter Test Conditions Min. Max. Min. Max. Unit VOH Output HIGH Voltage IOH = –4.0 mA (3.3V) IOH = –1.0 mA (2.5V) 2.4 — 2.0 — V VOL Output LOW Voltage IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V) — 0.4 — 0.4 V VIH Input HIGH Voltage 2.0 VDD + 0.3 1.7 VDD + 0.3 V VIL Input LOW Voltage –0.3 0.8 –0.3 0.7 V ILI Input Leakage Current VSS ≤ VIN ≤ VDD(1) –5 5 –5 5 µA ILO Output Leakage Current VSS ≤ VOUT ≤ VDDQ, OE = VIH –5 5 –5 5 µA -200 MAX x18 x36 -166 MAX x18 x36 Unit 450 475 400 400 450 450 340 mA POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions ICC Device Selected, OE = VIH, ZZ ≤ VIL, All Inputs ≤ 0.2V or ≥ VDD – 0.2V, Cycle Time ≥ tKC min. Com. Ind. typ.(2) 450 475 AC Operating Supply Current Temp. range 390 ISB Standby Current TTL Input Device Deselected, VDD = Max., All Inputs ≤ VIL or ≥ VIH, ZZ ≤ VIL, f = Max. Com. Ind. 260 270 260 270 250 260 250 260 mA ISBI Standby Current CMOS Input Device Deselected, VDD = Max., VIN ≤ VSS + 0.2V or ≥VDD – 0.2V f=0 Com. Ind. typ.(2) 105 110 105 110 105 110 105 110 30 mA 30 Note: 1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100µA maximum leakage current when tied to ≤ VSS + 0.2V or ≥ VDD – 0.2V. 2. Typical values are measured at Vcc = 3.3V, TA = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 9 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 Ω +3.3V Zo= 50Ω OUTPUT OUTPUT 5 pF Including jig and scope 50Ω 351 Ω 1.5V Figure 1 10 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 1,538 Ω 1.25V Figure 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 Figure 4 11 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -200 Min. Max. -166 Min. Max. Symbol Parameter fmax Clock Frequency — 200 — 166 MHz tKC Cycle Time 5 — 6 — ns tKH Clock High Time 2 — 2.5 — ns tKL Clock Low Time 2 — 2.5 — ns Clock Access Time — 3.1 — 3.5 ns Clock High to Output Invalid 1.5 — 1.5 — ns tKQLZ Clock High to Output Low-Z 1 — 1 — ns tKQHZ(2,3) Clock High to Output High-Z — 3.0 — 3.4 ns tOEQ tKQ tKQX (2) (2,3) Unit Output Enable to Output Valid — 3.1 — 3.5 ns (2,3) Output Enable to Output Low-Z 0 — 0 — ns (2,3) tOEHZ Output Disable to Output High-Z — 3.0 — 3.4 ns tAS Address Setup Time 1.4 — 1.5 — ns tWS Read/Write Setup Time 1.4 — 1.5 — ns tCES Chip Enable Setup Time 1.4 — 1.5 — ns tSE Clock Enable Setup Time 1.4 — 1.5 — ns tADVS Address Advance Setup Time 1.4 — 1.5 — ns tDS Data Setup Time 1.4 — 1.5 — ns tAH Address Hold Time 0.4 — 0.5 — ns tHE Clock Enable Hold Time 0.4 — 0.5 — ns tWH Write Hold Time 0.4 — 0.5 — ns tCEH Chip Enable Hold Time 0.4 — 0.5 — ns tADVH Address Advance Hold Time 0.4 — 0.5 — ns tDH Data Hold Time 0.4 — 0.5 — ns tPDS ZZ High to Power Down — 2 — 2 cyc tPUS ZZ Low to Power Down — 2 — 2 cyc tOELZ Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min. ISB2 Current during SLEEP MODE tPDS ZZ active to input ignored 2 cycle tPUS ZZ inactive to input sampled 2 cycle tZZI ZZ active to SLEEP current 2 cycle tRZZI ZZ inactive to exit SLEEP current 0 ns ZZ ≥ VIH Max. Unit 75 mA SLEEP MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 13 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A READ CYCLE TIMING tKH tKL CLK tKC tADVS tADVH ADV tAS tAH Address A1 A3 A2 tWS tWH WRITE tSE tHE CKE tCES tCEH CE OE tOEQ tOEHZ tKQX tKQ tKQHZ tOEHZ Data Out Q1-1 Q2-1 Q2-2 Q2-3 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 14 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A WRITE CYCLE TIMING tKH tKL CLK tKC ADV Address A1 A3 A2 WRITE tSE tHE CKE CE OE tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 tDH D3-2 D3-3 D3-4 tOEHZ Data Out Q0-3 Q0-4 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 Don't Care Undefined 15 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A SINGLE READ/WRITE CYCLE TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 Q1 Q3 A5 A6 A7 A8 A9 WRITE CE ADV OE tOEQ tOELZ Data Out Q4 Q6 Q7 tDS tDH Data In D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 16 D5 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A CKE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 WRITE CE ADV OE tKQ tKQHZ tKQLZ Data Out Q1 Q3 Q4 tDS tDH Data In D2 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 Don't Care Undefined 17 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A CE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 WRITE CE ADV OE tOEQ tKQHZ tKQ tKQLZ tOELZ Data Out Q1 Q2 Q4 tDS tDH Data In D3 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 18 D5 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A ORDERING INFORMATION (3.3V core/2.5V- 3.3V I/O) Commercial Range: 0°C to +70°C Configuration Access Time Order Part Number Package IS61NLP102436A-166TQ IS61NLP102436A-166TQL 100 TQFP 100 TQFP, Lead-free IS61NLP102436A-166B3 165 PBGA IS61NLP204818A-166TQ IS61NLP204818A-166TQL IS61NLP204818A-166B3 100 TQFP 100 TQFP, Lead-free 165 PBGA Order Part Number Package 166 IS61NLP102436A-166TQI IS61NLP102436A-166TQLI IS61NLP102436A-166B3I 100 TQFP 100 TQFP, Lead-free 165 PBGA 166 IS61NLP204818A-166TQI IS61NLP204818A-166TQLI IS61NLP204818A-166B3I 100 TQFP 100 TQFP, Lead-free 165 PBGA 1Mx36 166 2Mx18 166 Industrial Range: -40°C to +85°C Configuration Access Time 1Mx36 2Mx18 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 19 IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A ORDERING INFORMATION (2.5V core/2.5V I/O) Commercial Range: 0°C to +70°C Configuration Access Time Order Part Number Package 166 IS61NVP102436A-166TQ IS61NVP102436A-166TQL IS61NVP102436A-166B3 100 TQFP 100 TQFP, Lead-free 165 PBGA 166 IS61NVP204818A-166TQ IS61NVP204818A-166TQL 100 TQFP 100 TQFP, Lead-free IS61NVP204818A-166B3 165 PBGA 1Mx36 2Mx18 Industrial Range: -40°C to +85°C Configuration Access Time Order Part Number Package 166 IS61NVP102436A-166TQI IS61NVP102436A-166TQLI IS61NVP102436A-166B3I 100 TQFP 100 TQFP, Lead-free 165 PBGA 166 IS61NVP204818A-166TQI IS61NVP204818A-166B3I 100 TQFP 165 PBGA 1Mx36 2Mx18 20 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 09/13/07 PACKAGING INFORMATION Ball Grid Array Package Code: B (165-pin) BOTTOM VIEW TOP VIEW A1 CORNER 1 2 3 4 A1 CORNER φ b (165X) 5 6 7 8 9 10 11 10 11 9 8 7 6 5 4 3 2 1 A A B B C C D D E E e F F G G D D1 H H J J K K L L M M N N P P R R e E1 E A2 A A1 BGA - 13mm x 15mm MILLIMETERS Sym. Min. N0. Leads Nom. Max. Notes: 1. Controlling dimensions are in millimeters. INCHES Min. 165 Nom. Max. 165 A — — 1.20 — A1 0.25 0.33 0.40 0.010 — 0.047 0.013 0.016 A2 — 0.79 — — 0.031 — D 14.90 15.00 15.10 0.587 0.591 0.594 D1 13.90 14.00 14.10 0.547 0.551 0.555 E 12.90 13.00 13.10 0.508 0.512 0.516 E1 9.90 10.00 10.10 0.390 0.394 0.398 e — 1.00 — — 0.039 — b 0.40 0.45 0.50 0.016 0.018 0.020 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 06/11/03 PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ D D1 E E1 N L1 L C 1 e SEATING PLANE A2 A b A1 Millimeters Min Max Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max Symbol Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. o o C 0 7 0o 7o 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03 Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters.