MC100EP16VT 3.3V / 5VECL Differential Receiver/Driver with Variable Output Swing and Internal Input Termination http://onsemi.com Description • • • • 8 8 1 SOIC−8 D SUFFIX CASE 751 220 ps Propagation Delay Maximum Frequency > 4 GHz Typical (See Graph) The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State 50 W Internal Termination Resistor Pb−Free Packages are Available 1 KEP63 ALYW G 8 8 1 TSSOP−8 DT SUFFIX CASE 948R DFN8 MN SUFFIX CASE 506AA Features • • • • MARKING DIAGRAMS* 1 KP63 ALYWG G 3I MG G The MC100EP16VT is a differential receiver functionally equivalent to the 100EP16 with input pins controlling the amplitude of the outputs (pin 1) and providing an internal termination network (pin 4). The VCTRL input pin controls the output amplitude of the EP16VT and is referenced to VCC. (See Figure 4.) The operational range of the VCTRL input is from VBB (a supply at VCC−1.42 V, maximum output amplitude) to VCC (minimum output amplitude). VBB is an externally supplied voltage equal to VCC−1.42 V (See Figures 2 and Figure 3). A variable resistor between VCC and VBB, with the wiper driving VCTRL, can control the output amplitude. Typical application circuits and a VCTRL Voltage vs. Output Amplitude graph are described in this data sheet. When left open, the VCTRL pin will be internally pulled down to VEE and operate as a standard EP16, with 100% output amplitude. The VTT input pin offers an internal termination network for a 50 W line impedance environment, shown in Figure 1. For further reference, see Application Note AND8020, Termination of ECL Logic Devices. Input considerations are required for D and D under no signal conditions to prevent instability. Special considerations are required for differential inputs under No Signal conditions to prevent instability. A L Y W M G 1 4 = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 3 1 Publication Order Number: MC100EP16VT/D MC100EP16VT VCTRL D 1 8 2 7 Table 1. PIN DESCRIPTION VCC Q 50 W D 3 6 Q 50 W VTT 4 5 VEE PIN FUNCTION D, D ECL Data Inputs Q, Q ECL Data Outputs VCTRL* Output Swing Control VTT Termination Supply VCC Positive Supply VEE Negative Supply EP Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. Figure 1. 8−Lead Pinout (Top View) and Logic Diagram * Pin will default LOW when left open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC−8 TSSOP−8 DFN8 Flammability Rating Value Oxygen Index: 28 to 34 Transistor Count > 4 kV > 200 V > 2 kV Pb Pkg Pb−Free Pkg Level 1 Level 1 Level 1 Level 1 Level 3 Level 1 UL 94 V−0 @ 0.125 in 140 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC100EP16VT Table 3. MAXIMUM RATINGS Rating Unit VCC Symbol PECL Mode Power Supply Parameter VEE = 0 V Condition 1 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 8 SOIC 8 SOIC 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 8 SOIC 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 8 TSSOP 8 TSSOP 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 8 TSSOP 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free Condition 2 VI VCC VI VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2) −40°C Symbol Characteristic IEE Power Supply Current VOH Output HIGH Voltage (Max Swing) (Note 3) VCC VCTRL VEE VOL Output LOW Voltage (Max Swing) (Note 3) VCTRL VBB 85°C Min Typ Max Min Typ Max Min Typ Max Unit 30 36 42 31 38 44 32 40 48 mA 2405 2155 2405 2155 2405 mV 1605 1355 1605 1355 2155 mV 1355 VCC VCTRL > VBB VCTRL = VCC (Min Swing) 25°C 1490 See Fig.2 2105 2230 1520 See Fig.2 2355 2095 2220 1520 1605 See Fig.2 2345 2065 2190 2315 VIH D, D Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL D, D Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV VCTRL Input Voltage (VCTRL) VEE VCC VEE VCC VEE VCC mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 2.0 2.9 2.0 2.9 2.0 2.9 V IIH Input HIGH Current (VTT Open) 150 mA IIL Input LOW Current (VTT Open) 150 −150 150 −150 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 3. All loading with 50 W to VCC − 2.0 V. VOH does not change with VCTRL. VOL changes with VCTRL. VCTRL is referenced to VCC. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 MC100EP16VT Table 5. DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5) −40°C Symbol Characteristic IEE Power Supply Current VOH Output HIGH Voltage (Note 6) VCC > VCTRL > VEE VOL Output LOW Voltage (Max Swing) (Note 6) VCTRL VBB 85°C Typ Max Min Typ Max Min Typ Max Unit 30 36 42 31 38 44 32 40 48 mA 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV 3055 3190 3305 3055 3220 3305 3055 3220 3305 mV VCC VCTRL > VBB VCTRL = VCC (Min Swing) 25°C Min See Fig.2 3805 3930 See Fig.2 4055 3795 3920 See Fig.2 4045 3765 3890 4015 VIH D, D Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV VIL D, D Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV VCTRL Input Voltage (VCTRL) VEE VCC VEE VCC VEE VCC mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) 2.0 4.6 2.0 4.6 2.0 4.6 V IIH Input HIGH Current (VTT Open) 150 mA IIL Input LOW Current (VTT Open) 150 −150 150 −150 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 6. All loading with 50 W to VCC − 2.0 V. VOH does not change with VCTRL. VOL changes with VCTRL. VCTRL is referenced to VCC. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC100EP16VT Table 6. DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 8) −40°C Symbol Characteristic IEE Power Supply Current VOH Output HIGH Voltage (Note 9) VCC > VCTRL > VEE VOL Output LOW Voltage (Max Swing) (Note 9) VCTRL VBB 85°C Typ Max Min Typ Max Min Typ Max Unit 30 36 42 31 38 44 32 40 48 mA −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV −1945 −1810 −1695 −1945 −1780 −1695 −1945 −1780 −1695 mV VCC VCTRL > VBB VCTRL = VCC (Min Swing) 25°C Min See Fig.2 −1195 See Fig.2 −1070 −945 −1205 −1080 See Fig.2 −955 −1235 −1110 −985 VIH D, D Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL D, D Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV VCTRL Input Voltage (VCTRL) VEE VCC VEE VCC VEE VCC mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) −0.4 V IIH Input HIGH Current (VTT Open) 150 mA IIL Input LOW Current (VTT Open) VEE+2.0 −0.4 VEE+2.0 −0.4 150 VEE+2.0 150 −150 −150 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. 9. All loading with 50 W to VCC − 2.0 V. VOH does not change with VCTRL. VOL changes with VCTRL. VCTRL is referenced to VCC. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 11) −40°C Symbol Characteristic Min fmax Maximum Toggle Frequency (See Figure 8. Fmax/JITTER) tPLH, tPHL Propagation Delay to Output Differential Max Swing Min Swing tSKEW Typ 25°C Max Min >4 Max Min >4 Typ Max >4 Unit GHz ps 300 250 350 300 Duty Cycle Skew (Note 12) 5.0 tJITTER Cycle−to−Cycle Jitter (See Figure 8. Fmax/JITTER) VPP Input Voltage Swing (Differential Configuration) (Note 13) tr, tf Output Rise/Fall Times (20% − 80%) Max Swing Q Min Swing 250 200 Typ 85°C 250 200 300 250 350 300 20 5.0 0.2 <1 150 800 1200 70 30 120 80 170 130 250 200 300 250 350 300 20 5.0 20 ps 0.2 <1 0.2 <1 ps 150 800 1200 150 800 1200 mV 80 20 130 70 180 120 100 20 150 70 200 120 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. 12. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 13. VPP(min) is minimum input swing for which AC parameters are guaranteed. http://onsemi.com 5 MC100EP16VT 100 90 OUTPUT SWING (%) 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 VOLTS (V) 1.42 VBB 1.5 2.0 VPK−PK Figure 2. VCC − VCTRL (pin #1) VOH Min Swing Max Swing VOL 0.0 0.5 1.0 VOLTS (V) Figure 3. VCC − VCTRL http://onsemi.com 6 1.42 VBB 1.5 2.0 MC100EP16VT VCTRL + VCTRL D 1 8 2 7 Q* 6 Q* 5 VEE VCC 50 W D 3 50 W VTT 4 Figure 4. Voltage Source Implementation, VCTRL Pin 1 VCC VCTRL VBB D 1 8 2 7 Q* 6 Q* 5 VEE VCC 50 W D 3 50 W VEE VTT 4 Figure 5. Alternative Implementations, VCTRL Pin 1 VCTRL + VCTRL D 1 8 2 7 Q* 6 Q* 5 VEE VCC 50 W D 3 50 W VCC−2 V VTT 4 Figure 6. Standard Termination Method, VTT Pin 4 http://onsemi.com 7 MC100EP16VT VCTRL + VCTRL D 1 8 2 7 Q* 6 Q* 5 VEE VCC 50 W D 3 50 W VCC RT 5.0 V 112 W 3.3 V 46 W VTT 4 RT VEE 1000 10 900 9 VOUTpp (mV) 800 2.00 V Below VCC 700 8 7 1.25 V Below VCC 600 6 1.00 V Below VCC 500 5 0.75 V Below VCC 400 4 300 3 200 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 0.25 V Below VCC 100 0 (JITTER) 0 500 1000 1500 2000 2500 3000 3500 2 1 4000 FREQUENCY (MHz) Figure 8. Fmax/Jitter Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 9. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 8 JITTEROUT ps (RMS) Figure 7. Alternate “Y” Termination Method, VTT Pin 4 É É É MC100EP16VT ORDERING INFORMATION Package Shipping† SOIC−8 98 Units / Rail MC100EP16VTDG SOIC−8 (Pb−Free) 98 Units / Rail MC100EP16VTDR2 SOIC−8 2500 / Tape & Reel MC100EP16VTDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC100EP16VTDT TSSOP−8 100 Units / Rail MC100EP16VTDTG TSSOP−8 (Pb−Free) 100 Units / Rail MC100EP16VTDTR2 TSSOP−8 2500 / Tape & Reel MC100EP16VTDTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC100EP16VTMNR4 DFN8 1000 / Tape & Reel DFN8 (Pb−Free) 1000 / Tape & Reel Device MC100EP16VTD MC100EP16VTMNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 9 MC100EP16VT PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 1 0.25 (0.010) M Y M 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− H 0.10 (0.004) D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC100EP16VT PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U 0.10 (0.004) S 2X L/2 L 8 5 1 PIN 1 IDENT 0.15 (0.006) T U K REF S M T U V S 0.25 (0.010) B −U− 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S M A −V− F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E http://onsemi.com 11 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC100EP16VT PACKAGE DIMENSIONS DFN8 CASE 506AA−01 ISSUE D D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B PIN ONE REFERENCE 2X 0.10 C 2X 0.10 C ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ TOP VIEW 0.08 C SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 −−− 0.25 0.35 A 0.10 C 8X DIM A A1 A3 b D D2 E E2 e K L E (A3) SIDE VIEW A1 C D2 e e/2 4 1 8X L E2 K 8 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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