FEDL610406-05 Issue Date: May. 23, 2014 ML610404/ML610405/ML610406 8-bit Microcontroller with a Built-in LCD driver GENERAL DESCRIPTION ML610404/ML610405/ML610406 is a high-performance 8-bit CMOS microcontroller into which peripheral circuits, such as synchronous serial port, UART, melody driver, RC oscillation type A/D converter, and LCD driver, are incorporated around LAPIS Semiconductor-original 8-bit CPU nX-U8/100. ML610404/ML610405/ML610406 operates in both high/low-speed mode and power-saving mode, it is most suitable for battery operated products. The short TAT are entertained by offering MTP version ML610Q407/ML610Q408/ML610Q409. ML610404P/ ML610405P/ML610406P support industrial temperature -40°C to +85°C, are added to the product lineup. FEATURES • CPU − 8-bit RISC CPU (CPU name: nX-U8/100) − Instruction system: 16-bit instructions − Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on − Minimum instruction execution time 30.5 µs (@32.768 kHz system clock) 2µs (@500kHz system clock) 0.5µs(@2MHz system clock) • Internal memory − ML610404/5/6 : Internal 8KByte Mask ROM (4K×16 bits) (including unusable 128 Byte TEST area) Internal 256Byte Data RAM (256×8 bits) • Interrupt controller − 1 non-maskable interrupt sources Internal source: 1 (Watch dog timer) − 27 maskable interrupt sources Internal sources: 14 (Synchronous serial port 0, Synchronous serial port 1, Timer0, Timer1, Timer2, Timer3, UART0, Melody0, RC Oscillation type A/D converter, PWM0, TBC128Hz, TBC32Hz, TBC16Hz, TBC2Hz) External sources: 13 (P00, P01, P02, P03, P04, P50, P51, P52, P53, P54, P55, P56, P57) (One interrupt request is generated from P50 to P57 interrupt sources.) • Time base counter − Low-speed time base counter ×1 channel Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx. 0.48ppm) − High-speed time base counter ×1 channel • Watchdog timer − Non-maskable interrupt and reset − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s) • Timers − 8 bits × 4 channels [also available is 16-bit configuration (using Timers 0 and 1, or Timers 2 and 3) x 2 channels] − Clock frequency measurement function mode (16-bit configuration using Timers 2 and 3 x 1 channel only) 1/30 FEDL610406-05 ML610404/ML610405/ML610406 • Capture − Time base capture × 2 channels (4096 Hz to 32 Hz) • PWM − Resolution 16 bits × 1 channel • Synchronous serial port − Master/slave selectable × 2 channel − LSB first/MSB first selectable − 8-bit length/16-bit length selectable • UART − TXD/RXD × 1 channel − Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits − Positive logic/negative logic selectable − Built-in baud rate generator • Melody driver − Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz) − Tone length: 63 types − Tempo: 15 types − Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) • RC oscillation type A/D converter − 16-bit counter − Time division × 2 channels • General-purpose ports − Input-only port × 5 channels (including secondary functions) − Output-only port ML610404: × 12 channels (including secondary functions) ML610405: × 8 channels (including secondary functions) ML610406: × 4 channels (including secondary functions) − Input/output port × 22 channels (including secondary functions) • LCD driver Number of segments ML610404: Up to 105 dots (select among 21 segments x 5 commons, 22 segments x 4 commons, 23 segments x 3 commons, and 24segments x 2 commons) ML610405: Up to 125 dots (select among 25 segments x 5 commons, 26 segments x 4 commons, 27 segments x 3 commons, and 28 segments x 2 commons) ML610406: Up to 145 dots (select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments x 3 commons, and 32 segments x 2 commons) − 1/1 to 1/5 duty − 1/2, 1/3 bias (built-in bias generation circuit) − Frame frequency selecable: approx. 64Hz, 73Hz, 85Hz, and 102Hz − Bias voltage multiplying clock selectable (8 types) − LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable − Programmable display allocation function • Reset − Reset through the RESET_N pin − Power-on reset generation when powered on − Reset when oscillation stop of the low-speed clock is detected (Cancellation by a mask option is possible) − Reset by the watchdog timer (WDT) overflow 2/30 FEDL610406-05 ML610404/ML610405/ML610406 • Clock − Low-speed clock (Operation of this LSI is not guaranteed under a condition with no supply of low-speed crystal oscillation clock) Crystal oscillation (32.768 kHz) − High-speed clock: Built-in RC oscillation (500 kHz, 2MHz) • Power management − HALT mode: Suspends the instruction execution by CPU (peripheral circuits are in operating states) − STOP mode: Stops the low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) − High-speed clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) − Block control function: Completely stops the operation of any function block circuit that is not used (resets registers and stops clock) • Guaranteed operating range − Operating temperature: -20°C to +70°C (P version: -40°C to +85°C) − Operating voltage: VDD = 1.25V to 3.6V 3/30 FEDL610406-05 ML610404/ML610405/ML610406 • Product name – Supported Function - Chip (Die) - LCD bias Low-speed oscillation stop detect reset Cancellation by a mask option is possible Cancellation by a mask option is possible Operating temperature Product availability -20°C to +70°C Yes -20°C to +70°C Yes 1/2 1/3 ML610404-ｘｘｘWA Yes Yes ML610405-ｘｘｘWA Yes Yes ML610406-ｘｘｘWA Yes Yes Cancellation by a mask option is possible -20°C to +70°C Yes ML610404P-ｘｘｘWA Yes Yes Cancellation by a mask option is possible -40°C to +85°C Yes ML610405P-ｘｘｘWA Yes Yes Cancellation by a mask option is possible -40°C to +85°C Yes Yes Cancellation by a mask option is possible -40°C to +85°C Yes ML610406P-ｘｘｘWA -80-pin plastic TQFP - Yes LCD bias Low-speed oscillation stop detect reset Cancellation by a mask option is possible Cancellation by a mask option is possible Operating temperature Product availability -20°C to +70°C - -20°C to +70°C - 1/2 1/3 ML610404-ｘｘｘTB Yes Yes ML610405-ｘｘｘTB Yes Yes ML610406-ｘｘｘTB Yes Yes Cancellation by a mask option is possible -20°C to +70°C - ML610404P-ｘｘｘTB Yes Yes Cancellation by a mask option is possible -40°C to +85°C - ML610405P-ｘｘｘTB Yes Yes Cancellation by a mask option is possible -40°C to +85°C ML610406P-ｘｘｘTB Yes Yes Cancellation by a mask option is possible -40°C to +85°C - xxx: ROM code number (xxx of the blank product is NNN) Q: MTP version P: Wide range temperature version (P version) WA: Chip (Die) TB: TQFP 4/30 FEDL610406-05 ML610404/ML610405/ML610406 BLOCK DIAGRAM Block Diagram of ML610404/ML610405/ML610406 CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller ALU ECSR1～3 LR DSR/CSR EA PC SP Instruction Decoder Instruction Register Data-bus VDD VSS RESET_N TEST0 ELR1～3 Program Memory (ROM) 8Kbyte BUS Controller INT 2 RAM 256byte RESET & TEST SSIO ×2 Interrupt Controller XT0** XT1** INT 1 OSC LSCLK* OUTCLK* VDDL IN0* CS0* RS0* RT0* RCT0* RCM* IN1* CS1* RS1* RT1* INT 4 WDT TBC Power INT 1 RC-ADC ×2 INT ４ 8bit Timer ×4 Display Allocation RAM Display register 320bit SCK1* SIN1* SOUT1* INT 1 UART RXD0* TXD0* PWM PWM0* INT 1 INT 1 Capture ×2 SCK0* SIN0* SOUT0* Melody INT 6 GPIO MD0* P00 to P04 P20 to P23, P24 P30 to P35 P40 to P47 P50 to P57 P60 to P67 (ML610404) P60 to P63 (ML610405) LCD Driver LCD BIAS COM0 to COM4 (*1)(*2)(*3) SEG0 to SEG23 (ML610404) (*1) SEG0 to SEG27 (ML610405) (*2) SEG0 to SEG31 (ML610406) (*3) VL1, VL2, VL3 C1, C2 * Secondary function or Tertiary function “*1”: Select among 21 segments x 5 commons, 22 segments x 4 commons, 23 segments x 3 commons, and 24 segments x 2 commons with the register “*2”: Select among 25 segments x 5 commons, 26 segments x 4 commons, 27 segments x 3 commons, and 28 segments x 2 commons with the register “*3”: Select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments x 3 commons, and 32 segments x 2 commons with the register Figure 1 Block Diagram of ML610404/ML610405/ML610406 5/30 FEDL610406-05 ML610404/ML610405/ML610406 PIN CONFIGURATION 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 P22 P21 P20 VSS P60 P61 P62 P63 P64 P65 P66 P67 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 Pin Layout of ML610404 Chip 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 XT1 RESET_N TEST0 VL1 VL2 VL3 P50 P40 P41 P42 P43 P44 P45 P46 P47 VDD VSS VDDL XT0 2.1 mm SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 2.1 mm SEG6 SEG5 SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 C2 C1 14 15 16 17 18 19 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 1 2 3 4 5 6 7 8 9 10 11 12 13 P24 P00 P01 P02 P03 P04 P30 P31 P34 P32 P33 P35 P57 P56 P55 P54 P53 P52 P51 Y X Note: The assignment of the pads P30 to P35 are not in order. Chip size: 2.1 mm × 2.1 mm PAD count: 78 pins Minimum PAD pitch: 80µm PAD aperture: 70µm×70µm Chip thickness: 350µm Voltage of the rear side of chip: VSS leve Figure 2 Dimensions of ML610404 Chip 6/30 FEDL610406-05 ML610404/ML610405/ML610406 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 P22 P21 P20 VSS P60 P61 P62 P63 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 Pin Layout of ML610405 Chip 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 XT1 RESET_N TEST0 VL1 VL2 VL3 P50 P40 P41 P42 P43 P44 P45 P46 P47 VDD VSS VDDL XT0 2.1 mm SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 2.1 mm SEG6 SEG5 SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 C2 C1 14 15 16 17 18 19 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 1 2 3 4 5 6 7 8 9 10 11 12 13 P24 P00 P01 P02 P03 P04 P30 P31 P34 P32 P33 P35 P57 P56 P55 P54 P53 P52 P51 Y X Note: The assignment of the pads P30 to P35 are not in order. Chip size: 2.1 mm × 2.1 mm PAD count: 78 pins Minimum PAD pitch: 80µm PAD aperture: 70µm×70µm Chip thickness: 350µm Voltage of the rear side of chip: VSS level. Figure 3 Dimensions of ML610405 Chip 7/30 FEDL610406-05 ML610404/ML610405/ML610406 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 P22 P21 P20 VSS SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 Pin Layout of ML610406 Chip 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 XT1 RESET_N TEST0 VL1 VL2 VL3 P50 P40 P41 P42 P43 P44 P45 P46 P47 VDD VSS VDDL XT0 2.1 mm SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 2.1 mm SEG6 SEG5 SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 C2 C1 14 15 16 17 18 19 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 1 2 3 4 5 6 7 8 9 10 11 12 13 P24 P00 P01 P02 P03 P04 P30 P31 P34 P32 P33 P35 P57 P56 P55 P54 P53 P52 P51 Y X Note: The assignment of the pads P30 to P35 are not in order. Chip size: 2.1 mm × 2.1 mm PAD count: 78pins Minimum PAD pitch: 80 µm PAD aperture: 70 µm×70 µm Chip thickness: 350 µm Voltage of the rear side of chip: VSS level. Figure 4 Dimensions of ML610406 Chip 8/30 FEDL610406-05 ML610404/ML610405/ML610406 Pad Coordinates of ML610404/ML610405/M610406 Chip Table 1 Pad Coordinates of ML610404/ML610405/ML610406 (*1) PAD No. Pad Name 1 P50 2 P40 3 P41 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P42 P43 P44 P45 P46 P47 VDD VSS VDDL XT0 XT1 RESET_N TEST0 VL1 VL2 VL3 C1 21 C2 22 COM0 23 COM1 24 COM2/SEG0 25 COM3/SEG1 26 COM4/SEG2 27 SEG3 28 SEG4 29 SEG5 30 SEG6 31 SEG7 32 SEG8 33 SEG9 34 SEG10 35 SEG11 36 SEG12 37 SEG13 38 SEG14 39 SEG15 40 SEG16 41 SEG17 42 SEG18 43 SEG19 ML610404/5/6 X (µm) Y (µm) -773 -693 -613 -533 -453 -373 -293 -213 -133 -53 27 107 187 347 427 507 587 667 747 944 944 944 944 944 944 944 944 944 944 944 944 944 944 944 944 944 944 944 944 770 690 610 530 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -810 -730 -650 -570 -490 -410 -330 -250 -170 -90 -10 70 150 230 310 390 470 550 630 710 944 944 944 944 PAD No. Pad Name 44 SEG20 45 SEG21 46 SEG22 47 55 SEG23 P67 (*1) SEG24 (*2)(*3) P66 (*1) SEG25 (*2)(*3) P65 (*1) SEG26 (*2)(*3) P64 (*1) SEG27 (*2)(*3) P63 (*1)(*2) SEG28 (*3) P62 (*1)(*2) SEG29 (*3) P61 (*1)(*2) SEG30 (*3) P60 (*1)(*2) SEG31 (*3) 56 VSS 57 P20 58 P21 59 P22 60 P24 61 P00 62 P01 63 P02 64 P03 65 P04 66 P30 67 P31 68 P34 69 P32 70 P33 71 P35 72 P57 73 P56 74 P55 75 P54 76 P53 77 P52 78 P51 48 49 50 51 52 53 54 Chip Center: X=0,Y=0 ML610404/5/6 X (µm) Y (µm) 450 370 290 210 944 944 944 944 115 944 35 944 -45 944 -125 944 -205 944 -285 944 -365 944 -445 -525 -605 -685 -765 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 -944 944 944 944 944 944 717 617 537 457 377 297 217 137 57 -23 -103 -183 -263 -343 -423 -503 -583 -663 -743 Pad for ML610404 . (*2) Pad for ML610405. (*3) Pad for ML610406 9/30 FEDL610406-05 ML610404/ML610405/ML610406 List of Pins Primary function PIN No. PAD No. Pin name I/O Function 11,57 10 11,56 10 Vss VDD ⎯ ⎯ 12 12 VDDL ⎯ 18 17 VL1 ⎯ 19 18 VL2 ⎯ 20 19 VL3 ⎯ 21 20 C1 ⎯ 22 21 C2 ⎯ 17 16 14 15 16 15 13 14 TEST0 RESET_N XT0 XT1 I/O I I O 62 61 P00/EXI0/ CAP0 I 63 62 P01/EXI1/ CAP1 I 64 63 P02/EXI2/ RXD0 I 65 64 P03/EXI3 I 66 65 P04/EXI4/ T02P0CK I 58 59 60 61 57 58 59 60 P20/LED0 P21/LED1 P22/LED2 P24/LED4 O O O O Negative power supply pin Positive power supply pin Power supply pin for internal logic (internally generated) Power supply pin for LCD bias (internally generated or connected to positive power supply pin)(*1) Power supply pin for LCD bias (internally generated or connected to positive power supply pin)(*1) Power supply pin for LCD bias (internally generated or connected to positive power supply pin)(*1) Capacitor connection pin for LCD bias generation Capacitor connection pin for LCD bias generation Test input pin Reset input pin Low-speed clock oscillation pin Low-speed clock oscillation pin Input port, External interrupt, Capture 0 input Input port, External interrupt, Capture 1 input Input port, External interrupt, UART0 received data Input port, External interrupt Input port, Timer 0/Timer 2/PWM0 external clock input External interrupt Output port Output port Output port Output port 67 66 P30 I/O 68 67 P31 69 68 70 Secondary function or Tertiary function Secondary/ Tertiary ⎯ ⎯ Pin name I/O Function ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Secondary Secondary Secondary Secondary LSCLK OUTCLK MD0 PWM0 O O O O Input/output port Secondary IN0 I I/O Input/output port Secondary CS0 O P34 I/O Input/output port Secondary RCT0 O 69 P32 I/O Input/output port Secondary RS0 O 71 70 P33 I/O Input/output port Secondary RT0 O 72 71 P35 I/O Input/output port Secondary RCM O Low-speed clock output High-speed clock output Melody 0 output PWM0 output RC type ADC0 oscillation input pin RC type ADC0 reference capacitor connection pin RC type ADC0 resistor/capacitor sensor connection pin RC type ADC0 reference resistor connection pin RC type ADC0 measurement resistor sensor connection pin RC type ADC oscillation monitor 10/30 FEDL610406-05 ML610404/ML610405/ML610406 Primary function PIN No. PAD No. Pin name I/O 2 2 P40 I/O Input/output port 3 3 P41 I/O Input/output port 4 4 P42 I/O Input/output port 5 5 P43 I/O Input/output port 6 6 P44/ T02P0CK I/O Input/output port, Timer 0/Timer 2/PWM0 external clock input I/O Input/output port, Timer 1/Timer 3 external clock input 7 8 9 7 8 9 P45/T13CK P46 P47 I/O Function Input/output port Secondary function or Tertiary function Secondary /Tertiary Secondary Tertiary Secondary Pin name I/O Function ⎯ SIN0 ⎯ ⎯ I ⎯ Tertiary SCK0 I/O Secondary Tertiary Secondary Tertiary RXD0 SOUT0 TXD0 PWM0 I O O O Secondary IN1 I Tertiary SIN0 I Secondary CS1 O ⎯ SSIO0 data input ⎯ SSIO0 synchronous clock input/output UART data input SSIO0 data output UART data output PWM0 output RC type ADC1 oscillation input pin SSIO0 data input RC type ADC1 reference capacitor connection pin Tertiary SCK0 I/O Secondary RS1 O Tertiary SOUT0 O I/O Input/output port Secondary RT1 O Secondary Tertiary Secondary MD0 SIN1 ⎯ O I ⎯ Tertiary SCK1 I/O Secondary Tertiary ⎯ SOUT1 ⎯ O ⎯ ⎯ ⎯ Secondary Tertiary Secondary ⎯ SIN1 ⎯ ⎯ I ⎯ Tertiary SCK1 I/O Secondary Tertiary ⎯ SOUT1 ⎯ O ⎯ ⎯ ⎯ 1 1 P50/EXI8 I/O Input/output port, External interrupt 79 78 P51/EXI8 I/O Input/output port, External interrupt 78 77 P52/EXI8 I/O 77 76 P53/EXI8 I/O 76 75 P54/EXI8 I/O 75 74 P55/EXI8 I/O 74 73 P56/EXI8 I/O 73 72 P57/EXI8 I/O Input/output port, External interrupt Input/output port, External interrupt Input/output port, External interrupt Input/output port, External interrupt Input/output port, External interrupt Input/output port, External interrupt SSIO0 synchronous clock input/output RC type ADC1 reference resistor connection pin SSIO0 data output RC type ADC1 measurement resistor sensor connection pin Melody 0 output SSIO1 data input ⎯ SSIO1 synchronous clock input/output ⎯ SSIO1 data output ⎯ ⎯ SSIO1 data input ⎯ SSIO1 synchronous clock input/output ⎯ SSIO1 data output ⎯ 11/30 FEDL610406-05 ML610404/ML610405/ML610406 PIN No. PAD No. 23 24 22 23 25 24 26 25 27 26 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 49 48 50 49 51 50 52 51 53 52 54 53 55 54 56 55 Primary function Function Secondary function or Tertiary function Secondary/ Tertiary ⎯ ⎯ Pin name ⎯ ⎯ Pin name I/O COM0 COM1 COM2/ SEG0 COM3/ SEG1 COM4/ SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 P67(*2) SEG24(*3) P66(*2) SEG25(*3) P65(*2) SEG26(*3) P64(*2) SEG27(*3) P63(*4) SEG28(*5) P62(*4) SEG29*5) P61(*4) SEG30(*5) P60(*4) SEG31(*5) O O LCD common pin LCD common pin I/O Function ⎯ ⎯ ⎯ ⎯ O LCD common/segment pin ⎯ ⎯ ⎯ ⎯ O LCD common/segment pin ⎯ ⎯ ⎯ ⎯ O LCD common/segment pin ⎯ ⎯ ⎯ ⎯ O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin Output port LCD segment pin Output port LCD segment pin Output port LCD segment pin Output port LCD segment pin Output port LCD segment pin Output port LCD segment pin Output port LCD segment pin Output port LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (*1) Internally generated, or connect to either positive power supply pin (VDD) or power supply pin for internal logic (VDDL). For details, see user’s manual. (*2) Pin for ML610404 (*3) Pin for ML610405/ML610406 (*4) Pin for ML610404/ML610405 (*5) Pin for ML610406 12/30 FEDL610406-05 ML610404/ML610405/ML610406 PIN DESCRIPTION Pin name I/O Description Primary/ Secondary/ Tertiary Logic System Reset input pin. When this pin is set to a “L” level, system reset mode is — Negative set and the internal section is initialized. When this pin is set to a “H” level subsequently, program execution starts. A pull-up resistor is internally connected. XT0 I Crystal connection pin for low-speed clock. — — XT1 O A 32.768 kHz crystal resonator is connected to this pin. Capacitors CDL — — and CGL are connected across this pin and VSS. (see measuring circuit 1) . LSCLK O Low-speed clock output. Assigned to the secondary function of the P20 Secondary — pin. OUTCLK O High-speed clock output pin. This pin is used as the secondary function of Secondary — the P21 pin. General-purpose input port RESET_N I P00 to P04 I General-purpose input port. General-purpose output port P20 to P22, O General-purpose output port. P24 This cannot be used as the general output port when used as the secondary function. General-purpose input/output port P30 to P35 I/O General-purpose input/output port. This cannot be used as the general input/output port when used as the secondary function. P40 to P47 I/O General-purpose input/output port. This cannot be used as the general input/output port when used as the secondary or tertiary function. P50 to P57 I/O General-purpose input/output port. This cannot be used as the general input/output port when used as the secondary function. P60 to P63 O General-purpose output port. Incorporated only into ML610404/ML610405, and not into ML610406. P64 to P67 O General-purpose output port. Incorporated only into ML610404, and not into ML610405/ ML610406. Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive 13/30 FEDL610406-05 ML610404/ML610405/ML610406 Pin name Primary/ Secondary/ Tertiary Logic Secondary Positive Primary/ Secondary Positive Tertiary — Tertiary Positive Tertiary Positive Tertiary — Tertiary Positive Tertiary Positive Secondary Tertiary Primary Positive External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P00 to P04 pins. External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. Assigned to the primary function of the P50 to P57 pins. Primary Positive/ negative Primary Positive/ negative Capture trigger input pins. The value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. These pins are used as the primary functions of the P00 pin(CAP0) and P01 pin(CAP1). Primary Positive/ negative Positive/ negative I/O UART TXD0 O RXD0 I Description UART data output pin. This pin is used as the secondary function of the P43 pin. UART data input pin. This pin is used as the secondary function of the P42 or the primary function of the P02 pin. Synchronous serial (SSIO) SCK0 SIN0 SOUT0 SCK1 SIN1 SOUT1 PWM PWM0 T02P0CK I/O Synchronous serial clock input/output pin. This pin is used as the tertiary function of the P41 or P45 pin. I Synchronous serial data input pin. This pin is used as the tertiary function of the P40 or P44 pin. O Synchronous serial data output pin. This pin is used as the tertiary function of the P42 or P46 pin. I/O Synchronous serial clock input/output pin. Assigned to the tertiary function of the P51 pin and P55 pin. I Synchronous serial data input pin. Assigned to the tertiary function of the P50 pin and P54 pin. O Synchronous serial data output pin. Assigned to the tertiary function of the P52 pin and P56 pin. O PWM0 output pin. This pin is used as the secondary function of the P24 and tertiary function of the P43 pin. O PWM0 external clock input pin. This pin is used as the primary function of the P04 pin and P44 pin. External interrupt EXI0-4 I EXI8 I Capture CAP0 I CAP1 I Timer T02P0CK T13CK Melody MD0 LED drive LED0 to LED2, LED4 I I External clock input pin used for both Timer 0 and Timer 2. This pin is used as the primary function of the P04 pin and P44 pin. External clock input pin used for both Timer 1 and Timer 3. This pin is used as the primary function of the P45 pin. O Melody/buzzer signal output pin. This pin is used as the secondary function of the P22 and P50 pins. O N-channel open drain output pins to drive LED. This pin is used as the primary function of the P20 to P22 and P24 pins. Primary Primary Primary — — — Secondary Positive/ negative Primary Positive/ negative 14/30 FEDL610406-05 ML610404/ML610405/ML610406 Pin name I/O Description RC oscillation type A/D converter IN0 I Channel 0 oscillation input pin. This pin is used as the secondary function of the P30 pin. CS0 O Channel 0 reference capacitor connection pin. This pin is used as the secondary function of the P31 pin. RS0 O This pin is used as the secondary function of the P32 pin which is the reference resistor connection pin of Channel 0. RCT0 O Resistor/capacitor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P34 pin. RT0 O Resistor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P33 pin. RCM O RC oscillation monitor pin. This pin is used as the secondary function of the P35 pin. IN1 I Oscillation input pin of Channel 1. This pin is used as the secondary function of the P44 pin. CS1 O Reference capacitor connection pin of Channel 1. This pin is used as the secondary function of the P45 pin. RS1 O Reference resistor connection pin of Channel 1. This pin is used as the secondary function of the P46 pin. Resistor sensor connection pin for measurement of Channel 1. This pin is RT1 O used as the secondary function of the P47 pin. LCD drive signal COM0 to O Common output pins. COM2, COM3, and COM4 can be switched to SEG0, SEG1, and SEG2, respectively, through the register setting. To COM4 change the setting, switch between COM4 and SEG2 for one pin and switch between COM3, COM4 and SEG1, SEG2 for two pins. Segment output pin. The SEG0, SEG1, and SEG2 pins are for switching SEG0 to O the register setting with the COM2, COM3, and COM4. SEG23 SEG24 to O Segment output pin. Incorporated into ML610405/ML610406, not into ML610404. SEG27 SEG28 to O Segment output pin. Incorporated into ML610406, not into ML610404/ML610405. SEG31 LCD driver power supply VL1 — Power supply pin for LCD bias (internally generated) or power supply VL2 — connection pin. Depending on LCD Bias setting and VDD voltage level, VDD V — or VDDL or capacitor is connected. L3 C1 C2 For testing TEST0 Power supply VSS VDD VDDL — — Power supply pins for LCD bias (internally generated). Capacitor C12 (see measuring circuit 1) is connected between C1 and C2. I/O Pin for testing. A pull-down resistor is internally connected. — — — Negative power supply pin. Positive power supply pin. Positive power supply pin (internally generated) for internal logic. Capacitor CL (see measuring circuit 1) is connected between this pin and VSS. Primary/ Secondary/ Tertiary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Logic — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Positive — — — — — — 15/30 FEDL610406-05 ML610404/ML610405/ML610406 TERMINATION OF UNUSED PINS Table 3 shows methods of terminating the unused pins. Table 3 Pin VL1 VL2 VL3 C1, C2 RESET_N TEST0 P00 to P04 P20 to P22, P24 P30 to P35 P40 to P47 P50 to P57 P60 to P67 COM0 to COM4 SEG0 to SEG31 Termination of Unused Pins Recommended pin handling Open Open Open Open Open Open VDD or VSS Open Open Open Open Open Open Open Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 16/30 FEDL610406-05 ML610404/ML610405/ML610406 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (VSS = 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 VDD Ta = 25°C −0.3 to +4.6 V Power supply voltage 2 VDDL Ta = 25°C −0.3 to +3.6 V Power supply voltage 3 VL1 Ta = 25°C −0.3 to +2.0 V Power supply voltage 4 VL2 Ta = 25°C −0.3 to +4.0 V Power supply voltage 5 VL3 Ta = 25°C −0.3 to +6.0 V VIN Ta = 25°C −0.3 to VDD+0.3 V Output voltage VOUT Ta = 25°C −0.3 to VDD+0.3 V Output current 1 IOUT1 Port 3 to 6, Ta = 25°C −12 to +11 mA Output current 2 IOUT2 Port 2, Ta = 25°C −12 to +20 mA Power dissipation PD Ta = 25°C 0.9 W Storage temperature TSTG ⎯ −55 to +150 °C Input voltage RECOMMENDED OPERATING CONDITIONS (VSS = 0V) Parameter Symbol Condition Range Unit Operating temperature TOP without P version P version -20 to +70 -40 to +85 °C Operating voltage VDD fOP = 30k to 625kHz 1.25 to 3.6 fOP = 30k to 2.5MHz 1.8 to 3.6 Operating frequency (CPU) fOP VDD pin external capacitance VDDL pin external capacitance CV CL VDD = 1.25 to 3.6V VDD = 1.8 to 3.6V ― ⎯ 30k to 625k 30k to 2.5M 1 1.0±30% to 2.2±30%* 2 0.47±30% to 2.2±30%* Ca, b, c ⎯ 0.1±30% µF C12 ⎯ 0.47±30% µF VL1, 2, or 3 pin external capacitance Pin-to-pin (C1 to C2) external capacitance V Hz µF µF *1: Please select as CV is larger than CL or same as CL. *2: When the load of VDD is small and the power rise time is too short, it may happen that the power-on reset is not generated. In this case please select CL with larger capacitance CLOCK GENERATION CIRCUIT OPERATING CONDITIONS (VSS = 0V) Parameter Low-speed crystal oscillation frequency Recommended equivalent series resistance value of low-speed crystal oscillation Low-speed crystal oscillation external capacitor Symbol Condition fXTL Rating Unit Min. Typ. Max. ⎯ ⎯ 32.768k ⎯ Hz RL ⎯ ⎯ ⎯ 40k Ω ⎯ 12 ⎯ CDL/CGL CL=6pF of crystal oscillation CL=9pF of crystal oscillation CL=12pF of crystal oscillation ⎯ 18 ⎯ ⎯ 24 ⎯ pF 17/30 FEDL610406-05 ML610404/ML610405/ML610406 DC CHARACTERISTICS (1/5) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Measuring Rating Parameter Symbol Condition Unit circuit Min. Typ. Max. Typ. Typ. 500 Ta = 25°C +10% −10% VDD = 1.25 kHz to 3.6V Typ. Typ. 3 500 * +25% −25% 500kHz/2MHz RC oscillation fRC frequency Typ. Typ. 2.0 Ta = 25°C +10% −10% VDD = 1.80 MHz to 3.6V Typ. Typ. 3 2.0 * +25% −25% Low-speed crystal oscillation TXTL ⎯ ⎯ 0.6 2 s 2 1 start time* 500kHz/2MHz RC oscillation ⎯ ⎯ ⎯ 3 µs TRC start time Low-speed oscillation stop ⎯ 12 16.4 41 ms TSTOP *1 detect time Reset pulse width PRST ⎯ 200 ⎯ ⎯ µs Reset noise elimination ⎯ ⎯ ⎯ 0.3 PNRST pulse width Power-on reset generated TPOR ⎯ ⎯ ⎯ 10 ms power rise time 1 * : When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. 2 * : 32.768KHz Crystal resonator DT-26 (Load Capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF) 3 * : Recommended operating temperature (Ta=-20 to 70°C, Ta=-40 to 85°C for P version) VIL1 RESET_N VIL1 PRST Reset pulse width (PRST) 0.9xVDD VDD 0.1xVDD TPOR Power-on reset activation power rise time (TPOR ) 18/30 FEDL610406-05 ML610404/ML610405/ML610406 DC CHARACTERISTICS (2/5) Parameter VDDL voltage VDDL temperature 1 deviation * VDDL voltage 1 dependency * (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Measuring Rating Symbol Condition Unit circuit Min. Typ. Max. fOP = 30k to 625kHz 1.1 1.2 1.3 V VDDL 1.35 1.5 1.65 fOP = 30k to 2.5MHz ∆VDDL VDD = 3.0V ⎯ -1 ⎯ mV/°C ∆VDDL ⎯ ⎯ 5 20 mV/V 1 *1: The maximum VDDL voltage becomes the VDD voltage level when the VDDL voltage determined by the temperature and voltage deviations mathematically exceeds the VDD voltage. 19/30 FEDL610406-05 ML610404/ML610405/ML610406 DC CHARACTERISTICS (3/5) Parameter Supply current 1 Supply current 2 Supply current 3 Supply current 4-1 Symbol IDD1 IDD2 IDD3 IDD4-1 (VDD=3.0V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Measuring Rating Condition Unit circuit Min. Typ. Max. CPU: In STOP state. Low-speed/high-speed oscillation: stopped. CPU: In HALT state (LTBC and WDT 3 4 are Operating.).* * High-speed 500kHz/2MHz oscillation: Stopped. 6 LCD and BIAS circuits: Operating. * CPU: In 32.768kHz operating 1 3 state.* * High-speed 500kHz/2MHz oscillation: Stopped. 2 LCD and BIAS circuits: Operating. * CPU: In 500kHz RC operating state. 2 LCD/BIAS circuits: Operating. * Ta= 25°C ⎯ 0.4 0.8 µA 5 * ⎯ ⎯ 6.5 Ta= 25°C ⎯ 0.9 1.8 µA 5 * ⎯ ⎯ 7.5 Ta= 25°C ⎯ 4.0 7.5 1 µA 5 * ⎯ ⎯ 11.0 Ta= 25°C ⎯ 60 80 * ⎯ ⎯ 90 Ta= 25°C ⎯ 240 300 µA 5 1 Supply current 4-2 IDD4-2 CPU: In 2MHz RC operating state. 2 LCD/BIAS circuits: Operating. * µA 5 * ⎯ ⎯ 320 1 * : When the CPU operating rate is 100% (No HALT state). 2 * : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying clock: 1/128 LSCLK (256Hz) 3 * : 32.768KHz Crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF). 4 * : Significant bits of BLKCON0 to BLKCON4 registers are all “1” except DLCD bit on BLKCON4. 5 * : Recommended operating temperature (Ta=-20 to 70°C, Ta=-40 to 85°C for P version) 6 * : LCD stop mode, 1/3 bias, Bias voltage multiplying clock: 1/128 LSCLK (256Hz) 20/30 FEDL610406-05 ML610404/ML610405/ML610406 DC CHARACTERISTICS (4/5) Parameter Output voltage 1 (P20 to P22,P24 (N-channel open drain output mode is not selected)) (P30 to P35) (P40 to P47) (P50 to P57) *2 (P60 to P63) *1 (P60 to P67) Output voltage 2 (P20 to P22,P24 (N-channel open drain output mode is not selected)) Output voltage 3 (COM0 to 4) *1 (SEG0 to 23) *2 (SEG0 to 27) *3 (SEG0 to 31) Output leakage (P20 to P22,P24) (P30 to P35) (P40 to P47) (P50 to P57) *2 (P60 to P63) *1 (P60 to P67) Input current 1 (RESET_N) Input current 2 (TEST0) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Measuring Symbol Condition Unit circuit Min. Typ. Max. IOL1 = +0.5mA, VDD = 1.8 to 3.6V VDD −0.5 VDD −0.3 ⎯ IOL1 = +0.1mA, VDD = 1.25 to 3.6V VOL2 ⎯ ⎯ ⎯ ⎯ ⎯ 0.5 ⎯ ⎯ 0.3 IOL2 = +5mA, VDD = 1.8 to 3.6V ⎯ ⎯ 0.5 VOH3 IOH3 = −0.05mA, VL1=1.2V VL3 −0.2 ⎯ ⎯ VOML3 IOML3 = +0.05mA, VL1=1.2V ⎯ ⎯ VL2 +0.2 VOML3S IOML3S = −0.05mA, VL1=1.2V VL2 −0.2 ⎯ ⎯ VOLM3 IOLM3 = +0.05mA, VL1=1.2V ⎯ ⎯ VL1 +0.2 VOLM3S IOLM3S = −0.05mA, VL1=1.2V VL1 −0.2 ⎯ ⎯ VOL3 IOL3 = +0.05mA, VL1=1.2V ⎯ ⎯ 0.2 IOOH VOH = VDD (in high-impedance state) ⎯ ⎯ 1 IOH1 = −0.5mA, VDD = 1.8 to 3.6V VOH1 IOH1 = -0.03mA, VDD = 1.25 to 3.6V VOL1 IOOL VOL = VSS (in high-impedance state) −1 ⎯ ⎯ IIH1 IIL1 IIH2 IIL2 VIH1 = VDD VIL1 = VSS VIH2 = VDD VIL2 = Vss VIH3 = VDD, VDD = 1.8 to 3.6V (when pulled-down) VIH3 = VDD, VDD = 1.25 to 3.6V (when pulled-down) VIL3 = Vss, VDD = 1.8 to 3.6V (when pulled-up) VIL3 = Vss, VDD = 1.25 to 3.6V (when pulled-up) ⎯ -600 2 -1 ⎯ -300 300 ⎯ 1 -2 600 ⎯ 2 30 200 0.01 30 200 -200 -30 -2 -200 -30 -0.01 IIH3 Input current 3 (P00 to P04) (P30 to P35) (P40 to P47) (P50 to P57) IIL3 IIH3Z VIH3 = VDD (in high-impedance state) ⎯ ⎯ 1 IIL3Z VIL3 = VSS (in high-impedance state) −1 ⎯ ⎯ V 2 µA 3 µA 4 1 * : Characteristics for ML610404 2 * : Characteristics for ML610405 3 * : Characteristics for ML610406 21/30 FEDL610406-05 ML610404/ML610405/ML610406 DC CHARACTERISTICS (5/5) Parameter Input voltage 1 (RESET_N) (TEST0) (P00 to P04) (P30 to P35) (P40 to P47) (P50 to P57) Input pin capacitance (P00 to P04) (P30 to P35) (P40 to P47) (P50 to P57) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Measuring Symbol Condition Unit circuit Min. Typ. Max. VIH1 ⎯ 0.7 ×VDD ⎯ VDD = 1.8 to 3.6V 0 ⎯ VDD = 1.25 to 3.6V 0 ⎯ f = 10kHz Vrms = 50mV Ta = 25°C ⎯ ⎯ VIL1 CIN VDD 0.3 ×VDD 0.2 ×VDD 5 V 5 pF ⎯ 22/30 FEDL610406-05 ML610404/ML610405/ML610406 MEASURING CIRCUITS CGL XT0 CDL XT1 C2 32.768kHz crystal resonator C12 C1 VDD VDDL VL1 VL2 VL3 CV : 1µF CL : 2.2uF Ca,Cb,Cc : 0.1µF C12 : 0.47µF 32.768kHz crystal resonator : DT-26 (Load capacitance 6pF) VSS A CV CL (Made by KDS:DAISHINKU CORP.) Cc Ca CGL, CDL : 6pF MEASURING CIRCUIT 2 (Note 2) VIH Output pin VIL Input pin (Note 1) VDD VDDL VL1 VL2 VL3 V VSS (Note 1) Input logic circuit to determine the specified measuring conditions. (Note 2) Repeats for the specified output pin 23/30 FEDL610406-05 ML610404/ML610405/ML610406 MEASURING CIRCUIT 3 (Note 2) VIH Output pin Input pin (Note 1) VIL VDD VDDL VL1 VL2 VL3 A VSS (Note 1) Input logic circuit to determine the specified measuring conditions. (Note 2) Repeats for the specified output pin MEASURING CIRCUIT 4 (Note 3) Output pin Input pin A VDD VDDL VL1 VL2 VL3 VSS (Note 3) Repeats for the specified input pin MEASURING CIRCUIT 5 VIH VDD VDDL VL1 VL2 VL3 Waveform observation Output pin VIL Input pin (Note 1) VSS (Note 1) Input logic circuit to determine the specified measuring conditions. 24/30 FEDL610406-05 ML610404/ML610405/ML610406 AC CHARACTERISTICS (External Interrupt) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. External interrupt disable period TNUL Interrupt: Enabled (MIE = 1), CPU: NOP operation System clock: 32.768kHz ⎯ 76.8 106.8 µs P00 to P04 (Rising-edge interrupt mode) tNUL P00 to P04 (Falling-edge interrupt mode) tNUL P00 to P04 P50 to P57 (Both-edge interrupt mode) tNUL AC CHARACTERISTICS (UART) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Transmit baud rate ⎯ tTBRT 1 ⎯ BRT* 1 ⎯ s 1 BRT* BRT* 1 BRT* s −3% +3% *1: Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA0BRTL,H) and the UART mode register 0 (UA0MOD0). Receive baud rate ⎯ tRBRT tTBRT TXD0* tRBRT RXD0* *: Indicates the secondary function of the port. 25/30 FEDL610406-05 ML610404/ML610405/ML610406 AC CHARACTERISTICS (Synchronous Serial Port) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Parameter Symbol SCLK input cycle (slave mode) Rating Condition In the 500kHz oscillation mode* tSCYC In the 2MHz oscillation mode* Typ. Max. 10 ― ― µs 1 ― ― µs ― SCLK* ― s 4 ― ― µs 0.4 ― ― µs 2 3 VDD=1.8 to 3.6V SCLK output cycle (master mode) SCLK input pulse width (slave mode) tSCYC ― In the 500kHz oscillation mode* tSW In the 2MHz oscillation mode* 2 (master mode) 1 ― tSW In the 500kHz oscillation mode* SOUT output delay time (slave mode) tSD SCLK* ×0.4 ×0.5 ×0.6 ― ― 500 ― ― 240 ― ― 500 tSD ns 2 Output load 10pF In the 2MHz oscillation mode* s 2 3 In the 500kHz oscillation mode* (master mode) 1 SCLK* Output load 10pF In the 2MHz oscillation mode* 1 SCLK* Output load 10pF SOUT output delay time 1 3 VDD=1.8 to 3.6V SCLK output pulse width Unit Min. ns 3 ― ― 240 80 ― ― 500 ― ― 240 ― ― 300 ― ― 80 ― ― Output load 10pF, VDD=1.8 to 3.6V SIN input ― tSS setup time ns (slave mode) In the 500kHz oscillation mode* SIN input setup time tSS In the 2MHz oscillation mode* (master mode) 3 VDD=1.8 to 3.6V In the 500kHz oscillation mode* SIN input tSH hold time 2 In the 2MHz oscillation mode* 2 3 VDD=1.8 to 3.6V ns ns *1: Clock cycle selected with SnCK2–0 of the serial port n mode register (SIOnMOD1) (n= 0, 1) *2: When 500kHz oscillation is selected with OSCM2 of the frequency control register 0 (FCON0) *3: When 2MHz oscillation is selected with OSCM2 of the frequency control register 0 (FCON0) tSCYC tSW tSW SCLKn* tSD tSD SOUTn* tSS tSH SINn* *: Indicates the tertiary function of the port (n= 0,1) 26/30 FEDL610406-05 ML610404/ML610405/ML610406 AC CHARACTERISTICS (RC Oscillation A/D Converter) Condition for VDD=1.8 to 3.6V (VDD=1.8 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. RS0,RS1,RT0, Oscillation resistor 1 ― ― CS0, CT0, CS1≥740pF kΩ RT0-1,RT1 fOSC1 457.3 525.2 575.1 kHz Resistor for oscillation=1kΩ Oscillation frequency fOSC2 53.48 58.18 62.43 kHz Resistor for oscillation=10kΩ VDD = 3.0V fOSC3 5.43 5.89 6.32 kHz Resistor for oscillation=100kΩ Kf1 7.972 9.028 9.782 RT0, RT0-1, RT1=1kΩ ⎯ RS to RT oscillation *1 frequency ratio Kf2 0.981 1 1.019 RT0, RT0-1, RT1=10kΩ ⎯ VDD = 3.0V Kf3 0.099 0.101 0.104 RT0, RT0-1, RT1=100kΩ ⎯ *1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. fOSCX(RT0-1-CS0 oscillation) fOSCX(RS0-CS0 oscillation) IN0 CS0 RCT0 (Note 1) RT0 RS0 RS0 RT0 VIL RCM VDD CV VDDL RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ RS0, RS1: 10kΩ CS0, CT0, CS1: 560pF CVR0, CVR1: 820pF IN1 CS1 RS1 RT1 Input pin VIH CVR1 RT0-1 CT0 CS0 CVR0 fOSCX(RT1-CS1 oscillation) fOSCX(RS1-CS1 oscillation) , RT1 , RS1 fOSCX(RT0-CS0 oscillation) fOSCX(RS0-CS0 oscillation) ( x = 1, 2, 3 ) CS1 Kfx = Frequency measurement (fOSCX) VSS CL *1: Input logic circuit to determine the specified measuring conditions. 27/30 FEDL610406-05 ML610404/ML610405/ML610406 Condition for VDD=1.25 to 3.6V (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. RS0,RS1,RT0, Oscillation resistor 1 ― ― CS0, CT0, CS1≥740pF kΩ RT0-1,RT1 fOSC1 81.93 93.16 101.2 kHz Resistor for oscillation=6kΩ Oscillation frequency fOSC2 35.32 38.75 41.48 kHz Resistor for oscillation=15kΩ VDD = 1.5V fOSC3 5.22 5.65 6.03 kHz Resistor for oscillation=105kΩ Kf1 2.139 2.381 2.632 RT0, RT0-1, RT1=1kΩ ⎯ RS to RT oscillation *1 frequency ratio Kf2 0.973 1 1.028 RT0, RT0-1, RT1=10kΩ ⎯ VDD = 1.5V Kf3 0.142 0.147 0.152 RT0, RT0-1, RT1=100kΩ ⎯ fOSC1 85.28 94.58 103.3 kHz Resistor for oscillation=6kΩ Oscillation frequency fOSC2 35.72 38.87 41.78 kHz Resistor for oscillation=15kΩ VDD = 3.0V 5.189 5.622 6.012 kHz fOSC3 Resistor for oscillation=105kΩ Kf1 2.227 2.432 2.626 RT0, RT0-1, RT1=1kΩ ⎯ RS to RT oscillation *1 frequency ratio Kf2 0.982 1 1.018 RT0, RT0-1, RT1=10kΩ ⎯ VDD = 3.0V Kf3 0.141 0.145 0.149 RT0, RT0-1, RT1=100kΩ ⎯ *1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. fOSCX(RT0-1-CS0 oscillation) fOSCX(RS0-CS0 oscillation) , IN0 CS0 RCT0 VIH , RA1 RT1 RA0 RT0 RS0 RS0 RT0 RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ RA0, RA0-1, RA1: 5kΩ RS0, RS1: 15kΩ CS0, CT0, CS1: 560pF CVR0, CVR1: 820pF IN1 CS1 RS1 RT1 Frequency measurement (fOSCX) Input pin RCM (Note 1) fOSCX(RT1-CS1 oscillation) fOSCX(RS1-CS1 oscillation) CVR1 RT0-1 RA0-1 CT0 CS0 CVR0 RS1 fOSCX(RT0-CS0 oscillation) fOSCX(RS0-CS0 oscillation) ( x = 1, 2, 3 ) CS1 Kfx = VIL VDD CV VDDL VSS CL *1: Input logic circuit to determine the specified measuring conditions. Note: •Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wiring between IN0/IN1 and RS0/RS1. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. •When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal. •Please make wiring to components (capacitor, resistor, and so on) necessary for objective measurement. Wiring to reserved components may affect to the A/D conversion operation by noise the components itself may have. 28/30 FEDL610406-05 ML610404/ML610405/ML610406 Revision History Document No. Date FEDL610406-01 FEDL610406-02 Dec.15,2011 Dec.5,2012 FEDL610406-03 Feb.21,2014 FEDL610406-04 FEDL610406-05 Apr.18,2014 May.23,2014 Page Previous Current Edition Edition – 15 17 19 19,25 All – 15 17 19 19,25 All 3 4 20 18 Description Final edition Remove the word “appendixC” in the table. Correct the symbol of capacitor at VDDL. The notes about CV, CL were added. The value of capacitor CL was changed to 2.2uF. Change header and footer Change from "Shipment" to " Product name – Supported Function " Correct minimum time of Power-on reset generated power rise time 3,5,6,7, 31 4 - 4 Delete package products 4 17 18 18 18 18 18 18 Correct the “Product name – Supported Function” Add Clock Generation Circuit Operating Conditions Change "RESET" to " Reset pulse width (PRST)" and " Power-on reset activation power rise time (TPOR )". Correct minimum time of Power-on reset generated power rise time Correct the CGL’s value and the CDL’s value of DC CHARACTERISTICS (1/5)’s note No.2 29/30 FEDL610406-05 ML610404/ML610405/ML610406 NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. 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