FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13746-3E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90360E Series
MB90362E, MB90362ES, MB90362TE, MB90362TES,
MB90F362E, MB90F362ES, MB90F362TE, MB90F362TES,
MB90367E, MB90367ES, MB90367TE, MB90367TES,
MB90F367E, MB90F367ES, MB90F367TE, MB90F367TES,
MB90V340E-101, MB90V340E-102, MB90V340E-103, MB90V340E-104
■ DESCRIPTION
The MB90360E-series, loaded 1 channel FULL-CAN* interface and Flash ROM, is general-purpose FUJITSU
16-bit microcontroller designing for automotive and industrial applications. Its main feature is the on-board CAN
Interfaces, which conform to Ver 2.0 Part A and Part B, while supporting a very flexible message buffer scheme
and so offering more functions than a normal FULL-CAN approach. With the new 0.35 µm CMOS technology,
Fujitsu now offers on-chip Flash ROM program memory up to 64 Kbytes.
The power supply (3 V) is supplied to the MCU core from an internal regulator circuit. This creates a major
advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external
4 MHz clock. Also, main and sub clock can be monitored independently using the clock supervisor function.
The unit features a 4-channel input capture unit 1 channel 16-bit free running timer, 2-channel LIN-UART, and
16-channel 8/10-bit A/D converter as the peripheral resource.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in
system development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.8
MB90360E Series
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz)
• Operation by sub clock : internal operating clock frequency: up to 50 kHz (for operating with 100 kHz oscillation
clock divided two and devices without S-suffix only) is available
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock and 6-time multiplied
PLL clock)
• Clock supervisor (MB90x367x only)
• Main clock or sub clock is monitored independently
• Instruction system best suited to controller
• 16 Mbytes CPU memory space
• 24-bit internal addressing
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions with sign and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
4-byte instruction queue
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 8 channels external interrupts are supported
• Automatic data transfer function independent of CPU
Expanded intelligent I/O service function (EI2OS) : up to 16 channels
• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Main timer mode (timebase timer mode that is transferred from main clock mode)
• PLL timer mode (timebase timer mode that is transferred from PLL clock mode)
• Watch mode (a mode that operates sub clock and watch timer only, devices without S-suffix)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
• Process
CMOS technology
• I/O port
General purpose input/output port (CMOS output) :
- 34 ports (devices without S-suffix)
- 36 ports (devices with S-suffix)
• Sub clock pin (X0A and X1A)
• Provided (used for external oscillation), devices without S-suffix
• Not provided, devices with S-suffix
(Continued)
2
DS07-13746-3E
MB90360E Series
(Continued)
• Timer
• Timebase timer, watch timer (device without S-suffix) , watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 4 channels or 16-bit × 2 channels
• 16-bit reload timer : 2 channels
• 16- bit input/output timer
- 16-bit free-run timer : 1 channel (FRT0 : ICU 0/1/2/3)
- 16- bit input capture : (ICU) : 4 channels
• FULL-CAN interface : 1 channel
• Compliant with CAN specifications Version 2.0 Part A and B
• 16 message buffers are built in
• CAN wake-up function
• LIN-UART : 2 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
• DTP/External interrupt : up to 8 channels, CAN wakeup : up to 1 channel
Module for activation of expanded intelligent I/O service (EI2OS) and generation of external interrupt by external
input
• Delay interrupt generator module
Generates interrupt request for task switching
• 8/10-bit A/D converter : 16 channels
• Resolution is selectable between 8-bit and 10-bit
• Activation by external trigger input is allowed
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
• Address matching detection (program patch) function
Address matching detection for 6 address pointers
• Low voltage/CPU operation detection reset (devices with T-suffix)
• Detects low voltage (4.0 V ± 0.3 V) and resets automatically
• Resets automatically when program is runaway and counter is not cleared within interval time
(approx. 262 ms : external 4 MHz)
• Capable of changing input voltage for port
Automotive/CMOS-Schmitt input level (initial level is Automotive in single-chip mode)
• Flash memory security function
Protects the content of Flash memory (MB90F362x, MB90F367x only)
DS07-13746-3E
3
MB90360E Series
■ PRODUCT LINEUP
Features
MB90362E
MB90362TE
Type
MB90V340E- MB90V340E101
102
MB90362ES MB90362TES
MASK ROM product
Evaluation product
2
F MC-16LX CPU
CPU
System clock
PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6)
Sub clock pin
(X0A, X1A)
Yes
No
Clock supervisor
No
Yes
No
ROM
MASK ROM, 64 Kbytes
External
RAM capacitance
3 Kbytes
30 Kbytes
CAN interface
1 channel
3 channels
LIN-UART
Low voltage/CPU
operation
detection reset
2 channels
No
Yes
Package
No
No
LQFP-48P
PGA-299C
⎯
Yes
Emulator-specific
power supply *
Corresponding
evaluation product
Yes
MB90V340E-102
⎯
MB90V340E-101
* : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator
hardware manual for the details.
Features
MB90F362E
MB90F362TE
MB90F362ES
Type
Flash memory product
CPU
F2MC-16LX CPU
PLL clock multiplier
( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns
(4 MHz oscillation clock, PLL × 6)
System clock
Sub clock pin
(X0A, X1A)
Yes
No
Clock supervisor
No
ROM
Flash memory, 64 Kbytes
RAM capacitance
3 Kbytes
CAN interface
1 channel
LIN-UART
2 channels
Low voltage/CPU operation detection reset
No
Yes
Package
Corresponding
evaluation product
4
MB90F362TES
No
Yes
LQFP-48P
MB90V340E-102
MB90V340E-101
DS07-13746-3E
MB90360E Series
Features
MB90367E MB90367TE
Type
MB90367ES
MB90V340E- MB90V340E103
104
MB90367TES
MASK ROM product
Evaluation product
2
CPU
F MC-16LX CPU
PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6)
System clock
Sub clock pin
(X0A, X1A)
Yes
No
Clock supervisor
Yes
Yes
ROM
MASK ROM, 64 Kbytes
External
RAM capacitance
3 Kbytes
30 Kbytes
CAN interface
1 channel
3 channels
LIN-UART
Low voltage/CPU
operation
detection reset
2 channels
No
Yes
Package
No
No
LQFP-48P
PGA-299C
⎯
Yes
Emulator-specific
power supply *
Corresponding
EVA product
Yes
MB90V340E-104
⎯
MB90V340E-103
* : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator
hardware manual for the details.
Features
MB90F367E
MB90F367TE
MB90F367ES
Type
Flash memory product
CPU
F2MC-16LX CPU
PLL clock multiplier
( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns
(4 MHz oscillation clock, PLL × 6)
System clock
Sub clock pin
(X0A, X1A)
Yes
No
Clock supervisor
Yes
ROM
Flash memory, 64 Kbytes
RAM capacitance
3 Kbytes
CAN interface
1 channel
LIN-UART
2 channels
Low voltage/CPU
operation detection reset
No
Yes
Package
Corresponding EVA
product
DS07-13746-3E
MB90F367TES
No
Yes
LQFP-48P
MB90V340E-104
MB90V340E-103
5
MB90360E Series
■ PIN ASSIGNMENT
• MB90F362E/TE/ES/TES, MB90362E/TE/ES/TES, MB90F367E/TE/ES/TES, MB90367E/TE/ES/TES
P86/SOT1
P87/SCK1
P85/SIN1
37
40
38
P43/TX1
41
39
P83/SOT0/TOT2
P42/RX1/INT9R
42
P82/SIN0/INT14R/TIN2
P44/FRCK0
45
P84/SCK0/INT15R
X0A/P40 *1
46
43
X1A/P41 *1
47
44
AVss
48
(TOP VIEW)
AVcc
1
36
P20 *2
AVR
2
35
P21 *2
P60/AN0
3
34
P22/PPGD(C) *2
P61/AN1
4
33
P23/PPGF(E) *2
P62/AN2
5
32
P24/IN0
P63/AN3
6
31
P25/IN1
P64/AN4
7
30
P26/IN2
P65/AN5
8
29
P27/IN3
P66/AN6/PPGC(D)
9
28
X1
17
18
19
20
21
22
23
24
P55/AN13/INT10
P56/AN14/INT11
P57/AN15/INT13
MD2
MD1
MD0
RST
Vcc
Vss
16
25
P54/AN12/TOT3/INT8
12
15
P50/AN8
P53/AN11/TIN3
C
14
X0
26
P52/AN10
27
11
13
10
P51/AN9
P67/AN7/PPGE(F)
P80/ADTG/INT12R
(FPT-48P-M26)
*1 : MB90F362E/TE, MB90362E/TE, MB90F367E/TE, MB90367E/TE
: X0A, X1A
MB90F362ES/TES, MB90362ES/TES, MB90F367ES/TES, MB90367ES/TES : P40, P41
*2 : High current output port
6
DS07-13746-3E
MB90360E Series
■ PIN DESCRIPTION
Pin No.
Pin name
I/O circuit
type*
1
AVCC
I
2
AVR
⎯
3 to 8
P60 to P65
AN0 to AN5
H
P66, P67
9, 10
AN6, AN7
H
P50 to P52
F
H
16
Trigger input pin for A/D converter.
General-purpose I/O port (P50 has different I/O circuit type from
MB90V340E) .
General-purpose I/O port.
H
Analog input pin for A/D converter.
TIN3
Event input pin for reload timer 3.
P54
General-purpose I/O port.
AN12
TOT3
H
INT8
AN13 to AN15
Analog input pin for A/D converter.
Output pin for reload timer 3
External interrupt request input pin for INT8.
P55 to P57
17 to 19
Analog input pins for A/D converter.
Analog input pins for A/D converter.
P53
AN11
Analog input pins for A/D converter.
External interrupt request input pin for INT12.
AN8 to AN10
15
General-purpose I/O port.
General-purpose I/O port.
INT12R
12 to 14
Power (Vref+) input pin for A/D converter.
It should be below VCC.
Output pins for PPG.
P80
ADTG
VCC power input pin for analog circuit.
General-purpose I/O port.
PPGC (D) ,
PPGE (F)
11
Function
General-purpose I/O port.
H
INT10, INT11,
INT13
Analog input pins for A/D converter.
External interrupt request input pins for INT10, INT11, INT13.
20
MD2
D
Input pin for operation mode specification.
21, 22
MD1,
MD0
C
Input pins for operation mode specification.
23
RST
E
Reset input pin.
24
VCC
⎯
Power input pin (3.5 V to 5.5 V) .
25
VSS
⎯
Power input pin (0 V) .
26
C
I
Power supply stabilization capacitor pin. It should be connected
to a higher than or equal to 0.1 µF ceramic condenser.
(Continued)
DS07-13746-3E
7
MB90360E Series
Pin No.
Pin name
27
X0
28
X1
29 to 32
P27 to P24
I/O circuit
type*
A
G
38
39
40
P23, P22
J
P21, P20
P85
SIN1
P87
SCK1
P86
SOT1
P43
TX1
Output pins for PPG.
J
K
F
F
F
RX1
F
F
INT15R
General-purpose I/O port.
Clock I/O pin for LIN-UART1.
General-purpose I/O port.
Serial data output pin for LIN-UART1.
General-purpose I/O port.
TX output pin for CAN1 interface.
RX input pin for CAN1 interface.
Serial data output pin for LIN-UART0.
Output pin for reload timer 2.
P84
SCK0
Serial data input pin for LIN-UART1.
General-purpose I/O port.
TOT2
43
General-purpose I/O port.
External interrupt request input pin for INT9 (Sub) .
P83
SOT0
General-purpose I/O port.
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
High current output port.
General-purpose I/O port.
INT9R
42
General-purpose I/O port.
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
General-purpose I/O port.
The register can be set to select whether to use a pull-up
resistor. This function is enabled in single-chip mode.
High current output port.
P42
41
Oscillation output pin.
Event input pins for input capture 0 to 3.
PPGF (E) ,
PPGD (C)
37
Oscillation input pin.
IN3 to IN0
33, 34
35, 36
Function
General-purpose I/O port.
F
Clock I/O pin for LIN-UART0.
External interrupt request input pin for INT15.
(Continued)
8
DS07-13746-3E
MB90360E Series
(Continued)
Pin No.
Pin name
I/O circuit
type*
P82
44
45
SIN0
INT14R
General-purpose I/O port.
K
Serial data input pin for LIN-UART0.
External interrupt request input pin for INT14.
TIN2
Event input pin for reload timer 2.
P44
General-purpose I/O port
(Different I/O circuit type from MB90V340E) .
F
FRCK0
Free-run timer 0 clock pin.
P40, P41
F
General-purpose I/O port
(Devices with S-suffix and MB90V340E-101/103 only) .
X0A, X1A
B
Oscillation pins for sub clock
(Devices without S-suffix and MB90V340E-102/104 only) .
AVSS
I
VSS power input pin for analog circuit.
46, 47
48
Function
* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
DS07-13746-3E
9
MB90360E Series
■ I/O CIRCUIT TYPE
Type
Circuit
X1
A
Remarks
Oscillation circuit :
High-speed oscillation feedback resistor =
approx. 1 MΩ
Xout
X0
Standby control signal
X1A
B
Oscillation circuit :
Low-speed oscillation feedback resistor =
approx. 10 MΩ
Xout
X0A
Standby control signal
CMOS hysteresis
inputs
• MASK ROM product :
CMOS hysteresis input pin
• Flash memory product :
CMOS input pin
CMOS hysteresis
inputs
• MASK ROM product :
CMOS hysteresis input pin
• Flash memory product :
- CMOS input pin
- No Pull-down
R
C
R
D
Pull-down
resistor
CMOS hysteresis input pin
E
Pull-up
resistor
R
CMOS hysteresis
inputs
(Continued)
10
DS07-13746-3E
MB90360E Series
Type
Circuit
• CMOS level output
• CMOS hysteresis inputs (With the
standby-time input shutdown function)
• Automotive input (With the standbytime input shutdown function)
P-ch
Pout
N-ch
Nout
F
Remarks
R
CMOS hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Pull-up control
Pull-up
resistor
P-ch
P-ch
Pout
• CMOS level output
• CMOS hysteresis inputs (With the
standby-time input shutdown function)
• Automotive input (With the standbytime input shutdown function)
N-ch
Nout
G
R
CMOS hysteresis inputs
Automotive inputs
Standby control for
input shutdown
P-ch
Pout
N-ch
Nout
• CMOS level output
• CMOS hysteresis inputs (With the
standby-time input shutdown function)
• Automotive input (With the standbytime input shutdown function)
• A/D analog input
R
H
CMOS hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
(Continued)
DS07-13746-3E
11
MB90360E Series
(Continued)
Type
Circuit
Remarks
Protection circuit for power supply input
P-ch
I
N-ch
Pull-up control
Pull-up
resistor
P-ch
P-ch
Pout high current output
• CMOS level output
• CMOS hysteresis inputs (With the
standby-time input shutdown function)
• Automotive input (With the standbytime input shutdown function)
N-ch
Nout high current output
J
R
CMOS hysteresis inputs
Automotive inputs
Standby control for
input shutdown
P-ch
Pout
N-ch
Nout
K
• CMOS level output
• CMOS input (With standby-time input
shutdown function)
• Automotive input (With standby-time input shutdown function)
R
CMOS inputs
Automotive inputs
Standby control for
input shutdown
12
DS07-13746-3E
MB90360E Series
■ HANDLING DEVICES
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC pin or lower than VSS pin is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pin and VSS pin.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
Use meticulous care not to exceed the rating.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital
power-supply voltage.
2. Treatment of unused pins
Leaving unused input pins open may result in permanent damage of the device due to misbehavior or latch-up.
Therefore, they must be pulled up or pulled down through resistors. In this case, those resistors should be more
than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90360E Series
X0
Open
X1
4. Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin and leave the
X1A pin open.
5. Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
6. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent malfunction such as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS pins to the device from the current supply source at a low impedance.
DS07-13746-3E
13
MB90360E Series
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC pin and VSS pin in the vicinity of VCC and VSS pins of the device.
VCC
VSS
VCC
VSS
VSS
VCC
MB90360E
Series
VCC
VSS
VSS
VCC
7. Pull-up/down resistors
The MB90360E Series does not support internal pull-up/down resistors (Port 2 : built-in pull-up resistors) . Use
external components where needed.
8. Crystal oscillator circuit
Noises around X0 or X1 pin may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground
area for stabilizing the operation. Please ask the crystal maker to evaluate the oscillational characteristics of the
crystal and this device.
9. Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC and AVR) and analog inputs (AN0 to AN15) after
turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make
sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies
simultaneously is acceptable).
10. Connection of unused pins of A/D converter if A/D converter is not used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR = VSS.
11. Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V) .
14
DS07-13746-3E
MB90360E Series
12. Stabilization of power supply voltage
A sudden change in the power supply voltage may cause the device to malfunction even within the specified
VCC power supply voltage operating guarantee range. Therefore, the VCC power supply voltage should be
stabilized.
For reference, the power supply voltage should be controlled so that VCC ripple variations (peak-to-peak value)
at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard VCC power supply voltage and the
coefficient of transient fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,
turn on the power again.
14. Notes on using CAN function
To use CAN function, please set ’1’ to DIRECT bit of CAN direct mode register (CDMR) .
If DIRECT bit is set to ’0’ (initial value) , wait states will be performed when accessing CAN registers.
Note : Please refer to Hardware Manual of “MB90360E series for detail of CAN Direct Mode Register”.
15. Flash security function
The security bit is located in the area of the Flash memory.
If protection code 01H is written in the security bit, the Flash memory is in the protected state by security.
Therefore, please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security bit.
MB90F362E
MB90F362ES
MB90F362TE
MB90F362TES
MB90F367E
MB90F367ES
MB90F367TE
MB90F367TES
Flash memory size
Address for security bit
Embedded 512 Kbits Flash Memory
FF0001H
16. Correspondence with TA = +105 °C or more
There is a restriction of reliability if the product is used exceeding TA = +105 °C.
Contact the sales or support representative.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and +105 °C.
17. Serial communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of
receiving wrong data due to the noise.
DS07-13746-3E
15
MB90360E Series
■ BLOCK DIAGRAMS
• MB90V340E-101/102
X0, X1
X0A, X1A∗
Clock
controller
F2MC-16LX
core
RST
16-bit
Free-run
timer 0
Input
capture
8 channels
RAM
30 Kbytes
Output
compare
8 channels
16-bit
free-run
timer 1
Prescaler
(5 channels)
AVCC
AVSS
AN23 to AN0
AVRH
AVRL
ADTG
LIN-UART
5 channels
8/10-bit
A/D
converter
24 channels
Internal data bus
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
FRCK0
IN7 to IN0
OUT7 to OUT0
FRCK1
CAN
controller
3 channels
RX2 to RX0
TX2 to TX0
16-bit
reload timer
4 channels
TIN3 to TIN0
TOT3 to TOT0
AD15 to AD00
A23 to A16
ALE
DA01, DA00
10-bit
D/A converter
2 channels
PPGF to PPG0
8/16-bit
PPG
16/8 channels
SDA1, SDA0
SCL1, SCL0
I2C
interface
2 channels
DMA
External
bus
RD
WRL
WRH
HRQ
HAK
RDY
CLK
DTP/
External
interrupt
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
Clock
monitor
CKOT
* : Only for MB90V340E-102
16
DS07-13746-3E
MB90360E Series
• MB90V340E-103/104
X0, X1
X0A, X1A*
RST
Clock
controller/
monitor
F2MC-16LX
Core
16-bit
Free-run
timer 0
CR
oscillator
circuit
Input
capture
8 channels
RAM
30 Kbytes
Output
compare
8 channels
16-bit
free-run
timer 1
Prescaler
(5 channels)
AVCC
AVSS
AN23 to AN0
AVRH
AVRL
ADTG
LIN-UART
5 channels
8/10-bit
A/D
converter
24 channels
Internal data bus
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
FRCK0
IN7 to IN0
OUT7 to OUT0
FRCK1
CAN
controller
3 channels
RX2 to RX0
TX2 to TX0
16-bit
reload timer
4 channels
TIN3 to TIN0
TOT3 to TOT0
AD15 to AD00
A23 to A16
ALE
DA01, DA00
10-bit
D/A converter
2 channels
PPGF to PPG0
8/16-bit
PPG
16/8 channels
SDA1, SDA0
SCL1, SCL0
I2C
interface
2 channels
DMA
External
bus
RD
WRL
WRH
HRQ
HAK
RDY
CLK
DTP/
External
interrupt
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
Clock
monitor
CKOT
* : Only for MB90V340E-104
DS07-13746-3E
17
MB90360E Series
• MB90F362E/TE/ES/TES, MB90362E/TE/ES/TES
X0, X1
X0A, X1A∗1
Clock
controller
F2MC-16LX
core
RST
Input
capture
4 channels
Low voltage/CPU
operation detection *2
RAM
3 Kbytes
Prescaler
(2 channels)
SOT0, SOT1
SCK0, SCK1
SIN0, SIN1
AVCC
AVSS
AN15 to AN0
AVR
LIN-UART
2 channels
Internal data bus
ROM
64 Kbytes
IN0 to IN3
16-bit
free-run
timer 0
FRCK0
CAN
controller
1 channel
RX1
TX1
16-bit
reload
timer
2 channels
TIN2, TIN3
TOT2, TOT3
8/10-bit
A/D
converter
16 channels
ADTG
PPGF(E), PPGD(C),
PPGC(D), PPGE(F)
8/16-bit
PPG
4/2 channels
DTP/
External
interrupt
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
*1 : Only for devices without S-suffix
*2 : Only for devices with T-suffix
18
DS07-13746-3E
MB90360E Series
• MB90F367E/TE/ES/TES, MB90367E/TE/ES/TES
X0, X1
X0A, X1A*1
RST
Clock
controller/
monitor
F2MC-16LX
Core
CR
oscillator
circuit
Low voltage/CPU
operation detection *2
RAM
3 Kbytes
Prescaler
(2 channels)
SOT0, SOT1
SCK0, SCK1
SIN0, SIN1
AVCC
AVSS
AN15 to AN0
AVR
LIN-UART
2 channels
Internal data bus
ROM
64 Kbytes
Input
capture
4 channels
IN0 to IN3
16-bit
free-run
timer 0
FRCK0
CAN
controller
1 channel
RX1
TX1
16-bit
reload
timer
2 channels
TIN2, TIN3
TOT2, TOT3
DTP/
External
interrupt
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
8/10-bit
A/D
converter
16 channels
ADTG
PPGF(E), PPGD(C),
PPGC(D), PPGE(F)
8/16-bit
PPG
4/2 channels
*1 : Only for devices without S-suffix
*2 : Only for devices with T-suffix
DS07-13746-3E
19
MB90360E Series
■ MEMORY MAP
MB90F362E/TE/ES/TES
MB90362E/TE/ES/TES
MB90F367E/TE/ES/TES
MB90367E/TE/ES/TES
MB90V340E-101/102
MB90V340E-103/104
FFFFFFH
FFFFFFH
ROM (FF bank)
FF0000H
FEFFFFH
FF0000H
FEFFFFH
ROM (FF bank)
ROM (FE bank)
FE0000H
FDFFFFH
ROM (FD bank)
FD0000H
FCFFFFH
ROM (FC bank)
FC0000H
FBFFFFH
ROM (FB bank)
FB0000H
FAFFFFH
ROM (FA bank)
FA0000H
F9FFFFH
ROM (F9 bank)
F90000H
F8FFFFH
ROM (F8 bank)
F80000H
External access area
00FFFFH
008000H
007FFFH
007900H
0078FFH
ROM (image
of FF bank)
Peripheral
010000H
00FFFFH
008000H
007FFFH
007900H
ROM (image
of FF bank)
Peripheral
RAM 30 Kbytes
000100H
External access area
0000EFH
000000H
Peripheral
000CFFH
000100H
0000FFH
0000F0H
0000EFH
000000H
RAM 3 Kbytes
Peripheral
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referred without using
the far specification in the pointer declaration.
For example, an attempt to access 00C000H practically accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
20
DS07-13746-3E
MB90360E Series
■ I/O MAP
Address
Register
Abbreviation
Access
Resource name
Initial value
R/W
Port 2
XXXXXXXXB
000000H,
000001H
Reserved
000002H Port 2 Data Register
PDR2
000003H
Reserved
000004H Port 4 Data Register
PDR4
R/W
Port 4
XXXXXXXXB
000005H Port 5 Data Register
PDR5
R/W
Port 5
XXXXXXXXB
000006H Port 6 Data Register
PDR6
R/W
Port 6
XXXXXXXXB
000007H
Reserved
000008H Port 8 Data Register
PDR8
R/W
Port 8
XXXXXXXXB
000009H,
00000AH
Reserved
00000BH Port 5 Analog Input Enable Register
ADER5
R/W
Port 5, A/D
11111111B
00000CH Port 6 Analog Input Enable Register
ADER6
R/W
Port 6, A/D
11111111B
00000DH
Reserved
00000EH Input Level Select Register
ILSR0
R/W
Ports
XXXX0XXXB
00000FH Input Level Select Register
ILSR1
R/W
Ports
XXXXXXXXB
R/W
Port 2
00000000B
000010H,
000011H
Reserved
000012H Port 2 Direction Register
DDR2
000013H
Reserved
000014H Port 4 Direction Register
DDR4
R/W
Port 4
XXX00000B
000015H Port 5 Direction Register
DDR5
R/W
Port 5
00000000B
000016H Port 6 Direction Register
DDR6
R/W
Port 6
00000000B
000017H
Reserved
000018H Port 8 Direction Register
DDR8
R/W
Port 8
000000X0B
000019H
Reserved
W
Port A
XXX00XXXB
R/W
Port 2
00000000B
00001AH Port A Direction Register
00001BH
to
00001DH
00001EH Port 2 Pull-up Control Register
00001FH
DDRA
Reserved
PUCR2
Reserved
(Continued)
DS07-13746-3E
21
MB90360E Series
Abbreviation
Access
000020H Serial Mode Register 0
SMR0
W, R/W
00000000B
000021H Serial Control Register 0
SCR0
W, R/W
00000000B
000022H Reception/Transmission Data Register 0
RDR0/
TDR0
R/W
00000000B
000023H Serial Status Register 0
SSR0
R, R/W
ECCR0
R, W,
R/W
000025H Extended Status/Control Register 0
ESCR0
R/W
00000100B
000026H Baud Rate Generator Register 00
BGR00
R/W, R
00000000B
000027H Baud Rate Generator Register 01
BGR01
R/W, R
00000000B
000028H Serial Mode Register 1
SMR1
W, R/W
00000000B
000029H Serial Control Register 1
SCR1
W, R/W
00000000B
00002AH Reception/Transmission Data Register 1
RDR1/
TDR1
R/W
00000000B
00002BH Serial Status Register 1
SSR1
R, R/W
ECCR1
R, W,
R/W
00002DH Extended Status/Control Register 1
ESCR1
R/W
00000100B
00002EH Baud Rate Generator Register 10
BGR10
R/W, R
00000000B
00002FH Baud Rate Generator Register 11
BGR11
R/W, R
00000000B
Address
000024H
00002CH
Register
Extended Communication Control
Register 0
Extended Communication Control
Register 1
000030H
to
00003AH
Resource name
LIN-UART0
Initial value
00001000B
000000XXB
LIN-UART1
00001000B
000000XXB
Reserved
00003BH Address Detect Control Register 1
00003CH
to
000047H
PACSR1
R/W
Address Match
Detection 1
00000000B
Reserved
000048H PPG C Operation Mode Control Register
PPGCC
W, R/W
000049H PPG D Operation Mode Control Register
PPGCD
W, R/W
PPGCD
R/W
000000X0B
0X000XX1B
00004AH
PPG C/PPG D Count Clock Select
Register
00004BH
PPGCE
W, R/W
00004DH PPG F Operation Mode Control Register
PPGCF
W, R/W
PPGEF
R/W
00004FH
16-bit PPG C/D
0X000001B
Reserved
00004CH PPG E Operation Mode Control Register
00004EH
0X000XX1B
PPG E/PPG F Count Clock Select
Register
16-bit PPG E/F
0X000001B
000000X0B
Reserved
(Continued)
22
DS07-13746-3E
MB90360E Series
Abbreviation
Access
000050H Input Capture Control Status 0/1
ICS01
R/W
000051H Input Capture Edge 0/1
ICE01
R/W, R
000052H Input Capture Control Status 2/3
ICS23
R/W
000053H Input Capture Edge 2/3
ICE23
R
Address
Register
000054H
to
000063H
Resource name
Input Capture 0/1
Input Capture 2/3
Initial value
00000000B
XXX0X0XXB
00000000B
XXXXXXXXB
Reserved
000064H Timer Control Status 2
TMCSR2
R/W
000065H Timer Control Status 2
TMCSR2
R/W
000066H Timer Control Status 3
TMCSR3
R/W
000067H Timer Control Status 3
TMCSR3
R/W
000068H A/D Control Status 0
ADCS0
R/W
000XXXX0B
000069H A/D Control Status 1
ADCS1
R/W, W
0000000XB
00006AH A/D Data 0
ADCR0
R
00006BH A/D Data 1
ADCR1
R
00006CH ADC Setting 0
ADSR0
R/W
00000000B
00006DH ADC Setting 1
ADSR1
R/W
00000000B
LVRC
R/W, W
Low voltage/CPU
operation detection
reset
00111000B
ROMM
W
ROM Mirror
XXXXXXX1B
00006EH
Low Voltage/CPU Operation Detection
Reset Control Register
00006FH ROM Mirror Function Select
16-bit Reload Timer
2
16-bit Reload Timer
3
A/D Converter
000070H
to
00007FH
Reserved
000080H
to
00008FH
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
000090H
to
00009DH
Reserved
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXXXX00B
00009EH Address Detect Control Register 0
PACSR0
R/W
Address Match
Detection 0
00000000B
00009FH Delayed Interrupt/Release Register
DIRR
R/W
Delayed Interrupt
generation module
XXXXXXX0B
LPMCR
W, R/W
Low-Power
consumption
Control Circuit
00011000B
CKSCR
R, R/W
Low-Power
consumption
Control Circuit
11111100B
0000A0H
Low-power Consumption Mode
Control Register
0000A1H Clock Selection Register
(Continued)
DS07-13746-3E
23
MB90360E Series
Address
Register
0000A2H
to
0000A7H
Abbreviation
Access
Resource name
Initial value
Reserved
0000A8H Watchdog Control Register
WDTC
R, W
Watchdog Timer
XXXXX111B
0000A9H Timebase Timer Control Register
TBTC
W, R/W
Timebase Timer
1XX00100B
0000AAH Watch Timer Control register
WTC
R, R/W
Watch Timer
1X001000B
Flash Memory
000X0000B
0000ABH
to
0000ADH
0000AEH
Reserved
Flash Control Status
(Flash Devices only.
Otherwise reserved)
0000AFH
FMCS
R, R/W
Reserved
0000B0H Interrupt Control Register 00
ICR00
W, R/W
00000111B
0000B1H Interrupt Control Register 01
ICR01
W, R/W
00000111B
0000B2H Interrupt Control Register 02
ICR02
W, R/W
00000111B
0000B3H Interrupt Control Register 03
ICR03
W, R/W
00000111B
0000B4H Interrupt Control Register 04
ICR04
W, R/W
00000111B
0000B5H Interrupt Control Register 05
ICR05
W, R/W
00000111B
0000B6H Interrupt Control Register 06
ICR06
W, R/W
00000111B
0000B7H Interrupt Control Register 07
ICR07
W, R/W
0000B8H Interrupt Control Register 08
ICR08
W, R/W
0000B9H Interrupt Control Register 09
ICR09
W, R/W
00000111B
0000BAH Interrupt Control Register 10
ICR10
W, R/W
00000111B
0000BBH Interrupt Control Register 11
ICR11
W, R/W
00000111B
0000BCH Interrupt Control Register 12
ICR12
W, R/W
00000111B
0000BDH Interrupt Control Register 13
ICR13
W, R/W
00000111B
0000BEH Interrupt Control Register 14
ICR14
W, R/W
00000111B
0000BFH Interrupt Control Register 15
ICR15
W, R/W
00000111B
0000C0H
to
0000C9H
Interrupt Control
00000111B
00000111B
Reserved
0000CAH External Interrupt Enable 1
ENIR1
R/W
00000000B
0000CBH External Interrupt Source 1
EIRR1
R/W
XXXXXXXXB
ELVR1
R/W
0000CEH External Interrupt Source Select
EISSR
R/W
0000CFH PLL/Sub clock Control Register
PSCCR
W
0000CCH
0000CDH
Detection Level Setting 1
External Interrupt 1
00000000B
00000000B
00000000B
PLL
XXXX0000B
(Continued)
24
DS07-13746-3E
MB90360E Series
Address
Register
Abbreviation
Access
0000D0H
to
0000FFH
Reserved
007900H
to
007917H
Reserved
Resource name
Initial value
007918H Reload Register LC
PRLLC
R/W
007919H Reload Register HC
PRLHC
R/W
00791AH Reload Register LD
PRLLD
R/W
00791BH Reload Register HD
PRLHD
R/W
XXXXXXXXB
00791CH Reload Register LE
PRLLE
R/W
XXXXXXXXB
00791DH Reload Register HE
PRLHE
R/W
00791EH Reload Register LF
PRLLF
R/W
00791FH Reload Register HF
PRLHF
R/W
XXXXXXXXB
007920H Input Capture 0
IPCP0
R
XXXXXXXXB
007921H Input Capture 0
IPCP0
R
007922H Input Capture 1
IPCP1
R
007923H Input Capture 1
IPCP1
R
XXXXXXXXB
007924H Input Capture 2
IPCP2
R
XXXXXXXXB
007925H Input Capture 2
IPCP2
R
007926H Input Capture 3
IPCP3
R
007927H Input Capture 3
IPCP3
R
XXXXXXXXB
00000000B
007928H
to
00793FH
TCDT0
R/W
007941H Timer Data 0
TCDT0
R/W
007942H Timer Control Status 0
TCCSL0
R/W
007943H Timer Control Status 0
TCCSH0
R/W
007944H
to
00794BH
00794DH
00794EH
00794FH
16-bit PPG C/D
16-bit PPG E/F
Input Capture 0/1
Input Capture 2/3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
007940H Timer Data 0
00794CH
XXXXXXXXB
Free-run Timer 0
00000000B
00000000B
0XXXXXXXB
Reserved
Timer 2/Reload 2
TMR2/
TMRLR2
Timer 3/Reload 3
TMR3/
TMRLR3
007950H
to
00795FH
R/W
R/W
R/W
R/W
16-bit Reload
Timer 2
XXXXXXXXB
16-bit Reload
Timer 3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
(Continued)
DS07-13746-3E
25
MB90360E Series
Address
007960H
Register
Clock Supervisor Control
Register
007961H
to
00796DH
00796EH
Abbreviation
Access
Resource name
Initial value
CSVCR
R, R/W
Clock supervisor
00011100B
CAN clock sync
XXXXXXX0B
Reserved
CAN Direct Mode Register
(MB90V340E only)
00796FH
to
0079DFH
CDMR
R/W
Reserved
0079E0H Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E1H Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E2H Detect Address Setting 0
PADR0
R/W
XXXXXXXXB
0079E3H Detect Address Setting 1
PADR1
R/W
XXXXXXXXB
Address Match
Detection 0
0079E4H Detect Address Setting 1
PADR1
R/W
0079E5H Detect Address Setting 1
PADR1
R/W
XXXXXXXXB
0079E6H Detect Address Setting 2
PADR2
R/W
XXXXXXXXB
0079E7H Detect Address Setting 2
PADR2
R/W
XXXXXXXXB
0079E8H Detect Address Setting 2
PADR2
R/W
XXXXXXXXB
0079E9H
to
0079EFH
XXXXXXXXB
Reserved
0079F0H Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F1H Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F2H Detect Address Setting 3
PADR3
R/W
XXXXXXXXB
0079F3H Detect Address Setting 4
PADR4
R/W
XXXXXXXXB
Address Match
Detection 1
0079F4H Detect Address Setting 4
PADR4
R/W
0079F5H Detect Address Setting 4
PADR4
R/W
XXXXXXXXB
0079F6H Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F7H Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F8H Detect Address Setting 5
PADR5
R/W
XXXXXXXXB
0079F9H
to
007BFFH
Reserved
007C00H
to
007CFFH
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
007D00H
to
007DFFH
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
XXXXXXXXB
(Continued)
26
DS07-13746-3E
MB90360E Series
(Continued)
Address
007E00H
to
007FFFH
Register
Abbreviation
Access
Resource name
Initial value
Reserved
Notes : • Initial value of “X” represents unknown value.
• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
DS07-13746-3E
27
MB90360E Series
■ CAN CONTROLLERS
• Conforms to CAN Specification Ver 2.0 Part A and Part B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmitting of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
• 2 acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 kbps/s to 2 Mbps/s (when input clock is at 16 MHz)
List of Control Registers (1)
Address
CAN1
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
28
Register
Abbreviation
Access
Initial Value
Message buffer valid register
BVALR
R/W
00000000 00000000B
Transmit request register
TREQR
R/W
00000000 00000000B
Transmit cancel register
TCANR
W
00000000 00000000B
Transmission complete register
TCR
R/W
00000000 00000000B
Receive complete register
RCR
R/W
00000000 00000000B
Remote request receiving
register
RRTRR
R/W
00000000 00000000B
Receive overrun register
ROVRR
R/W
00000000 00000000B
Reception interrupt enable
register
RIER
R/W
00000000 00000000B
DS07-13746-3E
MB90360E Series
List of Control Registers (2)
Address
CAN1
007D00H
007D01H
007D02H
007D03H
007D04H
007D05H
007D06H
007D07H
007D08H
007D09H
007D0AH
007D0BH
007D0CH
007D0DH
007D0EH
007D0FH
Register
Abbreviation
Access
Initial Value
Control status register
CSR
R/W, W
R/W, R
0XXXX0X1 00XXX000B
Last event indicator register
LEIR
R/W
000X0000 XXXXXXXXB
Receive and transmit error
counter
RTEC
R
00000000 00000000B
Bit timing register
BTR
R/W
11111111 X1111111B
IDE register
IDER
R/W
XXXXXXXX XXXXXXXXB
Transmit RTR register
TRTRR
R/W
00000000 00000000B
Remote frame receive
waiting register
RFWTR
R/W
XXXXXXXX XXXXXXXXB
Transmit interrupt enable
register
TIER
R/W
00000000 00000000B
007D10H
007D11H
007D12H
XXXXXXXX XXXXXXXXB
Acceptance mask select
register
AMSR
R/W
XXXXXXXX XXXXXXXXB
007D13H
007D14H
007D15H
007D16H
XXXXXXXX XXXXXXXXB
Acceptance mask register 0
AMR0
R/W
XXXXXXXX XXXXXXXXB
007D17H
007D18H
007D19H
007D1AH
007D1BH
DS07-13746-3E
XXXXXXXX XXXXXXXXB
Acceptance mask register 1
AMR1
R/W
XXXXXXXX XXXXXXXXB
29
MB90360E Series
List of Message Buffers (ID Registers)
Address
CAN1
007C00H
to
007C1FH
Register
Abbreviation
Access
Initial Value
General-purpose RAM
⎯
R/W
XXXXXXXXB
to
XXXXXXXXB
007C20H
007C21H
007C22H
XXXXXXXX XXXXXXXXB
ID register 0
IDR0
R/W
XXXXXXXX XXXXXXXXB
007C23H
007C24H
007C25H
007C26H
XXXXXXXX XXXXXXXXB
ID register 1
IDR1
R/W
XXXXXXXX XXXXXXXXB
007C27H
007C28H
007C29H
007C2AH
XXXXXXXX XXXXXXXXB
ID register 2
IDR2
R/W
XXXXXXXX XXXXXXXXB
007C2BH
007C2CH
007C2DH
007C2EH
XXXXXXXX XXXXXXXXB
ID register 3
IDR3
R/W
XXXXXXXX XXXXXXXXB
007C2FH
007C30H
007C31H
007C32H
XXXXXXXX XXXXXXXXB
ID register 4
IDR4
R/W
XXXXXXXX XXXXXXXXB
007C33H
007C34H
007C35H
007C36H
XXXXXXXX XXXXXXXXB
ID register 5
IDR5
R/W
XXXXXXXX XXXXXXXXB
007C37H
007C38H
007C39H
007C3AH
XXXXXXXX XXXXXXXXB
ID register 6
IDR6
R/W
XXXXXXXX XXXXXXXXB
007C3BH
007C3CH
007C3DH
007C3EH
007C3FH
XXXXXXXX XXXXXXXXB
ID register 7
IDR7
R/W
XXXXXXXX XXXXXXXXB
(Continued)
30
DS07-13746-3E
MB90360E Series
(Continued)
Address
CAN1
Register
Abbreviation
Access
007C40H
007C41H
007C42H
XXXXXXXX XXXXXXXXB
ID register 8
IDR8
R/W
XXXXXXXX XXXXXXXXB
007C43H
007C44H
007C45H
007C46H
XXXXXXXX XXXXXXXXB
ID register 9
IDR9
R/W
XXXXXXXX XXXXXXXXB
007C47H
007C48H
007C49H
007C4AH
XXXXXXXX XXXXXXXXB
ID register 10
IDR10
R/W
XXXXXXXX XXXXXXXXB
007C4BH
007C4CH
007C4DH
007C4EH
XXXXXXXX XXXXXXXXB
ID register 11
IDR11
R/W
XXXXXXXX XXXXXXXXB
007C4FH
007C50H
007C51H
007C52H
XXXXXXXX XXXXXXXXB
ID register 12
IDR12
R/W
XXXXXXXX XXXXXXXXB
007C53H
007C54H
007C55H
007C56H
XXXXXXXX XXXXXXXXB
ID register 13
IDR13
R/W
XXXXXXXX XXXXXXXXB
007C57H
007C58H
007C59H
007C5AH
XXXXXXXX XXXXXXXXB
ID register 14
IDR14
R/W
XXXXXXXX XXXXXXXXB
007C5BH
007C5CH
007C5DH
007C5EH
007C5FH
DS07-13746-3E
Initial Value
XXXXXXXX XXXXXXXXB
ID register 15
IDR15
R/W
XXXXXXXX XXXXXXXXB
31
MB90360E Series
List of Message Buffers (DLC Registers and Data Registers)
Address
CAN1
007C60H
007C61H
007C62H
007C63H
007C64H
007C65H
007C66H
007C67H
007C68H
007C69H
007C6AH
007C6BH
007C6CH
007C6DH
007C6EH
007C6FH
007C70H
007C71H
007C72H
007C73H
007C74H
007C75H
007C76H
007C77H
007C78H
007C79H
007C7AH
007C7BH
007C7CH
007C7DH
007C7EH
007C7FH
Register
Abbreviation
Access
Initial Value
DLC register 0
DLCR0
R/W
XXXXXXXXB
DLC register 1
DLCR1
R/W
XXXXXXXXB
DLC register 2
DLCR2
R/W
XXXXXXXXB
DLC register 3
DLCR3
R/W
XXXXXXXXB
DLC register 4
DLCR4
R/W
XXXXXXXXB
DLC register 5
DLCR5
R/W
XXXXXXXXB
DLC register 6
DLCR6
R/W
XXXXXXXXB
DLC register 7
DLCR7
R/W
XXXXXXXXB
DLC register 8
DLCR8
R/W
XXXXXXXXB
DLC register 9
DLCR9
R/W
XXXXXXXXB
DLC register 10
DLCR10
R/W
XXXXXXXXB
DLC register 11
DLCR11
R/W
XXXXXXXXB
DLC register 12
DLCR12
R/W
XXXXXXXXB
DLC register 13
DLCR13
R/W
XXXXXXXXB
DLC register 14
DLCR14
R/W
XXXXXXXXB
DLC register 15
DLCR15
R/W
XXXXXXXXB
(Continued)
32
DS07-13746-3E
MB90360E Series
Address
Register
Abbreviation
Access
Initial Value
007C80H
to
007C87H
Data register 0
(8 bytes)
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
007C88H
to
007C8FH
Data register 1
(8 bytes)
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
007C90H
to
007C97H
Data register 2
(8 bytes)
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
007C98H
to
007C9FH
Data register 3
(8 bytes)
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
007CA0H
to
007CA7H
Data register 4
(8 bytes)
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
007CA8H
to
007CAFH
Data register 5
(8 bytes)
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
007CB0H
to
007CB7H
Data register 6
(8 bytes)
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
007CB8H
to
007CBFH
Data register 7
(8 bytes)
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
007CC0H
to
007CC7H
Data register 8
(8 bytes)
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
007CC8H
to
007CCFH
Data register 9
(8 bytes)
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
007CD0H
to
007CD7H
Data register 10
(8 bytes)
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
007CD8H
to
007CDFH
Data register 11
(8 bytes)
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
007CE0H
to
007CE7H
Data register 12
(8 bytes)
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
007CE8H
to
007CEFH
Data register 13
(8 bytes)
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN1
(Continued)
DS07-13746-3E
33
MB90360E Series
(Continued)
Address
Register
Abbreviation
Access
Initial Value
007CF0H
to
007CF7H
Data register 14
(8 bytes)
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
007CF8H
to
007CFFH
Data register 15
(8 bytes)
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN1
34
DS07-13746-3E
MB90360E Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause
EI2OS
corresponding
Interrupt vector
Interrupt control
register
Number
Address
Number
Address
Reset
N
#08
FFFFDCH
⎯
⎯
INT9 instruction
N
#09
FFFFD8H
⎯
⎯
Exception
N
#10
FFFFD4H
⎯
⎯
Reserved
N
#11
FFFFD0H
Reserved
N
#12
FFFFCCH
ICR00
0000B0H
CAN 1 reception
N
#13
FFFFC8H
CAN 1 transmission/node status
N
#14
FFFFC4H
ICR01
0000B1H
Reserved
N
#15
FFFFC0H
Reserved
N
#16
FFFFBCH
ICR02
0000B2H
Reserved
N
#17
FFFFB8H
Reserved
N
#18
FFFFB4H
ICR03
0000B3H
16-bit reload timer 2
Y1
#19
FFFFB0H
16-bit reload timer 3
Y1
#20
FFFFACH
ICR04
0000B4H
Reserved
N
#21
FFFFA8H
Reserved
N
#22
FFFFA4H
ICR05
0000B5H
PPG C/D
N
#23
FFFFA0H
PPG E/F
N
#24
FFFF9CH
ICR06
0000B6H
Timebase timer
N
#25
FFFF98H
External interrupt 8 to 11
Y1
#26
FFFF94H
ICR07
0000B7H
Watch timer
N
#27
FFFF90H
External interrupt 12 to 15
Y1
#28
FFFF8CH
ICR08
0000B8H
A/D converter
Y1
#29
FFFF88H
16-bit free-run timer 0
N
#30
FFFF84H
ICR09
0000B9H
Reserved
N
#31
FFFF80H
Reserved
N
#32
FFFF7CH
ICR10
0000BAH
Input capture 0 to 3
Y1
#33
FFFF78H
Reserved
N
#34
FFFF74H
ICR11
0000BBH
LIN-UART 0 reception
Y2
#35
FFFF70H
LIN-UART 0 transmission
Y1
#36
FFFF6CH
ICR12
0000BCH
LIN-UART 1 reception
Y2
#37
FFFF68H
LIN-UART 1 transmission
Y1
#38
FFFF64H
ICR13
0000BDH
(Continued)
DS07-13746-3E
35
MB90360E Series
(Continued)
Interrupt cause
EI2OS
corresponding
Interrupt vector
Number
Address
Reserved
N
#39
FFFF60H
Reserved
N
#40
FFFF5CH
Flash memory
N
#41
FFFF58H
Delayed interrupt generation module
N
#42
FFFF54H
Interrupt control
register
Number
Address
ICR14
0000BEH
ICR15
0000BFH
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When the peripheral resources sharing the ICR register use extended intelligent I/O service, only one
can use extended intelligent I/O service at a time.
• When either of the 2 peripheral resources sharing the ICR register specifies extended intelligent I/O
service, the other one cannot use interrupts.
36
DS07-13746-3E
MB90360E Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage*1
Input voltage*1
Output voltage*
1
Maximum clamp current
Total Maximum clamp current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
Symbol
“H” level average output current
“H” level maximum overall output current
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
VCC = AVCC*2
AVR
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVR*2
VI
VSS − 0.3
VSS + 6.0
V
*3
VO
VSS − 0.3
VSS + 6.0
V
*3
ICLAMP
−2.0
+2.0
mA
*6
Σ|ICLAMP|
⎯
40
mA
*6
IOL1
⎯
15
mA
*4
IOL2
⎯
40
mA
*5
IOLAV1
⎯
4
mA
*4
IOLAV2
⎯
30
mA
*5
ΣIOL1
⎯
125
mA
*4
ΣIOL2
⎯
160
mA
*5
⎯
40
mA
⎯
40
mA
IOH1
⎯
−15
mA
*4
IOH2
⎯
−40
mA
*5
IOHAV1
⎯
−4
mA
*4
IOHAV2
⎯
−30
mA
*5
ΣIOH1
⎯
−125
mA
*4
ΣIOH2
⎯
−160
mA
*5
⎯
−40
mA
⎯
−40
mA
⎯
308
mW
Flash memory updata not
performed
⎯
390
mW
Flash memory updata
performed
−40
+105
°C
−40
+125
°C
−55
+150
°C
ΣIOLAV2
ΣIOLAV1
ΣIOHAV1
“H” level average overall output current
ΣIOHAV2
ΣIOHAV1
ΣIOHAV2
Power consumption
Operating temperature
Storage temperature
Remarks
Max
ΣIOLAV2
“H” level maximum output current
Unit
Min
ΣIOLAV1
“L” level average overall output current
Rating
PD
TA
TSTG
*4 +105 °C < TA ≤ +125 °C
*5 +105 °C < TA ≤ +125 °C
*4 −40 °C ≤ TA ≤ +105 °C
*5 −40 °C ≤ TA ≤ +105 °C
*4 +105 °C < TA ≤ +125 °C
*5 +105 °C < TA ≤ +125 °C
*4 −40 °C ≤ TA ≤ +105 °C
*5 −40 °C ≤ TA ≤ +105 °C
*7
(Continued)
DS07-13746-3E
37
MB90360E Series
(Continued)
*1 : This parameter is based on VSS = AVSS = 0 V.
*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However, if the maximun
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*4 : Applicable to pins : P24 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87
*5 : Applicable to pins : P20 to P23
*6 : Applicable to pins : P20 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied a connecting limit resistance between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is inputted when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Recommended circuit sample :
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
*7 : There is a restriction of reliability if the product is used exceeding TA = +105 °C.
Contact the sales or support representative.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and +105 °C.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
38
DS07-13746-3E
MB90360E Series
2. Recommended Conditions
(VSS = AVSS = 0 V)
Parameter
Power supply voltage
Symbol
VCC,
AVCC
Smoothing capacitor
CS
Operating temperature
TA
Value
Unit
Remarks
Min
Typ
Max
4.0
5.0
5.5
V
Under normal operation
3.5
5.0
5.5
V
Under normal operation when not
using the A/D converter and not
Flash programming.
3.0
⎯
5.5
V
Maintains RAM data in stop mode
Use a ceramic capacitor or comparable capacitor of the AC characteristics. Bypass capacitor at the
VCC pin should be greater than this
capacitor.
0.1
⎯
1.0
µF
−40
⎯
+105
°C
−40
⎯
+125
°C
*
* : There is a restriction of reliability if the product is used exceeding TA = +105 °C.
Contact the sales or support representative.
It is ensured to write/erase data to the Flash memory between TA = − 40 °C and +105 °C.
• C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-13746-3E
39
MB90360E Series
3. DC Characteristics
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Condition
Value
Min
Typ
Max
Unit
Remarks
VIHS
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
Pin inputs if CMOS
hysteresis input levels
are selected (except
P82, P85)
VIHA
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
Pin inputs if
Automotive input
levels are selected
VIHS
⎯
⎯
0.7 VCC
⎯
VCC + 0.3
V
P82, P85 inputs if
CMOS input levels are
selected
VIHR
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
RST input pin (CMOS
hysteresis)
VIHM
⎯
⎯
VCC − 0.3
⎯
VCC + 0.3
V
MD input pin
Input “H”
voltage
VILS
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
Pin inputs if CMOS
hysteresis input levels
are selected (except
P82, P85)
VILA
⎯
⎯
VSS − 0.3
⎯
0.5 VCC
V
Pin inputs if
Automotive input
levels are selected
VILS
⎯
⎯
VSS − 0.3
⎯
0.3 VCC
V
P82, P85 inputs if
CMOS input levels are
selected
VILR
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
RST input pin (CMOS
hysteresis)
VILM
⎯
⎯
VSS − 0.3
⎯
VSS + 0.3
V
MD input pin
VCC − 0.5
⎯
⎯
V
VCC = 4.5 V,
VCC − 0.5
IOH = −14.0 mA
⎯
⎯
V
⎯
⎯
0.4
V
Input “L”
voltage
VOH
Other than VCC = 4.5 V,
P20 to P23 IOH = −4.0 mA
VOHI
P20 to P23
VOL
Other than VCC = 4.5 V,
P20 to P23 IOL = 4.0 mA
VOLI
P20 to P23
VCC = 4.5 V,
IOL = 20.0 mA
⎯
⎯
0.4
V
Input leak
current
IIL
⎯
VCC = 5.5 V,
VSS < VI < VCC
−1
⎯
+1
µA
Pull-up
resistance
RUP
P20 to P27,
RST
25
50
100
kΩ
Output “H”
voltage
Output “L”
voltage
⎯
(Continued)
40
DS07-13746-3E
MB90360E Series
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Parameter
Pull-down
resistance
Symbol
RDOWN
Pin
MD2
Condition
⎯
Value
Min
Typ
Max
Unit
Remarks
MB90362E,
MB90362ES,
MB90362TE,
MB90362TES
25
50
100
kΩ
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
⎯
35
45
mA
VCC = 5.0 V,
Internal frequency : 24 MHz,
At writing Flash memory.
⎯
50
60
mA
Flash memory
devices
VCC = 5.0 V,
Internal frequency : 24 MHz,
At erasing Flash memory.
⎯
50
60
mA
Flash memory
devices
ICCS
VCC = 5.0 V,
Internal frequency : 24 MHz,
At sleep mode.
⎯
12
20
mA
⎯
0.3
0.8
ICTS
VCC = 5.0 V,
Internal frequency : 2 MHz,
At main timer mode
⎯
0.4
1.0
⎯
4
7
ICC
VCC = 5.0 V,
Internal frequency : 24 MHz,
At PLL timer mode,
External frequency = 4 MHz
ICTSPLL6
Power supply
current*
mA
ICCL
ICCLS
VCC = 5.0 V
Internal frequency :
8 kHz,
At sub sleep,
TA = +25°C
Devices with
T-suffix
mA
VCC
VCC = 5.0 V
Internal frequency :
8 kHz,
At sub operation,
TA = +25°C
Devices without
T-suffix
Stopping clock
supervisor
⎯
40
100
MB90F362E,
MB90F367E,
MB90362E,
MB90367E
Operating clock
supervisor
⎯
60
150
MB90F367E,
MB90367E
µA
Stopping clock
supervisor
⎯
90
200
MB90F362TE,
MB90F367TE,
MB90362TE,
MB90367TE
Operating clock
supervisor
⎯
110
250
MB90F367TE,
MB90367TE
Stopping clock
supervisor
⎯
10
50
MB90F362E,
MB90F367E,
MB90362E,
MB90367E
Operating clock
supervisor
⎯
30
100
MB90F367E,
MB90367E
µA
Stopping clock
supervisor
⎯
60
150
MB90F362TE,
MB90F367TE,
MB90362TE,
MB90367TE
Operating clock
supervisor
⎯
80
200
MB90F367TE,
MB90367TE
(Continued)
DS07-13746-3E
41
MB90360E Series
(Continued)
Parameter
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Symbol
Pin
ICCT
Power supply
current*
VCC
CIN
VCC = 5.0 V
Internal frequency :
8 kHz,
At watch mode,
TA = +25°C
Other than
AVCC,
AVSS, AVR,
VCC, VSS, C
Value
Min
Typ
Max
Unit
Remarks
Stopping clock
supervisor
⎯
8
30
MB90F362E,
MB90F367E,
MB90362E,
MB90367E
Operating clock
supervisor
⎯
30
70
MB90F367E,
MB90367E
µA
Stopping clock
supervisor
⎯
60
130
MB90F362TE,
MB90F367TE,
MB90362TE,
MB90367TE
Operating clock
supervisor
⎯
80
170
MB90F367TE,
MB90367TE
⎯
5
25
µA
Devices without
T-suffix
⎯
50
130
µA
Devices with
T-suffix
⎯
5
15
pF
VCC = 5.0 V,
At stop mode, TA = +25°C
ICCH
Input capacity
Condition
⎯
* : The power supply current is measured with an external clock.
42
DS07-13746-3E
MB90360E Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Value
Unit
Remarks
16
MHz
1/2 when PLL stops,
When using an oscillation circuit
⎯
16
MHz
PLL × 1,
When using an oscillation circuit
4
⎯
12
MHz
PLL × 2,
When using an oscillation circuit
4
⎯
8
MHz
PLL × 3,
When using an oscillation circuit
4
⎯
6
MHz
PLL × 4,
When using an oscillation circuit
4
⎯
4
MHz
PLL × 6,
When using an oscillation circuit
3
⎯
24
MHz
1/2 when PLL stops,
When using an external clock
4
⎯
24
MHz
PLL × 1,
When using an external clock
4
⎯
12
MHz
PLL × 2,
When using an external clock
4
⎯
8
MHz
PLL × 3,
When using an external clock
4
⎯
6
MHz
PLL × 4,
When using an external clock
4
⎯
4
MHz
PLL × 6,
When using an external clock
X0A, X1A
—
32.768
100
kHz
X0, X1
62.5
⎯
333
ns
When using an oscillation circuit
X0, X1
41.67
⎯
333
ns
When using an external clock
tCYLL
X0A, X1A
10
30.5
—
µs
PWH, PWL
X0
10
⎯
⎯
ns
PWHL, PWLL
X0A
5
15.2
⎯
µs
tCR, tCF
X0
⎯
⎯
5
ns
fCP
⎯
1.5
⎯
24
MHz When using main clock
fCPL
⎯
⎯
8.192
50
kHz When using sub clock
tCP
⎯
41.67
⎯
666
ns
When using main clock
tCPL
⎯
20
122.1
⎯
µs
When using sub clock
Min
Typ
Max
3
⎯
4
X0, X1
Clock frequency*
fC
X0, X1
fCL
Clock cycle time
Input clock pulse width
Input clock rise and fall
time
Internal operating clock
frequency (machine
clock)
Internal operating clock
cycle time (machine clock)
tCYL
Duty ratio is about 30% to 70%.
When using external clock
(Continued)
DS07-13746-3E
43
MB90360E Series
(Continued)
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as mentioned
in “Relation among external clock frequency and internal clock frequency”.
• Clock Timing
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
tCYLL
0.8 VCC
X0A
0.2 VCC
PWHL
PWLL
tCF
44
tCR
DS07-13746-3E
MB90360E Series
• Guaranteed PLL Operation Range
Guaranteed operation range
Power supply voltage
VCC (V)
5.5
Guaranteed A/D converter
operation range
4.0
3.5
Guaranteed PLL operation range
1.5
4
24
Internal clock fCP (MHz)
Guaranteed operation range of MB90360E series
Guaranteed oscillation frequency range
Internal clock
fCP (MHz)
24
×6
×4
×3
×2
×1
16
×1/2
(PLL off)
12
8
4.0
1.5
3 4
8
12
16
24
External clock fC (MHz) *
* : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz.
DS07-13746-3E
45
MB90360E Series
(2) Reset Standby Input
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Parameter
Symbol
Reset input
time
tRSTL
Value
Pin
RST
Unit
Remarks
Min
Max
500
⎯
ns
Under normal operation
Oscillation time of oscillator*
+ 100 µs
⎯
µs
In stop mode, sub clock
mode, sub sleep mode,
and watch mode
100
⎯
µs
In timebase timer mode
* : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation
time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of µs
and several ms. With an external clock, the oscillation time is 0 ms.
• Under normal operation :
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, sub clock mode, sub sleep mode, and watch mode :
tRSTL
RST
0.2 VCC
X0
0.2 VCC
90% of
amplitude
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
46
DS07-13746-3E
MB90360E Series
(3) Power-on Reset
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Power on rise time
tR
VCC
tOFF
VCC
Power off time
Condition
⎯
Value
Unit
Min
Max
0.05
30
ms
1
⎯
ms
Remarks
Due to repetitive operation
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Note : If you change the power supply voltage too rapidly, a power-on reset may occur. We recommend that you
start up smoothly by restraining voltages when changing the power supply voltage during operation, as
shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within
1 V/s, you can operate while using the PLL clock.
VCC
We recommend a rise of
50 mV/ms maximum.
3V
VSS
DS07-13746-3E
Holds RAM data
47
MB90360E Series
(4) LIN-UART0/1
• Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
5 tCP
⎯
ns
−50
+50
ns
tCP + 80
⎯
ns
SCK0, SCK1,
SIN0, SIN1
0
⎯
ns
tSHSL
SCK0, SCK1
3 tCP - tR
⎯
ns
Serial clock “H” pulse width
tSLSH
SCK0, SCK1
tCP + 10
⎯
ns
SCK ↓ → SOT delay time
tSLOVE
SCK0, SCK1,
SOT0, SOT1
⎯
2 tCP + 60
ns
Valid SIN → SCK ↑
tIVSHE
SCK0, SCK1,
SIN0, SIN1
30
⎯
ns
SCK ↑ → Valid SIN hold time
tSHIXE
SCK0, SCK3,
SIN0, SIN1
tCP + 30
⎯
ns
SCK fall time
tF
SCK0, SCK1
⎯
10
ns
SCK rise time
tR
SCK0, SCK1
⎯
10
ns
Serial clock cycle time
tSCYC
SCK0, SCK1
SCK ↓ → SOT delay time
tSLOVI
SCK0, SCK1,
SOT0, SOT1
Valid SIN → SCK ↑
tIVSHI
SCK0, SCK1,
SIN0, SIN1
SCK ↑ → Valid SIN hold time
tSHIXI
Serial clock “L” pulse width
Internal shift clock
mode output pins are
CL = 80 pF + 1 TTL.
External shift clock
mode output pins are
CL = 80 pF + 1 TTL.
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
• Internal Shift Clock Mode
tSCYC
SCK0, SCK1
2.4 V
0.8 V
0.8 V
tSLOVI
SOT0, SOT1
2.4 V
0.8 V
tIVSHI
SIN0, SIN1
48
tSHIXI
VIH
VIH
VIL
VIL
DS07-13746-3E
MB90360E Series
• External Shift Clock Mode
tSLSH
tSHSL
VIH
VIH
SCK0, SCK1
VIL
VIL
tF
tSLOVE
tR
2.4 V
SOT0, SOT1
0.8 V
tIVSHE
SIN0, SIN1
tSHIXE
VIH
VIH
VIL
VIL
• Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
5 tCP
⎯
ns
−50
+50
ns
tCP + 80
⎯
ns
SCK0, SCK1,
SIN0, SIN1
0
⎯
ns
tSHSL
SCK0, SCK1
3 tCP - tR
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK0, SCK1
tCP + 10
⎯
ns
SCK ↑ → SOT delay time
tSHOVE
SCK0, SCK1,
SOT0, SOT1
⎯
2 tCP + 60
ns
Valid SIN → SCK ↓
tIVSLE
SCK0, SCK1,
SIN0, SIN1
30
⎯
ns
SCK ↓ → Valid SIN hold time
tSLIXE
SCK0, SCK1,
SIN0, SIN1
tCP + 30
⎯
ns
SCK fall time
tF
SCK0, SCK1
⎯
10
ns
SCK rise time
tR
SCK0, SCK1
⎯
10
ns
Serial clock cycle time
tSCYC
SCK0, SCK1
SCK ↑ → SOT delay time
tSHOVI
SCK0, SCK1,
SOT0, SOT1
Valid SIN → SCK ↓
tIVSLI
SCK0, SCK1,
SIN0, SIN1
SCK ↓ → Valid SIN hold time
tSLIXI
Serial clock “H” pulse width
Internal shift clock
mode output pins are
CL = 80 pF + 1 TTL.
External shift clock
mode output pins are
CL = 80 pF + 1 TTL.
Notes : • CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
DS07-13746-3E
49
MB90360E Series
• Internal Shift Clock Mode
tSCYC
SCK0, SCK1
2.4 V
0.8 V
tSHOVI
2.4 V
SOT0, SOT1
0.8 V
tIVSLI
SIN0, SIN1
tSLIXI
VIH
VIH
VIL
VIL
• External Shift Clock Mode
tSHSL
VIL
tR
SOT0, SOT1
VIH
VIH
SCK0, SCK1
tSLSH
tSHOVE
VIL
tF
2.4 V
0.8 V
tIVSLE
SIN0, SIN1
50
tSLIXE
VIH
VIH
VIL
VIL
DS07-13746-3E
MB90360E Series
• Bit setting: ESCR:SCES = 0, ECCR:SCDE = 1
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
Value
Condition
Unit
Min
Max
SCK0, SCK1
5 tCP
⎯
ns
tSHOVI
SCK0, SCK1,
SOT0, SOT1
−50
+50
ns
Valid SIN → SCK ↓
tIVSLI
SCK0, SCK1,
SIN0, SIN1
tCP + 80
⎯
ns
SCK ↓ → Valid SIN hold time
tSLIXI
SCK0, SCK1,
SIN0, SIN1
0
⎯
ns
SOT → SCK ↓ delay time
tSOVLI
SCK0, SCK1,
SOT0, SOT1
3 tCP − 70
⎯
ns
Internal clock operation
output pins are
CL = 80 pF + 1 TTL.
Notes : • CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
tSCYC
2.4 V
SCK0, SCK1
0.8 V
0.8 V
tSHOVI
tSOVLI
SOT0, SOT1
2.4 V
2.4 V
0.8 V
0.8 V
tIVSLI
SIN0, SIN1
DS07-13746-3E
VIH
VIL
tSLIXI
VIH
VIL
51
MB90360E Series
• Bit setting: ESCR:SCES = 1, ECCR:SCDE = 1
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
Value
Condition
Unit
Min
Max
SCK0, SCK1
5 tCP
⎯
ns
tSLOVI
SCK0, SCK1,
SOT0, SOT1
−50
+50
ns
Valid SIN → SCK ↑
tIVSHI
SCK0, SCK1,
SIN0, SIN1
tCP + 80
⎯
ns
SCK ↑ → Valid SIN hold time
tSHIXI
SCK0, SCK1,
SIN0, SIN1
0
⎯
ns
SOT → SCK ↑ delay time
tSOVHI
SCK0, SCK1,
SOT0, SOT1
3 tCP − 70
⎯
ns
Internal clock operation
output pins are
CL = 80 pF + 1 TTL.
Notes : • CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
tSCYC
2.4 V
2.4 V
SCK0, SCK1
0.8 V
tSLOVI
tSOVHI
SOT0, SOT1
2.4 V
2.4 V
0.8 V
0.8 V
tIVSHI
SIN0, SIN1
52
tSHIXI
VIH
VIH
VIL
VIL
DS07-13746-3E
MB90360E Series
(5) Trigger Input Timing
Parameter
Input pulse width
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Pin
Condition
Unit
Min
Max
Symbol
tTRGH
tTRGL
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
ADTG
⎯
⎯
5 tCP
ns
Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
ADTG
DS07-13746-3E
VIH
VIH
VIL
VIL
tTRGH
tTRGL
53
MB90360E Series
(6) Timer Related Resource Input Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
tTIWH
Input pulse width
TIN2, TIN3
IN0 to IN3
tTIWL
⎯
⎯
4 tCP
ns
Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
VIH
VIH
TIN2, TIN3
IN0 to IN3
VIL
VIL
tTIWH
tTIWL
(7) Timer Related Resource Output Timing
(TA = –40°C to +125°C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
CLK ↑ → TOUT change time
CLK
TOT2, TOT3
PPGC to PPGF
tTO
⎯
30
⎯
ns
2.4 V
2.4 V
TOT2, TOT3
PPGC to PPGF
0.8 V
tTO
54
DS07-13746-3E
MB90360E Series
5. A/D Converter
(TA = −40 °C to +125 °C, 3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Parameter
Symbol
Pin
Resolution
⎯
Total error
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
⎯
⎯
±3.0
LSB
Nonlinearity error
⎯
⎯
⎯
⎯
±2.5
LSB
Differential
nonlinearity error
⎯
⎯
⎯
⎯
±1.9
LSB
Zero reading voltage
VOT
AN0 to AN15
AVSS −
1.5 × LSB
AVSS +
AVSS +
0.5 × LSB 2.5 × LSB
V
Full scale reading
voltage
VFST
AN0 to AN15
AVR −
AVR −
AVR +
3.5 × LSB 1.5 × LSB 0.5 × LSB
V
Compare time
⎯
⎯
Sampling time
⎯
⎯
Analog port input
current
IAIN
AN0 to AN15
Analog input
voltage range
VAIN
Reference
voltage range
Power supply current
1.0
⎯
16500
µs
⎯
∞
µs
−0.3
⎯
+0.3
µA
AN0 to AN15
AVSS
⎯
AVR
V
⎯
AVR
AVSS + 2.7
⎯
AVCC
V
IA
AVCC
⎯
3.5
7.5
mA
IAH
AVCC
⎯
⎯
5
µA
2.0
0.5
1.2
Reference
voltage supply current
IR
AVR
⎯
600
900
µA
IRH
AVR
⎯
⎯
5
µA
Offset between
input channels
⎯
AN0 to AN15
⎯
⎯
4
LSB
Remarks
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
*
*
* : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVR = 5.0 V) .
DS07-13746-3E
55
MB90360E Series
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting A/
D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the resistor value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. And,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit model
R
Comparator
Analog input
C
During sampling : ON
MB90F362E/TE/ES/TES, MB90F367E/TE/ES/TES
R
C
2.0 kΩ (Max)
16.0 pF (Max)
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
8.2 kΩ (Max)
16.0 pF (Max)
MB90362E/TE/ES/TES, MB90367E/TE/ES/TES,
MB90V340E-101/102/103/104
R
4.5 V ≤ AVCC ≤ 5.5 V
2.0 kΩ (Max)
4.0 V ≤ AVCC < 4.5 V
8.2 kΩ (Max)
C
14.4 pF (Max)
14.4 pF (Max)
Note : The values are reference values.
56
DS07-13746-3E
MB90360E Series
• The relationship between external impedance and minimum sampling time
• At 4.5 V ≤ AVCC ≤ 5.5 V
(External impedance = 0 kΩ to 20 kΩ)
MB90362E/TE/ES/TES,
MB90367E/TE/ES/TES,
MB90V340E-101/102/103/104
100
90
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
80
MB90F362E/TE/ES/TES
MB90F367E/TE/ES/TES
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
MB90362E/TE/ES/TES,
MB90367E/TE/ES/TES,
MB90V340E-101/102/103/104
20
18
16
14
12
10
MB90F362E/TE/ES/TES
MB90F367E/TE/ES/TES
8
6
4
2
0
0
35
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
Minimum sampling time [µs]
• At 4.0 V ≤ AVCC < 4.5 V
(External impedance = 0 kΩ to 20 kΩ)
MB90362E/TE/ES/TES,
MB90367E/TE/ES/TES,
MB90V340E-101/102/103/104
100
90
80
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
MB90F362E/TE/ES/TES
MB90F367E/TE/ES/TES
70
60
50
40
30
20
10
0
0
5
10
15
20
25
Minimum sampling time [µs]
30
35
MB90362E/TE/ES/TES,
MB90367E/TE/ES/TES,
MB90V340E-101/102/103/104
20
18
16
14
12
10
8
6
4
MB90F362E/TE/ES/TES
MB90F367E/TE/ES/TES
2
0
0
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
• About errors
As | AVR − AVSS | becomes smaller, values of relative errors grow larger.
DS07-13746-3E
57
MB90360E Series
6. Definition of A/D Converter Terms
Resolution
Non linearity
error
Differential
linearity error
Total error
: Analog variation that is recognized by an A/D converter.
: Deviation between a line across zero-transition line ( “00 0000 0000B” ← → “00 0000 0001B” )
and full-scale transition line ( “11 1111 1110B” ← → “11 1111 1111B” ) and actual conversion
characteristics.
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
: Difference between an actual value and an theoretical value. A total error includes zero transition error, full-scale transition error, and linear error.
Total error
3FFH
3FEH
1.5 LSB
Actual conversion
characteristics
Digital output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Actually-measured value)
003H
Actual conversion
characteristics
Ideal characteristics
002H
001H
0.5 LSB
AVSS
AVR
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVR − AVSS
[V]
1024
Total error of digital output “N” =
1 LSB (Ideal value) =
[LSB]
N : A/D converter digital output value
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVR − 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N − 1) to N.
(Continued)
58
DS07-13746-3E
MB90360E Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FFH
Digital output
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
N + 1H
VFST (actual
measurement
value)
VNT (actual
measurement value)
004H
003H
Actual conversion
characteristics
Digital output
3FEH
Actual conversion
characteristics
NH
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
N − 1H
002H
Ideal characteristics
Actual conversion
characteristics
N − 2H
001H
VOT (actual measurement value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Non linearity error of digital output N =
Differential linearity error of digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N+1) T − VNT
1 LSB
VFST − VOT
1022
[LSB]
−1 LSB [LSB]
[V]
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
DS07-13746-3E
59
MB90360E Series
7. Flash Memory Program/Erase Characteristics
Parameter
Chip erase time
Word (16-bit width)
programming time
Program/Erase cycle
Flash memory data
retention time
Conditions
Value
Unit
Remarks
Min
Typ
Max
⎯
1
15
s
Excludes programming
prior to erasure
⎯
16
3600
µs
Except for the overhead
time of the system level
⎯
10000
⎯
⎯
cycle
Average
TA = +85 °C
20
⎯
⎯
year
TA = −40 °C to +105 °C
VCC = 5.0 V
*
* : Corresponding value comes from the technology reliability evaluation result (using Arrhenius equation to translate
high temperature measurements into normalized value at +85 °C) .
60
DS07-13746-3E
MB90360E Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB90F362EPMT
MB90F362TEPMT
MB90F362ESPMT
MB90F362TESPMT
MB90F367EPMT
MB90F367TEPMT
MB90F367ESPMT
MB90F367TESPMT
MB90362EPMT
48-pin plastic LQFP
(FPT-48P-M26)
MB90362TEPMT
MB90362ESPMT
MB90362TESPMT
MB90367EPMT
MB90367TEPMT
MB90367ESPMT
MB90367TESPMT
MB90V340E-101CR
MB90V340E-102CR
MB90V340E-103CR
299-pin ceramic PGA
(PGA-299C-A01)
For evaluation
MB90V340E-104CR
DS07-13746-3E
61
MB90360E Series
■ PACKAGE DIMENSION
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7 × 7 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.40
+.016
* 7.00 –0.10 .276 –.004 SQ
36
0.145±0.055
(.006±.002)
25
37
24
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
48
13
"A"
0˚~8˚
LEAD No.
0.50(.020)
1
(Mounting height)
.059 –.004
INDEX
0.10±0.10
(.004±.004)
(Stand off)
12
0.20±0.05
(.008±.002)
0.08(.003)
0.25(.010)
M
0.60±0.15
(.024±.006)
©2003-2008
FUJITSU
LIMITED F48040S-c-2-3
C
2003 FUJITSU
LIMITEDMICROELECTRONICS
F48040S-c-2-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
62
DS07-13746-3E
MB90360E Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
Change Results
Changed are following names.
UART → LIN-UART
16-bit I/O timer → 16-bit free-run timer
4, 5
■ PRODUCT LINEUP
Added the row of LIN-UART.
15
■ HANDLING DEVICES
Added the item “17.Serial communication”.
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Changed the maximum rating values and Remarks on
Ratings of Power consumption.
300 → 308 Flash memory updata not performed
390 Flash memory updata performed
4. AC Characteristics
Changed the characteristics of (4)LIN-UART0/1.
(4) UART0/UART1 → (4)LIN-UART0/1
5. A/D Converter
Changed the items of “Zero reading voltage” and “Full
scale reading voltage”.
■ ORDERING INFORMATION
Changed the part numbers;
MB90V340E-101 → MB90V340E-101CR
MB90V340E-102 → MB90V340E-102CR
MB90V340E-103 → MB90V340E-103CR
MB90V340E-104 → MB90V340E-104CR
37
48 to 52
55
61
The vertical lines marked in the left side of the page show the changes.
DS07-13746-3E
63
MB90360E Series
FUJITSU MICROELECTRONICS LIMITED
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Tsimshatsui, Kowloon
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Customers are advised to consult with sales representatives before ordering.
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of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information.
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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
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Edited
Business & Media Promotion Dept.