Hynix HY29F080T12 8 megabit (1m x 8), 5 volt-only, flash memory Datasheet

HY29F080
8 Megabit (1M x 8), 5 Volt-only, Flash Memory
KEY FEATURES
n 5 Volt Read, Program, and Erase
– Minimizes system-level power
requirements
n High Performance
– Access times as fast as 70 ns
n Low Power Consumption
– 15 mA typical active read current
– 30 mA typical program/erase current
– 5 µA maximum CMOS standby current
n Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
n Sector Erase Architecture
– Sixteen equal size sectors of 64K bytes
each
– A command can erase any combination of
sectors
– Supports full chip erase
n Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
n Sector Group Protection
– Sectors may be locked in groups of two to
prevent program or erase operations
within that sector group
n Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
n Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
n Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
n Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 16 sec typical
n Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
n Ready/Busy# Pin
– Provides hardware confirmation of
completion of program and erase
operations
n Minimum 100,000 Program/Erase Cycles
n Space Efficient Packaging
– Available in industry-standard 40-pin
TSOP and 44-pin PSOP packages
GENERAL DESCRIPTION
LOGIC DIAGRAM
The HY29F080 is an 8 Megabit, 5 volt-only CMOS
Flash memory organized as 1,048,576 (1M) bytes
of eight-bits each. The device is offered in industry-standard 44-pin PSOP and 40-pin TSOP packages.
The HY29F080 can be programmed and erased
in-system with a single 5-volt VCC supply. Internally generated and regulated voltages are provided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM programmers. Access times as fast as 70ns over the
full operating voltage range of 5.0 volts ± 10% are
offered for timing compatibility with the zero wait
state requirements of high speed microprocessors.
Revision 6.1, May 2001
20
8
A[19:0]
DQ[7:0]
RESET#
RY/BY#
CE#
OE#
WE#
HY29F080
To eliminate bus contention, the HY29F080 has
separate chip enable (CE#), write enable (WE#)
and output enable (OE#) controls.
The device is compatible with the JEDEC single
power-supply Flash command set standard. Commands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a byte at a time
by executing the four-cycle Program Command.
This initiates an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
the device has a Sector Group Protect function
which hardware write protects selected sector
groups. The sector group protect and unprotect
features can be enabled in a PROM programmer.
Temporary Sector Unprotect, which requires a high
voltage, allows in-system erasure and code
changes in previously protected sectors.
Erase Suspend enables the user to put erase on
hold for any period of time to read data from, or
program data to, any sector that is not selected
for erasure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
The HY29F080’s sector erase architecture allows
any number of array sectors to be erased and reprogrammed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase Command. This initiates an
internal algorithm that automatically preprograms
the array (if it is not already programmed) before
executing the erase operation. During erase
cycles, the device automatically times the erase
pulse widths and verifies proper cell margin.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (toggle) status bits.
Reading data from the device is similar to reading
from SRAM or EPROM devices. Hardware data
protection measures include a low VCC detector
that automatically inhibits write operations during
power transitions.
To protect data in the device from accidental or
unauthorized attempts to program or erase the
device while it is in the system (e.g., by a virus),
The host can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
BLOCK DIAGRAM
DQ[7:0]
RY/BY#
DQ[7:0]
STATE
CONTROL
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
COMMAND
REGISTER
I/O BUFFERS
WE#
I/O CONTROL
CE#
RESET#
DATA LATCH
PROGRAM
VOLTAGE
GENERATOR
V SS
VCC
A[19:0]
2
V C C DETECTOR
TIMER
ADDRESS LATCH
OE#
ELECTRONIC
ID
Y-DECODER
X-DECODER
Y-GATING
8 Mbit FLASH
MEMORY
ARRAY
(16 x 512 Kbit
Sectors)
Rev. 6.1/May 01
HY29F080
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V SS
V SS
21
22
Rev. 6.1/May 01
PSOP44
PIN CONFIGURATIONS
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V CC
CE#
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
24
23
DQ4
V CC
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V CC
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V CC
V SS
V SS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Standard
TSOP40
Reverse
TSOP40
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V CC
V SS
V SS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V CC
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
3
HY29F080
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this document, whereby the presence at a pin of a higher,
more positive voltage (nominally 5VDC) causes
assertion of the signal. A ‘#’ symbol following the
signal name, e.g., RESET#, indicates that the signal is asserted in a Low state (nominally 0 volts).
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadecimal notation. The designation 0bXXXX indicates a number expressed in binary notation (X =
0, 1).
SIGNAL DESCRIPTIONS
Name
Ty p e
Des c r ip t io n
A[19:0]
Inputs
Ad d r es s , ac t iv e Hig h . These twenty inputs select one of 1,048,576 (1M) bytes
within the array for read or write operations. A[19] is the MSB and A[0] is the
LSB.
DQ[7:0]
Inputs/Outputs Dat a B u s , ac t iv e Hig h . These pins provide an 8-bit data path for read and write
Tri-state
operations.
CE#
Input
Ch ip En ab le, ac t iv e L o w. This input must be asserted to read data from or
write data to the HY 29F080. When High, the data bus is tri-stated and the device
is placed in the Standby mode.
OE#
Input
Ou t p u t En ab le, ac t iv e L o w. This input must be asserted for read operations
and negated for write operations. When High, data outputs from the device are
disabled and the data bus pins are placed in the high impedance state.
Input
W r i t e E n a b l e , a c t i v e L o w. Co nt r o ls w r it ing o f c o mma nd s o r c o mma nd
sequences in order to program data or erase sectors of the memory array. A
write operation takes place when WE# is asserted while CE# is Low and OE#
is High.
Input
Har d war e Res et , ac t iv e L o w. Provides a hardware method of resetting the
HY 29F080 to the read array state. When the device is reset, it immediately
terminates any operation in progress. The data bus is tri-stated and all read/write
commands are ignored while the input is asserted. While RESET# is asserted,
the device will be in the Standby mode.
RY /BY #
Output
Open Drain
Re a d y / B u s y St a t u s . I nd ic a t e s w he t he r a w r it e o r e r a s e c o mma nd is in
progress or has been completed. RY /BY # is valid after the rising edge of the
final WE# pulse of a command sequence. It remains Low while the device is
actively programming data or erasing, and goes High when it is ready to read
array data.
VCC
--
5-v o lt p o wer s u p p ly.
VSS
--
Po wer an d s ig n al g r o u n d .
WE#
RESET#
MEMORY ARRAY ORGANIZATION
The 1 MByte Flash memory array is organized into
sixteen 64 KByte blocks called sectors (S0, S1, . .
. , S15). A sector is the smallest unit that can be
erased. Adjacent pairs of sectors (S0/S1, S2/S3,
. . . , S14/S15) are designated as a sector group.
A sector group is the smallest unit which can be
protected to prevent accidental or unauthorized
4
erasure. See ‘Bus Operations’ and ‘Command
Definitions’ sections of this document for additional
information on these functions.
Table 1 defines the sector addresses, sector group
addresses and corresponding address ranges for
the HY29F080.
Rev. 6.1/May 01
HY29F080
Table 1. HY29F080 Memory Array Organization
Sec t o r
Sec t o r
Gr o u p
S0
SG0
S1
S2
SG1
S3
S4
SG2
S5
S6
SG3
S7
S8
SG4
S9
S10
SG5
S11
S12
SG6
S13
S14
SG7
S15
Sec t o r /Sec t o r Gr o u p Ad d r es s 1
Ad d r es s Ran g e A[ 19: 0]
A[ 19]
A[ 18]
A[ 17]
A[ 16]
0
0
0
0
0x00000 - 0x0FFFF
0
0
0
1
0x10000 - 0x1FFFF
0
0
1
0
0x20000 - 0x2FFFF
0
0
1
1
0x30000 - 0x3FFFF
0
1
0
0
0x40000 - 0x4FFFF
0
1
0
1
0x50000 - 0x5FFFF
0
1
1
0
0x60000 - 0x6FFFF
0
1
1
1
0x70000 - 0x7FFFF
1
0
0
0
0x80000 - 0x8FFFF
1
0
0
1
0x90000 - 0x9FFFF
1
0
1
0
0xA0000 - 0xAFFFF
1
0
1
1
0xB0000 - 0xBFFFF
1
1
0
0
0xC0000 - 0xCFFFF
1
1
0
1
0xD0000 - 0xDFFFF
1
1
1
0
0xE0000 - 0xEFFFF
1
1
1
1
0xF0000 - 0xFFFFF
Notes:
1. A[19:16] are the sector address. A[19:17] are the sector group address.
BUS OPERATIONS
register serve as inputs to an internal state machine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 3.
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
Table 2. HY29F080 Normal Bus Operations 1
Operation
CE#
OE#
WE#
RESET #
A[19:0]
DQ[7:0]
Read
L
L
H
H
AIN
DOUT
Write
L
H
L
H
AIN
DIN
Output Disable
L
H
H
H
X
High-Z
CE# TTL Standby
H
X
X
H
X
High-Z
VCC ± 0.3V
X
X
VCC ± 0.3V
X
High-Z
Hardware Reset (TTL Standby)
X
X
X
L
X
High-Z
Hardware Reset (CMOS Standby)
X
X
X
VSS ± 0.5V
X
High-Z
CE# CMOS Standby
Notes:
1. L = VIL, H = VIH, X = Don’t Care, DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels.
Rev. 6.1/May 01
5
HY29F080
Table 3. HY29F080 Bus Operations Requiring High Voltage 1, 2
Operation 3
R E S E TA[19: 17]
#
C E#
OE#
WE#
Sector Group
Protect
L
VID
X
H
Sector Group
Unprotect
VID
VID
X
Temporary
Sector Group
Unprotect
X
X
Manufacturer
C ode
L
Device Code
L
Sector Group
Protection
Verification
L
A[9]
A[6]
A[1]
A[0]
DQ[7: 0]
SGA 4
VID
X
X
X
X
H
SGA 4
VID
X
X
X
X
X
VID
X
X
X
X
X
X
L
H
H
X
VID
L
L
L
Hynix = 0xAD
L
H
H
X
VID
L
L
H
HY29F080 =
0xD5
L
H
H
SGA 4
VID
L
H
L
0x00 =
Unprotected
0x01 =
Protected
Notes:
1. L = VIL, H = VIH, X = Don’t Care. See DC Characteristics for voltage levels.
2. Address bits not specified are Don’t Care.
3. See text for additional information.
4. SGA = sector group address. See Table 1.
Read Operation
Data is read from the HY29F080 by using standard microprocessor read cycles while placing the
address of the byte to be read on the device’s
address inputs, A[19:0]. As shown in Table 2, the
host system must drive the CE# and OE# inputs
Low and drive WE# High for a valid read operation to take place. The device outputs the specified array data on DQ[7:0].
The HY29F080 is automatically set for reading
array data after device power-up and after a hardware reset to ensure that no spurious alteration of
the memory content occurs during the power transition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register contents are altered.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
data from any sector of memory that is not marked
for erasure. If the host attempts to read from an
address within an erase-suspended sector, or
while the device is performing an erase or byte
program operation, the device outputs status data
6
instead of array data. After completing a programming operation in the Erase Suspend mode, the
system may once again read array data with the
same exceptions noted above. After completing
an internal program or internal erase algorithm,
the HY29F080 automatically returns to the read
array data mode.
The host must issue a hardware reset or the software reset command (see Command Definitions)
to return a sector to the read array data mode if
DQ[5] goes high during a program or erase cycle,
or to return the device to the read array data mode
while it is in the Electronic ID mode.
Write Operation
Certain operations, including programming data
and erasing sectors of memory, require the host
to write a command or command sequence to the
HY29F080. Writes to the device are performed
by placing the byte address on the device’s address inputs while the data to be written is input
on DQ[7:0]. The host system must drive the CE#
and WE# pins Low and drive OE# High for a valid
write operation to take place. All addresses are
Rev. 6.1/May 01
HY29F080
latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first.
The ‘Device Commands’ section of this document
provides details on the specific device commands
implemented in the HY29F080.
Output Disable Operation
When the OE# input is at VIH, output data from the
device is disabled and the data bus pins are placed
in the high impedance state.
Standby Operation
When the system is not reading from or writing to
the HY29F080, it can place the device in the
Standby mode. In this mode, current consumption is greatly reduced, and the data bus outputs
are placed in the high impedance state, independent of the OE# input. The Standby mode can
invoked using two methods.
The device enters the CE# CMOS Standby mode
if the CE# and RESET# pins are both held at VCC
± 0.5V. Note that this is a more restricted voltage
range than VIH. If both CE# and RESET# are held
High, but not within VCC ± 0.5V, the device will be
in the CE# TTL Standby mode, but the standby
current will be greater.
The device enters the RESET# CMOS Standby
mode when the RESET# pin is held at VSS ± 0.5V.
If RESET# is held Low but not within VSS ± 0.5V,
the HY29F080 will be in the RESET# TTL Standby
mode, but the standby current will be greater. See
Hardware Reset Operation section for additional
information on the reset operation.
The device requires standard access time (tCE) for
read access when the device is in either of the
standby modes, before it is ready to read data. If
the device is deselected during erasure or programming, it continues to draw active current until
the operation is completed.
Hardware Reset Operation
The RESET# pin provides a hardware method of
resetting the device to reading array data. When
the RESET# pin is driven Low for the minimum
specified period, the device immediately terminates any operation in progress, tri-states the data
bus pins, and ignores all read/write commands for
Rev. 6.1/May 01
the duration of the RESET# pulse. The device also
resets the internal state machine to reading array
data. If an operation was interrupted by the assertion of RESET#, it should be reinitiated once
the device is ready to accept another command
sequence to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse as described in the Standby Operation section above.
If RESET# is asserted during a program or erase
operation (RY/BY# pin is Low), the internal reset
operation is completed within a time of tREADY (during
Automatic Algorithms). The RY/BY# pin will go High
during the tREADY interval, and the system can perform a read or write operation after waiting for a minimum of tREADY or until tRH after the RESET# pin returns High, whichever is longer. If RESET# is asserted when a program or erase operation is not
executing (RY/BY# pin is High), the reset operation
is completed within a time of tRP. In this case, the
host can perform a read or write operation tRH after
the RESET# pin returns High.
The RESET# pin may be tied to the system reset
signal. Thus, a system reset would also reset the
device, enabling the system to read the boot-up
firmware from the Flash memory.
Sector Group Protect/Unprotect Operations
Hardware sector group protection can be invoked
to disable program and erase operations in any
single sector group or combination of sector
groups. This function is typically used to protect
data in the device from unauthorized or accidental attempts to program or erase the device while
it is in the system (e.g., by a virus) and is implemented using programming equipment. Sector
group unprotection re-enables the program and
erase operations in previously protected sectors.
Table 1 identifies the eight sector groups and the
address ranges that each covers. The device is
shipped with all sector groups unprotected.
The sector group protect/unprotect operations require a high voltage (VID) on address pin A9 and
the CE# and/or OE# control pins, as detailed in
Table 3. When implementing these operations,
note that VCC must be applied to the device before
applying VID, and that VID should be removed before removing VCC from the device.
7
HY29F080
the appropriate commands (see Device Commands section). Once VID is removed from RESET#, all the previously protected sectors are protected again. Figure 3 illustrates the algorithm.
The flow chart in Figure 1 illustrates the procedure for protecting sector groups, and timing specifications and waveforms are shown in the specifications section of this document. Verification of
protection is accomplished as described in the
Electronic ID Mode section and shown in the flow
chart.
Electronic ID Mode Operation
The Electronic ID mode provides manufacturer and
device identification and sector group protection
verification through identifier codes output on
DQ[7:0]. This mode is intended primarily for programming equipment to automatically match a
device to be programmed with its corresponding
programming algorithm. The Electronic ID information can also be obtained by the host through
a command sequence, as described in the Device Commands section.
The procedure for sector group unprotection is illustrated in the flow chart in Figure 2, and timing
specifications and waveforms are given at the end
of this document. Note that to unprotect any sector group, all unprotected sector groups must first
be protected prior to the first unprotect write cycle.
Sectors can also be temporarily unprotected as
described in the next section.
Temporary Sector Group Unprotect Operation
Operation in the Electronic ID mode requires VID
on address pin A[9], with additional requirements
for obtaining specific data items as listed in Table
2:
This feature allows temporary unprotection of previously protected sectors to allow changing the
data in-system. Temporary Sector Group Unprotect mode is activated by setting the RESET# pin
to VID. While in this mode, formerly protected sectors can be programmed or erased by invoking
n A read cycle at address 0xXXX00 retrieves the
manufacturer code (Hynix = 0xAD).
START
Wait t W P P 1
APPLY V
W E # = V IH
CC
A9 = V ID
A[19:17] = Group to Protect
OE# = CE# = A6 = A0 = V IL
A1 = V IH
Set TRYCNT = 1
Increment TRYCNT
Read Data
Set A9 = OE# = V
NO
ID
Data = 0x01?
Set Address:
A[19:17] = Group to Protect
CE# = V IL
RESET# = V IH
W E # = V IL
NO
TRYCNT = 25?
YES
YES
Remove V
Protect Another
Sector?
ID
from A9
NO
DEVICE FAILURE
SECTOR PROTECT
COMPLETE
YES
Figure 1. Sector Group Protect Procedure
8
Rev. 6.1/May 01
HY29F080
START
NOTE: All sectors must be
previously protected.
APPLY V
Increment TRYCNT
Set Sector Group Address:
A[19:17] = Group NGRP
A0 = A6 = V IL
A1 = V IH
CC
Set: TRYCNT = 1
Read Data
NO
Set: NGRP = 0
Data = 0x00?
Set: A9 = CE# = OE# = V
Set: RESET# = V
YES
NO
TRYCNT = 1000?
ID
YES
IH
W E # = V IL
NGRP = 7?
YES
Remove V
Wait t W P P 2
NO
ID
from A9
NGRP = NGRP + 1
SECTOR UNPROTECT
COMPLETE
W E # = V IH
Set:
A9 = V ID
OE# = CE# = V
DEVICE FAILURE
IL
Figure 2. Sector Group Unprotect Procedure
n A read cycle at address 0xXXX01 returns the
device code (HY29F080 = 0xD5).
START
n A read cycle containing a sector group address
(Table 1) in A[19:17] and the address 0x02 in
A[7:0] returns 0x01 if that sector is protected,
or 0x00 if it is unprotected.
R E S E T # = V ID
(All protected sector groups
become unprotected)
Perform Program or Erase
Operations
R E S E T # = V IH
(All previously protected
sector groups return to
protected state)
TEMPORARY SECTOR
UNPROTECT COMPLETE
Figure 3. Temporary Sector Group Unprotect
Rev. 6.1/May 01
9
HY29F080
DEVICE COMMANDS
Device operations are initiated by writing designated address and data command sequences into
the device. A command sequence is composed
of one, two or three of the following sub-segments:
an unlock cycle, a command cycle and a data
cycle. Table 4 summarizes the composition of the
valid command sequences implemented in the
HY29F080, and these sequences are fully described in Table 5 and in the sections that follow.
Note: When in the Electronic ID bus operation mode,
the device returns to the Read mode when VID is removed from the A[9] pin. The Read/Reset command is
not required in this case.
n If DQ[5] (Exceeded Time Limit) goes High during a program or erase operation, writing the
reset command returns the sectors to the Read
mode (or to the Erase Suspend mode if the
device was in Erase Suspend).
Writing incorrect address and data values or writing them in the improper sequence resets the
HY29F080 to the Read mode.
The Read/Reset command may also be used to
abort certain command sequences:
Table 4. Composition of Command Sequences
quence, the Read/Reset command may be
written at any time before erasing actually begins, including, for the Sector Erase command,
between the cycles that specify the sectors to
be erased (see Sector Erase command description). This aborts the command and resets the device to the Read mode. Once erasure begins, however, the device ignores Read/
Reset commands until the operation is complete.
Command
Sequence
Number of Bus Cycles
Unlock Command
Data
Read/Reset 1
0
1
Note 1
Read/Reset 2
2
1
Note 1
Byte Program
2
1
1
Chip Erase
4
1
1
Sector Erase
4
1
1 (Note 2)
Erase Suspend
0
1
0
Erase Resume
0
1
0
Electronic ID
2
1
Note 3
Notes:
1. Any number of Flash array read cycles are permitted.
2. Additional data cycles may follow. See text.
3. Any number of Electronic ID read cycles are permitted.
Read/Reset 1, 2 Commands
The HY29F080 automatically enters the Read
mode after device power-up, after the RESET#
input is asserted and upon the completion of certain commands. Read/Reset commands are not
required to retrieve data in these cases.
A Read/Reset command must be issued in order
to read array data in the following cases:
n If the device is in the Electronic ID mode, a
Read/ Reset command must be written to return to the Read mode. If the device was in the
Erase Suspend mode when the device entered
the Electronic ID mode, writing the Read/Reset command returns the device to the Erase
Suspend mode.
10
n In a Sector Erase or Chip Erase command se-
n In a Program command sequence, the Read/
Reset command may be written between the
sequence cycles before programming actually
begins. This aborts the command and resets
the device to the Read mode, or to the Erase
Suspend mode if the Program command sequence is written while the device is in the
Erase Suspend mode. Once programming
begins, however, the device ignores Read/Reset commands until the operation is complete.
n The Read/Reset command may be written between the cycles in an Electronic ID command
sequence to abort that command. As described
above, once in the Electronic ID mode, the
Read/ Reset command must be written to return to the Read mode.
Byte Program Command
The host processor programs the device a byte at
a time by issuing the Program command sequence
shown in Table 5. The sequence begins by writing two unlock cycles, followed by the Program
setup command and, lastly, a data cycle specifying the program address and data. This initiates
the Automatic Programming algorithm, which provides internally generated program pulses and
Rev. 6.1/May 01
Rev. 6.1/May 01
Group Protect Verify
AA
2AA
55
555
555
555
555
555
Add
90
80
80
A0
F0
Data
555
555
PA
RA
Add
STAT
2AA
2AA
Add
55
55
Data
Fifth
SA
555
Add
Notes:
1. All values are in hexadecimal.
2. All bus cycles are write operations unless otherwise noted.
3. Address is A[10:0] and A[19:11] are don’t care except as follows:
• For RA and PA, A[19:11] are the upper address bits of the byte to be read or programmed.
• For SA, A[19:16] are the sector address of the sector to be erased and A[15:0] are don’t care.
• For GPVA, A[19:17] are the sector group address of the sector to be verified, A[7:0] = 0x02, all other address bits are don’t care.
4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-erasing sectors, or enter the
Electronic ID mode, while in the Erase Suspend mode.
5. The Erase Resume command is valid only during the Erase Suspend mode.
6. The second bus cycle is a read cycle.
7. The fourth bus cycle is a read cycle.
8. Either command sequence is valid. The command is required only to return to the Read mode when the device is in the Electronic ID command mode or if
DQ[5] goes High during a program or erase operation. It is not required for normal read operations.
30
10
Data
Sixth
PA = Address of the data to be programmed
PD = Data to be programmed at address PA
SA = Sector address of sector to be erased (see Note 3 and Table 1).
GPVA = Address of the sector group to be verified (see Note 3 and Table 1).
GPVA
D5
AD
AA
AA
PD
RD
Data
Fourth
X01
555
55
55
55
55
RD
Data
T hird
Device Code
30
2AA
2AA
2AA
2AA
RA
Add
Second
X00
XXX
B0
AA
AA
AA
AA
F0
Data
Legend:
X = Don’t Care
RA = Memory address of data to be read
RD = Data read from location RA during the read operation
STAT = Group protect status: 0x00 = unprotected, 0x01 = protected.
Electronic
ID 7
3
1
XXX
555
555
555
555
XXX
Add
First
Bus Cycles 1, 2, 3
Manufacturer Code
Erase Resume
Erase Suspend
1
6
Sector Erase
5
6
4
4
3
1
Chip Erase
7, 8
Write
Cycles
Byte Program
Reset/Reset 2
Read/Reset 1
6, 8
Command Sequence
Table 5. HY29F080 Command Sequences
HY29F080
11
HY29F080
verifies the programmed cell margin. The host is
not required to provide further controls or timings
during this operation. When the Automatic Programming algorithm is complete, the device returns to the Read mode. Several methods are
provided to allow the host to determine the status
of the programming operation, as described in the
Write Operation Status section.
Commands written to the device during execution
of the Automatic Programming algorithm are ignored. Note that a hardware reset immediately
terminates the programming operation. To ensure data integrity, the aborted program command
sequence should be reinitiated once the reset
operation is complete.
Programming is allowed in any sequence. Only
erase operations can convert a stored “0” to a “1”.
Thus, a bit cannot be programmed from a “0” back
to a “1”. Attempting to do so will set DQ[5] to “1”,
and the Data# Polling algorithm will indicate that
the operation was not successful. A Read/Reset
command or a hardware reset is required to exit
this state, and a succeeding read will show that
the data is still “0”.
Figure 4 illustrates the procedure for the Program
operation.
Chip Erase Command
The Chip Erase command sequence consists of
two unlock cycles, followed by the erase command, two additional unlock cycles and then the
chip erase data cycle. During chip erase, all sectors of the device are erased except protected
sector groups. The command sequence starts the
Automatic Erase algorithm, which preprograms
and verifies the entire memory, except for protected sector groups, for an all zero data pattern
prior to electrical erase. The device then provides
the required number of internally generated erase
pulses and verifies cell erasure within the proper
cell margins. The host system is not required to
provide any controls or timings during these operations.
Commands written to the device during execution
of the Automatic Erase algorithm are ignored. Note
that a hardware reset immediately terminates the
erase operation. To ensure data integrity, the
aborted chip erase command sequence should be
reissued once the reset operation is complete.
When the Automatic Erase algorithm is finished,
the device returns to the Read mode. Several
methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section.
Figure 5 illustrates the Chip Erase procedure.
START
START
Issue PROGRAM
Command Sequence:
Last cycle contains
program Address/Data
Check Programming Status
(See Write Operation Status
Section)
Issue CHIP ERASE
Command Sequence
DQ[5] Error Exit
Check Erase Status
(See Write Operation Status
Section)
Normal Exit
DQ[5] Error Exit
Normal Exit
NO
CHIP ERASE COMPLETE
Last Byte Done?
GO TO
ERROR RECOVERY
YES
Figure 5. Chip Erase Procedure
PROGRAMMING
COMPLETE
GO TO
ERROR RECOVERY
Figure 4. Programming Procedure
12
Sector Erase Command
The Sector Erase command sequence consists
of two unlock cycles, followed by the erase command, two additional unlock cycles and then the
sector erase data cycle, which specifies which
Rev. 6.1/May 01
HY29F080
sector is to be erased. As described later in this
section, multiple sectors can be specified for erasure with a single command sequence. During
sector erase, all specified sectors are erased sequentially. The data in sectors not specified for
erasure, as well as the data in any sectors specified for erasure but located within protected sector groups, is not affected by the sector erase operation.
The Sector Erase command sequence starts the
Automatic Erase algorithm, which preprograms
and verifies the specified unprotected sectors for
an all zero data pattern prior to electrical erase.
The device then provides the required number of
internally generated erase pulses and verifies cell
erasure within the proper cell margins. The host
system is not required to provide any controls or
timings during these operations.
After the sector erase data cycle (the sixth bus
cycle) of the command sequence is issued, a sector erase time-out of 50 µs (typical), measured from
the rising edge of the final WE# pulse in that bus
cycle, begins. During this time, an additional sector erase data cycle, specifying the sector address
of another sector to be erased, may be written
into an internal sector erase buffer. This buffer
may be loaded in any sequence, and the number
of sectors specified may be from one sector to all
sectors. The only restriction is that the time between these additional data cycles must be less
than 50 µs, otherwise erasure may begin before
the last data cycle is accepted. To ensure that all
data cycles are accepted, it is recommended that
host processor interrupts be disabled during the
time that the additional cycles are being issued
and then be re-enabled afterwards.
Note: The device is capable of accepting three ways
of invoking Erase Commands for additional sectors
during the time-out window. The preferred method,
described above, is the sector erase data cycle after
the initial six bus cycle command sequence. However, the device also accepts the following methods
of specifying additional sectors during the sector
erase time-out:
n Repeat the entire six-cycle command sequence, specifying the additional sector in the sixth cycle.
n Repeat the last three cycles of the six-cycle command
sequence, specifying the additional sector in the third
cycle.
If all sectors scheduled for erasing are within protected sector groups, the device returns to reading array data after approximately 100 µs. If at
Rev. 6.1/May 01
least one selected sector is not protected, the
erase operation erases the unprotected sectors,
and ignores the command for the selected sectors that are protected.
The system can monitor DQ[3] to determine if the
50 µs sector erase time-out has expired, as described in the Write Operation Status section. If
the time between additional sector erase data
cycles can be insured to be less than the timeout, the system need not monitor DQ[3].
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
then rewrite the command sequence, including any
additional sector erase data cycles. Once the
sector erase operation itself has begun, only the
Erase Suspend command is valid. All other commands are ignored.
As for the Chip Erase command, note that a hardware reset immediately terminates the erase operation. To ensure data integrity, the aborted Sector Erase command sequence should be reissued
once the reset operation is complete.
When the Automatic Erase algorithm terminates,
the device returns to the Read mode. Several
methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section.
Figure 6 illustrates the Sector Erase procedure.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system
to interrupt a sector erase operation to read data
from, or program data in, any sector not being
erased. The command causes the erase operation to be suspended in all sectors selected for
erasure. This command is valid only during the
sector erase operation, including during the 50 µs
time-out period at the end of the initial command
sequence and any subsequent sector erase data
cycles, and is ignored if it is issued during chip
erase or programming operations.
The HY29F080 requires a maximum of 15 µs to
suspend the erase operation if the Erase Suspend
command is issued during active sector erasure.
However, if the command is written during the timeout, the time-out is terminated and the erase operation is suspended immediately. Any subsequent attempts to specify additional sectors for
13
HY29F080
START
Check Erase Status
(See Write Operation Status
Section)
DQ[5] Error Exit
Normal Exit
Write First Five Cycles of
SECTOR ERASE
Command Sequence
ERASE COMPLETE
GO TO
ERROR RECOVERY
Setup First (or Next) Sector
Address for Erase Operation
Write Last Cycle (SA/0x30)
of SECTOR ERASE
Command Sequence
Sectors which require erasure
but which were not specified in
this erase cycle must be erased
later using a new command
sequence
NO
Erase An
Additional Sector?
YES
Sector Erase
Time-out (DQ[3])
Expired?
YES
NO
Figure 6. Sector Erase Procedure
erasure by writing the sector erase data cycle (SA/
0x30) will be interpreted as the Erase Resume
command (XXX/0x30), which will cause the Automatic Erase algorithm to begin its operation. Note
that any other command during the time-out will
reset the device to the Read mode.
Once the erase operation has been suspended,
the system can read array data from or program
data to any sector not selected for erasure. Normal read and write timings and command definitions apply. Reading at any address within erasesuspended sectors produces status data on
DQ[7:0]. The host can use DQ[7], or DQ[6] and
DQ[2] together, to determine if a sector is actively
erasing or is erase-suspended. See “Write Operation Status” for information on these status bits.
After an erase-suspended program operation is
complete, the host can initiate another programming operation (or read operation) within non-suspended sectors. The host can determine the status of a program operation during the erase-suspended state just as in the standard programming
operation.
The system must write the Erase Resume command to exit the Erase Suspend mode and continue the sector erase operation. Further writes of
14
the Resume command are ignored. Another Erase
Suspend command can be written after the device has resumed erasing.
The host may also write the Electronic ID command sequence when the device is in the Erase
Suspend mode. The device allows reading Electronic ID codes even if the addresses used for the
ID read cycles are within erasing sectors, since
the codes are not stored in the memory array.
When the device exits the Electronic ID mode, the
device reverts to the Erase Suspend mode, and
is ready for another valid operation. See Electronic
ID section for more information.
Electronic ID Command
The Electronic ID operation intended for use in
programming equipment has been described previously. The host processor can also be obtain
the same data by using the Electronic ID command sequence shown in Table 5. This method
does not require VID on any pin. The Electronic ID
command sequence may be invoked while the
device is in the Read mode or the Erase Suspend
mode, but is invalid while the device is actively
programming or erasing.
Rev. 6.1/May 01
HY29F080
The Electronic ID command sequence is initiated
by writing two unlock cycles, followed by the Electronic ID command. The device then enters the
Electronic ID mode, and:
mand sequence. Thus, for example, the host may
determine the protection status for all sector
groups by doing successive reads at address 0x02
while changing the SGA in A[19:17] for each cycle.
n A read cycle at address 0xXXX00 retrieves the
manufacturer code (Hynix = 0xAD).
The system must write the Reset command to exit
the Electronic ID mode and return to the Read
mode, or to the Erase Suspend mode if the device was in that mode when the command sequence was issued.
n A read cycle at address 0xXXX01 returns the
device code (29F080 = 0xD5).
n A read cycle containing a sector group address
(SGA) in A[19:17] and the address 0x02 in
A[7:0] returns 0x01 if that sector is protected,
or 0x00 if it is unprotected.
The host system may read at any address any
number of times, without initiating another comWRITE OPERATION STATUS
The HY29F080 provides a number of facilities to
determine the status of a program or erase operation. These are the RY/BY# (Ready/Busy#)
pin and certain bits of a status word which can be
read from the device during the programming and
erase operations. Table 6 summarizes the status
indications and further detail is provided in the
subsections which follow.
Table 6. Write and Erase Operation Status Summary
Mode
Operation
DQ[7]
Programming in progress
Normal
1
DQ[7]#
DQ[6]
Toggle
DQ[5]
0/1
2
4
Data
0
Toggle
2
Erase completed
1
Data
4
Read within erase suspended
sector
1
Programming completed
Data
Erase in progress
Read within non-erase
Erase
Suspend suspended sector
Programming in progress 5
Programming completed
5
Data
0/1
1
DQ[3]
DQ[2]
N/A
N/A
0
Data
Data
1
Toggle
0
4
1
1
3
Data
Data
Data
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
DQ[7]#
Toggle
0/1 2
N/A
N/A
0
4
Data
Data
Data
1
Data
Data
Notes:
1. A valid address is required when reading status information. See text for additional information.
2. DQ[5] status switches to a ‘1’ when a program or erase operation exceeds the maximum timing limit.
3. A ‘1’ during sector erase indicates that the 50 µs timeout has expired and active erasure is in progress.
applicable to the chip erase operation.
4. Equivalent to ‘No Toggle’ because data is obtained in this state.
5. Programming can be done only in a non-suspended sector (a sector not marked for erasure).
RY/BY# - Ready/Busy#
RY/BY# is an open-drain output pin that indicates
whether a programming or erase Automatic Algorithm is in progress or has completed. A pull-up
resistor to VCC is required for proper operation. RY/
BY# is valid after the rising edge of the final WE#
pulse in the corresponding command sequence.
Rev. 6.1/May 01
RY/BY#
DQ[3] is not
If the output is Low (busy), the device is actively
erasing or programming, including programming
while in the Erase Suspend mode. If the output is
High (ready), the device has completed the operation and is ready to read array data in the normal or Erase Suspend modes, or it is in the standby
mode.
15
HY29F080
DQ[7] - Data# Polling
START
The Data# (“Data Bar”) Polling bit, DQ[7], indicates
to the host system whether an Automatic Algorithm is in progress or completed, or whether the
device is in Erase Suspend mode. Data# Polling
is valid after the rising edge of the final WE# pulse
in the Program or Erase command sequence.
The system must do a read at the program address to obtain valid programming status information on this bit. While a programming operation is
in progress, the device outputs the complement
of the value programmed to DQ[7]. When the programming operation is complete, the device outputs the value programmed to DQ[7]. If a program operation is attempted within a protected
sector, Data# Polling on DQ[7] is active for approximately 2 µs, then the device returns to reading array data.
The host must read at an address within any nonprotected sector scheduled for erasure to obtain
valid erase status information on DQ[7]. During
an erase operation, Data# Polling produces a “0”
on DQ[7]. When the erase operation is complete,
or if the device enters the Erase Suspend mode,
Data# Polling produces a “1” on DQ[7]. If all sectors selected for erasing are protected, Data#
Polling on DQ[7] is active for approximately 100
µs, then the device returns to reading array data.
If at least one selected sector is not protected, the
erase operation erases the unprotected sectors,
and ignores the command for the selected sectors that are protected.
When the system detects that DQ[7] has changed
from the complement to true data (or “0” to “1” for
erase), it should do an additional read cycle to read
valid data from DQ[7:0]. This is because DQ[7]
may change asynchronously with respect to the
other data bits while Output Enable (OE#) is asserted low.
Figure 7 illustrates the Data# Polling test algorithm.
DQ[6] - Toggle Bit I
Toggle Bit I on DQ[6] indicates whether an Automatic Program or Erase algorithm is in progress
or complete, or whether the device has entered
the Erase Suspend mode. Toggle Bit I may be
read at any address, and is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence, including during the sector
16
Read DQ[7:0]
at Valid Address (Note 1)
Test for DQ[7] = 1?
for Erase Operation
DQ[7] = Data?
YES
NO
NO
DQ[5] = 1?
YES
Read DQ[7:0]
at Valid Address (Note 1)
Test for DQ[7] = 1?
for Erase Operation
DQ[7] = Data?
(Note 2)
YES
NO
PROGRAM/ERASE
EXCEEDED TIME ERROR
PROGRAM/ERASE
COMPLETE
Notes:
1. During programming, the program address.
During sector erase, an address within any non-protected sector
scheduled for erasure.
During chip erase, an address within any non-protected sector.
2. Recheck DQ[7] since it may change asynchronously at the same time
as DQ[5].
Figure 7. Data# Polling Test Algorithm
erase time-out. The system may use either OE#
or CE# to control the read cycles.
Successive read cycles at any address during an
Automatic Program algorithm operation (including
programming while in Erase Suspend mode)
cause DQ[6] to toggle. DQ[6] stops toggling when
the operation is complete. If a program address
falls within a protected sector, DQ[6] toggles for
approximately 2 µs after the program command
sequence is written, then returns to reading array
data.
While the Automatic Erase algorithm is operating,
successive read cycles at any address cause
DQ[6] to toggle. DQ[6] stops toggling when the
erase operation is complete or when the device is
placed in the Erase Suspend mode. The host may
use DQ[2] to determine which sectors are erasing
Rev. 6.1/May 01
HY29F080
START
DQ[5] = 1?
Read DQ[7:0]
at Valid Address (Note 1)
NO
Read DQ[7:0]
YES
Read DQ[7:0]
at Valid Address (Note 1)
YES
DQ[6] Toggled?
NO
(Note 4)
NO
(Note 3)
PROGRAM/ERASE
COMPLETE
NO
Read DQ[7:0]
at Valid Address (Note 1)
Read DQ[7:0]
DQ[6] Toggled?
(Note 2)
DQ[2] Toggled?
NO
YES
YES
PROGRAM/ERASE
EXCEEDED TIME ERROR
SECTOR BEING READ
IS IN ERASE SUSPEND
SECTOR BEING READ
IS NOT IN ERASE SUSPEND
Notes:
1. During programming, the program address.
During sector erase, an address within any sector scheduled for erasure.
2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.
3. Use this path if testing for Program/Erase status.
4. Use this path to test whether sector is in Erase Suspend mode.
Figure 8. Toggle Bit I and II Test Algorithm
or erase-suspended (see below). After an Erase
command sequence is written, if all sectors selected for erasing are protected, DQ[6] toggles for
approximately 100 µs, then returns to reading array data. If at least one selected sector is not
protected, the Automatic Erase algorithm erases
the unprotected sectors, and ignores the selected
sectors that are protected.
DQ[2] - Toggle Bit II
Toggle Bit II, DQ[2], when used with DQ[6], indicates whether a particular sector is actively erasing or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the
final WE# pulse in the command sequence. The
device toggles DQ[2] with each OE# or CE# read
cycle.
DQ[2] toggles when the host reads at addresses
within sectors that have been selected for erasure,
but cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ[6], by
comparison, indicates whether the device is actively erasing or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure.
Rev. 6.1/May 01
Thus, both status bits are required for sector and
mode information.
Figure 8 illustrates the operation of Toggle Bits I
and II.
DQ[5] - Exceeded Timing Limits
DQ[5] is set to a ‘1’ when the program or erase
time has exceeded a specified internal pulse count
limit. This is a failure condition that indicates that
the program or erase cycle was not successfully
completed. DQ[5] status is valid only while DQ[7]
or DQ[6] indicate that an Automatic Algorithm is
in progress.
The DQ[5] failure condition will also be signaled if
the host tries to program a ‘1’ to a location that is
previously programmed to ‘0’, since only an erase
operation can change a ‘0’ to a ‘1’.
For both of these conditions, the host must issue
a Read/Reset command to return the device to
the Read mode.
17
HY29F080
DQ[3] - Sector Erase Timer
After writing a Sector Erase command sequence,
the host may read DQ[3] to determine whether or
not an erase operation has begun. When the
sector erase time-out expires and the sector erase
operation commences, DQ[3] switches from a ‘0’
to a ‘1’. Refer to the “Sector Erase Command”
section for additional information. Note that the
sector erase timer does not apply to the Chip Erase
command.
After the initial Sector Erase command sequence
is issued, the system should read the status on
HARDWARE DATA PROTECTION
The HY29F080 provides several methods of protection to prevent accidental erasure or programming which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
These methods are described in the sections that
follow.
Command Sequences
Commands that may alter array data require a
sequence of cycles as described in Table 5. This
provides data protection against inadvertent writes.
Low VCC Write Inhibit
To protect data during VCC power-up and powerdown, the device does not accept write cycles
when VCC is less than VLKO (typically 3.7 volts). The
command register and all internal program/erase
circuits are disabled, and the device resets to the
Read mode. Writes are ignored until VCC is greater
than VLKO . The system must provide the proper
signals to the control pins to prevent unintentional
writes when VCC is greater than VLKO.
18
DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to
ensure that the device has accepted the command
sequence, and then read DQ[3]. If DQ[3] is a ‘1’,
the internally controlled erase cycle has begun and
all further sector erase data cycles or commands
(other than Erase Suspend) are ignored until the
erase operation is complete. If DQ[3] is a ‘0’, the
device will accept a sector erase data cycle to mark
an additional sector for erasure. To ensure that
the data cycles have been accepted, the system
software should check the status of DQ[3] prior to
and following each subsequent sector erase data
cycle. If DQ[3] is high on the second status check,
the last data cycle might not have been accepted.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#,
CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by asserting any one of
the following conditions: OE# = VIL , CE# = VIH, or
WE# = VIH. To initiate a write cycle, CE# and WE#
must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to the Read mode on powerup.
Sector Group Protection
Additional data protection is provided by the
HY29F080’s sector group protect feature, described previously, which can be used to protect
sensitive areas of the Flash array from accidental
or unauthorized attempts to alter the data.
Rev. 6.1/May 01
HY29F080
ABSOLUTE MAXIMUM RATINGS 4
Symbol
Value
Unit
TSTG
Storage Temperature
Parameter
-65 to +125
ºC
TBIAS
Ambient Temperature with Power Applied
-55 to +125
ºC
VIN2
Voltage on Pin with Respect to VSS :
VCC 1
A[9], OE#, RESET# 2
All Other Pins 1
-2.0 to +7.0
-2.0 to +13.5
-2.0 to +7.0
V
V
V
I OS
Output Short Circuit Current 3
200
mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to
-2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10.
2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET#
may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on these pins is +12.5
V which may overshoot to 13.5 V for periods up to 20 ns.
3. No more than one output at a time may be shorted to VSS. Duration of the short circuit should be less than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
TA
V CC
1
Parameter
Ambient Operating Temperature
Operating Supply Voltage
Value
Unit
0 to +70
+4.50 to +5.50
ºC
V
Notes:
1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.
20 ns
20 ns
20 ns
V C C + 2.0 V
0.8 V
- 0.5 V
V C C + 0.5 V
2.0 V
- 2.0 V
20 ns
Figure 9. Maximum Undershoot Waveform
Rev. 6.1/May 01
20 ns
20 ns
Figure 10. Maximum Overshoot Waveform
19
HY29F080
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Description
Test Setup
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC Max
ILIT
A[9] Input Load Current
VCC = VCC Max,
A[9] = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC Max
ICC1
VCC Active Read Current 1
2, 3
Min
Typ
Max
Unit
±1.0
µA
50
µA
±1.0
µA
CE# = VIL, OE# = VIH
25
40
mA
ICC2
VCC Active Write Current
CE# = VIL, OE# = VIH
40
60
mA
ICC3
VCC CE# Controlled
TTL Standby Current
VCC = VCC Max,
CE# = RESET# = VIH
0.4
1.0
mA
ICC4
VCC RESET# Controlled
TTL Standby Current
VCC = VCC Max,
RESET# = VIL
0.4
1.0
mA
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VID
Voltage for Electronic ID and
Temporary Sector Unprotect
VCC = 5.0V
11.5
12.5
V
VOL
Output Low Voltage
VCC = VCC Min,
IOL = 12.0ma
0.45
V
VOH
Output High Voltage
VCC = VCC Min,
IOH = -2.5 mA
VLKO
Low VCC Lockout Voltage 3
2.4
3.2
V
4.2
V
Notes:
1. Includes both the DC Operating Current and the frequency dependent component at 6 MHz. The read component of the
ICC current is typically less than 1 ma/MHz with OE# at VIL.
2. ICC active while Automatic Erase or Automatic Program algorithm is in progress.
3. Not 100% tested.
20
Rev. 6.1/May 01
HY29F080
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Setup
Min
Typ
Max
Unit
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC Max
±1.0
µA
ILIT
A[9] Input Load Current
VCC = VCC Max,
A[9] = 12.5 V
50
µA
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC Max
±1.0
µA
ICC1
VCC Active Read Current 1
2, 3
CE# = VIL, OE# = VIH
25
40
mA
CE# = VIL, OE# = VIH
30
40
mA
ICC2
VCC Active Write Current
ICC3
VCC CE# Controlled
CMOS Standby Current
VCC = VCC Max, CE# =
RESET# = VCC ± 0.5V
1
5
µA
ICC4
VCC RESET# Controlled
CMOS Standby Current
VCC = VCC Max,
RESET# = VSS ± 0.5V
1
5
µA
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
V
VID
Voltage for Electronic ID and
Temporary Sector Unprotect
VCC = 5.0V
11.5
12.5
V
VOL
Output Low Voltage
VCC = VCC Min,
IOL = 12.0ma
0.45
V
VOH
Output High Voltage
VCC = VCC Min,
IOH = -2.5 mA
0.85 x
VCC
V
VCC = VCC Min,
IOH = -100 µA
VCC - 0.4
V
Low VCC Lockout Voltage 3
VLKO
3.2
4.2
V
Notes:
1. Includes both the DC Operating Current and the frequency dependent component at 6 MHz. The read component of the
ICC current is typically less than 1 ma/MHz with OE# at VIL.
2. ICC active while Automatic Erase or Automatic Program algorithm is in progress.
3. Not 100% tested.
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUT S
OUT PUT S
Steady
Changing from H to L
Changing from L to H
Rev. 6.1/May 01
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Centerline is High Impedance State
(High Z)
21
HY29F080
TEST CONDITIONS
+ 5V
Table 7. Test Specifications
Test
Condition
2.7
KOhm
Output Load
DEVICE
UNDER
TEST
CL
All diodes
are
1N3064
or
equivalent
6.2
KOhm
- 70
- 90
- 12
Unit
1 TTL Gate
Output Load Capacitance (CL)
100
pF
Input Rise and Fall Times
20
ns
Input Signal Low Level
0.45
V
Input Signal High Level
2.4
V
0.8
V
2.0
V
Low Timing Measurement
Signal Level
High Timing Measurement
Signal Level
Figure 11. Test Setup
2.4 V
2.0 V
Input
0.45 V
Measurement
Levels
0.8 V
2.0 V
Output
0.8 V
HY29F080-70, -90, -12 Versions
Figure 12. Input Waveforms and Measurement Levels
22
Rev. 6.1/May 01
HY29F080
AC CHARACTERISTICS
Read Operations
Parameter
Description
JE D E C
Std
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tEHQZ
tGLQV
tGHQZ
tCE
tDF
tOE
tDF
Chip Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output Delay
Output Enable to Output High Z (Note 1)
Read
Output Enable
Hold Time (Note 1) Toggle and
Data# Polling
Output Hold Time from Addresses, CE#
or OE#, Whichever Occurs First (Note 1)
tOEH
tAXQX
tOH
Speed Option
Test Setup
CE# = VIL
OE# = VIL
OE# = VIL
CE# = VIL
Unit
- 70
- 90
- 12
Min
70
90
120
ns
Max
70
90
120
ns
Max
Max
Max
Max
Min
70
20
30
20
90
20
35
20
0
120
30
50
30
ns
ns
ns
ns
ns
Min
10
ns
Min
0
ns
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test conditions.
tR C
Addresses Stable
Addresses
tA C C
CE#
tO E
OE#
tO E H
WE#
Outputs
tD F
tC E
tO H
Output Valid
RESET#
RY/BY#
0 V
Figure 13. Read Operation Timings
Rev. 6.1/May 01
23
HY29F080
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JE D E C
Std
Description
Speed Option
Test Setup
RESET# Pin Low (During Automatic
tREADY Algorithms) to Read or Write (see Note
1)
RESET# Pin Low (NOT During
tREADY Automatic Algorithms) to Read or Write
(see Note 1)
tRP RESET# Pulse Width
RESET# High Time Before Read (see
tRH
Note 1)
- 70
- 90
- 12
Unit
Max
20
µs
Max
500
ns
Min
500
ns
Min
50
ns
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test conditions.
RY/BY#
0 V
CE#, OE#
tR H
RESET#
tR P
tR E A D Y
Reset
Timings
NOT
Automatic
Algorithms
Reset
Timings
NOT During
During Automatic
Algorithms
RY/BY#
tR E A D Y
CE#, OE#
RESET#
tR P
tR H
Reset Timings During Automatic Algorithms
Reset Timings During Automatic Algorithms
Figure 14. RESET# Timings
24
Rev. 6.1/May 01
HY29F080
AC CHARACTERISTICS
Program and Erase Operations
Parameter
JE D E C
Std
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
tGHWL
tELWL
tWHEH
tWLWH
tWHWL
tWC
tAS
tAH
tDS
tDH
tGHWL
tCS
tCH
tWP
tWPH
tWHWH1
tWHWH1 Byte Programming Operation (Notes 1, 2, 3)
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Read Recovery Time Before Write
CE# Setup Time
CE# Hold Time
Write Pulse Width
Write Pulse Width High
Chip Programming Operation (Notes 1, 2, 3, 5)
tWHWH2
tWHWH2 Sector Erase Operation (Notes 1, 2, 4)
tWHWH3
tWHWH3 Chip Erase Operation (Notes 1, 2, 4)
Erase and Program Cycle Endurance
tVCS
tRB
tBUSY
Speed Option
Description
VCC Setup Time
Recovery Time from RY/BY#
WE# to RY/BY# Delay
- 70
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Min
Min
Min
Min
70
- 90
- 12
90
120
0
45
45
50
30
45
50
0
0
0
0
35
45
50
20
7
300
7.2
21.6
1
8
16
128
1,000,000
100,000
50
0
40
40
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
se c
se c
se c
se c
se c
se c
cycles
cycles
µs
ns
ns
Notes:
1. Not 100% tested.
2. Typical program and erase times assume the following conditions: 25 °C, VCC = 5.0 volts, 100,000 cycles. In addition,
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 °C, VCC = 4.5 volts, 100,000 cycles.
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program
command. See Table 5 for further information on command sequences.
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes
are programmed to 0x00 before erasure.
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most
bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum
byte program time specified is exceeded. See Write Operation Status section for additional information.
Rev. 6.1/May 01
25
HY29F080
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tW C
Addresses
tA S
0x555
Read Status Data (last two cycles)
tA H
PA
PA
PA
CE#
tG H W L
OE#
tC H
tW P
WE#
tC S
tW P H
Data
0xA0
PD
tD S
tD H
RY/BY#
tW H W H 1
Status
tB U S Y
D OUT
tR B
V CC
tV C S
Notes:
1. PA = Program Address, PD = Program Data, DOUT is the true data at the program address.
2. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
Figure 15. Program Operation Timings
26
Rev. 6.1/May 01
HY29F080
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tW C
Addresses
tA S
0x2AA
Read Status Data (last two cycles)
tA H
SA
VA
VA
0x555 for chip erase
CE#
tG H W L
OE#
tC H
tW P
WE#
tC S
tW P H
Data
0x55
0x30
tD S
tD H
RY/BY#
0x10 for
chip erase
t W H W H 2 or t W H W H 3
Status
tB U S Y
D OUT
tR B
V CC
tV C S
Notes:
1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section),
DOUT is the true data at the read address.(0xFF after an erase operation).
2. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
Figure 16. Sector/Chip Erase Operation Timings
Rev. 6.1/May 01
27
HY29F080
AC CHARACTERISTICS
tR C
VA
Addresses
VA
VA
tA C C
tC H
tC E
CE#
tO E
OE#
tD F
tO E H
WE#
tO H
DQ[7]
Complement
DQ[6:0]
Status Data
Complement
Status Data
True
Valid Data
True
Valid Data
tB U S Y
RY/BY#
Notes:
1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section).
2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.
Figure 17. Data# Polling Timings (During Automatic Algorithms)
tR C
VA
Addresses
VA
VA
VA
Valid Data
tA C C
tC H
tC E
CE#
tO E
OE#
tO E H
WE#
tD F
tO H
DQ[6], [2]
tB U S Y
Valid Status
Valid Status
Valid Status
(first read)
(second read)
(stops toggling)
RY/BY#
Notes:
1. VA = Valid Address for reading Toggle Bits (DQ2, DQ6) status data (see Write Operation Status section).
2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle.
Figure 18. Toggle Polling Timings (During Automatic Algorithms)
28
Rev. 6.1/May 01
HY29F080
AC CHARACTERISTICS
Enter
Automatic
Erase
WE#
Erase
Suspend
Erase
Enter Erase
Suspend
Program
Erase
Suspend
Read
Erase
Resume
Erase
Suspend
Program
Erase
Suspend
Read
Erase
Erase
Complete
DQ[6]
DQ[2]
Notes:
1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an
erase-suspended sector.
Figure 19. DQ[2] and DQ[6] Operation
Sector Group Protect and Unprotect, Temporary Sector Group Unprotect
Parameter
JE D E C
Std
tST
tRSP
tCE
tOE
tVIDR
tVLHT
tWPP1
tWPP2
tOESP
tCSP
Speed Option
Description
Voltage Setup Time
RESET# Setup Time for
Temporary Sector Group Unprotect
Chip Enable to Output Delay
Output Enable to Output Delay
Voltage Transition Time for
Temporary Sector Group Unprotect (Note 1)
Voltage Transition Time for
Sector Group Protect and Unprotect (Note 1)
Write Pulse Width for Sector Group Protect
Write Pulse Width for Sector Group Unprotect
OE# Setup Time to WE# Active (Note 1)
CE# Setup Time to WE# Active (Note 1)
- 70
- 90
- 12
Unit
Min
50
µs
Min
4
µs
Max
Max
70
30
90
35
120
50
ns
ns
Min
500
ns
Min
4
µs
Min
Min
Min
Min
100
100
4
4
µs
ms
µs
µs
Notes:
1. Not 100% tested.
Rev. 6.1/May 01
29
HY29F080
AC CHARACTERISTICS
Group Protect Cycle
A[19:17]
Protect Verify Cycle
SGA X
SGA Y
A[0]
A[1]
A[6]
V ID
A[9]
tV L H T
tV L H T
tV L H T
V ID
OE#
tO E S P
tV L H T
tW P P 1
WE#
tO E
CE#
Data
0x01
RESET#
tS T
tS T
V CC
tS T
Figure 20. Sector Group Protect Timings
30
Rev. 6.1/May 01
HY29F080
AC CHARACTERISTICS
Group Unprotect Cycle
Unprotect Verify Cycle
SGA 0
A[19:17]
SGA 1
A[0]
A[1]
A[6]
V ID
A[9]
tV L H T
tV L H T
V ID
OE#
tO E
tO E S P
V ID
CE#
tC S P
tW P P 2
tC E
WE#
Data
0x00
RESET#
V CC
tS T
Figure 21. Sector Group Unprotect Timings
Rev. 6.1/May 01
31
HY29F080
AC CHARACTERISTICS
V ID
RESET#
0 or 5V
0 or 5V
t VIDR
t VIDR
CE#
WE#
tR S P
RY/BY#
Figure 22. Temporary Sector Group Unprotect Timings
32
Rev. 6.1/May 01
HY29F080
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Option
Description
JE D E C
Std
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
tWC
tAS
tAH
tDS
tDH
tGHEL
tWS
tWH
tCP
tCPH
tWHWH1
tWHWH1 Byte Programming Operation (Notes 1, 2, 3)
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Read Recovery Time Before Write
WE# Setup Time
WE# Hold Time
CE# Pulse Width
CE# Pulse Width High
Chip Programming Operation (Notes 1, 2, 3, 5)
tWHWH2
tWHWH2 Sector Erase Operation (Notes 1, 2, 4)
tWHWH3
tWHWH3 Chip Erase Operation (Notes 1, 2, 4)
Erase and Program Cycle Endurance
- 70
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Min
70
- 90
- 12
90
120
0
45
45
50
30
45
50
0
0
0
0
35
45
50
20
7
300
7.2
21.6
1
8
16
128
1,000,000
100,000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
se c
se c
se c
se c
se c
se c
cycles
cycles
Notes:
1. Not 100% tested.
2. Typical program and erase times assume the following conditions: 25 °C, VCC = 5.0 volts, 100,000 cycles. In addition,
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 °C, VCC = 4.5 volts, 100,000 cycles.
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program
command. See Table 5 for further information on command sequences.
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes
are programmed to 0x00 before erasure.
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most
bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum
byte program time specified is exceeded. See Write Operation Status section for additional information.
Rev. 6.1/May 01
33
HY29F080
AC CHARACTERISTICS
0x555 for Program
0x2AA for Erase
PA for Program
SA for Sector Erase
0x555 for Chip Erase
Addresses
VA
tW C
tA S
tA H
WE#
tG H E L
tW H
OE#
tW S
tC P
tC P H
t W H W H 1 or t W H W H 2 or t W H W H 3
CE#
tD S
tD H
tB U S Y
Data
Status
0xA0 for Program
0x55 for Erase
D OUT
PD for Program
0x30 for Sector Erase
0x10 for Chip Erase
RY/BY#
tR H
RESET#
Notes:
1. PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write
Operation Status section), DOUT = array data read at VA.
2.
Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle.
3. Word mode addressing shown.
4. RESET# shown only to illustrate tRH measurement references. It cannot occur as shown during a valid
command sequence.
Figure 23. Alternate CE# Controlled Write Operation Timings
34
Rev. 6.1/May 01
HY29F080
Latchup Characteristics
Description
Minimum
Maximum
Unit
Input voltage with respect to VSS on all I/O pins
- 1.0
VCC + 1.0
V
VCC Current
- 100
100
mA
Notes:
1. Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time.
TSOP Pin Capacitance
Symbol
CIN
Parameter
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Test Setup
Typ
Max
Unit
VIN = 0
6
7.5
pF
VOUT = 0
8.5
12
pF
VIN = 0
8
9
pF
Test Setup
Typ
Max
Unit
VIN = 0
6
7.5
pF
VOUT = 0
8.5
12
pF
VIN = 0
7.5
10
pF
Test Conditions
Minimum
Unit
150 ºC
10
Years
125 ºC
20
Years
Notes:
1. Sampled, not 100% tested.
2. Test conditions: TA = 25 ºC, f = 1.0 MHz.
PSOP Pin Capacitance
Symbol
CIN
Parameter
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions: TA = 25 ºC, f = 1.0 MHz.
Data Retention
Parameter
Minimum Pattern Data Retention Time
Rev. 6.1/May 01
35
HY29F080
PACKAGE DRAWINGS
Physical Dimensions
TSOP40 - 40-pin Thin Small Outline Package (measurements in millimeters)
0.95
1.05
Pin 1 ID
1
40
9.90
10.10
20
0.50 BSC
21
18.30
18.50
0.05
0.15
19.90
20.10
0.08
0.20
1.20
MAX
0.10
0.20
o
0
o
5
0.25 BSC
0.50
0.68
PSOP44 - 44-pin Plastic Small Outline Package (measurements in millimeters)
23
44
15.70
16.30
13.10
0.10
0.21
13.50
O
0
O
8
1
0.60
1.00
22
1.27 NOM.
28.00
28.40
2.17
2.45
2.80
MAX.
SEATING PLANE
0.35
0.50
36
0.10
0.35
Rev. 6.1/May 01
HY29F080
ORDERING INFORMATION
Hynix products are available in several speeds, packages and operating temperature ranges. The
ordering part number is formed by combining a number of fields, as indicated below. Refer to the ‘Valid
Combinations’ table, which lists the configurations that are planned to be supported in volume. Please
contact your local Hynix representative or distributor to confirm current availability of specific configurations and to determine if additional configurations have been released.
HY29F080
X
-
X
X
X
SPECIAL INSTRUCTIONS
TEMPERATURE RANGE
Blank = Commercial ( 0 to +70 °C)
SPEED OPTION
70 = 70 ns
90 = 90 ns
12 = 120 ns
PACKAGE TYPE
G = 44-Pin Plastic Small Outline Package (PSOP)
T = 40-Pin Thin Small Outline Package (TSOP)
R = 40-Pin Thin Small Outline Package (TSOP) with
Reverse Pinout
DEVICE NUMBER
HY29F080 = 8 Megabit (1M x 8) CMOS 5-Volt Only Sector Erase
Flash Memory
VALID COMBINATIONS
P ackag e an d S p eed
PSOP
TSOP
Reverse TSOP
Temperature
70 n s
90 n s
120 n s
70 n s
90 n s
120 n s
70 n s
90 n s
120 n s
Commercial
G-70
G-90
G-12
T-70
T-90
T-12
R-70
R-90
R-12
Note:
1. The complete part number is formed by appending the suffix shown in the table to the Device Number. For example, the
part number for a 90 ns, Commercial temperature range device in the TSOP package is HY29F080T-90.
Rev. 6.1/May 01
37
HY29F080
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Revision Record
Rev.
Date
6.1
5/01
Details
Change to Hynix format.
Removed 55 ns speed option and Industrial and Extended temperature options.
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