IRFR9024, IRFU9024, SiHFR9024, SiHFU9024 Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) - 60 RDS(on) (Ω) VGS = - 10 V 0.28 Qg (Max.) (nC) 19 Qgs (nC) 5.4 Qgd (nC) 11 Configuration Single S • • • • • • • • Dynamic dV/dt Rating Repetitive Avalanche Rated Surface Mount (IRFR9024/SiHFR9024) Straight Lead (IRFU9024/SiHFU9024) Available in Tape and Reel P-Channel Fast Switching Lead (Pb)-free Available Available RoHS* COMPLIANT DESCRIPTION DPAK (TO-252) IPAK (TO-251) G D P-Channel MOSFET Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effictiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU/SiHFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surcace mount applications. ORDERING INFORMATION Package Lead (Pb)-free SnPb DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251) IRFR9024PbF IRFR9024TRPbFa IRFR9024TRLPbFa IRFR9024TRRPbFa IRFU9024PbF SiHFR9024-E3 SiHFR9024T-E3a SiHFR9024TL-E3a SiHFR9024TR-E3a SiHFU9024-E3 IRFR9024 IRFR9024TRa IRFR9024TRLa - IRFU9024 SiHFR9024 SiHFR9024Ta SiHFR9024TLa - SiHFU9024 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER SYMBOL LIMIT VDS VGS - 60 ± 20 - 8.8 - 5.6 - 35 0.33 0.020 300 - 8.8 5.0 42 2.5 - 4.5 - 55 to + 150 260d Drain-Source Voltage Gate-Source Voltage Continuous Drain Current VGS at - 10 V TC = 25 °C TC = 100 °C ID IDM Pulsed Drain Currenta Linear Derating Factor Linear Derating Factor (PCB Mount)e Single Pulse Avalanche Energyb EAS IAR Repetitive Avalanche Currenta Repetitive Avalanche Energya EAR Maximum Power Dissipation TC = 25 °C PD TA = 25 °C Maximum Power Dissipation (PCB Mount)e c dV/dt Peak Diode Recovery dV/dt Operating Junction and Storage Temperature Range TJ, Tstg Soldering Recommendations (Peak Temperature) for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = - 25 V, starting TJ = 25 °C, L = 4.5 mH, RG = 25 Ω, IAS = - 8.8 A (see fig. 12). c. ISD ≤ - 11 A, dI/dt ≤ 140 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). www.kersemi.com UNIT V A W/°C mJ A mJ W V/ns °C 1 IRFR9024, IRFU9024, SiHFR9024, THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - - 110 Maximum Junction-to-Ambient (PCB Mount)a RthJA - - 50 Maximum Junction-to-Case (Drain) RthJC - - 3.0 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance VDS VGS = 0 V, ID = 250 µA - 60 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - - 0.063 - V/°C VGS(th) VDS = VGS, ID = 250 µA - 2.0 - - 4.0 V nA IGSS IDSS RDS(on) gfs VGS = ± 20 V - - ± 100 VDS = - 60 V, VGS = 0 V - - - 100 VDS = - 48 V, VGS = 0 V, TJ = 125 °C - - - 500 - - 0.28 Ω VDS = - 25 V, ID = - 5.3 A 2.9 - - S VGS = 0 V, VDS = - 25 V, f = 1.0 MHz - 570 - - 360 - - 65 - - - 19 - - 5.4 ID = - 5.3 Ab VGS = - 10 V µA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs VGS = - 10 V ID = - 11 A, VDS = - 48 V, see fig. 6 and 13b pF nC Gate-Drain Charge Qgd - - 11 Turn-On Delay Time td(on) - 13 - - 68 - - 15 - - 29 - - 4.5 - - 7.5 - - - - 8.8 S - - - 35 TJ = 25 °C, IS = - 8.8 A, VGS = 0 Vb - - - 6.3 V - 100 200 ns - 0.32 0.64 µC Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = - 30 V, ID = - 11 A, RG = 18 Ω, RD = 2.5 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact D ns nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode A G TJ = 25 °C, IF = - 11 A, dI/dt = 100 A/µsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. 2 D www.kersemi.com IRFR9024, IRFU9024, SiHFR9024, SiHFU9024 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 -Typical Output Characteristics, TC = 150 °C Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.kersemi.com 3 IRFR9024, IRFU9024, SiHFR9024, Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area www.kersemi.com IRFR9024, IRFU9024, SiHFR9024, SiHFU9024 RD VDS VGS D.U.T. RG + - VDD - 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit td(on) tr td(off) tf VGS 10 % 90 % VDS Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case www.kersemi.com 5 IRFR9024, IRFU9024, SiHFR9024, L Vary tp to obtain required IAS IAS VDS VDS D.U.T. RG + V DD VDD IAS tp - 10 V 0.01 Ω tp VDS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG - 10 V 12 V 0.2 µF 0.3 µF QGS - QGD D.U.T. VG + VDS VGS - 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform 6 Fig. 13b - Gate Charge Test Circuit www.kersemi.com IRFR9024, IRFU9024, SiHFR9024, SiHFU9024 Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG + • dV/dt controlled by RG • ISD controlled by duty factor "D" • D.U.T. - device under test + - VDD Compliment N-Channel of D.U.T. for driver Driver gate drive P.W. Period D= P.W. Period VGS = - 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % * ISD VGS = - 5 V for logic level and - 3 V drive devices Fig. 14 - For P-Channel www.kersemi.com 7