Allegro A1363LLUTR-1-T Low noise, high precision, programmable linear hall effect sensor ic Datasheet

A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation and High Bandwidth (120 kHz) Analog Output
FEATURES AND BENEFITS
DESCRIPTION
• Proprietary segmented linear interpolated temperature
compensation (TC) technology provides a typical
accuracy of 1% across the full operating temperature
range
• Customer programmable, high resolution offset and
sensitivity trim
• Factory programmed sensitivity and quiescent
output voltage TC with extremely stable temperature
performance
• High sensitivity Hall element for maximum accuracy
• Extremely low noise and high resolution achieved via
proprietary Hall element and low noise amplifier circuits
• 120 kHz nominal bandwidth achieved via proprietary
packaging and chopper stabilization techniques
• Patented circuits suppress IC output spiking during fast
current step inputs
The Allegro™ A1363 programmable linear Hall-effect
current sensor IC has been designed to achieve high accuracy
and resolution without compromising bandwidth. The goal
is achieved through new proprietary linearly interpolated
temperature compensation technology that is programmed
at the Allegro factory and provides sensitivity and offset that
are virtually flat across the full operating temperature range.
Temperature compensation is done in the digital domain with
integrated EEPROM technology, without sacrificing the analog
signal path 120 kHz bandwidth, making this device ideal for
HEV inverter, DC-to-DC converter, and electric power steering
(EPS) applications.
This ratiometric Hall-effect sensor IC provides a voltage output
that is proportional to the applied magnetic field. The customer
can configure the sensitivity and quiescent (zero field) output
voltage through programming on the VCC and output pins,
to optimize performance in the end application. The quiescent
output voltage is user-adjustable around 50% of the supply
voltage, VCC , and the output sensitivity is adjustable within
the range of 0.6 to 14 mV/G.
Continued on the next page…
Package: 8-pin TSSOP (suffix LU)
The sensor IC incorporates a highly sensitive Hall element with
a BiCMOS interface integrated circuit that employs a low noise
small-signal high-gain amplifier, a clamped, low-impedance
output stage, and a proprietary, high bandwidth dynamic offset
Not to scale
Continued on the next page…
V+
VCC
(Programming)
To all subcircuits
Programming
Control
Temperature
Sensor
C BYPASS
EEPROM and
Control Logic
Dynamic Offset
Cancellation
Sensitivity Control
Offset Control
Signal Recovery
GND
Functional Block Diagram
A1363LU-DS, Rev. 4
VOUT
(Programming)
CL
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
Features and Benefits (continued)
• Open circuit detection on ground pin (broken wire)
• Undervoltage lockout for VCC below specification
• Selectable sensitivity range between 0.6 and 14 mV/G through
use of coarse sensitivity programming bits
• Ratiometric sensitivity, quiescent voltage output, and clamps
for interfacing with application A-to-D converter (ADC)
• Precise recoverability after temperature cycling
• Output voltage clamps provide short circuit diagnostic
capabilities
• Wide ambient temperature range: –40°C to 150°C
• Immune to mechanical stress
• Extremely thin package: 1 mm case thickness
• AEC Q-100 automotive qualified
Selection Guide
Part Number
A1363LLUTR-1-T
A1363LLUTR-2-T
A1363LLUTR-5-T
A1363LLUTR-10-T
Packing1
4000 pieces per 13-in. reel
4000 pieces per 13-in. reel
4000 pieces per 13-in. reel
4000 pieces per 13-in. reel
Description (continued)
cancellation technique. These advances in Hall-effect technology
work together to provide an industry leading sensing resolution at
the full 120 kHz bandwidth. Broken ground wire detection, as well
as user-selectable output voltage clamps, are also built into this
device, for high reliability in automotive applications.
Device parameters are specified across the full automotive
temperature range: –40°C to 150°C. The A1363 sensor IC is provided
in a low-profile 8-pin surface mount TSSOP package (thin shrink
small outline package, suffix LU) that is lead (Pb) free, with 100%
matte tin leadframe plating.
Sensitivity Range2
(mV/G)
SENS_COARSE 00: 0.6 to 1.3
SENS_COARSE 01: 1.3 to 2.9
SENS_COARSE 10: 2.9 to 6.4
SENS_COARSE 11: 6.4 to 14
1Contact Allegro
for additional packing options
recommends against changing Coarse Sensitivity settings when programming devices that will be used in production. Each
A1363 has been Factory Temperature Compensated at a specific Sensitivity Range and changing coarse bits setting could cause sensitivity drift through temperature range ,ΔSensTC , to exceed specified limits..
2Allegro
Specifications
Absolute Maximum Ratings
Pin-out Diagram and Terminal List
Thermal Characteristics
Operating Characteristics
Characteristic Performance Data
Characteristic Definitions
Functional Description
Programming Sensitivity and Quiescent
Voltage Output
Coarse Sensitivity
Memory Locking Mechanisms
Power-On Reset (POR) and Undervoltage
Lock-Out (UVLO) Operation
Detecting Broken Ground Wire
Table of Contents
2
3
3
3
4
8
12
17
17
17
17
18
19
20
Chopper Stabilization Technique
Programming Serial Interface
21
Transaction Types
21
Writing the Access Code
21
Writing to Volatile Memory
21
Writing to EEPROM
22
Reading from EEPROM or Volatile Memory
22
Error Checking
22
Serial Interface Reference
23
Serial Interface Message Structure
24
VCC Levels During Manchester Communication 24
EEPROM Cell Organization
26
EEPROM Error Checking and Correction (ECC) 27
Detecting ECC Error
27
Package Drawing
28
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
SPECIFICATIONS
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Unit
Forward Supply Voltage
VCC
6
V
Reverse Supply Voltage
VRCC
–0.1
V
Forward Output Voltage
VOUT
25
V
Reverse Output Voltage
VROUT
–0.1
V
Output Source Current
IOUT(source)
VOUT to GND
2.8
mA
IOUT(sink)
VCC to VOUT
10
mA
100
cycle
–40 to 150
ºC
Output Sink Current
Maximum Number of EEPROM Write Cycles
Operating Ambient Temperature
EEPROMW(max)
TA
Storage Temperature
Maximum Junction Temperature
L temperature range
Tstg
–65 to 165
ºC
TJ(max)
165
ºC
Value
Unit
145
ºC/W
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic
Symbol
Package Thermal Resistance
RθJA
Test Conditions*
LU package, estimated, on 4-layer PCB based on
JEDEC standard
*Additional thermal information available on the Allegro website
Pin-out Diagram and Terminal List Table
GND 1
8 VCC
VOUT 2
7 NF
NF 3
6 NF
NF 4
5 NF
Package LU, 8-Pin TSSOP
Terminal List Table
Number
Name
Function
1
GND
Ground
2
VOUT
Output signal, also used for programming
3, 4, 5, 6, 7
NF
8
VCC
No function; do not leave floating, connect to GND
Input power supply, use bypass capacitor to connect to ground; also
used for programming
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
OPERATING CHARACTERISTICS Valid through the full operating temperature range, TA, CBYPASS = 0.1 µF, VCC = 5 V; un-
less otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
Electrical Characteristics
Supply Voltage
VCC
4.5
5.0
5.5
V
Supply Current
ICC
No load on VOUT
–
10
15
mA
Power-On Time2
tPO
TA = 25°C, CBYPASS = Open, CL = 1 nF, Sens =
2 mV/G, constant magnetic field of 400 G
–
78
–
µs
Temperature Compensation
Power-On Time2
tTC
TA = 150°C, CBYPASS = Open, CL= 1 nF, Sens
= 2 mV/G, constant magnetic field of 400 G
–
30
–
µs
VUVLOH
TA = 25°C, VCC rising and device function
enabled
–
3.8
–
V
VUVLOL
TA = 25°C, VCC falling and device function
disabled
–
3.3
–
V
tUVLOE
TA = 25°C, CBYPASS = Open, CL = 1 nF, Sens =
2 mV/G, VCC Fall Time (5 V to 3 V) = 1.5 µs
–
64
–
µs
tUVLOD
TA = 25°C, CBYPASS = Open, CL = 1 nF, Sens
= 2 mV/G, VCC Recover Time (3 V to 5 V) =
1.5 µs
–
14
–
µs
VPORH
TA = 25°C, VCC rising
–
2.6
–
V
VPORL
TA = 25°C, VCC falling
–
2.3
–
V
tPORR
TA = 25°C, VCC rising
–
64
–
µs
Undervoltage Lockout (UVLO)
Threshold2
UVLO Enable/Disable Delay Time2
Power-On Reset Voltage2
Power-On Reset Release Time2
Supply Zener Clamp Voltage
Vz
6.5
7.5
–
V
Small signal –3 dB, CL = 1 nF, TA = 25°C
–
120
–
kHz
fC
TA = 25°C
–
500
–
kHz
Propagation Delay Time2
tPD
TA = 25°C, magnetic field step of 400 G,
CL = 1 nF, Sens = 2 mV/G
–
1.9
–
µs
Rise Time2
tR
TA = 25°C, magnetic field step of 400 G,
CL = 1 nF, Sens = 2 mV/G
–
4.3
–
µs
Response Time2
tRESPONSE
TA = 25°C, magnetic field step of 400 G,
CL = 1 nF, Sens = 2 mV/G
–
3.8
–
µs
Delay to Clamp2
tCLP
TA = 25°C, Step magnetic field from 800 to
1200 G, CL = 1 nF, Sens = 2 mV/G
–
10
–
µs
Internal Bandwidth
Chopping Frequency3
BWi
TA = 25°C, ICC = 30 mA
Output Characteristics
Output Voltage Clamp4
Output Saturation Voltage2
Broken Wire Voltage2
VCLP(HIGH)
TA = 25°C, RL(PULLDWN) = 10 kΩ to GND
4.55
–
4.85
V
VCLP(LOW)
TA = 25°C, RL(PULLUP) = 10 kΩ to VCC
0.15
–
0.45
V
VSAT(HIGH)
TA = 25°C, RL(PULLDWN) = 10 kΩ to GND
4.7
–
–
V
VSAT(LOW)
TA = 25°C, RL(PULLUP) = 10 kΩ to VCC
–
–
400
mV
VBRK(HIGH)
TA = 25°C, RL(PULLUP) = 10 kΩ to VCC
–
VCC
–
V
VBRK(LOW)
TA = 25°C, RL(PULLDWN) = 10 kΩ to GND
–
100
–
mV
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
OPERATING CHARACTERISTICS (continued): valid through the full operating temperature range, TA, CBYPASS = 0.1 µF,
VCC = 5 V; unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
TA = 25°C, CL = 1 nF, BWf = BWi
–
1.1
–
mGRMS/√¯(Hz)
TA = 25°C, CL = 1 nF, Sens = 2 mV/G,
BWf = BWi
–
6.3
–
mVp-p
TA = 25°C, CL = 1 nF, Sens = 2 mV/G,
BWf = BWi
–
1
–
mVRMS
TA = 25°C, VOUT = 2.5 V
–
<1
–
Ω
Output Characteristics (continued)
Noise5
VN
DC Output Resistance
Output Load Resistance
Output Load
Capacitance6
Output Slew Rate7
ROUT
RL(PULLUP)
VOUT to VCC
4.7
–
–
kΩ
RL(PULLDWN)
VOUT to GND
4.7
–
–
kΩ
CL
VOUT to GND
–
1
10
nF
SR
Sens = 2 mV/G, CL = 1 nF
–
230
–
V/ms
Quiescent Voltage Output (VOUT(Q))2
Initial Unprogrammed Quiescent
Voltage Output2,8
VOUT(Q)init
TA = 25°C
2.4
2.5
2.6
V
Quiescent Voltage Output
Programming Range2,4,9
VOUT(Q)PR
TA = 25°C
2.3
–
2.7
V
Quiescent Voltage Output
Programming Bits10
QVO
–
9
–
bit
1.9
2.3
2.8
mV
–
±0.5 ×
StepVOUT(Q)
–
mV
Average Quiescent Voltage Output
Programming Step Size2,11,12
StepVOUT(Q)
Quiescent Voltage Output
Programming Resolution2,13
ErrPGVOUT(Q) TA = 25°C
TA = 25°C
Sensitivity (Sens)2
Initial Unprogrammed Sensitivity8
Sensitivity Programming Range4,9
Sensinit
SensPR
SENS_COARSE = 00, TA = 25°C
–
1
–
mV/G
SENS_COARSE = 01, TA = 25°C
–
2.2
–
mV/G
SENS_COARSE = 10, TA = 25°C
–
4.7
–
mV/G
SENS_COARSE = 11, TA = 25°C
–
9.6
–
mV/G
SENS_COARSE = 00, TA = 25°C
0.6
–
1.3
mV/G
SENS_COARSE = 01, TA = 25°C
1.3
–
2.9
mV/G
SENS_COARSE = 10, TA = 25°C
2.9
–
6.4
mV/G
SENS_COARSE = 11, TA = 25°C
6.4
–
14
mV/G
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
OPERATING CHARACTERISTICS (continued): valid through the full operating temperature range, TA, CBYPASS = 0.1 µF,
VCC = 5 V; unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
–
2
–
bit
Sensitivity Programming (continued)
Coarse Sensitivity Programming
Bits14
Fine Sensitivity Programming Bits10
SENS_
COARSE
SENS_FINE
SENS_COARSE = 00, TA = 25°C
Average Fine Sensitivity Programming
Step Size2,11,12
Sensitivity Programming
Resolution2,13
StepSENS
ErrPGSENS
–
9
–
bit
2.4
3.2
4.1
µV/G
SENS_COARSE = 01, TA = 25°C
5
6.6
8.5
µV/G
SENS_COARSE = 10, TA = 25°C
11
14.2
18
µV/G
SENS_COARSE = 11, TA = 25°C
22
29
38
µV/G
–
±0.5 ×
StepSENS
–
µV/G
–
0
–
%/°C
TA = 25°C to 150°C
–3.5
–
3.5
%
TA = –40°C to 25°C
–3.5
–
3.5
%
–
< 0.3
–
%
–
0
–
mV/°C
TA = 25°C to 150°C
–15
–
15
mV
TA = –40°C to 25°C
–30
–
30
mV
TA = 25°C
Factory Programmed Sensitivity Temperature Coefficient
Sensitivity Temperature Coefficient2
TCSENS
Sensitivity Drift Through Temperature
Range2,9,15,20
ΔSensTC
Average Sensitivity Temperature
Compensation Step Size
TA=150°C, TA= –40°C, calculated relative to
25°C
StepSENSTC
Factory Programmed Quiescent Voltage Output Temperature Coefficient
Quiescent Voltage Output
Temperature Coefficient2
TCQVO
TA = 150°C, TA = –40°C, calculated relative to
25°C
Quiescent Voltage Output Drift
Through Temperature Range2,9,15
ΔVOUT(Q)TC
Average Quiescent Voltage
Output Temperature Compensation
Step Size
StepQVOTC
–
2.3
–
mV
EELOCK
–
1
–
bit
Lock Bit Programming
EEPROM Lock Bit
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
OPERATING CHARACTERISTICS (continued): valid through the full operating temperature range, TA, CBYPASS = 0.1 µF,
VCC = 5 V; unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
–1
< ±0.25
1
%
Error Components
Linearity Sensitivity Error2,16
Symmetry Sensitivity
Error2
LinERR
–1
< ±0.25
1
%
RatERRVOUT(Q)
Through supply voltage range (relative to VCC
= 5 V)
–1
0
1
%
Ratiometry Sensitivity Error2,17
RatERRSens
Through supply voltage range (relative to VCC
= 5 V)
–2
< ±0.5
2
%
Ratiometry Clamp Error2,18
RatERRCLP
Through supply voltage range (relative to VCC
= 5 V), TA = 25°C
–
< ±1.0
–
%
Sensitivity Drift Due to Package
Hysteresis2
ΔSensPKG
TA = 25°C, after temperature cycling, 25°C to
150°C and back to 25°C
–
–1.5 ±
1.5
–
%
Sensitivity Drift Over Lifetime19
ΔSensLIFE
TA = 25°C, shift after AEC Q100 grade 0
qualification testing
–
±1
–
%
Ratiometry Quiescent Voltage Output
Error2,17
SymERR
11
G (gauss) = 0.1 mT (millitesla).
Characteristic Definitions section.
3f varies up to approximately ± 20% over the full operating ambient temperature range, T , and process.
C
A
4Sens, V
OUT(Q) , VCLP(LOW) , and VCLP(HIGH) scale with VCC due to ratiometry.
5Noise, measured in mV
and
in
mV
,
is
dependent
on
the
sensitivity
of
the
device.
PP
RMS
6Output stability is maintained for capacitive loads as large as 10 nF.
7High-to-low transition of output voltage is a function of external load components and device sensitivity.
8Raw device characteristic values before any programming.
9Exceeding the specified ranges will cause sensitivity and Quiescent Voltage Output drift through the temperature range to deteriorate beyond the specified values.
10Refer to Functional Description section.
11Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Definitions section.
12Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be greater than twice the maximum specified value of
StepVOUT(Q) or StepSENS.
13Overall programming value accuracy. See Characteristic Definitions section.
14Each A1363 part number is factory programmed and temperature compensated at a different coarse sensitivity setting. Changing coarse bits setting could cause sensitivity drift through temperature range ,ΔSensTC , to exceed specified limits.
15Allegro tests and temperature compensates each device at 150°C. Allegro does not test devices at –40°C. Temperature compensation codes will be applied based on
characterization data.
16Linearity applies to output voltage ranges of ±2 V from the quiescent output for bidirectional devices.
17Percent change from actual value at V
CC = 5 V, for a given temperature, through the supply voltage operating range.
18Percent change from actual value at V
CC = 5 V, TA = 25°C, through the supply voltage operating range.
19Based on characterization data obtained during standardized stress test for Qualification of Integrated Circuits. Can not be guaranteed. Drift is a function of customer application conditions. Please contact Allegro MicroSystems for further information.
20Includes sensitivity drift due to package hysteresis observed during factory testing.
2See
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
CHARACTERISTIC PERFORMANCE DATA
Response Time (tRESPONSE)
400 G excitation signal with 10%-90% rise time = 1 µs
Sensitivity = 2 mV/G, CBYPASS=0.1 µF, CL=1 nF
Input = 400 G Excitation Signal
80% of Input
Output (VOUT, mV)
tRESPONSE = 3.8 µs
80% of Output
Propagation Delay (tPD)
400 G excitation signal with 10%-90% rise time = 1 µs
Sensitivity = 2 mV/G, CBYPASS=0.1 µF, CL=1 nF
Input = 400 G Excitation Signal
Output (VOUT, mV)
tPD = 1.9 µs
20% of Input
20% of Output
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
Rise Time (tR)
400 G excitation signal with 10%-90% rise time = 1 µs
Sensitivity = 2 mV/G, CBYPASS=0.1 µF, CL=1 nF
Input = 400 G Excitation Signal
Output (VOUT, mV)
90% of Output
tR = 4.3 µs
10% of Output
Power-On Time(t PO )
400 G constant excitation signal, with VCC 10%- 90% rise time = 1.5 µs
Sensitivity = 2 mV/G, CBYPASS= Open, CL=1 nF
Supply (VCC, V)
VCC(min)
tPO = 78 µs
Output (VOUT, V)
90% of Output
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
UVLO Enable Time (t UVLOE )
VCC 5 V-3 V fall time = 1.5 µs
Sensitivity = 2 mV/G, CBYPASS= Open, CL=1 nF
Supply (VCC, V)
VUVLOL
tUVLOE = 65 µs
Output (VOUT, V)
Output = 0 V
UVLO Disable Time (t UVLOD )
VCC 3 V-5 V recovery time = 1.5 µs
Sensitivity = 2 mV/G, CBYPASS= Open, CL=1 nF
Supply (VCC, V)
VCC(min)
tUVLOD
= 13 µs
Output (VOUT, V)
90% of Output
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
Quiescent Voltage Output Drift Through Temperature Range
versus Ambient Temperature
∆VOUT(Q) TC (typ), (mV)
30
20
Relative to ∆VOUT(Q)TC (typ) at TA = 25°C
10
0
-10
-20
-30
-50
0
50
100
150
200
TA (°C)
Sensitivity Drift Through Temperature Range
versus Ambient Temperature
3
Relative to ∆SensTC (typ) at TA = 25°C
∆Sens TC (typ), (%)
2
1
0
-1
-2
-3
-50
0
50
100
150
200
TA (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
CHARACTERISTIC DEFINITIONS
Power-On Time (tPO) When the supply is ramped to its operat-
ing voltage, the device requires a finite time to power its internal
components before responding to an input magnetic field.
Power-On Time, tPO , is defined as: the time it takes for the output
voltage to settle within ±10% of its steady state value under an
applied magnetic field, after the power supply has reached its
minimum specified operating voltage, VCC(min), as shown in
Figure 1.
Temperature Compensation Power-On Time (tTC ) After Power-
On Time, tPO , elapses, tTC is also required before a valid temperature compensated output.
(%)
90
Applied Magnetic Field
Transducer Output
Rise Time, tR
20
10
0
Propagation Delay, tPD
Propagation Delay (tPD) The time interval between a) when the
t
applied magnetic field reaches 20% of it’s final value, and b)
when the output reaches 20% of its final value (see figure 2).
Rise Time (tR) The time interval between a) when the sensor IC
reaches 10% of its final value, and b) when it reaches 90% of its
final value (see Figure 2).
Response Time (tRESPONSE) The time interval between a) when
the applied magnetic field reaches 80% of its final value, and b)
when the sensor reaches 80% of its output corresponding to the
applied magnetic field (see Figure 3).
Delay to Clamp (tCLP ) A large magnetic input step may cause the
clamp to overshoot its steady state value. The Delay to Clamp,
tCLP , is defined as: the time it takes for the output voltage to
Figure 2: Propagation Delay and Rise Time definitions
(%)
80
Applied Magnetic Field
Transducer Output
Response Time, tRESPONSE
0
V
t
VCC
VCC(typ.)
Figure 3: Response Time definition
VOUT
90% VOUT
VCC(min.)
t1
t2
tPO
t1= time at which power supply reaches
minimum specified operating voltage
t2= time at which output voltage settles
within ±10% of its steady state value
under an applied magnetic field
0
+t
Figure 1: Power-on Time definition
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
settle within ±1% of its steady state value, after initially passing
through its steady state voltage, as shown in Figure 4.
Quiescent Voltage Output (VOUT(Q)) In the quiescent state (no
significant magnetic field: B = 0 G), the output, VOUT(Q) , has a
constant ratio to the supply voltage, VCC , throughout the entire
operating ranges of VCC and ambient temperature, TA .
Initial Unprogrammed Quiescent Voltage
Output ( VOUT(Q)init ) Before any programming, the Quiescent
Voltage Output, VOUT(Q) , has a nominal value of VCC / 2, as
shown in Figure 5.
Quiescent Voltage Output Programming Range ( VOUT(Q)PR )
The Quiescent Voltage Output, VOUT(Q) , can be programmed
within the Quiescent Voltage Output Range limits: VOUT(Q)PR
(min) and VOUT(Q)PR (max). Exceeding the specified Quiescent
Voltage Output Range will cause Quiescent Voltage Output Drift
Through Temperature Range ΔVOUT(Q)TC to deteriorate beyond
the specified values, as shown in Figure 5.
Average Quiescent Voltage Output Programming Step Size
(StepVOUT(Q)) The Average Quiescent Voltage Output Progam-
ming Step Size, StepVOUT(Q) , is determined using the following
calculation:
StepVOUT(Q) =
VOUT(Q)maxcode –VOUT(Q)mincode
2n–1
(1)
,
where n is the number of available programming bits in the trim
range, 9 bits, VOUT(Q)maxcode is at decimal code 255, and VOUT(Q)
mincode
is at decimal code 256.
Quiescent Voltage Output Programming Resolution
(ErrPGVOUT(Q) ) The programming resolution for any device is half
of its programming step size. Therefore, the typical programming
resolution will be:
ErrPGVOUT(Q)(typ) = 0.5 × StepVOUT(Q)(typ)
(2)
Quiescent Voltage Output Temperature Coefficient (TCQVO)
Device VOUT(Q) changes as temperature changes, with respect to
its programmed Quiescent Voltage Output Temperature Coefficient, TCQVO . TCQVO is programmed at 150°C, and calculated
relative to the nominal VOUT(Q) programming temperature of
25°C. TCQVO (mV/°C) is defined as:
TCQVO = [VOUT(Q)T2 – VOUT(Q)T1][1/(T2-T1)]
(3)
where T1 is the nominal VOUT(Q) programming temperature of
25°C, and T2 is the TCQVO programming temperature of 150°C.
The expected VOUT(Q) through the full ambient temperature
range, VOUT(Q)EXPECTED(TA) , is defined as:
VOUT(Q)EXPECTED(TA) = VOUT(Q)T1 + TCQVO(TA –T1)
(4)
VOUT(Q)EXPECTED(TA) should be calculated using the actual measured values of VOUTQ)T1 and TCQVO rather than programming
target values.
Quiescent Voltage Output Drift Through Temperature Range
(ΔVOUT(Q)TC) Due to internal component tolerances and thermal
Magnetic Input
V
VCLP(HIGH)
VOUT
tCLP
t1
VOUT(Q)PR(min)
value
t2
t1= time at which output voltage initially
reaches steady state clamp voltage
t2= time at which output voltage settles to
within 1% of steady state clamp voltage
Note: Times apply to both high clamp
(shown) and low clamp.
0
Figure 4: Delay to Clamp Definition
t
Distribution of values
resulting from minimum
programming code
(QVO programming bits
set to decimal code 256)
VOUT(Q)
Programming range
(specified limits)
Typical initial value before
customer programming
VOUT(Q)init
(QVO programming
bits set to code 0)
VOUT(Q)PR(max)
value
Distribution of values
resulting from maximum
programming code
(QVO programming bits
set to decimal code 255)
Figure 5: Quiescent Voltage Output Range Definition
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13
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
considerations, the Quiescent Voltage Output, VOUT(Q) , may drift
from its nominal value through the operating ambient temperature, TA . The Quiescent Voltage Output Drift Through Temperature Range, ΔVOUT(Q)TC , is defined as:
∆VOUT(Q)TC = VOUT(Q)(TA) –VOUT(Q)EXPECTED(TA)
(5)
∆VOUT(Q)TC should be calculated using the actual measured
values of ∆VOUT(Q)(TA) and ∆VOUT(Q)EXPECTED(TA) rather than
programming target values.
Sensitivity (Sens) The presence of a south polarity magnetic
field, perpendicular to the branded surface of the package face,
increases the output voltage from its quiescent value toward the
supply voltage rail. The amount of the output voltage increase is
proportional to the magnitude of the magnetic field applied.
Conversely, the application of a north polarity field decreases the
output voltage from its quiescent value. This proportionality is
specified as the magnetic sensitivity, Sens (mv/G), of the device,
and it is defined as:
Sens =
VOUT(BPOS) – VOUT(BNEG)
BPOS – BNEG
,
(6)
where BPOS and BNEG are two magnetic fields with opposite
polarities.
Initial Unprogrammed Sensitivity ( Sensinit ) Before any programming, Sensitivity has a nominal value that depends on the
SENS_COARSE bits setting. Each A1363 variant has a different
SENS_COARSE setting.
Sensitivity Programming Range (SensPR) The magnetic sensi-
tivity, Sens, can be programmed around its initial value within the
sensitivity range limits: SensPR(min) and SensPR(max). Exceeding the specified Sensitivity Range will cause Sensitivity Drift
Through Temperature Range ΔSensTC to deteriorate beyond the
specified values. Refer to the Quiescent Voltage Output Range
section for a conceptual explanation of how value distributions
and ranges are related.
Average Fine Sensitivity Programming Step Size (StepSENS)
Refer to the Average Quiescent Voltage Output Programming
Step Size section for a conceptual explanation.
Sensitivity Programming Resolution ( ErrPGSENS ) Refer to the
Quiescent Voltage Output Programming Resolution section for a
conceptual explanation.
Sensitivity Temperature Coefficient (TCSENS) Device sensi-
tivity changes as temperature changes, with respect to its programmed sensitivity temperature coefficient, TCSENS . TCSENS
is programmed at 150°C, and calculated relative to the nominal
sensitivity programming temperature of 25°C. TCSENS (%/°C) is
defined as:
 1 
SensT2 – SensT1

TCSENS = 
100% 
×
SensT1
 T2–T1

, (7)
where T1 is the nominal Sens programming temperature of 25°C,
and T2 is the TCSENS programming temperature of 150°C. The
expected value of Sens over the full ambient temperature range,
SensEXPECTED(TA), is defined as:
SensEXPECTED(TA) = SensT1 × [100% + TCSENS (TA –T1)] .
(8)
SensEXPECTED(TA) should be calculated using the actual measured
values of SensT1 and TCSENS rather than programming target
values.
Sensitivity Drift Through Temperature Range (ΔSensTC )
Second order sensitivity temperature coefficient effects cause the
magnetic sensitivity, Sens, to drift from its expected value over
the operating ambient temperature range, TA . The Sensitivity
Drift Through Temperature Range, ∆SensTC , is defined as:
∆SensTC =
SensTA – SensEXPECTED(TA)
SensEXPECTED(TA)
× 100% . (9)
Sensitivity Drift Due to Package Hysteresis (ΔSensPKG ) Pack-
age stress and relaxation can cause the device sensitivity at TA =
25°C to change during and after temperature cycling. The sensitivity drift due to package hysteresis, ∆SensPKG , is defined as:
∆SensPKG =
Sens(25°C)2 – Sens(25°C)1
× 100%
Sens(25°C)1
, (10)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
where Sens(25°C)1 is the programmed value of sensitivity at TA
= 25°C, and Sens(25°C)2 is the value of sensitivity at TA = 25°C,
after temperature cycling TA up to 150°C and back to 25°C.
Linearity Sensitivity Error (LinERR ) The A1363 is designed to
provide a linear output in response to a ramping applied magnetic
field. Consider two magnetic fields, B1 and B2. Ideally, the sensitivity of a device is the same for both fields, for a given supply
voltage and temperature. Linearity error is present when there is a
difference between the sensitivities measured at B1 and B2.
Ratiometry Error (RatERR ) The A1363 device features ratiometric output. This means that the Quiescent Voltage Output,
VOUT(Q) , magnetic sensitivity, Sens, and Output Voltage Clamp,
VCLP(HIGH) and VCLP(LOW) , are proportional to the Supply Voltage, VCC. In other words, when the supply voltage increases
or decreases by a certain percentage, each characteristic also
increases or decreases by the same percentage. Error is the difference between the measured change in the supply voltage relative
to 5 V, and the measured change in each characteristic.
Linearity Error is calculated separately for the positive
The ratiometric error in Quiescent Voltage Output,
RatERRVOUT(Q) (%), for a given supply voltage, VCC , is defined
as:
 SensBPOS2 
 × 100%
LinERRPOS = 1–
 SensBPOS1 
,
 VOUT(Q)(VCC) / VOUT(Q)(5V) 
 × 100% .(15)
RatERRVOUT(Q) = 1–
V
/
5
V
CC


 SensBNEG2
 × 100%
LinERRNEG = 1–
 SensBNEG1
,
(LinERRPOS ) and negative (LinERRNEG ) applied magnetic fields.
Linearity Error (%) is measured and defined as:
(11)
 Sens(VCC) / Sens(5V) 
 × 100% .
RatERRSens = 1–
VCC / 5 V


where:
SensBx =
|VOUT(Bx) – VOUT(Q)|
Bx
The ratiometric error in magnetic sensitivity, RatERRSens (%), for
a given Supply Voltage, VCC , is defined as:
,
(12)
and BPOSx and BNEGx are positive and negative magnetic
fields, with respect to the quiescent voltage output such that
|BPOS2| = 2 × |BPOS1| and |BNEG2| = 2 × |BNEG1|.
(16)
The ratiometric error in the clamp voltages, RatERRCLP (%), for a
given supply voltage, VCC, is defined as:
 VCLP(VCC) / VCLP(5V) 
 × 100% ,
RatERRCLP = 1–
VCC / 5 V


(17)
where VCLP is either VCLP(HIGH) or VCLP(LOW).
Then:
LinERR = max( LinERRPOS , LinERRNEG )
.
(13)
Symmetry Sensitivity Error (SymERR ) The magnetic sensitivity of an A1363 device is constant for any two applied magnetic
fields of equal magnitude and opposite polarities. Symmetry
Error, SymERR (%), is measured and defined as:
 SensBPOS
SymERR = 1–
 SensBNEG

 × 100%

,
(14)
where SensBx is as defined in equation 12, and BPOSx and
BNEGx are positive and negative magnetic fields such that
|BPOSx| = |BNEGx|.
Power-On Reset Voltage (VPOR ) On power-up, to initialize to a
known state and avoid current spikes, the A1363 is held in Reset
state. The Reset signal is disabled when VCC reaches VUVLOH and
time tPORR has elapsed, allowing output voltage to go from a high
impedance state into normal operation. During power-down, the
Reset signal is enabled when VCC reaches VPORL , causing output
voltage to go into a high impedance state. (Note that detailed
description of POR and UVLO operation can be found in the
Functional Description section).
Power-On Reset Release Time (tPORR) When VCC rises to
VPORH , the Power-On Reset Counter starts. The A1363 output
voltage will transition from a high impedance state to normal
operation only when the Power-On Reset Counter has reached
tPORR and VCC has exceeded VUVLOH .
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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15
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
Undervoltage Lockout Threshold (VUVLO ) If VCC drops below
VUVLOL output voltage will be locked to GND. If VCC starts
rising A1363 will come out of Lock state when VCC reaches
VUVLOH .
UVLO Enable/Disable Delay Time (tUVLO ) When a falling VCC
reaches VUVLOL , time tUVLOE is required to engage Undervoltage
Lockout state. When VCC rises above VUVLOH , time tUVLOD is
required to disable UVLO and have a valid output voltage.
Output Saturation Voltage (VSAT ) When output voltage
clamps are disabled, output voltage can swing to a maximum of
VSAT(HIGH) and to a minimum of VSAT(LOW) .
Broken Wire Voltage (VBRK ) If the GND pin is disconnected
(broken wire event), output voltage will go to VBRK(HIGH) (if a
load resistor is connected to VCC) or to VBRK(LOW) (if a load
resistor is connected to GND).
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
FUNCTIONAL DESCRIPTION
Programming Sensitivity and Quiescent Voltage Output
Sensitivity and VOUT(Q) can be adjusted by programming
SENS_FINE and QVO bits, as illustrated in Figures 6 and 7.
Customers should not program sensitivity or VOUT(Q) beyond
the maximum or minimum programming ranges specified in the
Operating Characteristics table. Exceeding the specified limits
will cause sensitivity and VOUT(Q) drift through temperature
range, ΔSensTC and ΔVOUT(Q)TC , to deteriorate beyond the specified values.
Programming sensitivity might cause a small drift in VOUT(Q) . As
a result, Allegro recommends programming sensitivity first, then
VOUT(Q) .
Coarse Sensitivity
Each A1363 variant is programmed to a different coarse sensitivity setting. Devices are tested and temperature compensation is
factory programmed under that specific coarse sensitivity setting.
If the coarse sensitivity setting is changed ,by programming
SENS_COARSE bits, Allegro can not guarantee the specified
sensitivity drift through temperature range limits ,ΔSensTC .
Memory Locking Mechanisms
The A1363 is equipped with two distinct memory locking mechanisms:
• Default Lock At power-up, all registers of the A1363 are
locked by default. EEPROM and volatile memory cannot be
read or written. To disable Default Lock, a very specific 30
bits customer access code has to be written to address 0x24
within Access Code Time Out, tACC = 8 ms, from power-up.
At this point, registers can be accessed. If VCC is power
cycled, the Default Lock will automatically be re-enabled.
This ensures that during normal operation, memory content
will not be altered due to unwanted glitches on VCC or the
output pin.
• Lock Bit After EEPROM has been programmed by the
customer, the EELOCK bit can be set high and VCC power
cycled to permanently disable the ability to read or write
any register. This will prevent the ability to disable Default
Lock using the method described above. Please note that
after EELOCK bit is set high and VCC pin power cycled, the
customer will not have the ability to clear the EELOCK bit or
to read/write any register.
Quiescent Voltage Output,
VOUT(Q) (mV)
Sensitivity, Sens (mV/G)
Max Specified
VOUT(Q)PR
Max Specified
SensPR
Specified Sensitivity
Programming Range
Mid Range
Specified VOUT(Q)
Programming Range
Mid Range
Min Specified
VOUT(Q)PR
Min Specified
SensPR
0
255 256
511
SENS_FINE Code
Figure 6: Device Sensitivity versus SENS_FINE
Programmed Value
0
255 256
511
QVO Code
Figure 7: Device VOUT(Q) versus QVO Programmed
Value
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
Power-On Reset (POR) and Undervoltage
Lock-Out (UVLO) Operation
does not exceed VUVLOH [2], the output will stay in the high
impedance state until VCC reaches VUVLOH [3] and then will
go to VCC / 2 after tUVLOD [4].
The descriptions in this section assume: temperature = 25°C, no
output load (RL, CL ) , and no significant magnetic field is present.
• VCC drops below VCC(min)= 4.5 V If VCC drops below
VUVLOL [4', 5], the UVLO Enable Counter starts counting. If
VCC is still below VUVLOL when counter reaches tUVLOE , the
UVLO function will be enabled and the ouput will be pulled
near GND [6]. If VCC exceeds VUVLOL before the UVLO
Enable Counter reaches tUVLOE [5'] , the output will continue
to be VCC / 2.
• Power-Up At power-up, as VCC ramps up, the output is in a
high impedance state. When VCC crosses VPORH (location
[1] in Figure 8 and [1'] in figure 9), the POR Release counter
starts counting for tPORR. At this point, if VCC exceeds VUVLOH
[2'], the output will go to VCC / 2 after tUVLOD [3']. If VCC
VCC
1
2
3
5.0
5
4
VUVLOH
VUVLOL
VPORH
VPORL
6
7
9
8
tUVLOE
10 11
tUVLOE
GND
VOUT
Time
Slope =
VCC / 2
2.5
tPORR
tUVLOD
GND
tUVLOD
High Impedance
High Impedance
Time
Figure 8: POR and UVLO Operation: Slow Rise Time Case
VCC
5.0
VUVLOH
VUVLOL
VPORH
VPORL
1’
2’
3’
4’ 5’
6’ 7’
<tUVLOE
GND
VOUT
Time
tPORR
2.5
Slope =
VCC / 2
<tUVLOE
Slope =
VCC / 2
tUVLOD
GND
High Impedance
Time
High Impedance
Figure 9: POR and UVLO Operation: Fast Rise Time Case
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
• Coming out of UVLO While UVLO is enabled [6] , if VCC
exceeds VUVLOH [7] , UVLO will be disabled after tUVLOD ,
and the output will be VCC / 2 [8].
• Power-Down As VCC ramps down below VUVLOL [6’, 9], the
UVLO Enable Counter will start counting. If VCC is higher
than VPORL when the counter reaches tUVLOE, the UVLO
function will be enabled and the ouput will be pulled near
GND [10]. The output will enter a high impedance state as
VCC goes below VPORL [11]. If VCC falls below VPORL before
the UVLO Enable Counter reaches tUVLOE , the output will
transition directly into a high impedance state [7'].
Detecting Broken Ground Wire
If the GND pin is disconnected, node A becoming open
(Figure 11), the VOUT pin will go to a high impedance
state. Output voltage will go to VBRK(HIGH) if a load resistor
RL(PULLUP) is connected to VCC or to VBRK(LOW) if a load resistor
RL(PULLDWN) is connected to GND. The device will not respond
to any applied magnetic field.
V+
VCC
VOUT
A1363
CBYPASS
GND
CL
(Recommended)
Figure 10:Typical Application Drawing
If the ground wire is reconnected, A1363 will resume normal
operation.
VCC
VCC
VCC
RL(PULLUP)
VCC
VOUT
A1363
VCC
VOUT
A1363
RL(PULLDWN)
GND
GND
A
A
Connecting VOUT to RL(PULLUP)
Connecting VOUT to RL(PULLDWN)
Figure 11: Connections for Detecting Broken Ground Wire
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
19
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for total
accuracy is the small signal voltage developed across the Hall
element. This voltage is disproportionally small relative to the
offset that can be produced at the output of the Hall sensor. This
makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and
voltage ranges. Chopper stabilization is a unique approach used
to minimize Hall offset on the chip.
The patented Allegro technique removes key sources of the output drift induced by thermal and mechanical stresses. This offset
reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the
magnetic field-induced signal in the frequency domain, through
modulation. The subsequent demodulation acts as a modulation
process for the offset, causing the magnetic field-induced signal
to recover its original spectrum at base band, while the DC offset
becomes a high-frequency signal. The magnetic-sourced signal
then can pass through a low-pass filter, while the modulated DC
offset is suppressed. This high-frequency operation allows a
greater sampling rate, which results in higher accuracy and faster
signal-processing capability. This approach desensitizes the chip
to the effects of thermal and mechanical stresses, and produces
devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This
technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in
combination with high-density logic integration and a proprietary,
dynamic notch filter. The new Allegro filtering techniques are
far more effective at suppressing chopper induced signal noise
compared to the previous generation of Allegro chopper stabilized devices.
Regulator
Clock/Logic
Hall Element
Amp
Anti-Aliasing Tuned
LP Filter
Filter
Figure 12: Concept of Chopper Stabilization
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
20
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
Programming Serial Interface
WRITING THE ACCESS CODE
The A1363 incorporates a serial interface that allows an external
controller to read and write registers in the EEPROM and volatile
memory. The A1363 uses a point-to-point communication protocol, based on Manchester encoding per G. E. Thomas (a rising
edge indicates 0 and a falling edge indicates 1), with address and
data transmitted MSB first.
In order for the external controller to write or read from the
A1363 memory during the current session, it must establish serial
communication with the A1363 by sending a Write command
including the Access Code within Access Code Time Out, tACC ,
from power-up. If this deadline is missed, all write and read
access is disabled until the next power-up.
TRANSACTION TYPES
WRITING TO VOLATILE MEMORY
Each transaction is initiated by a command from the controller;
the A1363 does not initiate any transactions. Three commands
are recognized by the A1363: Write Access Code, Write, and
Read. One response frame type is generated by the A1363, Read
Acknowledge. If the command is Read, the A1363 responds by
transmitting the requested data in a Read Acknowledge frame. If
the command is any other type, the A1363 does not acknowledge.
As shown in Figure 13, the A1363 receives all commands via the
VCC pin. It responds to Read commands via the VOUT pin. This
implementation of Manchester encoding requires the communication pulses be within a high (VMAN(H)) and low (VMAN(L)) range
of voltages for the VCC line and the VOUT line. The Write command to EEPROM is supported by two high voltage pulses on the
VOUT line.
In order for the external controller to write to volatile memory,
a Write command must be transmitted on the VCC pin. Successive Write commands to volatile memory must be separated by
tWRITE . The required sequence is shown in Figure 14.
VCC
Previous
Command
Write
to Register R#
tWRITE
Next
Command
tWRITE
t
Figure 14: Writing to Volatile Memory
Write/Read Command
– Manchester Code
Controller
High Voltage pulses to
activate EEPROM cells
VCC
A1363
VOUT
GND
Read Acknowledge
– Manchester Code
Figure 13. Top Level Programming Interface
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
21
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
WRITING TO EEPROM
In order for the external controller to write to non-volatile
EEPROM, a Write command must be transmitted on the VCC
pin. The controller must also send two Programming pulses,
long high-voltage strobes, via the VOUT pin. These strobes are
detected internally, allowing the A1363 to boost the voltage on
the EEPROM gates. The required sequence is shown in Figures
15 and 16.
To ensure EEPROM integrity over life time, EEPROM should
not be exposed to more than 100 Write cycles.
READING FROM EEPROM OR VOLATILE MEMORY
In order for the external controller to read from EEPROM or volatile memory, a Read command must be transmitted on the VCC
line. Within time tstart_read , the VOUT line will stop responding
VCC
VOUT
Write
to Register R#
Normal Operation
EEPROM
Programming
Pulses
High
Impedance
to the magnetic field and the Read Acknowledge frame will be
transmitted on the VOUT line. The Read Acknowledge frame
contains Read data.
After the Read Acknowledge frame has been received from the
A1363, the VOUT line resumes normal operation after time
tREAD . The required sequence is shown in Figure 17.
ERROR CHECKING
The serial interface uses a cyclic redundancy check (CRC) for
data-bit error checking (synchronization bits are ignored during
the check). The CRC algorithm is based on the polynomial g(x)
= x3 + x + 1 , and the calculation is represented graphically in
Figure 18. The trailing 3 bits of a message frame comprise the
CRC token. The CRC is initialized at 111. If the serial interface
receives a command with a CRC error, the command is ignored.
VOUT
Normal Operation
t
t
tsPULSE(E)
tWRITE(E)
Figure 15: Writing to EEPROM
VCC
Figure 16: EEPROM Programming Pulses
Read from
Register R#
C0
VOUT
Normal Operation
Read Acknowledge
R#
Input Data
C2
Normal Operation
t
tstart_read
C1
1x 0
1x 1
0x 2
1x 3
= x3 + x + 1
tREAD
Figure 17: Reading from EEPROM or Volatile Memory
Figure 18: CRC Calculation
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115 Northeast Cutoff
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22
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
SERIAL INTERFACE REFERENCE
Required timing parameters for successful serial communication with A1363 device are given in table below.
Table 1: Required Serial Interface Timing Parameters
Characteristics
Symbol
Note
Min.
Typ.
Max.
Unit
Input/Output Signal Timing
Access Code Time Out
tACC
Customer Access Code should be fully entered
in less than tACC , measured from when VCC
crosses VUVLOH .
–
–
8
ms
Bit Rate
tBITR
Defined by the input message bit rate sent from
the external controller
32
–
80
kbps
tBIT
Bit Time
Data bit pulse width at 70 kbps
13.6
14.3
15
µs
Bit Time Error
errTBIT
Deviation in tBIT during one command frame
–11
–
+ 11
%
Volatile Memory Write Delay
tWRITE
Required delay from the trailing edge of certain
Write command frames to the leading edge of a
following command frame
2 × tBIT
–
–
µs
Required delay from the trailing edge of the
second EEPROM Programming pulse to the
leading edge of a following command frame
2 × tBIT
–
–
µs
tREAD
Required delay from the trailing edge of a Read
Acknowledge frame to the leading edge of a
following command frame
2 × tBIT
–
–
µs
tstart_read
Delay from the trailing edge of a Read
command frame to the leading edge of the Read
Acknowledge frame
25 μs –
0.25 ×
tBIT
50 μs
–0.25 ×
tBIT
150 μs
– 0.25 ×
tBIT
µs
tsPULSE(E)
Delay from last edge of write command to start
of EEPROM programming pulse
40
–
–
μs
Non-Volatile Memory Write Delay
Read Acknowledge Delay
Read Delay
tWRITE(E)
EEPROM Programming Pulse
EEPROM Programming Pulse
Setup Time
Input/Output Signal Voltage
Applied to VCC line
Manchester Code High Voltage
VMAN(H)
Manchester Code Low Voltage
VMAN(L)
Manchester Level to VCC Delay
tMAN_VCC
5.1
–
–
V
VCC –
0.2 V
–
–
V
Applied to VCC line
–
–
3.9
V
Read from VOUT line
–
–
0.2
V
–
–
15
µs
Read from VOUT line
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23
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
SERIAL INTERFACE MESSAGE STRUCTURE
The general format of a command message frame is shown in
Figure 19. Note that, in the Manchester coding used, a bit value
of one is indicated by a falling edge within the bit boundary, and
a bit value of zero is indicated by a rising edge within the bit
boundary.
Read/Write
Synchronize
0
Data
0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
MSB
VCC LEVELS DURING MANCHESTER COMMUNICATION
For all devices with UVLO functionality, after power-up it is
important that the VCC pin be held at VCC until the first Synchronization pulse of a read/write transaction is sent (see Figure 20).
During the transaction, the VCC pin varies between VMAN(H)
and VMAN(L) , but right after the last CRC bit has been sent, the
controller must bring the VCC pin back to the VCC level in less
than tMAN_VCC . This is important in order to avoid triggering the
UVLO functionality during EEPROM read/write.
Memory Address
...
CRC
0/1 0/1 0/1 0/1
MSB
0 0 1 1 0
Manchester Code per G. E. Thomas
Bit boundaries
Figure 19: General Format for Serial Interface
Commands
Read/Write
Memory Address
Synchronize
0
0 0/1
0
0
Data
CRC
0/1
VMAN(H)
VCC
VMAN(L)
0V
1
0
tMAN_VCC
Bit boundaries
Figure 20: VCC Levels During Manchester Communication
Table 2: Serial Interface Command General Format
Quantity
of Bits
Parameter Name
Values
2
Synchronization
00
Used to identify the beginning of a serial interface command
0
[As required] Write operation
1
[As required] Read operation
Description
1
Read/Write
6
Address
0/1
[Read/Write] Register address (volatile memory or EEPROM)
30
Data
0/1
24 data bits and 6 ECC bits
3
CRC
0/1
Incorrect value indicates errors
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24
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
Figure 23 shows the sequence for a Write Command. Bits [29:24]
are Don’t Care because the A1363 automatically generates 6 ECC
bits based on the content of bits [23:0]. These ECC bits will be
stored in EEPROM at locations [29:24].
Read (Controller to A1363)
The fields for the read command are:
• Sync (2 zero bits)
• Read/Write (1 bit, must be 1 for read)
• Address (6 bits) - ADDR[5] is 0 for EEPROM, 1 for register.
• CRC (3 bits)
Figure 21 shows the sequence for a Read Command.
Read/Write
0
0
Memory Address
0
0
CRC
1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
MSB
MSB
Read Acknowledge (A1363 to Controller)
The fields for the data return frame is:
MSB
Figure 23: Write Sequence
Write Access Code (Controller to A1363)
The fields for the Access Code command are:
• Read/Write (1 bit, must be 0 for write)
• Address (6 bits) (Address 0X24 for Customer Access)
• Data - 30 bits (0x2781_1F77 for Customer Access)
• Sync (2 zero bits)
• Data (30 bits: [29:26] Don’t Care, [25:24] ECC Pass/Fail,
[23:0] Data)
• CRC (3 bits)
Figure 24 shows the sequence for a Access Code Command.
Read/Write
• CRC (3 bits)
Figure 22 shows the sequence for a Read Acknowledge. Refer to
the Detecting ECC Error section for instructions on how to detect
and ECC failure.
Synchronize
0
0
0/1 0/1 0/1 0/1
• Sync (2 zero bits)
Figure 21: Read Sequence
Data
(30 bits)
CRC
0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 . . .
Read/Write
Synchronize
Data
(30 bits)
Memory Address
Synchronize
0
0
Data
(30 bits)
Memory Address
Synchronize
0
1
0
0
1
0
MSB
0 0/1 0/1 0/1 . . .
CRC
0/1 0/1 0/1 0/1
MSB
Figure 24: Access Code Write Sequence
CRC
0/1 0/1 0/1 0/1 . . . 0/1 0/1 0/1 0/1 0/1
MSB
Figure 22: Read Acknowledge Sequence
Write (Controller to A1363)
The fields for the write command are:
• Sync (2 zero bits)
The controller has to open the serial communication with the
A1363 device by sending an Access Code. It has to be sent within
Access Code Time Out, tACC , from power-up or the device will
be disabled for read and write access.
Table 3: Access Codes Information
Name
• Read/Write (1 bit, must be 0 for write)
• Address (6 bits) - ADDR[5] is 0 for EEPROM, 1 for register.
Refer to the address map.
Customer
Serial Interface Format
Register Address
(Hex)
Data (Hex)
0x24
0x2781_1F77
• Data (30 bits: [29:24] Don’t Care, [23:0] Data)
• CRC (3 bits)
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25
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
Table 4: Memory Address Map
Register Name
Address
Description
r/w
Bits
Location
Customer Access EEPROM
SENS_FINE1
Sensitivity, two’s complement DAC profile
r/w
9
8:0
SENS_COARSE
Coarse Sensitivity
r/w
2
10:9
QVO1
Quiescent Output Voltage, two’s complement
DAC profile
r/w
9
19:11
Factory reserved bit
r/w
1
20
0x00
(Factory reserved)2
POL
Reverses output polarity
r/w
1
21
CLAMP_DIS
Clamp Disable
r/w
1
22
EELOCK
EEPROM LOCK
ID_C3
0x01
w
1
23
r/w
24
23:0
Turns off the analog output for serial
communications
w
1
0
Enables register shadowing to bypass
EEPROM register 0x00 bits 22:0
w
1
1
Customer Reserved
Customer Debug Register (Volatile Memory)
Disable Analog Output
0x10
Shadow Enable
19-bit
two’s complement integers, where the most positive number is indicated by code 255 (decimal) and the most negative number by code 256 (decimal).
should not write to this bit.
3Can be used to store any information required in the customer’s application.
2Customer
EEPROM CELL ORGANIZATION
Programming coefficients are stored in non-volatile EEPROM,
which is separate from the digital subsystem, and accessed by the
digital subsystem EEPROM Controller module. The EEPROM
is organized as 30 bit wide words, each word is made up of 24
data bits and 6 ECC (Error Checking and Correction) check bits,
stored as shown in table below.
EEPROM Bit
29
28
27
26
25
24
Contents
C5
C4
C3
C2
C1
C0
23
22
21
20
19
18
17
16
15
D23 D22 D21 D20 D19 D18 D17 D16 D15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 25: EEPROM Word Bit Sequence; C# – Check Bit, D# – Data Bit
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26
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
EEPROM ERROR CHECKING AND CORRECTION
(ECC)
Hamming code methodology is implemented for EEPROM
checking and correction. The device has ECC enabled after
power-up.
The device always returns 30 bits.
DETECTING ECC ERROR
If an uncorrectable error has occurred, bits 25:24 are set to 10, the
VOUT pin will go to a high impedance state, and the device will
not respond to the applied magnetic field. Output voltage will go
to VBRK(HIGH) if a load resistor RL(PULLUP) is connected to VCC
or to VBRK(LOW) if a load resistor RL(PULLDWN) is connected to
GND.
The message received from controller is analyzed by the device
EEPROM driver and ECC bits are added. The first 6 received bits
from device to controller are dedicated to ECC.
Table 5: EEPROM ECC Errors
Bits
Name
29:26
–
Description
No meaning
00 = No Error
25:24
ECC
01 = Error Detected and message corrected
10 = Uncorrectable error
11 = No meaning
23:0
D[23:0]
EPROM data
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
27
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
A1363LU
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference MO-153 AA)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
3.00 ±0.10
D
E
0.45
0.65
8º
0º
1.50 ±0.05
8
8
0.20
0.09
1.70
D
1.43 ±0.05 D
6.40 BSC
±2°
4.40 ±0.10
6.10
+0.15
0.60
–0.10
A
1.00 REF
1
2
1
0.25 BSC
B
SEATING PLANE
Branded Face
2
PCB Layout Reference View
GAUGE PLANE
C
8X
0.10
1.10 MAX
C
NNN
SEATING
PLANE
0.30
0.19
0.65 BSC
YYWW
0.15
0.05
C
A
Terminal #1 mark area
B
Reference land pattern layout (reference IPC7351 SOP65P640X110-8M); all pads a minimum of 0.20 mm from all adjacent pads;
adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB,
thermal vias can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
C
Branding scale and appearance at supplier discretion
D
Hall element, not to scale
E
Active Area Depth 0.36 mm REF
Standard Branding Reference View
N = Last 3 digits of device part number
= Supplier emblem
Y = Last 2 digits of year of manufacture
W = Week of manufacture
Figure 26: Package LU, 8-Pin TSSOP
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
28
A1363LU
Low Noise, High Precision, Programmable Linear Hall Effect Sensor IC
With Advanced Temperature Compensation
And High Bandwidth (120 kHz) Analog Output
Document Revision History
Revision
Date
Change
–
January 24, 2014
1
September 3, 2014
Revised Selection Guide
Initial Release
2
September 10, 2014
Updated RatERRSens Limits
3
November 4, 2014
Revised part numbers in selection guide
4
December 16, 2015
Revised Sensitivity Drift Through Temperature Range electrical characteristic and added footnote 20
Copyright ©2015, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
29