Rohm BD8918F-E2 Ic care interface ics with built-in low ldo regulator Datasheet

IC Card Interface ICs
IC Card Interface ICs
with Built-in Low Noise LDO Regulator
BD8918F,BD8918FV,BD8919F,BD8919FV
No.09056EDT01
●Overview
This is an interface IC for a 5V smart card.
It works as a bidirectional signal buffer between a smart card and a controller. Also, it supplies 5V power to a smart card.
With an electrostatic breakdown voltage of more than HBM; ±6000V, it protects the card contact pins.
●Features
1) 1 half duplex bidirectional buffers
2) Protection against short-circuit for all the card contact pins
3) 5V power source for the card (VCC)
4) Over-current protection for card power source
5) Built-in thermal shutdown circuit
6) Built-in supply voltage detector
7) Automatic activation/deactivation sequence function for card contact pin
Activation sequence: driven by a signal from controller (CMDVCCB)
Deactivation sequence: driven by a signal from controller (CMDVCCB) and fault detection (card removal, short
circuit of card power, IC overheat detection, VDD or VDDP drop)
8) Card contact pin ESD voltage ≧ ±6000V
9) Recommend frequency of crystal oscillator: 8MHz (BD8918F/FV), 16MHz (BD8919F/FV)
10) Programmable for card clock division of output signal: 1/1 and 1/2(BD8918F/FV), 1/2 and 1/4(BD8919F/FV).
11) RST output control by RSTIN input signal (positive output)
12) One multiplexed card status output by OFFB signal
●Applications
Interface for CLASS A smart cards
Interface for B-CAS cards
●Line up matrix
Part No
BD8918F
BD8918FV
BD8919F
BD8919FV
Card clock
Ratio of dividing frequency
1/1f, 1/2f
1/2f, 1/4f
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© 2009 ROHM Co., Ltd. All rights reserved.
Package
SOP16
SSOP-B16
SOP16
SSOP-B16
1/15
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
●Absolute maximum ratings (Ta=25°C)
Parameter
Symbol
Ratings
Unit
Notes
VDD Input Voltage
VDD
-0.3 ~ 6.5
V
VDDP Input Voltage
VDDP
-0.3 ~ 6.5
V
I/O Pin Voltage
VMIN
VMOUT
-0.3 ~ +6.5
V
Pin: XTAL1, XTAL2, CLKSEL, RSTIN, IO_U
CMDVCCB, OFFB
Card Contact Pin Voltage
VCD
-0.3 ~ +6.5
V
Pin: PRES, CLK, RST, IO_C
Junction Temperature
Tjmax
+150
°C
Storage Temperature
Tstg
-55 ~ +150
°C
*1
Power Dissipation
0.375
*2
0.500
Ptot
W
T = -20 ~ +85°C
(Refer to the following package power dissipation)
Unit
Notes
*1 BD8918F/BD8919F, *2 BD8918FV/BD8919FV
• This product is not designed to be radiation tolerant.
• Absolute maximum ratings are not meant for guarantee of operation.
●Operating Conditions (Ta=25°C)
Symb
ol
Parameter
Ratings
MIN
TYP
MAX
VDD Input Voltage
VDD
2.7
-
5.5
V
VDDP Input Voltage
VDDP
4.75
-
5.5
V
Operating Temperature
Topr
-40
-
+85
°C
VCC ≥ 4.55V
●Package Power Dissipation
The power dissipation of a simple package in case of a boadless will be as follows.
Use of this device beyond the following the power dissipation may cause permanent damage.
BD8918F/BD8919F
BD8918FV/BD8919FV
Pd=375mW; however, reduce 3mW per 1°C when used at Ta ≥ 25°C.
Pd=500mW; however, reduce 4mW per 1°C when used at Ta ≥ 25°C.
Package power
Package power
0.6
0.4
0.5
0.3
Pd (W)
Pd (W)
0.4
0.2
0.3
0.2
0.1
0.1
0.0
0.0
0
25
50
75
Temp (℃)
100
125
0
150
Fig. 1.1 BD8918F/BD8919F Power Dissipation
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© 2009 ROHM Co., Ltd. All rights reserved.
25
50
75
Temp (℃)
100
125
150
Fig. 1.2 BD8918FV/BD8919FV Power Dissipation
2/15
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
●Block Diagram
2.7V-5.5V
4.75V-5.5V
0.1uF
VDD
10µF
VDDP
VREF
VIREF
TSD
VDET
TSD
ALARM
LVS
POWER_ON
VDD
ALARM
LVS
OFFB
SEQUENCER
50k
VDD
CMDVCCB
CLKSEL
50k
RSTEN
CLK
DIV
1µF
VCC
ALARM
50k
CLKEN
DIVEN
LDO
5V
CGND
LV S
RSTIN
VCC
VCCEN
RST BUF
RST
LVS
20k
CLK BUF
CLK
DIVCLK
VDD
VDD
22pF
XTAL 2
IO_U
PRES
VCC
VDD
11k
LVS
F 220Ω
XT
OSC
I OEN
XTAL1
22pF
50k
MAX 1MHz
11k
IO TRANS
IO_C
GND
Fig. 2
BD8918F/FV
BD8919F/FV
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3/15
F=8MHz
F=16MHz
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
●Pin Description
Pin No. Pin Name
I/O
Signal
Level
Pin Function
1
XTAL1
I
VDD
Crystal connection or input for external clock
2
XTAL2
O
VDD
Crystal connection (leave open pin when external clock source is used)
3
VDD
S
VDD
4
CLKSEL
I
VDD
5
RSTIN
I
VDD
Card reset signal input. Pulled down to GND with a 50k resistor.
6
IO_U
I/O
VDD
Host data I/O line; Pulled up to VDD with an 11k resistor
7
CGND
S
GND
GND
8
IO_C
I/O
VCC
I/O data line on the card side. Pulled up to VCC with an 11kresistor.
9
RST
O
VCC
Card reset output
10
CLK
O
VCC
Card clock output
11
VCC
O
VCC
Card supply voltage. Connect 1µF capacitor between VCC and the CGND pins.
12
VDDP
S
VDDP
13
PRES
I
VDD
14
OFFB
O
VDD
15
CMDVCCB
I
VDD
16
GND
S
GND
3.3 V power source pin for host interface.
Connect 0.1µF capacitor between the VDD and GND pins.
Input for clock frequency
BD8918F/FV H: 1/1 division; L: 1/2 division.
division setting.
Pulled down to GND
BD8919F/FV H: 1/2 division; L: 1/4 division.
with a 50k resistor.
5V power source pin for card power feed. Connect 10µF capacitor between the
VDDP and CGND pins.
Card presence contact input (“H” active). Pulled up to VDD with a 50k resistor.
Connected to a switch where GND level is inputted when no card is inserted and
OPEN is inputted when a card is inserted. When “H” level is detected, a card is
assumed to be inserted and waits for the CMDVCCB input for the confirmation,
after the debounce time of typ. 8ms.
Alarm output pin (“L” active).
NMOS open drain output. Pulled up to VDD with a 20k resistor.
Activation sequence command input; The activation sequence starts by signal
input (HL) from the host
GND
*Capacitors to be connected to VDD, VDDP and VCC should be placed immediately next to the pins (ESR<100m).
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4/15
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
●Pin Function Diagram
Pin
No.
Pin
Name
VDD
1
Pin
No.
Pin function Diagram
Pin
Name
Pin function Diagram
VDD
VDDP VREG
VREG
XTAL1
11KΩ
1
100Ω
1.2MΩ
8
IO_C
8
2
2
XTAL2
VREG
VDDP
3
3
VDD
9
VDD
4
VREG
VDDP
CLKSEL
4,5
10
RSTIN
VDD
VDD
VDDP
IO_U
7
CGND
11
5
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5/15
VCC
VDDP
1Ω
11KΩ
6
10
CLK
50K Ω
5
9
RST
11
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
Pin No. Pin Name
Pin No.
Pin function Diagram
Pin Name
Pin function Diagram
VDD
12
20KΩ
12
VDDP
14
VDD
14
OFFB
VDD
VDD
50KΩ
5KΩ
13
PRES
13
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© 2009 ROHM Co., Ltd. All rights reserved.
VDD
6/15
15
CMDVCCB
16
GND
15
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
●Package
Package Name:
SOP16
Note : X is 8 or 9.
10 ± 0.2
(MAX 10.35 include BURR)
16
BD891XF
0.3MIN
4.4±0.2
6.2±0.3
9
1
8
1PIN MARK
Lot No.
0.11
1.5±0.1
0.15 ± 0.1
0.4 ± 0.1
1.27
0.1
(UNIT : mm)
Fig. 3.1 SOP16 Package Dimension
Package Name:
SSOP-B16
5.0±0.2
4.4±0.2
9
D891X
0.3Min.
6.4±0.3
16
Lot No.
1
8
1PIN MARK
0.10
1.15±0.1
0.15±0.1
0.1
0.65
(UNIT : mm)
0.22±0.1
Fig. 3.2 SSOP-B16 Package Dimension
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© 2009 ROHM Co., Ltd. All rights reserved.
7/15
(Un
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
●Function
1) Power supply
Power supply pins are VDD and VDDP. Set VDD at the same voltage as the signal from the system controller side.
VDDP and CGND are for the 5V power source and GND, respectively, on the card side.
2) Input voltage detector
The IC remains in wait mode until the power on reset is released 16ms after the VDD supply voltage is increased over
Vthd and the VDDP supply voltage is increased over Vthp, making the CMDVCCB signal turn from H to L.
Vthd=1.7V(typ)
Vthp=2.25V(typ)
3) Operation sequence
3-1) Wait mode
The IC remains in wait mode until the power on reset is released after the VDD supply voltage is increased over Vthd and
the VDDP supply voltage is increased over Vthp, making the CMDVCCB signal turn from H to L.
In this mode, the VDD and VDDP supply voltage detector (VDET), thermal shutdown circuit (TSD), reference circuit
(VREF) and crystal oscillation circuit (XT OSC) are activated.
IO_U is pulled up to VDD with an 11k resistor and all the card contact pins are at Lo level.
3-2) Card presence
Card presence is detected by PRES pin. When the PRES pin is active, a card is assumed to be present.
Table 1
PRES
“High” active
When a card is present in wait mode, the card insertion identification pin, PRES (“H” active) becomes active and OFFB
becomes “H” after approx. 8ms (debounce time).
If a card is present before the VDD and VDDP power sources are applied and the internal reset is released, it is internally
reset and OFFB becomes “H” after the debounce time.
The PRES pin is pulled up to VDD with a 50k resistor.
Descriptions of transition times (example. Debounce time: 8msec) for the operation
sequences are adapted in the conditions of the following input frequency.
8MHz (BD8918F/ FV), 16MHz (BD8919F/ FV)
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8/15
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
3-3) Activation sequence
When OFFB is in the “High” state and the CMDVCCB signal from the controller turns from H to L, the activation sequence
starts to activate each functional block in the following order:
The RST outputs signals based on the RSTIN input, being reset approximately 472sec after the CMDVCCB signal turns
from H to L. The RSTIN input becomes effective approximately 48s after I/O TRANS turns ON. If RSTIN becomes Lo
after RSTIN becomes effective and the RST output is released, the CLK signal is output. If RSTIN is High when the RST
output is released, the CLK signal is output as soon as the RST output is released. (Refer to Fig. 4-1, 4-2 and 4-3)
LDO ON
(VCC output)

I/O TRANS ON
(IO_C, IO_U Bus: Pull-up)
__________________________________________________

 When RSTIN remains High until RST is released
 (RSTINAlways High)
 (RSTIN=Always High)


CLK BUF ON
(CLK output)
CLK, RST BUF ON (CLK output, RST release)

RST BUF ON
(RST release)
[Activation sequence under different RSTIN input timings]
CMDVCCB
CMDVCCB
VCC
VCC
ART
IO_C
ART
IO_C
CLK
CLK
Min:200ns
RSTIN
RSTIN
RST
RST
IO_U
t0
t1
t2 t3
IO_U
t4= tact
t0
Fig. 4-1 Activation sequence 1
t1
t2
t3
t4= tact
Fig. 4-2 Activation sequence 2
t1: LDO startup time
= typ. 24µs
Fig.6-3
t2: I/O ON
time 立ち上げシーケンス 3= typ. 424µs
t3: CLK output release time (t3-t2)
= Min. 200ns
t4: RST release time
= typ,472µs,
481s
(Activation time)
CMDVCCB
VCC
ART
IO_C
CLK
RSTIN
max.
RST
IO_U
t0
t1
t2 t3
t4= tact
Fig. 4-3 Activation sequence 3
(RSTIN input sequence not specified by ISO7816)
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9/15
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
3-4) Deactivation sequence
When the CMDVCCB input turns from L to H or the alarm signal (described later) is detected, the following deactivation
sequence is initiated in the following order, transitioning to the wait mode.
RST BUF OFF
(RST: Lo)

CLK BUF OFF
(CLK: Lo)

I/O TRANS OFF
(I/O Bus on the controller side: Pull-up)

(I/O Bus on the card side: Lo)

LDO OFF
(VCC: Lo)
CMDVCCB
t11: CLK OFF time
t12: I/O OFF time
t13: Starting time of VCC fall
tde: Operational sequence completion time
RST
= typ. 10µs
= typ. 20μs
= typ. 30μs
=Max. 200μs
CLK
I/O
VCC
t11
t10
t12
t13
tde
Fig. 5 Deactivation sequence
4) LDO
LDO supplies power to the IC card through VCC pin.
This regulator has a built-in over-current limiter circuit. It generates an internal alarm with a load current of approximately
140mA or more and enters into the deactivation sequence. Also, the output voltage is regarded as abnormal if it drops to
less than 1.6V and the output current is shut off; an internal alarm signal is generated and the deactivation sequence is
initiated.
Connect a capacitor of 1µF or 2.2µF between VCC and CGND as close as possible to the VCC pin, in order to reduce
the output voltage variation as much as possible. Also, ensure that ESR is kept at less than 100m.
LDO output is also a power source for CLK, RST and IO_C output. Therefore, the CLK, RST and IO_C output level is the
same as the VCC output level.
5) I/O data transitions
The data line, IO_C - IO_U, transmits/receives two-way data.
The IO_U pin for the controller side is pulled up with an 11k resistor to High (VDD voltage) and card contact pins IO_C
is set to Lo until I/O TRANS becomes ON by the activation sequence.
When I/O TRANS becomes On, IC becomes idle mode and the I/O pin is pulled up with an 11k resistor to keep the
IO_U pin to VDD voltage (High) and the IO_C pin to VCC voltage (High).
The pin which turns to L from H first becomes the master and the other output side becomes the slave between the pins
on the controller side and card contact pins. Then the data are transferred from the master side to the slave side.
When the both signal levels become High, they become idle mode.
When the signal transits from L to H and it passes over a threshold, an active pull-up (100 ns or less) works to drive the
data High at high speed. After the active pull-up is completed, the pin is pulled up with an 11k resistor. After the active
pull-up is completed, the pin is pulled up with an 11k resistor. This function enables signal transmission up to 1MHz.
Also, an over-current limiter of 30mA in the card contact pin, IO_C.
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10/15
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
6) Card clock supply
Card clock is supplied from the CLK pin dividing the input frequency of XTAL1 pin with the CLKSEL pin setting. The clock
division switching time is within the 8 clocks of the XTAL1 signal.
The input signal to the XTAL1 pin is made by a crystal oscillator (BD8918F/FV:8Hz, BD8919F/FV:16MHz) between the
XTAL1 pin and XTAL2 pin or external pulse signal.
When a crystal oscillator is used, the voltage between XTAL1 and XTAL2 may decrease to become close to “-1V”, which
is not a problem.
When an external pulse signal is applied to the XTAL1 pin (except for signal input by crystal oscillation), the duty of the
XTAL1 pin should be 48% - 52% and the transition time of the XTAL1 pin should be within 5% of the signal cycle to
ensure the duty factor of 45% - 55% at the CLK pin.
Table 2 Clock frequency selection (fXTAL: Frequency at XTAL1)
CLKSEL
fclk
BD8918F/FV
1
f XTAL
0
f XTAL
2
CLKSEL
BD8919F/FV
1
0
fclk
f XTAL
2
f XTAL
4
7) RSTIN input, RST output
The RSTIN input becomes effective after the CMDVCCB signal input turns to L from H, activation sequence is initiated
and approximately 48s after I/O TRANS turns ON. The RST output is released in approximately 472sec (max.
481sec) after the CMDVCCB signal turns from H to L to output a signal based on the RSTIN input.
8) Fault detection
When the following fault state is detected, the circuit enters the wait mode after it generates an internal alarm signal and
is deactivated.
If a card is not present, it remains in the wait mode.
•
•
•
•
When the VCC pin becomes less than 1.6V, or is loaded high current (TYP: 140mA)
When VDDP voltage is less than the threshold voltage (detected by supply voltage detector)
When a high temperature is detected by the thermal shutdown circuit
When the card is removed during operation or the card is not present from the beginning (PRES=L)
9) OFFB output
The OFFB output pin indicates the IC is ready to operate. It is pulled up to VDD with a 20k resistor.
When the IC is in the ready state, OFFB is High.
After activation, the OFFB outputs OFF state (Lo) when a fault state is detected.
When a card is present and CMDVCCB becomes High, the internal alarm is released and the OFFB output becomes
High.
PRES
OFFB
CMDVCCB
tdebounce
tdebounce
tdebounce = typ 8ms
VCC
Shutdown by card removal
カード取り外しによる停止動作
Fig. 6
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Shutdown
by short-circuiting of pins
端子ショート等による停止動作
OFFB, CMDVCCB, PRES, VCC operation
11/15
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
●An example of software control
Start
OFFB=H ?
No (No card)
Yes (Card detect)
Error message 1
･Card insert
CMDVCCB: H→L
End
Activation start
↓
Regulator on (VCC)
↓
IO enable (IO)
OFFB=L ?
No alarm
Card communication start
RSTIN: L→H
↓
Complete
Alarm detect
･Card off
･Over current
･Drop VDDP
･Thermal
shutdown
Error message 2
･Detects error at card
communication
CMDVCCB: L→H
Deactivation start
↓
IO disable (IO)
↓
Regulator off (VCC)
Deactivation start
↓
IO disable (IO)
↓
Regulator off (VCC)
CMDVCCB: L→H
* Ensure to set CMDVCCB LH to confirm that LSI
could detect alarm at the host side
End
End
Fig. 7 An example of software control
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12/15
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
●Application examples
BD8918F/FV application examples
CONTROLLER
0.1µF
+3.3V
10µF
(22pF)
(22pF
)
XTAL1
XTAL2
220Ω
VDD
CLKSEL
8MHz
RSTIN
IO_U
CGND
IO_C
1
2
3
4
5
6
7
8
16
15
14
BD8918F/
13
BD8918FV
12
11
10
9
GND
CMDVCCB
OFFB
PRES
VDDP
VCC
+5V
CLK
RST
1µF
CARD CONNECTION
0.22µF
C5
C6
C1
C2
C7
C3
C8
C4
K1
K2
Fig.8
CONTROLLER
0.1uF
10uF
+3.3V
XTAL 1
1
16
2
15
VDD 3
CLKSEL 4
RSTIN
5
IO _U
6
CGND
7
IO _C
8
BD8918F/
BD8918FV
14
13
12
11
10
9
GND
CMDVCCB
OFFB
PRES
VDDP
VCC
+5V
CLK
RST
1uF
CARD CONNECTION
0.22 uF
C5
C6
C7
C8
C1
C2
C3
C4
K1
K2
Fig.9
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13/15
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
BD8919F/FV application examples
CONTROLLER
0.1µF
+3.3V
10µF
(22pF)
(22pF)
220Ω
XTAL1
1
16
2
VDD 3
CLKSEL 4
15
16MHz
XTAL2
RSTIN 5
IO_U 6
CGND
7
IO_C
8
14
GND
CMDVCCB
OFFB
BD8919F/ 13 PRES
BD8919FV 12 VDDP
VCC
11
10 CLK
+5V
9 RST
1µF
CARD CONNECTION
0.22µF
C5
C6
C1
C2
C7
C3
C8
C4
K1
K2
●Precautions for use
1) The capacitor for the VCC pin should be placed as close as possible to the IC between VCC and CGND so that the ESR
becomes less than 100Ω
2) Connect a capacitor of over 0.1µF for VDD and over 10µF for VDDP as close as possible to the IC so that the ESR
becomes less than 100m to reduce the power line noise. We recommend the use of capacitors with the largest possible
capacitance.
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14/15
2010.4 - Rev.D
Technical Note
BD8918F,BD8918FV,BD8919F,BD8919FV
 Ordering part number
B
D
8
Part No.
9
1
8
F
Part No.
8918
8919
V
-
E
2
Packaging and forming specification
E2: Embossed tape and reel
Package
F: SOP16
FV: SSOP-B16
SOP16
<Tape and Reel information>
10 ± 0.2
(MAX 10.35 include BURR)
9
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
0.3MIN
4.4±0.2
6.2±0.3
16
1
8
0.11
1.5±0.1
0.15 ± 0.1
1.27
0.4 ± 0.1
0.1
1pin
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
SSOP-B16
<Tape and Reel information>
5.0±0.2
9
0.3Min.
4.4±0.2
6.4±0.3
16
1
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
8
0.10
1.15±0.1
0.15±0.1
0.1
0.65
1pin
0.22±0.1
Reel
(Unit : mm)
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© 2009 ROHM Co., Ltd. All rights reserved.
15/15
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.4 - Rev.D
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
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http://www.rohm.com/contact/
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© 2010 ROHM Co., Ltd. All rights reserved.
R1010A