ICST ICS840024AGIT Femtoclocksâ ¢ crystal-to lvcmos/lvttl frequency synthesizer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840024I
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS840024I is a 4 output LVCMOS/LVTTL
Synthesizer optimized to generate Ethernet
HiPerClockS™ reference clock frequency and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. The ICS840024I uses ICS’ 3rd
generation low phase noise VCO technology and can achieve
1ps or lower typical random rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS840024I is packaged in a
small 20-pin TSSOP package.
• Four LVCMOS/LVTTL outputs, 15Ω typical output impedance
ICS
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following output frequency: 125MHz
• RMS phase jitter @125MHz (1.875MHz - 20MHz):
0.60ps (typical)
• Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
OE Pullup
nPLL_SEL
nXTAL_SEL
XTAL_IN
Pulldown
Pulldown
25MHz
OSC
0
Q0
1
XTAL_OUT
TEST_CLK Pulldown
1
Phase
Detector
VCO
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
GND
Q0
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
Q1
0
ICS840024I
÷5
Q2
M = ÷25 (fixed)
MR
nc
nc
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
nc
VDD
Q3
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840024AGI
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1
REV. A DECEMBER 16, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840024I
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2, 9, 20
nc
Unused
Type
Description
3
nXTAL_SEL
Input
Pulldown
4
TEST_CLK
Input
Pulldown
5
OE
Input
Pullup
6
MR
Input
Pulldown
7
nPLL_SEL
Input
Pulldown
8
VDDA
Power
10
11,
12
13, 19
14, 15
17, 18
16
VDD
XTAL_OUT,
XTAL_IN
GND
Q3, Q2,
Q1, Q0
VDDO
Power
Input
Power
Output
Power
No connect.
Selects between the crystal or TEST_CLK inputs as the PLL reference
source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
Single-ended LVCMOS/LVTTL clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the otuputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency =
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Power supply ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
15Ω typical output impedence.
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
Maximum
Units
4
pF
VDD, VDDA, VDDO = 3.465V
TBD
pF
VDD, VDDA = 3.465V, VDDO = 2.625V
TBD
pF
VDD, VDDA, VDDO = 2.625V
TBD
pF
51
KΩ
CPD
Power Dissipation Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN
Input Pulldown Resistor
51
KΩ
ROUT
Output Impedance
15
Ω
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REV. A DECEMBER 16, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840024I
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
VDD
Parameter
Core Supply Voltage
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
75
mA
IDDA
IDDO
Analog Supply Current
Output Supply Current
6
3
mA
mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
VDD
Parameter
Core Supply Voltage
VDDA
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
Analog Supply Voltage
3.135
3.3
3.465
V
2.375
2.5
2.625
VDDO
Output Supply Voltage
IDD
Power Supply Current
75
mA
IDDA
IDDO
Analog Supply Current
Output Supply Current
6
3
mA
mA
V
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
VDD
Parameter
Core Supply Voltage
VDDA
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
Units
V
Analog Supply Voltage
2.375
2.5
2.625
V
2.375
2.5
2.625
VDDO
Output Supply Voltage
IDD
Power Supply Current
70
mA
IDDA
IDDO
Analog Supply Current
Output Supply Current
6
3
mA
mA
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V
REV. A DECEMBER 16, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840024I
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 3D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% OR 2.5V±5%, OR
VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
VIH
VIL
IIH
Input
High Voltage
Input
Low Voltage
Input
High Current
Test Conditions
OE, MR,
nPLL_SEL, nXTAL_SEL,
TEST_CLK
OE, MR,
nPLL_SEL, nXTAL_SEL,
TEST_CLK
OE
nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
OE
IIL
Input
Low Current
nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VDD = VIN = 3.465V or
2.625V
VDD = VIN = 3.465V or
2.625V
VDD = 3.465V or 2.625V,
VIN = 0V
Minimum Typical
Maximum
Units
2
VDD + 0.3
V
2
VDD + 0.3
V
-0.3
0.8
V
-0.3
1.3
V
5
µA
150
µA
-150
µA
-5
µA
VDDO = 3.3V ± 5%
2.6
V
VDDO = 2.5V ± 5%
1.8
V
VDD = 3.465V or 2.625V,
VIN = 0V
VDDO = 3.3V or 2.5V ± 5%
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pf parallel resonant crystal.
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REV. A DECEMBER 16, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840024I
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
tL
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
PLL Lock Time
tR / tF
Output Rise/Fall Time
tjit(Ø)
Test Conditions
Minimum
Intergration Range
1.875MHz - 20MHz
20% to 80%
Typical
Maximum
Units
125
MHz
TBD
ps
0.60
ps
TBD
ms
400
ps
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
%
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
tL
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
PLL Lock Time
tR / tF
Output Rise/Fall Time
tjit(Ø)
Test Conditions
Minimum
Intergration Range
1.875MHz - 20MHz
20% to 80%
Typical
Maximum
Units
125
MHz
TBD
ps
0.55
ps
TBD
ms
400
ps
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
%
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
125
MHz
tsk(o)
TBD
ps
0.50
ps
tL
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
PLL Lock Time
TBD
ms
tR / tF
Output Rise/Fall Time
400
ps
tjit(Ø)
Intergration Range
1.875MHz - 20MHz
20% to 80%
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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%
REV. A DECEMBER 16, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840024I
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 125MHZ (3.3V/3.3V)
➤
0
-10
-20
Ethernet Filter
-40
125MHz
-50
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.60ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-30
-120
-130
-140
-150
➤
-160
-170
-180
Phase Noise Result by adding
Ethernet Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 125MHZ (3.3V/2.5V)
0
➤
-10
-20
-30
Ethernet Filter
-50
125MHz
-60
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.55ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-40
-120
-130
-140
-150
➤
-160
-170
Phase Noise Result by adding
Ethernet Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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REV. A DECEMBER 16, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840024I
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 125MHZ (2.5V/2.5V)
➤
0
-10
-20
Ethernet Filter
-40
125MHz
-50
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.50ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-30
-120
-130
-140
-150
➤
-160
-170
Phase Noise Result by adding
Ethernet Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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REV. A DECEMBER 16, 2004
PRELIMINARY
Integrated
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Systems, Inc.
ICS840024I
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2.05V±5% 1.25V±5%
1.65V±5%
SCOPE
VDD,
VDDA, VDDO
Qx
LVCMOS
SCOPE
VDD,
VDDA
VDDO
Qx
LVCMOS
GND
GND
-1.25V±5%
-1.65V±5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V±5%
Noise Power
Phase Noise Plot
SCOPE
VDD,
VDDA, VDDO
Qx
LVCMOS
Phase Noise Mask
GND
Offset Frequency
f1
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.25V±5%
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
V
DDO
Qx
80%
80%
tR
tF
2
Clock
Outputs
V
DDO
Qy
f2
20%
20%
2
t sk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
V
DDO
2
Q0:Q3
Pulse Width
t
odc =
PERIOD
t PW
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A DECEMBER 16, 2004
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Systems, Inc.
ICS840024I
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS840024I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VDDA.
3.3V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840024I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2
below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
ICS84332
ICS840024I
Figure 2. CRYSTAL INPUt INTERFACE
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REV. A DECEMBER 16, 2004
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Systems, Inc.
ICS840024I
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840024I is: 3085
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REV. A DECEMBER 16, 2004
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Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
ICS840024I
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
FOR
20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
N
MAX
20
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
E
E1
6.60
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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REV. A DECEMBER 16, 2004
PRELIMINARY
Integrated
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Systems, Inc.
ICS840024I
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
ICS840024AGI
ICS840024AGIT
Temperature
TBD
20 Lead TSSOP
72 per tube
-40°C to 85°C
TBD
20 Lead TSSOP on Tape and Reel
2500
-40°C to 85°C
The aforementioned trademarks, HiPerClockS™ and FEMTOCLOCKS™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. A DECEMBER 16, 2004
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