E2B0035-27-Y3
¡ Semiconductor
MSM6562B-xx
¡ Semiconductor
This version:
Nov. 1997
MSM6562B-xx
Previous version: Mar. 1996
DOT MATRIX LCD CONTROLLER DRIVER
GENERAL DESCRIPTION
The MSM6562B-xx controls a character type dot matrix LCD in combination with an 8-bit or 4bit microcontroller.
The MSM6562B-xx can control a display of up to 40 characters. With the display data serial
transfer function, the MSM6562B-xx, when used in combination with the character extension IC
(MSM5259), can control a maximum of 80 characters.
FEATURES
•
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•
•
•
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Easy interface with an 8-bit or 4-bit microcontroller.
Dot matrix LCD controller driver for 5 ¥ 7 dots font or 5 ¥ 10 dots font.
Automatic power ON reset.
16 COMMON signal drivers and 100 SEGMENT signal drivers are built in.
Can control up to 80 characters when used in combination with MSM5259.
Built-in character generator ROM for 160 characters with 5 ¥ 7 dots font and 32 characters with
5 ¥ 10 dots font.
Character patterns can be programmed by CG RAM. (5 ¥ 8 dots font: 8 kinds, 5 ¥ 11 dots font:
4 kinds)
1/8 duty (1 line; 5 ¥ 7 dots + cursor), 1/11 duty (1 line; 5 ¥ 10 dots + cursor), or 1/16 duty (2
lines; 5 ¥ 7 dots + cursor) selectable.
Built-in RC oscillation circuit by an external resistor or an internal resistor.
Built-in bias dividing resistors for LCD driving.
Built-in contrast adjusting circuit.
Bidirectional transfer available on segment output.
Aluminum pad chip (Product name: MSM6562B-xx)
xx indicates code number.
1/50
OSC1
OSCR
OSC2
Timing
generation
circuit
DB0 - DB3
8
Character
generator
RAM
(CG RAM)
Address
counter
(ADC)
7
SEG1 - 100
Display data
RAM
(DD RAM)
DO
2/50
SHL1 SHL0
MSM6562B-xx
Contrast
register
(CR)
100
5
100
8
5
100-bit latch
Busy flag
(BF)
COM1 - 16
5
8
8
100
Test
circuit
Data
register
(DR)
5
SEGMENT signal driver
4
Instruction
decoder
(ID)
7
Input/
output
buffer
LCD bias
voltage dividing circuit
V1
V2
V3'
V3
V4
V5
V5'
8
100-bit shift register
T1
T2
T3
4
Instruction
register
(IR)
16-bit 16 COMMON 16
signal
shift
driver
register
Character generator
ROM (CG ROM)
DB4 - DB7
8
Cursor blink
control
Parallel/ serial
conversion
E
R/W
RS0
RS1
7
¡ Semiconductor
L
CP
DF
BLOCK DIAGRAM
VDD
VSS
¡ Semiconductor
MSM6562B-xx
INPUT AND OUTPUT CONFIGURATION
VDD
VDD
VDD
VDD
P
P
P
N
N
N
Applied to Pin E.
Applied to Pins T1, T2 and T3.
Applied to Pins R/W, RS0 and RS1.
VDD
VDD
P
N
VDD
P
VDD
P
N
N
Applied to DO, CP, L and DF.
Applied to DB0 - DB7.
3/50
¡ Semiconductor
MSM6562B-xx
PIN DESCRIPTIONS
Symbol
Description
Read/write selection input pin.
R/W
"H": Read, and "L": Write
Register selection input pins.
RS0, RS1
RS0 "H" RS1 "H": Data register
RS0 "L" RS1 "H" : Instruction register
RS0 "L" RS1 "L" : Contrast register
Input pin for data input/output between CPU and MSM6562B-xx and for activating
E
instruction.
DB0 - DB7
Input/output pins for data send/receive between CPU and MSM6562B-xx.
OSC1, OSC2,
Clock oscillating pins required for internal operation upon receipt of CPU instruction and
OSCR
the LCD drive signal.
When oscillated by an external resistor, connect a resistor between OSC1 and OSC2.
When oscillated by a built-in resistor, connect OSCR and OSC2 externally.
COM1 - COM16
LCD COMMON signal output pins.
SEG1 - SEG100
LCD SEGMENT signal output pins.
SHL0, SHL1
Input pins to control the transfer direction of the SEGMENT signal output data. See table below.
DO
Data output pin to send serial data to the character extension IC.
CP
Clock output pin to transfer the serial data to the character extension IC.
L
Latch output pin to latch the transferred data to the character extension IC.
DF
Output pin for the alternating signal (DF, display frequency) required for an LCD display.
VDD
Power supply pin.
VSS
Ground pin.
V1 - V5, V3'
Bias voltage input pins to drive an LCD and bias setting pin. (Built-in bias dividing resistor)
1/4 bias : Connect V2 and V3. Leave V3' open.
1/5 bias : Connect V3 and V3'.
Since VLCD value depends on V5 voltage, connect a variable resistor between V5 pin and
VSS potential or connect V5 pin and V5' pin to adjust VLCD.
V5'
Contrast adjusting voltage output pin.
SHL0
SHL1
Segment data transfer direction
L
L
SEG1ÆSEG100
L
H
SEG100ÆSEG1
H
L
SEG1ÆSEG50fiSEG100ÆSEG51
H
H
SEG100ÆSEG1
4/50
¡ Semiconductor
MSM6562B-xx
ABSOLUTE MAXIMUM RATINGS
Symbol
Condition
Rating
Unit
Applicable Pin
VDD
Ta = 25°C
–0.3 to + 7.0
V
VDD, VSS
V1, V2, V3,
V4, V5
Ta = 25°C
–0.3 to VDD + 0.3
V
V1, V2, V3,
V4, V5
Input voltage
VI
Ta = 25°C
–0.3 to VDD + 0.3
V
R / W, RS1,
RS0, E,
DB0 - DB7
OSC1
Junction temperature
Tj
—
150
°C
—
Storage temperature
TSTG
—
–55 to + 150
°C
—
Parameter
Supply voltage
Supply voltage for LCD
display
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Range
Unit
Applicable Pin
VDD
—
V
VDD, VSS
LCD driving voltage
VLCD
VDD – VSS 1/4 bias *1
VDD – VSS 1/5 bias *2
4.5 to 5.5
3.0 to 5.5 *3
3.0 to 5.5 *3
V
Operating temperature
Top
—
–30 to +85
°C
Supply voltage
V
*1
This voltage should be applied to VDD – V5.
Voltages applicable to V1, V2, V3 and V4 are as follows:
V1 = VDD – 1/4 (VDD – V5)
V2 = V3 = VDD – 1/2 (VDD – V5)
V4 = VDD – 3/4 (VDD – V5)
*2
This voltage should be applied to VDD – V5.
Voltages applicable to V1, V2, V3 and V4 are as follows:
V1 = VDD – 1/5 (VDD – V5)
V2 = VDD – 2/5 (VDD – V5)
V3 = VDD – 3/5 (VDD – V5)
V4 = VDD – 4/5 (VDD – V5)
*3
The relation of VDD > V1 > V2 ≥ V3 (=V3') > V4 > V5 ≥ VSS must be kept.
(High ¨
Æ Low)
LCD driving voltage can be adjusted by varying V5.
However, V5 cannot be used under VSS voltage.
VDD, V5
—
5/50
¡ Semiconductor
MSM6562B-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 4.5 to 5.5V, Ta = -30 to +85°C)
Parameter
"H" input voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
Applied Pin
VIH1
—
2.2
—
VDD
V
R/W, RS0, RS1, E,
DB0 - DB7
"L" input voltage
VIL1
—
–0.3
—
0.6
V
"H" input voltage
VIH2
—
VDD – 0.8
—
VDD
V
"L" input voltage
VIL2
—
–0.3
—
0.8
V
"H" output voltage
VOH1
IO = –0.205mA
2.4
—
—
V
"L" output voltage
VOL1
IO = 1.6mA
—
—
0.4
V
"H" output voltage
VOH2
IO = –40mA
0.9VDD
—
—
V
"L" output voltage
VOL2
IO = 40mA
—
—
0.1VDD
V
DO, CP, L,
DF, OSC2
COM voltage drop
VC
IO = ± 40mA
(Note 1)
—
—
2.3
V
COM1 - COM16
SEG voltage drop
VS
IO = ± 40mA
(Note 1)
—
—
3.0
V
SEG1 - SEG100
Input leakage current
IIL
VI = VDD
—
—
1
mA
VI = VSS
—
—
–1
mA
—
—
2
mA
"H" input current
"L" input current
IIH2
IIL2
VI = VDD
Except the current flowing
to the pull-up resistor and
output driving MOS.
VDD = 5.0V
mA
—
—
1
mA
VDD
2
4
8
kW
VDD – V1, V1 – V2
V2 – V3', V3 – V4
V4 – V5
VDD = 5.0V, 1/5 bias
4.6
—
—
V
VDD – V5 (V5')
VDD = 5.0V, 1/5 bias
—
—
3.7
3.0
—
5.5
V
VDD, V1, V2, V3,
V3', V4, V5
LCD driving bias
resistance
LBR
—
VLCD2
R/W, RS0, RS1,
DB0 - DB7
–204
IDD
VLCD1
E, SHL0, SHL1
–83
Supply current
LCD driving bias voltage
(external input)
DB0 - DB7
–34
VI = VSS
VDD = 5.0V
E = "L" level, SHL0, SHL1 = "L" level
Built-in Rf oscillation or external
clock input to OSC1.
External clock frequency (fIN) is
270kHz.
R/W, RS0, RS1, and DB0 to DB7 are
open.
Output pins are all no load. Except
bias current for LCD driving.
(Note 2, 3, 4)
Variable range by built-in VLCD MAX
variable resistor for LCD
driving voltage
VLCD MIN
OSC1
SHL0, SHL1
VDD – V5
(Note 5)
1/5 bias
1/4 bias
3.0
—
5.5
6/50
¡ Semiconductor
(Note
1)
MSM6562B-xx
Applies to the voltage drop (VC) from VDD, V1, V4 and V5 to each COMMON pin
(COM1 to COM16) as well as to voltage drop (VS) from VDD, V2, V3 and V5 to each
SEG pin (SEG1 to SEG100) when 40mA is flowed through one COM or SEG pin.
When output level is at VDD, V1, or V2 level, 40mA is flowed out, while 40mA is
flowed in when the output level is at V3, V4 or V5 level.
This occurs when 5V is input to VDD, V1 and V2 , and 0V is input to V3, V4 and
V5.
(Note
2)
Applies to the current value flowed in the pin VDD, in the case of VDD = 5V,
VSS = 0V, V1, V2 = 5V, V3, V4, V5 = 0V and V5' is open.
(Note
3)
Built-in Rf oscillation circuit
OSC1
Minimum wiring is required between OSCR and OSC2.
Leave OSC1 open.
OSCR
OSC2
(Note
4)
External clock input circuit
Input pulse
Leave OSCR and OSC2 open.
OSC1
OSCR
OSC2
(Note
5) Input the voltage to V5. (However, V5 cannot be used under VSS voltage.)
N (number of LCD lines)
Pin
1-line mode
Bias : 1/4
2-line mode
Bias : 1/5
V1
VDD –
VLCD
4
VDD –
VLCD
5
V2
VDD –
VLCD
2
VDD –
2VLCD
5
V3
VDD –
VLCD
2
VDD –
3VLCD
5
V4
VDD –
3VLCD
4
VDD –
4VLCD
5
V5
VDD – VLCD
VDD – VLCD
At 1/4 bias : Connect V2 and V3 externally and leave V3' open.
At 1/5 bias : Connect V3 and V3' externally.
VLCD is the LCD driving voltage. (For N [number of LCD lines], refer to
the explanation of the Function setting instruction of the instruction code.)
7/50
¡ Semiconductor
MSM6562B-xx
AC Characteristics
Parameter
Symbol
Condition
Min.
Typ.
Max.
Rf = 120 kW ± 2%
(Note 1)
175
270
350
kHz
OSC1
OSC2
OSCR and OSC2 are open.
Input a pulse to OSC1.
(Note 4)
125
—
480
kHz
OSC1
fduty
(Note 2)
45
50
55
%
OSC1
External clock rise time
trf
(Note 3)
—
—
0.2
ms
OSC1
External clock fall time
tff
(Note 3)
—
—
0.2
ms
OSC1
OSC1 is open.
(Note 5)
Connect OSCR and OSC2.
140
280
480
kHz
OSC1
OSCR
OSC2
Rf clock oscillation
frequency
fOSC1
External clock frequency
fIN
External clock duty
Built-in Rf clock
oscillation frequency
(Note
fOSC2
1)
Rf = 120kW ± 2%
OSC1
OSCR
OSC2
(Note
Unit Applicable Pin
Minimum wiring is required between OSC1 and Rf and
between OSC2 and Rf.
Leave OSCR open.
Rf
2)
tHW
tLW
Applies to the pulse to be
input to OSC1
fIN
waveform
VDD
2
VDD
2
VDD
2
fduty = tHW /(tHW + tLW) ¥ 100 (%)
(Note
3)
Applies to the pulse to be input to OSC1.
Applies to the pulse to be
input to OSC1
fIN
waveform
VDD – 0.8V
VDD – 0.8V
0.8V
0.8V
(Note
4)
trf
tff
See Note 4 to "DC Characteristics."
(Note
5)
See Note 3 to "DC Characteristics."
8/50
¡ Semiconductor
MSM6562B-xx
Switching Characteristics
1. Timing for input from the CPU (write operation)
(VDD = 4.5 to 5.5V, Ta = –30 to +85°C)
Parameter
Symbol
Typ.
Max.
Unit
tB
tW
tA
tr
tf
tL
tC
tI
tH
R/W, RS0 and RS1 setup time
E "H" pulse width
R/W, RS0 and RS1 hold time
E rise time
E fall time
E "L" pulse width
E cycle time
DB0 to DB7 input data setup time
DB0 to DB7 input data hold time
40
—
—
ns
220
—
—
ns
10
—
—
ns
—
—
20
ns
—
—
20
ns
210
—
—
ns
500
—
—
ns
100
—
—
ns
10
—
—
ns
VIH1
VIL1
VIH1
VIL1
RS1, 0
R/W
VIL1
VIL1
tr
tB
tL
E
Min.
VIL1
tf
tW
VIH1
tA
VIH1
VIL1
VIL1
tI
VIH1
Input data
VIL1
DB0-7
tH
VIH1
VIL1
tc
9/50
¡ Semiconductor
MSM6562B-xx
2. Timing for output to the CPU (read operation)
(VDD = 4.5 to 5.5V, Ta = –30 to +85°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
tB
tW
tA
tr
tf
tL
tC
tD
tO
40
—
—
ns
220
—
—
ns
10
—
—
ns
—
—
20
ns
—
—
20
ns
210
—
—
ns
500
—
—
ns
—
—
150
ns
20
—
—
ns
R/W, RS0 and RS1 setup time
E "H" pulse width
R/W, RS0 and RS1 hold time
E rise time
E fall time
E "L" pulse width
E cycle time
DB0 to DB7 data ouput delay time
DB0 to DB7 data ouput hold time
VIH1
VIL1
RS1, 0
VIH1
VIL1
VIL1
R/W
VIL1
tr
tB
tL
E
VIL1
tW
VIL1
tf
tA
VIH1
VIL1
VIL1
tD
tO
VOH1
Output data
VOL1
DB0-7
VOH1
VOL1
tc
10/50
¡ Semiconductor
MSM6562B-xx
3. Timing for output to character extension IC
(VDD = 4.5 to 5.5V, Ta = –30 to +85°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
tHW1
tLW
tS
tDH
tSU
tHO
tHW2
tM
800
—
—
ns
800
—
—
ns
300
—
—
ns
300
—
—
ns
500
—
—
ns
100
—
—
ns
800
—
—
ns
–1000
—
1000
ns
CP "H" pulse width
CP "L" pulse width
DO setup time
DO hold time
L clock setup time
L clock hold time
L "H" pulse width
DF delay time
VOH2
VOL2
DO
tHW1
CP
L
VOH2
tLW
tS
VOH2
VOH2
VOH2
tDH
VOH2
VOL2
VOL2
VOH2
VOL2
tSU
VOH2
tHW2
tHO
VOH2
VOL2
tM
VOH2
DF
11/50
¡ Semiconductor
MSM6562B-xx
FUNCTIONAL DESCRIPTION
1. Instruction Register (IR), Data Register (DR), Contrast Register (CR)
These three registers are selected by the register selector pins, RS0 and RS1.
When RS0 and RS1 are "H" level input, the DR is selected and when RS0 = "L" level input and RS1
= "H", the IR is selected. On the other hand, when RS0 and RS1 are "L" level input, the CR is
selected. (When RS0 = "H" level input and RS1 = "L", the registers are ignored.)
The IR is used to store the address codes for the display data RAM (DD RAM) or character
generator RAM (CG RAM) and instruction codes.
The IR can be written into, but not be read out by the microcomputer (CPU).
The CR can be used to read out and write. The CR values provide 0 to 1F (hexadecimal) and when
this value is 0, VLCD is lowest. On the other hand, when it is 1F, it is highest. (The initial value is
1F.) Therefore, the contrast can be adjusted by varying the CR value (providing that V5 and V5'
are connected).
The DR is used to write into/read out the data to/from the DD RAM or CG RAM.
The data written to the DR by the CPU is automatically written to the DD RAM or CG RAM as
an internal operation.
When an address code is written to the IR, the data (of the specified address) is automatically
transferred from the DD RAM or CG RAM to the DR. By having the CPU subsequently read the
DR (from the DR data), it is possible to verify the DD RAM or CG RAM data.
After the writing of the DR by the CPU, the DD RAM or CG RAM of the next address is selected
to be ready for the next CPU writing. Likewise, after the reading out of the DR by the CPU, the
DD RAM or CG RAM data is read out by the DR to be ready for the next CPU reading.
Write/read to and from the three registers is carried out by the READ/WRITE (R/W) pin.
Table 1
R/W
RS0
Register and R/W pins function table
RS1
Function
L
L
H
IR write
H
L
H
Read of busy flag (BF) and address counter (ADC)
L
H
H
DR write
H
H
H
DR read
L
L
L
CR write
H
L
L
CR read
2. Busy Flag (BF)
When the busy flag output is at "H", it indicates that the MSM6562B-xx is engaged in internal
operation.
When the busy flag is at "H" level, any new instruction is ignored.
When R/W = "H", RS0 = "L", and RS1 = "H", the busy flag is output from DB7.
New instruction should be input when BF is "L" level.
When the busy flag is set to "H", the output code of the address counter (ADC) are undefined.
12/50
¡ Semiconductor
MSM6562B-xx
3. Address Counter (ADC)
The address counter (ADC) allocates the address for the DD RAM and CG RAM and also for the
cursor display.
When the instruction code for the DD RAM address or CG RAM address setting is input to the
IR, after deciding whether it is the DD RAM or CG RAM, the address code is transferred from
the IR to the ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM,
the ADC is automatically incremented (decremented) by 1 as its internal operation.
The data of the ADC is output to DB0 - DB6 under the conditions that R/W = "H", RS0 = "L", RS1
= "H" and BF = "L".
4. Timing Generator Circuit
This circuit generates timing signals used for internal operations upon receipt of CPU instruction. It also generates timing signals for activating such internal circuits as the DD RAM, CG RAM
and CG ROM.
It is so designed that the internal operation caused by accessing from the CPU will not interfere
with the internal operation caused by the LCD display.
Consequently, when data is written from the CPU to DD RAM no ill effect, e.g., flickering occurs
in portions other than the display where the data is written.
In addition, the circuit generates transfer signals to the character extension IC (MSM5259).
13/50
¡ Semiconductor
MSM6562B-xx
5. Display Data RAM (DD RAM)
This RAM is used to store the display data of 8-bit character codes (see Table 2).
DD RAM address corresponds to the display position of the LCD. The correspondence between
the two is described in the following.
DD RAM address (set to ADC) is expressed in hexadecimal notation as shown below:
ADC
DB6
DB0
MSB
LSB
Hexadecimal notation
(Example)
When DD RAM address
is 2A
L
H
Hexadecimal notation
L
H
L
2
1-1)
H
L
A
Correspondence between address and display position in the 1-line display mode
First digit
2
3
4
5
79
80
Display position
00
01
02
03
04
4E
4F
DD RAM address (hex.)
MSB
1-2)
LSB
When the MSM6562B-xx alone is used, up to 20 characters can be displayed from the
first digit to the twentieth digit.
First digit
2
3
4
19
20
00
01
02
03
12
13
display
When the display is shifted by instruction, the correspondence between the LCD
position and the DD RAM address changes as shown below:
First digit
2
3
4
19
20
4F
00
01
02
11
12
First digit
2
3
4
19
20
01
02
03
04
13
14
(Display shifted to right)
(Display shifted to left)
14/50
¡ Semiconductor
1-3)
MSM6562B-xx
When the MSM6562B-xx is used with one MSM5259, up to 28 characters can be
displayed from the first digit to the twenty-eighth digit as shown below:
First digit
2
3
4
19
20
21
22
23
24
25
26
27
28
00
01
02
03
12
13
14
15
16
17
18
19
1A
1B
MSM6562B-xx display
MSM5259 display
When the display is shifted by instruction, the correspondence between the
LCD display and DD RAM address changes as shown below:
First digit 2
(Display shifted to right)
4F
00
3
4
19
20
21
22
23
24
25
26
27
28
01
02
11
12
13
14
15
16
17
18
19
1A
1B
1C
MSM6562B-xx display
(Display shifted to left)
1-4)
First
digit 2
01
02
03
04
13
MSM5259 display
14
15
16
17
18
19
1A
Since the MSM6562B-xx has a DD RAM with a capacity of 80 characters, up to 8 devices
of MSM5259 can be connected to MSM6562B-xx so that 80 characters can be displayed.
3
4
19 20 21 22 23 24 25 26 27 28 29 30
77 78 79 80
00 01 02 03
12 13 14 15 16 17 18 19 1A 1B 1C 1D
4C 4D 4E 4F
MSM6562B-xx display
MSM5259 (1) display
MSM5259
(2)-(7) display
MSM5259
(8) display
(Only the half of the
segment output pins,
i.e., O1 to O20, are used.)
15/50
¡ Semiconductor
2-1)
MSM6562B-xx
Correspondence between address and display position in the 2-line display mode
First digit
2
3
4
5
39
40
Display position
DD RAM address (hex.)
First line
00
01
02
03
04
26
27
Second line
40
41
42
43
44
66
67
(Note) Note that the last address of the first line and the leading address of the
second line are not consecutive.
2-2)
When the MSM6562B-xx alone is used, up to 40 characters (20 character ¥ 2 lines) can
be displayed from the first digit to the twentieth digit.
First digit
2
3
4
19
20
First line
00
01
02
03
12
13
Second line
40
41
42
43
52
53
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
(Display shifted to right)
(Display shifted to left)
2-3)
First digit
2
3
4
19
20
First line
27
00
01
02
11
12
Second line
67
40
41
42
51
52
First digit
2
3
4
19
20
First line
01
02
03
04
13
14
Second line
41
42
43
44
53
54
When the MSM6562B-xx is used with one MSM5259, up to 56 characters (28 characters
¥ 2 lines) can be displayed from the first digit to the twenty-eighth digit as shown
below:
First digit
2
3
4
19
20
21
22
23
24
25
26
27
28
First line
00
01
02
03
12
13
14
15
16
17
18
19
1A
1B
Second line
40
41
42
43
52
53
54
55
56
57
58
59
5A
5B
MSM6562B-xx display
MSM5259 display
16/50
¡ Semiconductor
MSM6562B-xx
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
(Display shifted to right)
First digit
2
3
4
19
20
21
22
23
24
25
26
27
28
First line
27
00
01
02
11
12
13
14
15
16
17
18
19
1A
Second line
67
40
41
42
51
52
53
54
55
56
57
58
59
5A
MSM6562B-xx display
MSM5259 display
(Display shifted to left)
First digit
2
3
4
19
20
21
22
23
24
25
26
27
28
First line
01
02
03
04
13
14
15
16
17
18
19
1A
1B
1C
Second line
41
42
43
44
53
54
55
56
57
58
59
5A
5B
5C
MSM6562B-xx display
2-4)
MSM5259 display
Since the MSM6562B-xx has a DD RAM with a capacity of 80 characters, up to 3 devices
of MSM5259 can be connected to the MSM6562B-xx in the 2-line display mode.
First
digit 2
3
4
19 20 21 22 23 24 25 26 27 28 29 30
37 38 39 40
00 01 02 03
12 13 14 15 16 17 18 19 1A 1B 1C 1D
24 25 26 27
40 41 42 43
52 53 54 55 56 57 58 59 5A 5B 5C 5D
64 65 66 67
MSM6562B display
MSM5259 (1) display
MSM5259
(2) display
MSM5259
(3) display
(Only the half of the segment
output pins, i.e., O1 to O20, are used.)
6. Character Generator ROM (CG ROM)
The CG ROM is used to generate 5 ¥ 7 dot (160 kinds) character patterns or 5 ¥ 10 dot (32 kinds)
character patterns from an 8-bit DD RAM character code signal.
The correspondence of 8-bit character codes to character patterns is shown in Table 2.
When the 8-bit character code of the CG ROM is written to the DD RAM, the character pattern
of the CG ROM corresponding to the code is displayed on the LCD display position corresponding to the DD RAM address.
17/50
MSB
0000
0001
(2)
0010
(3)
0011
(4)
0100
0010
0011
0100
0101
0110
0111
1010
1011
1100
1101
1110
1111
@
P
/
p
a
R
1
A
Q
a
q
ä
q
2
B
R
b
r
b
Q
#
3
C
S
c
s
e
•
(5)
$
4
D
T
d
t
m
W
0101
(6)
%
5
E
U
e
u
s
ü
0110
(7)
&
6
F
V
f
v
r
S
0111
(8)
7
G
W
n
w
g
p
1000
(1)
(
8
H
X
h
x
√
X
1001
(2)
)
9
I
Y
i
y
–1
1010
(3)
*
:
J
Z
j
z
j
1011
(4)
+
;
K
[
k
{
x
1100
(5)
<
L
¥
l
Ù
¢
1101
(9)
–
=
M
]
m
}
£
1110
(7)
.
>
N
^
n
Æ
n
1111
(8)
/
?
O
_
o
¨
!
°
ö
÷
MSM6562B-xx
18/50
0
Character codes and character patterns of standard code (MSM6562B-01)
0000
LSB
CG
RAM (1)
¡ Semiconductor
Upper
4 bits
Table 2
Lower
4 bits
¡ Semiconductor
MSM6562B-xx
7. Character Generator RAM (CG RAM)
The CG RAM is used to display user's original character patterns other than those stored in the
CG ROM.
The CG RAM has the capacity (64 bytes = 512 bits) to write 8 kinds for 5 ¥ 7 dots or 4 kinds for
5 ¥ 10 dots.
When displaying character patterns stored in the CG RAM, write 8-bit character codes (00 to 07
or 08 to 0F; hex.) shown on the left in Table 2 to the DD RAM. It is then possible to output the
character pattern to the LCD display position corresponding to the DD RAM address.
The following is a description on how to write and read character patterns to and from the CG
RAM.
(1) When the character pattern is 5 ¥ 7 dots (see Table 3)
• Method of writing character pattern into the CG RAM by the CPU :
The CG RAM address bits 0 to 2 correspond to the line position of the character pattern.
First, set increment or decrement by the CPU, and then input the CG RAM address.
After this, write character pattern into the CG RAM through DB0 to DB7 line by line.
DB0 to DB7 correspond to the CG RAM data bits 0 to 7 in Table 3.
The display of the character pattern is turned on when "H" is set as input data, while it is
turned off when "L" is set as the input data.
Since the ADC is automatically incremented or decremented by 1 after writing the data
to the CG RAM, it is not necessary to set the CG RAM address again.
When performing a cursor indication, set to "0" all the input data for the line the CG RAM
address bits 0 to 2 of which are all "1".
Although the CG RAM data bits 0 ~ 4 are output to the LCD as display data, the CG RAM
data bits 5 ~ 7 are not. It is possible, however, to use the CG RAM as a data RAM.
• Method of displaying the CG RAM character pattern to the LCD :
The CG RAM is selected when high-order 4 bits of the character code are all "L".
Since bit 3 of the character code is invalid, the display of "0" in Table 3 is selected by
character code "00" or "08" (hex.). When the 8-bit character code of the CG RAM is written
to the DD RAM, the character pattern of the CG RAM is displayed on the LCD display
position corresponding to the DD RAM address. (DD RAM data bits 0 to 2 correspond to
CG RAM address bits 3 to 5.)
19/50
¡ Semiconductor
MSM6562B-xx
(2) When the character pattern is 5 ¥ 10 dots (see Table 4).
• Method of writing character pattern into the CG RAM by the CPU :
The CG RAM address bits 0 to 3 correspond to the line position of the character pattern.
First, set increment or decrement by the CPU, and then input the CG RAM address.
After this, write the character pattern into the CG RAM through DB0 to DB7 line by line.
DB0 to DB7 correspond to the CG RAM data bits 0 to 7, in Table 4.
The display of the character pattern is turned on when "H" is set as the input data, while
it is turned off when "L" is set as the input data.
Since the ADC is automatically incremented or decremented by 1 after writing the data
to the CG RAM, it is not necessary to set the CG RAM address again.
When performing a cursor indication, set to "0" all the input data for the line the CG RAM
address bits 0 to 2 are all "1".
CG RAM data is displayed on the LCD when the CG RAM data ranges from CG RAM data
bits 0 to 4 and the CG RAM addresses (address bits 0 to 3) are "0" to "A" (hex.). Other CG
RAM data is not displayed on the LCD (that is, when the CG RAM data ranges from CG
RAM data bits 5 to 7 and the CG RAM addresses (address bits 0 to 3) are "B" to "F" (hex.)).
It is possible, however, to read such CG RAM data through DB0 to DB7.
• Method of displaying the CG RAM character pattern to the LCD :
The CG RAM is selected when high-order 4 bits of the character code are all "L".
Since bits 0 and 3 of the character code are invalid, the display of "b" in Table 4 is selected
by character codes "00", "01", "08" and "09" (hex.).
When the 8-bit character code of the CG RAM character code is written to the DD RAM,the
character pattern of the CG RAM is displayed on the LCD display position corresponding
to the DD RAM address.
(DD RAM data bits 1 to 2 correspond to CG RAM address bits 4 to 5.)
20/50
¡ Semiconductor
Table 3
,
,
,
,
Example of the CG RAM data (character pattern) corresponding to the CG RAM
addresses when the character pattern is 5 ¥ 7 dots, and relationship between character
patterns and the DD RAM data
CG RAM address
5 4
MSB
3
2
1 0
LSB
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
MSM6562B-xx
1
1
X : Don't Care
CG RAM data
(character pattern)
7 6 5 4 3 2 1 0
MSB
LSB
0
1
0
1
0
1
0
1
X X
0
1
0
1
0
1
0
1
X X
0
1
0
1
0
1
0
1
X X
X
X
X
0
1
1
1
1
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
DD RAM data
(character code)
7 6 5 4 3 2 1 0
MSB
LSB
0
0
0
0
X
0
0
0
0
0
0
0
X
0
0
1
0
0
0
0
X
1
1
1
21/50
¡ Semiconductor
Table 4
,
,
,
,
,
,
,
Example of the CG RAM data (character pattern) corresponding to the CG RAM
addresses when the character pattern is 5 ¥ 10 dots, and relationship between
character patterns and the DD RAM data
CG RAM address
5 4
MSB
3
2
1 0
LSB
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
MSM6562B-xx
0
0
0
CG RAM data
(character pattern)
7 6 5 4 3 2 1 0
MSB
LSB
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X X
X
X
X
0
0
0
1
1
1
1
1
1
1
0
X
0
0
1
0
1
0
1
0
0
0
0
X
0
0
1
0
1
0
1
0
0
0
0
X
0
0
1
0
1
0
1
0
0
0
0
X
0
0
0
1
0
1
0
0
0
0
0
X
0
0
0
1
1
1
0
0
0
0
0
X
0
0
1
0
0
0
1
0
0
1
0
X
0
0
1
0
0
0
1
0
0
1
0
X
0
0
1
0
0
0
1
0
0
1
0
X
0
0
1
1
1
1
1
1
1
0
0
X
0
0
1
0
1
1
0
0
0
0
0
X
0
0
1
1
0
0
1
0
0
0
0
X
0
0
0
0
0
0
1
0
0
0
0
X
0
0
1
1
0
0
1
0
0
0
0
X
0
0
1
0
1
1
0
0
0
0
0
X
DD RAM data
(character code)
7 6 5 4 3 2 1 0
MSB
LSB
0
0
0
0
X
0
0
X
0
0
0
0
X
0
1
X
0
0
0
0
X
1
1
X
X : Don't care
22/50
¡ Semiconductor
MSM6562B-xx
8. Cursor and Blink Control Circuit
This circuit generates the LCD cursor and blink.
This circuit is under the control of the CPU program. The display of the cursor or blink on the LCD
is made at a position corresponding to the DD RAM address set to the ADC.
The figure below shows an example of the cursor and blink position when the value of the ADC
is set at "07" (hex.).
DB6
ADC
L
DB0
L
L
L
H
0
First digit 2
In 1-line display mode
00
01
H
H
7
3
4
5
6
7
8
9
79
80
02
03
04
05
06
07
08
4E
4F
Cursor and blink position
In 2-line display mode
First digit 2
3
4
5
6
7
8
9
39
40
First line
00
01
02
03
04
05
06
07
08
26
27
Second line
40
41
42
43
44
45
46
47
48
66
67
Cursor and blink position
(Note)
The cursor and blink are displayed even when the CG RAM address is set to the ADC.
For this reason, it is necessary to inhibit the display of the cursor and blink while the
CG RAM address is set to the ADC.
23/50
¡ Semiconductor
MSM6562B-xx
9. LCD Display Circuit (COM1 to COM16, SEG1 to SEG100, L, CP, DO, DF, SHL0, SHL1) :
Since the MSM6562B-xx provides the COM signal outputs (16 outputs) and the SEG signal
outputs (100 outputs), even a single MSM6562B-xx device can display 20 characters (1-line
display) or 40 characters (2-line display).
The character pattern data is converted into the serial data and is serially transferred through the
shift register. The transfer direction of the serial data is controlled by SHL0 and SHL1 and is
shown as follows.
SHL0
SHL1
Transfer direction
L
L
SEG1ÆSEG100
L
H
SEG100ÆSEG1
H
L
SEG1ÆSEG50fiSEG100ÆSEG51
H
H
SEG100ÆSEG1
Connect SHL0 and SHL1 to VDD or VSS. Keep the set states of the SHL0 and SHL1 pins unchanged
during IC operation.
The SEG1 to SEG100 are used to display 20-digit display on the LCD. To display more than 20
digits, the character extension IC (MSM5259) is used.
The character extension IC (MSM5259) is an extended IC for segment signal output. Interfacing
with the MSM5259 is provided through data output pin (DO), clock output pin (CP), latch output
pin (L), and display frequency pin (DF). The character pattern data is serially transferred to the
MSM5259 through DO and CP. When 60-character (= 1-line display) or 20-character (= 2-line
display) is output, the latch pulse is also output through pin L. By this latch pulse, the data
transferred serially to the MSM5259 is latched to be used as the display data. The display
frequency (DF) signal required when the LCD is displayed is also output from DF pin in
synchronization with this latch pulse.
24/50
¡ Semiconductor
MSM6562B-xx
10. Built-in Reset Circuit
The MSM6562B-xx is automatically initialized when the power is turned on.
During initialization, the busy flag (BF) holds "H" and does not accept instructions (other than
the busy flag read).
The busy flag goes to "H" for 15 ms after VDD reaches 4.5V or more.
During initialization, the MSM6562B-xx executes the following instructions :
• Display clear
• Data length of interface with CPU : 8 bits (8B/4B = "H")
• LCD : 1-line display (N = "L")
• Character font : 5 ¥ 7 dots (F = "L")
• ADC : increment (I/D = "H")
• No display shift (S = "L")
• Display : Off (D = "L")
• Cursor : Off (C = "L")
• No blink (B = "L")
• Contrast data : 1F (hex.) set
When the built-in reset circuit is used, the power supply conditions shown in the figure below
must be satisfied. If they are not satisfied, because in that case the built-in reset circuit does not
operate normally, initialize the MSM6562B-xx by instruction through the CPU (see the section
on instruction initialization).
If a battery is used as supply voltage source, be sure to initialize the instruction.
4.5V
0.2V
0.2V
0.2V
VDD
tON
tOFF
0.1ms £ tON £ 100ms
1ms £ tOFF
Power ON/OFF waveform
25/50
¡ Semiconductor
MSM6562B-xx
11. Data Bus with CPU
The MSM6562B-xx has either a one-step access in 8 bits or a two-step access in 4 bits to execute
an instruction so that the MSM6562B-xx can interface with both an 8-bit CPU and a 4-bit CPU.
(1) When the interface data length is 8 bits
Data buses DB0 to DB7 (8 lines) are all used and data input/output is carried out in one
step.
(2) When the interface data length is 4 bits
The 8-bit data input/output is carried out in two steps by using only high-order 4 bits of
data buses DB4 to DB7 (4 lines).
The first time data input/output is made for high-order 4 bits (DB4 to DB7 when the
interfaces data length is 8 bits) and the second time data input/output is made for loworder 4 bits (DB0 to DB3 when the interface data length is 8 bits). Even when the data
input/output can be completely made through high-order 4 bits, be sure to make another
input/output of low-order 4 bits. (Example : Busy flag read)
Since the data input/output is carried out in two steps but as one execution, no normal
data transfer is executed from the next input/output if accessed only once.
26/50
¡ Semiconductor
MSM6562B-xx
RS1
RS0
R/W
E
Busy
(internal
operation)
No
Busy
DR7
IR6
ADC6
DR6
DB5
IR5
ADC5
DR5
DB4
IR4
ADC4
DR4
DB3
IR3
ADC3
DR3
DB2
IR2
ADC2
DR2
DB1
IR1
ADC1
DR1
DB0
IR0
ADC0
DR0
DB7
IR7
DB6
Instruction register
(IR) write
Busy
Busy flag (BF) and
address counter (ADC) read
Data register
(DR) write
Example of 8-bit data transfer
27/50
¡ Semiconductor
RS1
RS0
R/W
E
Busy
(internal operation)
No
Busy
ADC3
DR7
DR3
DB7
IR7
IR3
DB6
IR6
IR2
ADC6
ADC2
DR6
DR2
DB5
IR5
IR1
ADC5
ADC1
DR5
DR1
DB4
IR4
IR0
ADC4
ADC0
DR4
DR0
Instruction register
(IR) write
Busy
Busy flag (BF) and
address counter (ADC) read
28/50
MSM6562B-xx
Example of 4-bit data transfer
Data register
(DR) write
¡ Semiconductor
MSM6562B-xx
12. Instruction Code
• Instruction code table
Code
Instruction
Description
RS1 RS0R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
After all display are cleared,
1 address counter for DD RAM is
set to "00".
Address counter for DD RAM is set
to "00". The shifted display returns
] to the position before shift. The
contents of the DD RAM are not
changed.
Display clear
1
0
0
0
0
0
0
0
0
0
Cursor home
1
0
0
0
0
0
0
0
0
1
0
Direction of the cursor move and
whether display is shifted are set.
1 I/D S Upon data write or read, the cursor
and the display will actually be
moved and shifted.
Entry mode setting
1
0
0
0
0
0
0
Display on/off control
1
0
0
0
0
0
0
Cursor/display shift
1
0
0
0
0
0
1 S/C R/L ]
Function setting
1
0
0
0
0
1
CG RAM address setting
1
0
0
0
1
DD RAM address setting
1
0
0
1
ADD
Busy flag/address read
1
0
1
BF
ADC
CG RAM/DD RAM data
write
1
1
0
CG RAM/DD RAM data
read
1
1
1
Contrast adjusting data
write
0
0
0
0
0
1
Contrast adjusting data
read
0
0
1
0
0
0
I/D=1 :
S=1
:
S/C=1 :
R/L=1 :
8B/4B=1:
N=1
:
F=1
:
BF=1 :
1
8B/
N
4B
D
F
C
]
ACG
The on/off of all display (D), the
on/off of the cursor (C) and the
B
blink (B) of the character at the
cursor position are set.
The cursor and display are
] shifted without changing the
contents of the DD RAM.
The interface data length (8B/4B),
] the display line numbers (N)
and the character font (F) are set.
The address of the CG RAM is set
and then the CG RAM data is
specified for the data for
transmission and reception.
The address of the DD RAM is set
and then the DD RAM data is
specified for the data for
transmission and reception.
Execution Time
ƒCP=ƒOSC=250kHz
1.64ms
1.64ms
40ms
40ms
40ms
40ms
40ms
40ms
The busy flag (BF) indicating that
the internal circuits are operating
and the contents of address counter
are read out.
1ms
WRITE DATA
Data is written into the DD RAM
or CG RAM
40ms
READ DATA
Data is read out from the DD RAM
or CG RAM.
40ms
WRITE CONTRAST
DATA
The data for contrast adjustment
is written.
40ms
READ CONTRAST
DATA
The data for contrast adjustment
is read.
40ms
Increment
, I/D=0 :
Always involves display shift
Shift of display , S/C=0 :
Shift to the right , R/L=0 :
8 bits
, 8B/4B=0 :
2 lines
, N=0
:
5¥10-dots
, F=0
:
Engaged in
, BF=0
:
internal operation
Decrement
DD RAM :
CG RAM :
Shift of cursor ACG
:
Shift to the left ADD
:
4 bits
1 line
5¥7-dots
ADC
:
Instruction
acceptable
Display data RAM
Character generator RAM
CG RAM address
DD RAM address,
corresponding to the
cursor address
Address counter, used for
both DD RAM and CG
RAM
When the frequency
is changed, the
execution time is
also changed.
(Example)
When
ƒCP or ƒOSC=270kHz,
40µs ¥ 250 = 37µs
270
]: Don't Care
29/50
¡ Semiconductor
MSM6562B-xx
13. Description of Instructions
The instruction code is defined as the signal through which the MSM6562B-xx is accessed by
the CPU.
The MSM6562B-xx begins operation upon receipt of the instruction code input.
As the internal processing operation of MSM6562B-xx is started with a timing that does not affect
the LCD display, the busy status continues longer than the CPU cycle time.
Under the busy status (when the busy flag is set to "H"), the MSM6562B-xx does not execute any
instructions other than the busy flag read.
Therefore, it must be confirmed before an instruction code is input from the CPU that the busy
flag is set to "L".
(1) Display clear
When this instruction is executed, the LCD display is cleared.
The I/D value for the entry mode set instruction is set to 1 (increment). The S value for the
entry mode set instruction does not change.
When the cursor and blink are being displayed, the blinking and cursor position moves
to the left end of the LCD (the left end of the first line in the 2-line display mode).
Instruction code
(Note)
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
0
0
1
All DD RAM data goes to "20" (hex.), while the address counter (ADC) goes to
"00" (hex.) of the DD RAM address. The execution time when the OSC
oscillation frequency is 250kHz is 1.64ms (max.).
(2) Cursor home
When this instruction is executed, the cursor and blinking position move to the left end
of the LCD (to the left end of the first line in the 2-line display mode) when the cursor and
blink are being displayed.
When the display is in shift, the display returns to its original position before shifting.
Instruction code
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
0
1
X
X : Don't Care
(Note)
The address counter (ADC) goes to "00" (hex.) of the DD RAM address. The
execution time when the OSC oscillation frequency is 250kHz is 1.64ms (max.).
30/50
¡ Semiconductor
MSM6562B-xx
(3) Entry mode set
Instruction code
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
1
I/D
S
1 When the I/D is set, the 8-bit character code is written or read to and from the DD
RAM, the cursor and blink shift to the right by 1 character position (I/D = "H";
increment) or to the left by 1 character position (I/D = "L"; decrement).
The address counter (ADC) is incremented (I/D = "H") or decremented (I/D = "L") by
1 at this time. Even after the character pattern code is written or read to and from the
CG RAM, the address counter (ADC) is incremented (I/D = "H") or decremented (I/
D = "L") by 1.
2 When S = "H" is set, the character code is written to the DD RAM, and then the cursor
and blink stop and the entire display shifts to the left (I/D = "H") or to the right (I/D
= "L") by 1 character position.
When the character is read from the DD RAM when S = "H" is set, or when the
character pattern data is written or read to or from the CG RAM when S = "H" is set,
the entire display does not shift, but normal write/read is performed (the entire
display does not shift, but the cursor and blink shift to the right (I/D = "H") or to the
left (I/D = "L") by 1 character position).
When S = "L" is set, the display does not shift, but normal write/read is performed.
The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
(4) Display ON/OFF control
Instruction code
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
1
D
C
B
1 The D bit controls whether the character pattern is displayed or not.
When D is "H", this bit makes the character pattern display on the LCD.
When D is "L", this bit makes the display of the character pattern turned off. The cursor
and blink are also cancelled at this time.
(Note)
Different from the display clear, the DD RAM data is absolutely not
rewritten.
2 The cursor goes off when C = "L" and it is displayed when D = "H" and C = "H".
3 A blink is cancelled when B = "L" and a blink is executed when D = "H" and B = "H".
In the blink mode, all dots (including the cursor) and displaying character pattern
(including the cursor) are displayed alternately at 409.6ms (in 5 ¥ 7 dots character font)
or 563.2ms (in 5 ¥ 10 dots character font) when the OSC oscillation frequency is
250kHz.
The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
31/50
¡ Semiconductor
MSM6562B-xx
(5) Cursor/display shift
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
1
S/C
R/L
X
X
Instruction code
X : Don't Care
When S/C = "L" and R/L = "L", the cursor and blink position are shifted to the left by 1
character position (the ADC is then decremented by 1).
When S/C = "L" and R/L = "H", the cursor and blink position are shifted to the right by
1 character position (the ADC is then incremented by 1).
When S/C = "H" and R/L = "L", the entire display is shifted to the left by 1 character
position.
The cursor and blink position are also shifted together with the display (ADC
remains unchanged).
When S/C = "H" and R/L = "H", the entire display is shifted to the right by 1 character
position. The cursor and blink position are also shifted together with the display (ADC
remains unchanged).
In the 2-line display mode, the cursor and blink position are shifted from the first line to
the second line when the cursor is shifted to the right next to the fortieth digit (27; hex.)
in the first line. No such shifting is made in other cases.
When shifting the entire display, the display pattern, cursor and blink position are not
shifted between lines (from the first line to the second line or vice versa).
The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
(6) Function set
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
1
8B/4B
N
F
X
X
Instruction code
X : Don't Care
1 When 8B/4B = "H", the data input/output to and from the CPU is carried out in one
step using 8 bits of DB7 to DB0 . When 8B/4B = "L", the data input/output to and from
the CPU is carried out in two steps using 4 bits of DB7 to DB4.
2 The 2-line display mode of the LCD is selected when N = "H", while the 1-line display
mode is selected when N = "L".
3 The 5 ¥ 7 dots character font is slected when F = "L", while the 5 ¥ 10 dots character
font is selected when F = "H" and N = "L".
Do this initial setting prior to other instructions except the busy flag read after power is
applied to the MSM6562B-xx. After that, no initial setting other than setting of 8B/4B
value can be done.
F
Number of display
lines
L
L
1
L
H
1
H
L
2
H
H
2
N
Character font
Number of
COMMON signals
Duty ratio
Number of biases
5x7 dots
1/8
4
8
5x10 dots
1/11
4
11
5x7 dots
1/16
5
16
5x7 dots
1/16
5
16
The execution time, when the OSC oscillation frequency is 250kHz, is 40ms
32/50
¡ Semiconductor
MSM6562B-xx
(7) CG RAM address set
Instruction code
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
C5
C4
C3
C2
C1
C0
The CG RAM address is set to a value indicated by C5 to C0 (binary).
Once the CG RAM address is set, the CG RAM is specified until the DD RAM address is
set.
Write/read of the character pattern to and from the CPU begins with the current CG RAM
address indicated by C5 to C0.
The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
(8) DD RAM address set
Instruction code
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
D6
D5
D4
D3
D2
D1
D0
The DD RAM address is set to a value indicated by D6 to D0 (binary).
Once the DD RAM address is set, the DD RAM is specified until the CG RAM address is
set.
Write/read of the character code to and from the CPU begins with the current DD RAM
address indicated by D6 to D0.
In the 1-line mode (N="L"), D6 to D0 (binary) must be set to one of the values among "00"
to "4F" (hex.).
Likewise, in the 2-line mode (N="H"), D6 to D0 (binary) must be set to one of the values
among "00" to "27" (hex.) or "40" to "67" (hex.).
When any value other than the above is input, it is impossible to make a normal write/
read of character codes to and from the DD RAM.
The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
(9) DD RAM and CG RAM data write
Instruction code
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
0
E7
E6
E5
E4
E3
E2
E1
E0
E7 to E0 (binary) codes are written to the DD RAM or CG RAM. Once they are written,
the cursor and display move as described in "(5) Cursor/display shift". The execution
time, when the OSC oscillation frequency is 250kHz, is 40ms.
33/50
¡ Semiconductor
MSM6562B-xx
(10) Busy flag and address counter read (execution time = 1ms)
Instruction code
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
BF
O6
O5
O4
O3
O2
O1
O0
The busy flag (BF) is output by this instruction to indicate whether the MSM6562B is
engaged in internal operations (BF = "H") or not (BF = "L").
When BF = "H", no new instruction is accepted. It is therefore necessary to confirm BF =
"L" before inputting a new instruction.
When BF = "L", a correct address counter value is output. The address counter value must
match the DD RAM address or CG RAM address. The decision of whether it is a DD RAM
address or CG RAM address is made by the address previously set.
Since the address counter value when BF = "H" may be incremented or decremented by
1 during internal operations, it is not always a correct value.
(11) DD RAM and CG RAM data read
Instruction code
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
1
P7
P6
P5
P4
P3
P2
P1
P0
Character codes (P7 to P0) are read from the DD RAM, and character patterns (P7 to P0)
are read from the CG RAM.
Selection of DD RAM or CG RAM is decided by the address previously set.
After reading those data, the address counter (ADC) is incremented or decremented by
1 as set by the shift mode mentioned in item "(3) Entry mode setting".
The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
(Note)
Correct data is read if any of the following conditions are met:
1 When the DD RAM address or CG RAM address setting instruction is input
before inputting this instruction.
2 When the cursor/display shift instruction is input before inputting this
instruction in cases where case the character code from the DD RAM is read.
3 When reading the data after the second reading from RAM when read more
than once.
Correct data is not output in any other case.
The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
34/50
¡ Semiconductor
MSM6562B-xx
(12) Contrast adjusting data write
Instruction code
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
F4
F3
F2
F1
F0
The contrast adjusting data (F4 to F0) is written to the contrast register. After writing, the
voltage output to V5' is changed according to the data. When the contents of the contrast
register are "1F" (hex.), the VLCD becomes maximum. When they are "00" (hex.), it becomes
minimum.
(The contrast adjusting is valid only when the V5' and V5 pins are connected externally.)
VDD
V5' Pin voltage
The voltage between VDD and
V5' becomes VLCD.
V5' Pin voltage
0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 191A1B1C1D1E 1F
Contrast Data
The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
35/50
¡ Semiconductor
MSM6562B-xx
(13) Contrast adjusting data read
Instruction code
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
0
0
G4
G3
G2
G1
G0
The contents (G4 to G0) of the contrast register are read out.
The execution time, when the OSC oscillation frequency is 250kHz, is 40ms.
36/50
¡ Semiconductor
MSM6562B-xx
14. Interface with LCD and the Character Extension IC (MSM5259)
Display examples when setting the 5 ¥ 7 dots character font 1-line mode (Figure 1), 5 ¥ 10 dots
character font 1-line mode (Figure 2), and 5 ¥ 7 dots character font 2-line mode (Figs. 3 and 4)
through instructions are shown below.
When the 5 ¥ 7 dots character font is set in the 1-line display mode, COM9 to COM16 output the
COM signals for turning the display off.
Likewise, when the 5 ¥ 10 dots character font is set in the 1-line display mode, COM12 to COM16
output the COM signals for turning the display off.
The display examples show 20 characters (40 characters in Figure 3, 32 characters in Figure 4).
When the number of MSM5259s are increased according to the increase in the number of
characters, it is possible to display a maximum of 80 characters.
The bias voltage required to operate the LCD is made by a bias dividing resistor built in the
MSM6562B-xx and this voltage must be input to the MSM5259.
These bias examples are shown in Figures 5, 6, 7 and 8 and there are following two ways for
adjusting the bias voltage.
As shown in Figures 5 and 6, this method divides the bias by installing VR to V5. On the other
hand, as shown in Figures 7 and 8, this uses the built-in contrast adjusting circuit by connecting
V5 and V5'.
Figure 9 shows the connection of the MSM6562B-xx and the MSM5259 including the bias circuit.
(The example shows the display of 40 characters and 2 lines using the built-in contrast adjusting
circuit.)
In addition, the bias voltage must keep the potential relation of VDD > V1 > V2 ≥ V3 (= V3') > V4
> V5 ≥ VSS.
• In the case of 1-line 20-character display (5 ¥ 7 dot/font)
COM1
COM8
SEG1
SEG100
DO
CP
MSM6562B-xx
DF
L
Figure 1
37/50
¡ Semiconductor
MSM6562B-xx
• In the case of 1-line 20-character display (5 ¥ 10 dot/font)
COM1
COM11
SEG1
SEG100
DO
CP
MSM6562B-xx
DF
L
Figure 2
• In the case of 2-line 20 character display (5 ¥ 7 dot/font)
COM1
COM8
COM9
COM16
SEG1
SEG100
DO
CP
MSM6562B-xx
DF
L
Figure 3
38/50
¡ Semiconductor
MSM6562B-xx
• In the case of 2-line 16-character display (5 ¥ 7 dot/font)
COM1
COM8
COM9
COM16
SEG1
SEG80
SEG100
DO
CP
MSM6562B-xx
DF
L
Figure 4
39/50
¡ Semiconductor
MSM6562B-xx
• VLCD variable circuit using external VR
(1-line display mode, 1/4 bias)
• VLCD variable circuit using external VR
(2-line display mode, 1/5 bias)
VDD
VDD
VDD
VDD
V1
V1
V2
V2
MSM6562B-xx
VLCD
V3
MSM6562B-xx V3'
V3
V4
V4
V3'
VLCD
V5
V5
VR
V5'
V5'
VR
VSS
VSS
Figure 6
Figure 5
• Internal VLCD variable circuit
(1-line display mode, 1/4 bias)
• Internal VLCD variable circuit
(2-line display mode, 1/5 bias)
VDD
VDD
VDD
VDD
V1
V1
V2
V2
MSM6562B-xx
V3'
VLCD
MSM6562B-xx
V3'
V3
V3
V4
V4
V5
V5'
V5
V5'
Figure 7
Figure 8
VLCD
(VLCD : LCD driving voltage)
40/50
SEG1-100
DO
O1 - O40
O1 - O40
O1 - O20
MSM5259
MSM5259
MSM5259
DI1
CP
LOAD
DF
DO40
DO20
DI21
VDD VSS V2 V3 VEE
Figure 9
MSM6562B-xx
DI1
CP
LOAD
DF
DO20
DI21
VDD VSS V2 V3 VEE
CP
L
DF
VDD
VSS
V1
V2
V3'
V3
V4
V5
V5'
0V
DI1
CP
LOAD
DF
DO40
DO20
DI21
VDD VSS V2 V3 VEE
MSM6562B-xx
41/50
+5V
DO40
¡ Semiconductor
COM1-16
• Connection between MSM6562B-xx and MSM5259 (40 characters, 2 lines)
LCD
¡ Semiconductor
MSM6562B-xx
15. Instruction Initialization
(1) When data input/output to and from the CPU is carried out by 8 bits (DB0 to DB7) :
1
2
3
4
5
6
7
8
9
•
•
•
•
•
•
•
•
•
0
A
B
C
D
E
F
G
•
•
•
•
•
•
•
•
Turn on the power.
Wait for 15ms or more after VDD has reached 4.5V or more.
Set 8B/4B to "H" by the Function setting instruction.
Wait for 4.1ms or more.
Set 8B/4B to "H" by the Function setting instruction.
Wait for 100ms or more.
Set 8B/4B to "H" by the Function setting instruction.
Check the busy flag as No Busy.
Set 8B/4B to "H", the number of lines displayed on LCD (N) and character font (F)
by the Function setting instruction.
(After this, the number of lines displayed on LCD and character font cannot be
changed.)
Check No Busy.
Display off by the Display on/off control instruction.
Check No Busy.
Execute the Display clear instruction.
Check No Busy.
Execute the Entry mode setting instruction.
Check No Busy.
Initialization completed.
Example of Instruction Code for Steps 3, 5 and 7.
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
1
1
X
X
X
X
X : Don't Care
(2) When data input/output to and from the CPU is carried out by 4 bits (DB4 to DB7) :
1
2
3
4
5
6
7
8
9
0
A
•
•
•
•
•
•
•
•
•
•
•
Turn on the power.
Wait for 15ms or more after VDD has reached 4.5V or more.
Set 8B/4B to "H" by the Function setting instruction.
Wait for 4.1ms or more.
Set 8B/4B to "H" by the Function setting instruction.
Wait for 100ms or more.
Set 8B/4B to "H" by the Function setting instruction.
Check the busy flag as No Busy (or wait for 100ms or more).
Set 8B/4B to "L" by the Function setting instruction.
Wait for 100ms or more.
Set 8B/4B to "L", the number of lines displayed on LCD (N) and character font (F)
by the Function setting instruction.
(After this, the number of lines displayed on LCD and character font cannot be
changed.)
42/50
¡ Semiconductor
B
C
D
E
F
G
H
I
•
•
•
•
•
•
•
•
MSM6562B-xx
Check No Busy.
Display off by the Display on/off control instruction.
Check No Busy.
Execute the Display clear instruction.
Check No Busy.
Execute the Entry mode setting instruction.
Check No Busy.
Initialization completed.
Example of Instruction Code for Steps 3, 5 and 7.
RS1
RS0
R/W
DB7
DB6
DB5
DB4
1
0
0
0
0
1
1
Example of Instruction Code for Step 8.
RS1
RS0
R/W
DB7
DB6
DB5
DB4
1
0
1
BF
O6
O5
O4
Example of Instruction Code for Step 9.
RS1
RS0
R/W
DB7
DB6
DB5
DB4
1
0
0
0
0
1
0
Execute steps A to H with two-step accesses in 4 bits.
43/50
¡ Semiconductor
MSM6562B-xx
16. LCD Driving Waveforms
Figures 10, 11 and 12 show the LCD driving waveforms that consist of COM waveforms, SEG
waveform, DF (display frequency) signal and L (latch pulse) signal, in the duty of 1/8, 1/11 and
1/16 respectively.
The relation between duty and frame frequency is as follows:
(Note)
Duty
Frame frequency
1/8
78.1Hz
1/11
56.8Hz
1/16
78.1Hz
The OSC oscillation frequency is assumed to be 250kHz.
44/50
¡ Semiconductor
MSM6562B-xx
7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2
VDD
V1
V2,V3
V4
V5
COM1
1 frame
COM2
VDD
V1
V2,V3
V4
V5
COM8
VDD
V1
V2,V3
V4
V5
COM9
VDD
V1
V2,V3
V4
V5
COM16
VDD
V1
V2,V3
V4
V5
Display turning-off waveform
VDD
V1
V2,V3
V4
V5
SEG
(Output
example)
Display turning-on waveform
DF
L
Figure 10 LCD driving waveforms at 1/8 duty
45/50
¡ Semiconductor
MSM6562B-xx
10 11 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5
VDD
V1
V2,V3
V4
V5
COM1
1 frame
COM2
VDD
V1
V2,V3
V4
V5
COM11
VDD
V1
V2,V3
V4
V5
COM12
VDD
V1
V2,V3
V4
V5
COM16
VDD
V1
V2,V3
V4
V5
Display turning-off
waveform
VDD
V1
V2,V3
V4
V5
SEG
(Output
example)
Display turning-on
waveform
DF
L
Figure 11 LCD driving waveforms at 1/11 duty
46/50
¡ Semiconductor
MSM6562B-xx
15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
VDD
V1
V2
V3
V4
V5
COM1
1 frame
VDD
V1
V2
V3
V4
V5
COM2
VDD
V1
V2
V3
V4
V5
COM16
Display turning-off
waveform
VDD
V1
V2
V3
V4
V5
SEG
(Output
example)
Display turning-on
waveform
DF
L
Figure 12 LCD driving waveforms at 1/16 duty
47/50
¡ Semiconductor
MSM6562B-xx
PAD CONFIGURATION
Pad Layout
Chip Size : 7.12 ¥ 4.09 mm
Pad Size : 100 ¥ 100 mm
(PV Hole) 210 ¥ 100 mm (VDD, VSS)
Chip Thickness : 525 ± 20 mm
Y
122
76
75
123
X
149
1
Note :
47
48
The chip substrate should be
connected to VDD or left open.
Pad Coordinates
Pad
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol
T2
T3
VSS
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
SEG100
X (µm)
–3275
–3135
–2940
–2745
–2605
–2465
–2325
–2185
–2045
–1905
–1765
–1625
–1485
–1345
–1205
–1065
–925
–785
–645
–505
Y (µm)
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
Pad
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
X (µm)
–365
–225
–85
55
195
335
475
615
755
895
1035
1175
1315
1455
1595
1735
1875
2015
2155
2295
Y (µm)
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
48/50
¡ Semiconductor
MSM6562B-xx
Pad Coordinates (continued)
Pad
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Symbol
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
X (µm)
2435
2527
2715
2855
2995
3135
3275
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3415
3275
3135
2995
2855
2715
2575
2435
2295
2155
2015
Y (µm)
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1900
–1750
–1610
–1470
–1330
–1190
–1050
–910
–770
–630
–490
–350
–210
–70
70
210
350
490
630
770
910
1050
1190
1330
1470
1610
1750
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
Pad
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
Symbol
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
VDD
SHL0
SHL1
OSC1
OSCR
OSC2
V1
V2
V3'
V3
V4
X (µm)
1875
1735
1595
1455
1315
1175
1035
895
755
615
475
335
195
55
–85
–225
–365
–505
–645
–785
–925
–1065
–1205
–1345
–1485
–1625
–1765
–1905
–2045
–2185
–2325
–2465
–2605
–2745
–2940
–3135
–3275
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
Y (µm)
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1820
1680
1540
1400
1260
1120
980
840
49/50
¡ Semiconductor
MSM6562B-xx
Pad Coordinates (continued)
Pad
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
Symbol
V5
V5'
L
CP
DF
DO
RS0
RS1
R/W
E
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
T1
X (µm)
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
–3415
Y (µm)
700
560
420
280
140
0
–140
–280
–420
–560
–700
–840
–980
–1120
–1260
–1400
–1540
–1680
–1820
Pad
Symbol
X (µm)
Y (µm)
50/50