T F1456 TX Digital VGA 2100 MHz to 2950 MHz Datasheet Description Features The F1456 is a High Gain / High Linearity 2100 MHz to 2950 MHz TX Digital Variable Gain Amplifier used in transmitter applications. The F1456 TX DVGA provides 32.1 dB maximum gain +38 dBm OIP3 and 3.9 dB noise figure. Up to 31.5 dB control is achieved using the combination of a digital attenuator (DSA) and a KLINTM RF Digital Gain Amplifier. device uses a single 5 V supply and 215 mA of ICC. with gain step This This device is packaged in a 6 mm x 6 mm, 28-pin QFN with 50 Ω single-ended RF input and RF output impedances for ease of integration into the signal-path. Competitive Advantage In typical Base Stations, RF VGAs are used in the TX traffic paths to drive the transmit power amplifier. The F1456 TX DVGA offers very high reliability due to its construction from a monolithic silicon die in a QFN package. The F1456 is configured to provide an optimum balance of noise and linearity performance consisting of a KLINTM RF amplifier, digital step attenuator (DSA) and a PA driver amplifier. The KLINTM amplifier maintains the OIP3 and output P1dB performance over an extended attenuation range when compared to competitive devices. Broadband 2100 MHz to 2950 MHz 32.1 dB max gain 3.9 dB NF @ max gain (2650 MHz) 31.5 dB total gain control range, 0.5 dB step < 2 dB overshoot between gain transitions Maintains flat +21.5 dBm OP1dB for more than 13 dB gain adjustment range Maintains flat +38 dBm OIP3 for more than 15 dB gain adjustment range SPI interface for DSA control Single 5 V supply voltage ICC = 215 mA Up to +105 °C TCASE operating temperature 50 Ω input and output impedance Standby mode for power savings Pin compatible 700 MHz and 2100 MHz versions 6 mm x 6 mm, 28-pin QFN package Block Diagram Figure 1. Block Diagram Typical Applications KLIN Multi-mode, Multi-carrier Transmitters WiMAX and LTE Base Stations UMTS/WCDMA 3G Base Stations PHS/PAS Base Stations Public Safety Infrastructure Constant High LinearityTM KLINTM DVGA DSA PA Driver RF IN RF OUT SPI & Decoder 6 mm x 6 mm 28-pin Bias 3 Digital CTL © 2016 Integrated Device Technology, Inc 1 /STBY November 9, 2016 F1456 Datasheet Pin Assignments VCC GND NC NC NC GND NC 28 27 26 25 24 23 22 Figure 2. Pin Assignments for 6 mm x 6 mm x 0.9 mm QFN Package – Top View CSb 1 21 GND DATA 2 20 NC CLK 3 19 NC RSET 4 18 NC GND 5 17 GND RFIN 6 16 RFOUT GND 7 15 GND © 2016 Integrated Device Technology, Inc F1456 12 13 14 NC NC /STBY 10 NC 11 9 NC NC 8 NC Exposed Pad (GND) 2 November 9, 2016 F1456 Datasheet Pin Descriptions Table 1. Pin Descriptions Number Name 1 CSb Chip Select Input: 1.8 V or 3.3 V logic compatible. 2 DATA Data Input: 1.8 V or 3.3 V logic compatible. 3 CLK Clock Input: 1.8 V or 3.3 V logic compatible. RSET Connect 2.2 kΩ external resistor to GND to set amplifier bias. 5, 7, 15, 17, 21, 23, 27 GND Pins internally tied to exposed paddle. Connect to ground on PCB. 6 RFIN RF input internally matched to 50 Ω. Must use external DC block. 8, 9, 10, 11, 12, 13, 18, 19, 20, 22, 24, 25, 26 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended). 14 /STBY Standby pin. Device will be placed in standby mode when pin 14 is set to a logic low or when pin 14 is left floating (pulled low via internal high impedance to GND). In standby mode, SPI circuitry is still active. With a logic high applied to pin 14 the part is set to full operation mode. 16 RFOUT RF output internally matched to 50 Ω. Must use external DC block. 28 VCC 5 V Power Supply. Connect to Vcc and use bypass capacitors as close to the pin as possible. — EP Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the noted RF performance. 4 [a] Description a. External resistor on pin 4 used to optimize the overall device for DC current and linearity performance across the entire frequency band. © 2016 Integrated Device Technology, Inc 3 November 9, 2016 F1456 Datasheet Absolute Maximum Ratings Stresses above those listed below may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Symbol Minimum Maximum Units Vcc to GND VCC -0.5 5.5 V DATA, CSb, CLK, /STBY VCntrl -0.5 VCC V RSET IRSET +1.5 mA RFIN externally applied DC voltage VRFIN +1.4 +3.6 V VRFOUT VCC - 0.15 VCC + 0.15 V Pmax_in +12 dBm Pmax_out +26 dBm Pdiss 1.75 W Junction Temperature Tj 150 °C Storage Temperature Range Tst 150 °C 260 °C ElectroStatic Discharge – HBM (JEDEC/ESDA JS-001-2012) 2000 (Class 2) V ElectroStatic Discharge – CDM (JEDEC 22-C101F) 1000 (Class C3) V RFOUT externally applied DC voltage RF Input Power (RFIN) applied for 24 hours max. RF Output Power (RFOUT) present for 24 hours maximum [a] Continuous Power Dissipation [a] -65 Lead Temperature (soldering, 10s) a. Exposure to these maximum RF levels can result in significantly higher Icc current draw due to overdriving the amplifier stages. © 2016 Integrated Device Technology, Inc 4 November 9, 2016 F1456 Datasheet Recommended Operating Conditions Table 3. Recommended Operating Conditions Parameter Symbol Power Supply Voltage Operating Temperature Range RF Frequency Range [a] Condition Maximum Units 4.75 5.25 V Exposed Paddle -40 +105 °C High Linearity Bandwidth 2100 2700 Extended band for DPD 2700 2950 VCC TCASE FRF Maximum Operating Average RF Output Power Minimum Typical ZS = ZL = 50 14 MHz dBm RFIN Port Impedance ZRFI Single Ended 50 RFOUT Port Impedance ZRFO Single Ended 50 a. Device linearity is optimized over the range from 2100 MHz to 2700 MHz. Gain flatness is optimized up to 2950 MHz to account for systems with extended DPD bandwidth requirements. © 2016 Integrated Device Technology, Inc 5 November 9, 2016 F1456 Datasheet Electrical Characteristics - General See Typical Application Circuit. Unless otherwise stated, specifications apply when operated as a TX VGA, VCC = +5.0 V, FRF = 2.65 GHz, TCASE = +25 °C, /STBY = High, ZS = ZL = 50 , maximum gain setting. Evaluation Kit trace and connector losses are de-embedded. Table 4. Electrical Characteristics Parameter Symbol Condition Minimum Typical Maximum Units Logic Input High Threshold VIH JEDEC 1.8V or 3.3V logic 1.1 [a] VCC V Logic Input Low Threshold VIL JEDEC 1.8V or 3.3V logic -0.3 0.8 V Logic Current DC Current Standby Current Maximum Step Error (DNL) [over voltage, temperature and attenuation states] Maximum Absolute Error (INL) Gain Settling Time [c] SPI [d] Serial Clock Speed SPI -1 +1 ISTBY /STBY -10 +10 ICC ICC_STBY Standby Switching Time Gain Step Maximum Attenuator Glitching IIH, IIL TSTBY GSTEP ATTNG ERRORSTEP /STBY = Low 50% /STBY control to within 0.2 dB of the on state final gain value Least Significant Bit Any state to state transition FRF = 2.10 GHz FRF = 2.30 GHz FRF = 2.50 GHz FRF = 2.65 GHz FRF = 2.80 GHz FRF = 2.95 GHz 215 245 mA 1 2 mA 250 ns 0.5 2 dB dB -0.27 [b] -0.32 -0.36 -0.36 -0.36 -0.37 ERRORABS GST 50% of CSb to 10% / 90% RF +0.24 +0.26 +0.29 +0.31 +0.33 +0.36 0.8 200 FCLOCK µA dB dB ns 25 MHz CSb to CLK Setup Time TLS 5 ns CLK to Data Hold Time TH 5 ns CSb Trigger to CLK Setup Time TLC 5 ns a. b. c. d. Items in min/max columns in bold italics are Guaranteed by Test. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. Excludes SPI write time. SPI 3 wire bus (refer to serial Control Mode Timing diagram). © 2016 Integrated Device Technology, Inc 6 November 9, 2016 F1456 Datasheet Electrical Characteristics - RF See Typical Application Circuit. Unless otherwise stated, specifications apply when operated as a TX VGA, VCC = +5.0 V, FRF = 2.65 GHz, TCASE = +25 °C, /STBY = High, ZS = ZL = 50 , maximum gain setting. Evaluation Kit trace and connector losses are de-embedded. Table 5. Electrical Characteristics Parameter Symbol Condition Minimum Typical Maximum Units RF Input Return Loss RLRFIN 12 dB RF Output Return Loss RLRFOUT 12 dB Gain - Max Gain Setting GMAX Gain - Min Gain Setting GMIN Max attenuation Gain Flatness [c] GFLAT FRF = 2100 MHz to 2700 MHz any 400 MHz BW 0.5 0 dB attenuation 3.9 10 dB attenuation 5.9 20 dB attenuation 10.9 29.5 dB attenuation 19.5 31.5 dB attenuation 21.5 0 dB attenuation Pout = +7 dBm / tone 5 MHz tone separation 41.9 6 dB attenuation Pin = -21 dBm / tone 5 MHz tone separation 45.4 Noise Figure NF Output Third Order Intercept Point Output 1dB Compression Point OIP3 OP1dB 10 dB attenuation Pin = -21 dBm / tone 5 MHz tone separation 30.6 32.1 33.6 dB -1.5 0 1.5 dB 35.5 dB 43.6 dBm 20 dB attenuation Pin = -21 dBm / tone 5 MHz tone separation 36.1 29.5 dB attenuation Pin = -21 dBm / tone 5 MHz tone separation 27.4 31.5 dB attenuation Pin = -21 dBm / tone 5 MHz tone separation 25.7 0 dB attenuation 21.9 0 dB attenuation, TCASE = +105 °C 21.4 6 dB attenuation dB 20.9 dBm 21.9 a. Items in min/max columns in bold italics are Guaranteed by Test. b. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. c. Includes a positive slope feature over the noted RF range to compensate for typical system roll-off. © 2016 Integrated Device Technology, Inc 7 November 9, 2016 F1456 Datasheet Thermal Characteristics Table 6. Package Thermal Characteristics Parameter Symbol Value Units Junction to Ambient Thermal Resistance. θJA 40 °C/W Junction to Case Thermal Resistance. (Case is defined as the exposed paddle) θJC 4 °C/W Moisture Sensitivity Rating (Per J-STD-020) MSL 1 Typical Operating Conditions (TOC) Unless otherwise stated the typical operating graphs were measured under the following conditions: Vcc = 5.0 V ZL = ZS = 50 Ohms Single Ended FRF = 2.65 GHz TCASE = +25 °C /STBY = High 5 MHz Tone Spacing Gain setting = Maximum Gain All temperatures are referenced to the exposed paddle ACLR measurements used with a Basic LTE FDD Downlink 20 MHz TM1.2 Test signal EVM measurements used with a Basic LTE FDD Downlink 20 MHz TM3.1 Test signal Note TN1: Atten ≤ 4 dB Fixed Pout = 7 dBm per waveform or per tone, Atten > 4 dB Fixed Pin = -21 dBm per waveform or per tone Note TN2: Atten ≤ 7 dB Fixed Pout = 10.5 dBm per waveform or per tone, Atten > 7 dB Fixed Pin = -14.5 dBm per waveform or per tone Evaluation Kit traces and connector losses are de-embedded © 2016 Integrated Device Technology, Inc 8 November 9, 2016 F1456 Datasheet Typical Performance Characteristics Figure 3. Maximum Gain vs. Frequency over Temp and Voltage [Attn = 0.0 dB] Figure 4. Reverse Isolation vs. Frequency over Temp and Voltage [Attn = 0.0 dB] 35 0 34 -5 Reverse Isolation (dB) 33 Gain (dB) 32 31 30 29 28 27 26 -10 -40 C / +5.00 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V -20 -25 -30 -35 -40 -45 -40 C / +5.00 V -40 C / +5.25 V -50 +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V -55 -60 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1.0 1.5 2.0 Frequency (GHz) 3.0 3.5 4.0 Figure 6. Output Return Loss vs. Frequency over Temp and Voltage [Attn = 0.0 dB] 0 0 -5 -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V -40 C / +4.75 V -40 C / +5.00 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V -5 -10 Match (dB) Match (dB) 2.5 Frequency (GHz) Figure 5. Input Return Loss vs. Frequency over Temp and Voltage [Attn = 0.0 dB] -15 -20 -25 -40 C / +5.25 V -10 -15 -20 -25 -30 -30 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1.0 1.5 2.0 Frequency (GHz) 2.5 3.0 3.5 4.0 Frequency (GHz) Figure 7. Stability vs. Frequency over Temperature and Voltage [Attn = 0.0 dB] Figure 8. EvKit Insertion Loss vs. Frequency over Temperature 10 0.0 9 -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V -0.5 Insertion Loss (dB) 8 7 K Factor -40 C / +5.25 V -15 -40 C / +4.75 V 25 -40 C / +4.75 V 6 5 4 3 2 -1.0 -1.5 -2.0 -40 C -2.5 +25 C 1 +105 C 0 -3.0 0 1 2 3 4 5 6 7 8 9 0 Frequency (GHz) © 2016 Integrated Device Technology, Inc 1 2 3 4 5 6 7 8 9 Frequency (GHz) 9 November 9, 2016 F1456 Datasheet Typical Performance Characteristics Figure 10. Gain vs. Attenuation over Temperature and Voltage [2.65 GHz] 35 35 30 30 25 25 20 20 Gain (dB) Gain (dB) Figure 9. Gain vs. Frequency [+25 °C, All States] 15 10 15 10 5 5 0 0 -40 C / +4.75 V -40 C / +5.00 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V -5 -5 1.0 1.5 2.0 2.5 3.0 3.5 0 4.0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Attenuation (dB) Frequency (GHz) Figure 11. Worse Case Attenuator Absolute Accuracy vs. Freq [All parameters] Figure 12. Attenuator Absolute Accuracy vs. Atten over Temp and Voltage [2.65 GHz] 2.5 2.0 2.0 1.5 1.5 Error (dB) Error (dB) 1.0 Min 0.5 Max 0.0 -0.5 -40 C / +4.75 V -40 C / +5.00 V +25 C / +4.75 V +25 C / +5.00 V -40 C / +5.25 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V 1.0 0.5 0.0 -1.0 -1.5 -0.5 Statistically Based on 30 Devices For all Temperatures, Voltages, and Attenuation States. Standard Deviation is included. -2.0 -2.5 1.9 2.0 2.1 2.2 2.3 2.4 -1.0 2.5 2.6 2.7 2.8 2.9 3.0 3.1 0 3.2 2 4 6 8 Figure 13. Worse Case Step Accuracy vs. Freq [All parameters] Figure 14. Step Accuracy vs. Attenuation over Temperature and Voltage [2.65 GHz] 0.4 0.3 0.3 0.2 0.2 0.1 Error (dB) 0.4 Min Max 0.0 -0.1 Statistically Based on 30 Devices For all Temperatures, Voltages, and Attenuation States. Standard Deviation is included. -0.2 10 12 14 16 18 20 22 24 26 28 30 32 Attenuation (dB) Frequency (GHz) Error (dB) -40 C / +5.25 V -40 C / +4.75 V -40 C / +5.00 V +25 C / +4.75 V +25 C / +5.00 V -40 C / +5.25 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V 0.1 0.0 -0.1 -0.2 -0.3 -0.3 -0.4 -0.4 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 0 3.2 © 2016 Integrated Device Technology, Inc 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Attenuation (dB) Frequency (GHz) 10 November 9, 2016 F1456 Datasheet Typical Performance Characteristics Figure 15. Input Return Loss vs. Frequency [+25 °C, All states] Figure 16. Input Return Loss vs. Attenuation over Temperature and Voltage [2.65 GHz] 0 -5 -5 -10 -10 Match (dB) Match (dB) 0 -15 -20 -40 C / +4.75 V -40 C / +5.00 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V -15 -20 -25 -25 -30 -30 1.0 1.5 2.0 2.5 3.0 3.5 0 4.0 2 4 6 8 Figure 17. Output Return Loss vs. Frequency [+25 °C, All states] Figure 18. Output Return Loss vs. Attenuation over Temperature and Voltage [2.65 GHz] 0 0 -5 -5 -10 -10 Match (dB) Match (dB) 10 12 14 16 18 20 22 24 26 28 30 32 Attenuation (dB) Frequency (GHz) -15 -20 -40 C / +4.75 V -40 C / +5.00 V +25 C / +4.75 V +25 C / +5.00 V -40 C / +5.25 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V -15 -20 -25 -25 -30 -30 1.0 1.5 2.0 2.5 3.0 3.5 0 4.0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Attenuation (dB) Frequency (GHz) Figure 19. Reverse Isolation vs. Frequency [+25 °C, All states] Figure 20. Reverse Isolation vs. Attenuation over Temperature and Voltage [2.65 GHz] -20 0 -5 -25 -10 -30 Reverse Isolation (dB) Reverse Isolation (dB) -40 C / +5.25 V -35 -40 -45 -50 -55 -60 -40 C / +4.75 V -40 C / +5.00 V +25 C / +4.75 V +25 C / +5.00 V -40 C / +5.25 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -65 -70 -70 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 Frequency (GHz) © 2016 Integrated Device Technology, Inc 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Attenuation (dB) 11 November 9, 2016 F1456 Datasheet Typical Performance Characteristics Figure 22. Output IP3 vs. Attn over Temp and Voltage [2.3 GHz] (Test Note TN2) 50 50 45 45 40 40 OIP3 (dBm) OIP3 (dBm) Figure 21. Output IP3 vs. Attn over Temp and Voltage [2.3 GHz] (Test Note TN1) 35 30 25 35 30 25 -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V 20 20 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 2 4 6 8 Attenuator State (dB) Figure 24. Output IP3 vs. Attn over Temp and Voltage [2.5 GHz] (Test Note TN2) 50 50 45 45 40 40 OIP3 (dBm) OIP3 (dBm) Figure 23. Output IP3 vs. Attn over Temp and Voltage [2.5 GHz] (Test Note TN1) 35 30 25 35 30 25 -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V 20 20 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 2 4 6 8 Attenuator State (dB) Figure 26. Output IP3 vs. Attn over Temp and Voltage [2.65 GHz] (Test Note TN2) 50 45 45 40 40 OIP3 (dBm) 50 35 30 25 -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V 10 12 14 16 18 20 22 24 26 28 30 32 Attenuator State (dB) Figure 25. Output IP3 vs. Attn over Temp and Voltage [2.65 GHz] (Test Note TN1) OIP3 (dBm) 10 12 14 16 18 20 22 24 26 28 30 32 Attenuator State (dB) 35 30 25 20 -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V 20 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 Attenuator State (dB) © 2016 Integrated Device Technology, Inc 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Attenuator State (dB) 12 November 9, 2016 F1456 Datasheet Typical Performance Characteristics Figure 27. Output IP3 vs. Frequency over Temperature and Voltage [Attn = 0.0 dB] Figure 28. Output P1dB vs. Attenuation over Temperature and Voltage [2.3 GHz] 25 48 24 46 23 Output P1dB (dBm) 50 OIP3 (dBm) 44 42 40 38 36 34 32 -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V 22 21 20 19 18 17 -40 C / +4.75 V / +25 C / +4.75 V / +105 C / +4.75 V / 16 30 -40 C / +5.25 V / +25 C / +5.25 V / +105 C / +5.25 V / 15 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 0 1 2 Frequency (GHz) 24 23 23 Output P1dB (dBm) 25 24 22 21 20 19 18 16 4 5 6 7 8 9 Figure 30. Output P1dB vs. Attenuation over Temp and Voltage [2.5 GHz] 25 17 3 Attenuation State (dB) Figure 29. Output P1dB vs. Frequency over Temp and Voltage [Attn = 0.0 dB] Output P1dB (dBm) -40 C / +5.00 V / +25 C / +5.00 V / +105 C / +5.00 V / -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V 22 21 20 19 18 17 -40 C / +4.75 V / +25 C / +4.75 V / +105 C / +4.75 V / 16 -40 C / +5.00 V / +25 C / +5.00 V / +105 C / +5.00 V / -40 C / +5.25 V / +25 C / +5.25 V / +105 C / +5.25 V / 15 15 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 0 1 2 Frequency (GHz) 3 4 5 6 7 8 9 Attenuation State (dB) Figure 31. Output P1dB vs. Attenuation over Temp and Voltage [2.65 GHz] 25 24 Output P1dB (dBm) 23 22 21 20 19 18 17 -40 C / +4.75 V / +25 C / +4.75 V / +105 C / +4.75 V / 16 -40 C / +5.00 V / +25 C / +5.00 V / +105 C / +5.00 V / -40 C / +5.25 V / +25 C / +5.25 V / +105 C / +5.25 V / 15 0 1 2 3 4 5 6 7 8 9 Attenuation State (dB) © 2016 Integrated Device Technology, Inc 13 November 9, 2016 F1456 Datasheet Typical Performance Characteristics Figure 32. Gain Compression vs. Pout over Temperature and Voltage [2.3 GHz] -40 C / +4.75 V +25 C / +4.75 V +105 C / +4.75 V -40 C / +5.00 V +25 C / +5.00 V +105 C / +5.00 V 5 -40 C / +5.25 V +25 C / +5.25 V +105 C / +5.25 V Phase Compression (degrees) Power Compression (dB) 0.5 Figure 33. Phase Compression vs. Pout over Temperature and Voltage [2.3 GHz] 0.0 -0.5 -1.0 -1.5 -2.0 -40 C / +4.75 V +25 C / +4.75 V +105 C / +4.75 V 0 -5 -10 -15 -20 13 14 15 16 17 18 19 20 21 22 23 24 25 12 13 14 15 Output Power (dBm) -40 C / +4.75 V +25 C / +4.75 V +105 C / +4.75 V -40 C / +5.00 V +25 C / +5.00 V +105 C / +5.00 V 17 18 19 20 21 22 23 24 25 Figure 35. Phase Compression vs. Pout over Temperature and Voltage [2.5 GHz] 5 -40 C / +5.25 V +25 C / +5.25 V +105 C / +5.25 V Phase Compression (degrees) 0.5 16 Output Power (dBm) Figure 34. Gain Compression vs. Pout over Temperature and Voltage [2.5 GHz] Power Compression (dB) -40 C / +5.25 V +25 C / +5.25 V +105 C / +5.25 V -25 12 0.0 -0.5 -1.0 -1.5 -2.0 -40 C / +4.75 V +25 C / +4.75 V +105 C / +4.75 V 0 -40 C / +5.00 V +25 C / +5.00 V +105 C / +5.00 V -40 C / +5.25 V +25 C / +5.25 V +105 C / +5.25 V -5 -10 -15 -20 -25 12 13 14 15 16 17 18 19 20 21 22 23 24 25 12 13 14 15 Output Power (dBm) -40 C / +4.75 V +25 C / +4.75 V +105 C / +4.75 V -40 C / +5.00 V +25 C / +5.00 V +105 C / +5.00 V 17 18 19 20 21 22 23 24 25 Figure 37. Phase Compression vs. Pout over Temperature and Voltage [2.65 GHz] 5 -40 C / +5.25 V +25 C / +5.25 V +105 C / +5.25 V Phase Compression (degrees) 0.5 16 Output Power (dBm) Figure 36. Gain Compression vs. Pout over Temperature and Voltage [2.65 GHz] Power Compression (dB) -40 C / +5.00 V +25 C / +5.00 V +105 C / +5.00 V 0.0 -0.5 -1.0 -1.5 -2.0 -40 C / +4.75 V +25 C / +4.75 V +105 C / +4.75 V 0 -40 C / +5.00 V +25 C / +5.00 V +105 C / +5.00 V -40 C / +5.25 V +25 C / +5.25 V +105 C / +5.25 V -5 -10 -15 -20 -25 12 13 14 15 16 17 18 19 20 21 22 23 24 25 12 Output Power (dBm) © 2016 Integrated Device Technology, Inc 13 14 15 16 17 18 19 20 21 22 23 24 25 Output Power (dBm) 14 November 9, 2016 F1456 Datasheet Typical Performance Characteristics Figure 38. Noise Figure vs. Frequency over Temperature and Voltage [Attn = 0.0 dB] Figure 39. Noise Figure vs. Attenuation over Temperature and Voltage [2.3 GHz] 6 25 5 Noise Figure (dB) 20 Noise Figure (dB) 4 3 2 1 -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V 15 10 5 0 0 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 0 2 4 6 8 Frequency (GHz) Figure 40. Noise Figure vs. Attenuation over Temperature and Voltage [2.5 GHz] Figure 41. Noise Figure vs. Attenuation over Temperature and Voltage [2.65 GHz] 25 25 -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V -40 C / +4.75 V -40 C / +5.00 V -40 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +25 C / +4.75 V +25 C / +5.00 V +25 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V +105 C / +4.75 V +105 C / +5.00 V +105 C / +5.25 V 20 Noise Figure (dB) 20 Noise Figure (dB) 10 12 14 16 18 20 22 24 26 28 30 32 Attenuation State (dB) 15 10 5 15 10 5 0 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 Attenuation State (dB) © 2016 Integrated Device Technology, Inc 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Attenuation State (dB) 15 November 9, 2016 F1456 Datasheet Typical Performance Characteristics Figure 43. Switching Speed 31.5 to 0.0 dB 0.6 2.0 0.6 0.5 1.8 0.5 0.4 1.6 0.4 0.3 1.4 0.3 1.4 0.2 1.2 0.2 1.2 0.1 1.0 0.1 1.0 0.0 0.8 0.0 0.8 -0.1 0.6 -0.1 0.6 -0.2 0.4 -0.2 0.4 -0.3 0.2 -0.3 0.2 -0.4 0.0 -0.4 0.0 -0.2 -0.5 -0.2 -0.4 -0.6 -0.2 RF -0.5 -0.6 -0.2 Trigger -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 2.0 1.8 RF Trigger 1.6 -0.4 -0.1 0.0 Time (us) 0.1 0.2 0.3 0.4 0.5 0.6 Time (us) Figure 44. Switching Speed Standby Mode to Full Operation Mode Figure 45. Switching Speed Full Operation Mode to Standby Mode 3.2 0.6 2.9 0.5 0.4 2.6 0.4 2.6 0.3 2.3 0.3 2.3 0.2 2.0 0.2 2.0 0.1 1.7 0.1 1.7 0.0 1.4 0.0 1.4 -0.1 1.1 -0.1 1.1 -0.2 0.8 -0.2 0.8 -0.3 0.5 -0.3 0.5 -0.4 0.2 -0.4 0.2 -0.5 -0.1 -0.5 -0.1 -0.6 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 -0.6 -0.10 -0.4 0.25 Trigger -0.05 0.00 0.05 0.10 0.15 0.20 2.9 -0.4 0.25 Time (us) Time (us) © 2016 Integrated Device Technology, Inc 3.2 RF Trigger Volage (V) Trigger RF Voltage (V) 0.5 RF Trigger Volage (V) 0.6 RF Voltage (V) Trigger Volage (V) RF Voltage (V) Trigger Volage (V) RF Voltage (V) Figure 42. Switching Speed 0.0 to 31.5 dB 16 November 9, 2016 F1456 Datasheet Typical Performance Characteristics Figure 46. ACLR vs. Attn [2.3 GHz] -50 -52 Figure 47. EVM (RMS) vs. Attn [2.3 GHz] ACLR_low [TN1] ACLR_high [TN1] ACLR_low [TN2] ACLR_high [TN2] System ACLR Low System ACLR High 0.60 0.55 0.50 -54 0.45 0.40 -58 EVM (%) ACLR (dB) -56 -60 -62 0.35 0.30 0.25 0.20 -64 0.15 -66 0.10 -68 0.05 -70 0.00 0 2 4 6 8 10 12 14 16 EVM_rms [TN1] EVM_rms [TN2] System EVM 0 2 4 Attenuation Setting (dB) Figure 48. ACLR vs. Attn [2.5 GHz] -50 -52 ACLR_low [TN1] ACLR_high [TN1] ACLR_low [TN2] ACLR_high [TN2] 10 12 14 16 System ACLR Low System ACLR High 14 16 14 16 0.60 0.55 0.50 0.45 -56 0.40 -58 EVM (%) ACLR (dB) 8 Figure 49. EVM (RMS) vs. Attn [2.5 GHz] -54 -60 -62 0.35 0.30 0.25 0.20 -64 0.15 -66 0.10 -68 0.05 -70 0.00 0 2 4 6 8 10 12 14 16 EVM_rms [TN1] EVM_rms [TN2] System EVM 0 2 4 Attenuation Setting (dB) -50 -52 6 8 10 12 Attenuation Setting (dB) Figure 50. ACLR vs. Attn [2.65 GHz] Figure 51. EVM (RMS) vs. Attn [2.65GHz] ACLR_low [TN1] ACLR_high [TN1] ACLR_low [TN2] ACLR_high [TN2] System ACLR Low System ACLR High 0.60 0.55 0.50 -54 0.45 EVM (%) -56 ACLR (dB) 6 Attenuation Setting (dB) -58 -60 -62 0.40 0.35 0.30 0.25 0.20 -64 0.15 -66 0.10 -68 0.05 -70 0.00 0 2 4 6 8 10 12 14 16 EVM_rms [TN2] System EVM 0 Attenuation Setting (dB) © 2016 Integrated Device Technology, Inc EVM_rms [TN1] 2 4 6 8 10 12 F1456 Attenuation Setting (dB) 17 November 9, 2016 F1456 Datasheet Serial Port Interface Serial data is formatted as a 6-bit word clocking data in MSB first. Table 7. Attenuation Word Truth Table Control Bit D5 D4 D3 D2 D1 D0 Attenuator Setting 1 1 1 1 1 1 0.0 dB 1 1 1 1 1 0 0.5 dB 1 1 1 1 0 1 1.0 dB 1 1 1 0 1 1 2.0 dB 1 1 0 1 1 1 4.0 dB 1 0 1 1 1 1 8.0 dB 0 1 1 1 1 1 16.0 dB 0 0 0 0 0 0 31.5 dB Figure 52. Serial Register Timing Diagram CLK (pin 3) DATA (pin 2) D5 D0 Attenuation CSb (pin 1) Clock in MSB first Increasing time © 2016 Integrated Device Technology, Inc 18 November 9, 2016 F1456 Datasheet Figure 53. SPI Timing Diagram TH TP TS TLC TCH TCL CLK DATA TLS CSb TL TL Table 8. SPI Timing Diagram Values for Figure 53 Parameter Symbol CLK Frequency FC CLK High Duration Time TCH 20 ns CLK Low Duration Time TCL 20 ns DATA to CLK Setup Time TS 5 ns CLK Period [a] TP 40 ns CLK to DATA Hold Time TH 5 ns CSb to CLK Setup Time TLS 5 ns TL 10 ns TLC 5 ns CSb Trigger Pulse Width CSb Trigger to CLK Setup Time [b] Test Condition Min Typ Max Units 25 MHz a. (TCH + TCL) ≥ 1/FC b. Once all desired DATA is clocked in, TLC represents the time a CSb high needs to occur before any subsequent CLK signals. Table 9. Standby Truth Table /STBY (pin 14) 0V Vcc © 2016 Integrated Device Technology, Inc Condition Amplifier OFF with SPI powered ON Full operation 19 November 9, 2016 F1456 Datasheet Application Information The F1456 has been optimized for use in high performance RF applications from 2100 MHz to 2950 MHz. The device maintains good performance outside of the optimized band as shown by the Typical Performance Characteristics. Power Up Attenuation Setting When the part is initially powered up, the default VGA setting is the 31.5 dB [000000] attenuation state. Chip Select (CSb) When CSb is set to logic high, the CLK input is disabled. When CSb is set to logic low, the CLK input is enabled and the DATA word can be programmed into the shift registers. The programmed word is then latched into the F1456 on the CSb rising edge (refer Figure 53). The operation of the SPI bus in independent of the /STBY pin setting (see Standby Mode section below). Standby Mode (/STBY) The F1456 has a power down feature for power savings which is on Pin 14. For normal operation pin 14 must be set to a logic high. When a logic low is applied to pin 14 the amplifier is placed in standby mode. The Standby mode is a high isolation state. The level of this isolation is not specified and is dependent on the device and attenuation state. In Standby mode the SPI bus is operational and the device attenuation setting can be programmed. Therefore, the device will present the desired attenuation when it is enabled. Power Supplies A common VCC power supply should be used for all power supply pins. To minimize noise and fast transients de-coupling capacitors to all supply pins. Supply noise can degrade noise figure and fast transients can trigger ESD clamps causing them to fail. Supply voltage change or transients should have a slew rate smaller than 1 V / 20 µs. In addition, all control pins should remain at 0 V (± 0.3 V) while the supply voltage ramps or while it returns to zero. Control Pin Interface If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit at the input of each control pin is recommended. This applies to SPI and control pins 1, 2, 3 and 14 as shown below. Note the recommended resistor and capacitor values do not necessarily match the EV kit BOM for the case of poor control signal integrity. For multiple devices driven by a single control line, the component values will need to be adjusted accordingly so as not to load down the control line. CSb 22 23 24 25 26 27 28 Figure 54. Control Pin Interface for Signal Integrity 1 k 2 pF 21 1 DATA 1 k 20 2 F1456 2 pF 19 3 Exposed Pad (GND) 4 2 pF 18 /STBY 14 15 13 7 12 16 11 6 9 17 8 5 10 CLK 1 k 1 k 2 pF © 2016 Integrated Device Technology, Inc 20 November 9, 2016 F1456 Datasheet Evaluation Kit Picture Figure 55. Top View Figure 56. Bottom View © 2016 Integrated Device Technology, Inc 21 November 9, 2016 F1456 Datasheet Evaluation Kit / Applications Circuit Figure 57. Electrical Schematic VCC3 R7 3 GND R1 B5 4 5 1 VCC C12 22 GND NC 23 24 NC 25 NC 26 NC 29 27 NC GND GND 19 18 17 J2 GND GND B1 C8 C9 B2 B3 R11 R12 RFOUT C15 C16 VCC2 R3 B4 VCC R13 R14 C10 VCC VCC J4 C11 R16 GND3 2 R15 15 14 13 8 R2 /STBY RFOUT NC RFIN 16 1 2 3 GND2 F1456 RSET 20 1 2 3 J3 NC NC 7 C14 VCC1 VCC CLK 21 C2 6 C13 NC 12 RFIN C1 DATA NC J1 GND 11 R10 2 GND4 CSb NC DATA R6 1 10 R9 R5 GND C5 VCC NC CLK C6 C7 VCC R8 CSb 9 7 5 3 1 NC J7 8 6 4 2 EP U1 R4 C3 28 C4 GND1 J5 J6 Not All Components are used. Please check the Bill of Material (BOM) table. © 2016 Integrated Device Technology, Inc 22 November 9, 2016 F1456 Datasheet Table 10. Bill of Material (BOM) Part Reference QTY Description Manufacturer Part # Manufacturer C1, C2 2 22 pF ±5%, 50V, C0G Ceramic Capacitor (0402) GRM1555C1H220J MURATA C3 1 100 nF ±10%, 16V, X7R Ceramic Capacitor (0402) GRM155R71C104K MURATA C4 1 1000 pF ±5%, 50V, C0G Ceramic Capacitor (0402) GRM1555C1H102J MURATA C5, C6, C7 3 2 pF ±0.1pF, 50V, C0G Ceramic Capacitor (0402) GRM1555C1H2R0B MURATA C12 1 10 uF ±20%, 16V, X6S Ceramic Capacitor (0603) GRM188C81C106M MURATA R1 1 2.2 kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF2201X PANASONIC R4 - R7 4 0 Ω Resistor (0402) ERJ-2GE0R00X PANASONIC R8 - R10, R16 4 1 kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF1001X PANASONIC J4 1 CONN HEADER VERT SGL 2 X 1 POS GOLD 961102-6404-AR 3M J6 1 CONN HEADER VERT SGL 3 X 1 POS GOLD 961103-6404-AR 3M J7 1 CONN HEADER VERT DBL 4 X 2 POS GOLD 67997-108HLF FCI J1, J2 2 Edge Launch SMA (0.375 inch pitch ground, tab) 142-0701-851 Emerson Johnson J3 1 Edge Launch SMA (0.250 inch pitch ground, round) 142-0711-821 Emerson Johnson U1 1 VGA AMP F1456NKGK IDT C8 - C11, C13 - C16, R2, R3, R11 - R15, J5 DNP 1 © 2016 Integrated Device Technology, Inc Printed Circuit Board 23 F145X EVKIT REV 02 November 9, 2016 F1456 Datasheet Evaluation Kit Operation Standby Connector J6 allows the F1456 to be put into the standby mode. Connecting J6 pin 2 (the center pin) to Vcc the amplifier will be placed in normal operating mode. To put the F1456 into standby mode for very low power consumption ground J6 pin 2 (the center pin). If J6 pin 2 (the center pin) is left open, then the F1456 will default to the standby mode. Figure 58. Image of J6 connector for Standby mode control Serial Programming Pins Connector J7 pins 1, 2, 4, 6, 8 are ground. Pin 3 is DATA, pin 5 is Clock (CLK), pin 7 is Chip Select (CSB). Figure 59. Image of J7 connector for SPI © 2016 Integrated Device Technology, Inc 24 November 9, 2016 F1456 Datasheet Package Drawings Figure 60. Package Outline Drawing NKG28 PSC-4606 TOP VIEW BOTTOM VIEW SIDE VIEW © 2016 Integrated Device Technology, Inc 25 November 9, 2016 F1456 Datasheet Recommended Land Pattern Figure 61. Recommended Land Pattern © 2016 Integrated Device Technology, Inc 26 November 9, 2016 F1456 Datasheet Ordering Information Orderable Part Number Package MSL Rating Shipping Packaging Temperature F1456NKGK 6 x 6 x 0.9 mm QFPN 1 Tray -40° to +105°C F1456NKGK8 6 x 6 x 0.9 mm QFPN 1 Tape and Reel -40° to +105°C F1456EVBK Evaluation Board F1456EVSK Evaluation Solution Marking Diagram 1. Line 2 and 3 are the part number. 2. Line 4 “ZW” is Assembly Stepping. 3. Line 4 “yyww = 1629 has two digits for the year and week that the part was assembled. 4. Line 4 “L” denotes Assembly Site. 5. Line 5 “Q54E042PY” is the Assembly Lot number © 2016 Integrated Device Technology, Inc 27 November 9, 2016 F1456 Datasheet Revision History Revision O Revision Date Description of Change 2016-November 09 Initial Release Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products an d/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the s ame way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar dev ices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved © 2016 Integrated Device Technology, Inc 28 November 9, 2016