Ordering number : ENA2055A LC87F0N04A CMOS IC 4.5K-byte FROM and 128-byte RAM integrated http://onsemi.com 8-bit 1-chip Microcontroller Overview The LC87F0N04A is an 8-bit microcomputer that, integrates on a single chip a number of hardware features such as 4.5K-byte flash ROM, 128-byte RAM, 16-bit timers/counters, a 16-bit timer, an asynchronous/synchronous SIO interface, motor control 10-bit PWM, two Analog Comparators, a 6-channel AD converter, a system clock frequency divider, an internal reset and an interrupt feature. Package Dimensions 5.2 16 9 6.4 Flash ROM 4608 8 bits (4096 + 512-byte) Capable of On-board programming with wide range (2.8 to 5.5V) of voltage source. Block-erasable in 128 byte units Writable in 2-byte units unit : mm (typ) 3178B 4.4 Features 0.5 RAM 128 9 bits 1 0.15 0.22 1.5max (0.33) 0.1 (1.3) Package Form SSOP16 (225mil) : Lead-/Halogen-free type 8 0.65 SANYO : SSOP16(225mil) * This product is licensed from Silicon Storage Technology, Inc. (USA). Semiconductor Components Industries, LLC, 2013 February, 2013 Ver.1.01 22713HK/53012HKIM 20120426-S00003 No.A2055-1/19 LC87F0N04A Minimum Bus Cycle 100.0ns (10MHz at VDD=2.8V to 5.5V) Note: The bus cycle time here refers to the ROM read speed. Ports Normal withstand voltage I/O ports Ports I/O direction can be designated in 1 bit units Reset pin On-chip Debugger pin Power pins 12(P00 to P03, P1n) 1 (RES) 1 (OWP0) 2 (VSS, VDD) Timers Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) 2 channels Mode 1: 8-bit PWM with an 8-bit prescaler 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) Base timer 1) The clock is selectable from system clock, and timer 0 prescaler output. 2) Interrupts are programmable in 5 different time schemes SIO SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) AD Converter: 10 bits/8 bits 6 channels 10/8 bits AD converter resolution selectable Auto start function (It links an interrupt factor of Motor control PWM) Remote Control Receiver Circuit (sharing pins with P11, INT3) Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Clock Output Function Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the system clock. Analog Comparator 2 channels Analog comparator Interrupt. Analog comparator reference selectable (External input / Programmable on-chip voltage reference). The voltage reference has 2 ranges with 16-level voltage levels in each range. Rang1: CMP1vref1= (CMP1vref-Register<3:0> + 1 )/16 VDD 0.64 CMP2vref2= (CMP2vref-Register<3:0> + 1 )/16 VDD 0.64 Rang2: CMP1vref1= (CMP1vref-Register<3:0> + 1 )/64 VDD 0.64 CMP2vref2= (CMP2vref-Register<3:0> + 1 )/64 VDD 0.64 MCPWM2: Motor control 10bits PWM with Full-Bridge Dead time is programmable. Forced stop is possible by the output of the analog comparator and the INT terminals. Edge-aligned / center-aligned selectable. No.A2055-2/19 LC87F0N04A Watchdog Timer Can generate the internal reset signal on a timer overflow monitored by the WDT-dedicated low-speed RC oscillation clock (30kHz). Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/HOLD mode. Interrupts 14 sources, 9 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level 1 00003H X or L INT0 Interrupt Source 2 0000BH X or L INT1 3 00013H H or L INT2/T0L 4 0001BH H or L INT3/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L - 8 0003BH H or L SIO1/PWM 9 00043H H or L ADC 10 0004BH H or L CMP1/CMP2 Priority levels X > H > L Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 64levels (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions 16 bits 8 bits (5 tCYC execution time) 24 bits 16 bits (12 tCYC execution time) 16 bits 8 bits (8 tCYC execution time) 24 bits 16 bits (12 tCYC execution time) Oscillation Circuits Internal oscillation circuits Medium-speed RC oscillation circuit : For system clock (1MHz) High-speed RC oscillation circuit : For system clock (10MHz) Low-speed RC oscillation circuit : For watch dog timer (30kHz) System Clock Divider Function Can run on low current. The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and 76.8s (at a main clock rate of 10MHz). Internal Reset Function Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and 4.35V) through option configuration. Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use / disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V, 4.28V). No.A2055-3/19 LC87F0N04A Standby Function ● HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are three ways of resetting the HALT mode. (1) Setting the reset pin to the low level (2) System resetting by watchdog timer or low-voltage detection (3) Occurrence of an interrupt ● HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The RC oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) System resetting by watchdog timer or low-voltage detection (3) Having an interrupt source established at either INT0, INT1, INT2 * INT0 and INT1 HOLD mode reset is available only when level detection is set. On-chip Debugger Supports software debugging with the IC mounted on the target board. Data Security Function (flash versions only) Protects the program data stored in flash memory from unauthorized read or copy. Note: This data security function does not necessarily provide absolute data security. Development Tools On-chip-debugger : TCB87 TypeC + LC87F0N04A Programming Boards Package Programming boards SSOP16(225mil) W87F0NS Flash ROM Programmer Maker Model Single AF9709/AF9709B/AF9709C Programmer (Including Ando Electric Co., Ltd. models) AF9723/AF9723B(Main body) Flash Support Group, Inc. (FSG) Gang Programmer (Including Ando Electric Co., Ltd. models) AF9833(Unit) (Including Ando Electric Co., Ltd. models) Sanyo Supported version Rev 03.28 or later Device 87F008SU (3B247) - - - - Single/Gang SKK / SKK Type B Programmer (SanyoFWS) 1.07 or later Gang SKK-4G Chip Data Version Programmer (SanyoFWS) Application Version 2.40 or later Application Version In-circuit/Gang SKK-DBG Type C 1.07 or later Programmer (SanyoFWS) Chip Data Version LC87F0N04 2.40 or later For information about AF-Series: Flash Support Group, Inc. TEL: +81-53-459-1050 E-mail: [email protected] No.A2055-4/19 LC87F0N04A Pin Assignment RES VSS1 OWP0 VDD1 P10/AN0/INT2/T0LCP/T0IN P11/AN1/INT3/T0HCP/T0IN/CMP1IB(+) P12/AN2/CMP1IA(-) P13/SO1/AN3/CMP1O 1 2 3 4 5 6 7 8 LC87F0N04A 16 15 14 13 12 11 10 9 P03/MP2OT1 P02/MP2OT1/CKO P01/MP2OT0 P00/MP2OT0 P17/AN5/T1PWMH/BUZ/CMP2IA(-) P16/AN4/T1PWML/CMP2IB(+) P15/SCK1/INT1/T0HCP/CMP2O P14/SI1/SB1/INT0/T0LCP Top view SANYO: SSOP16(225mil) “Lead-/Halogen-free Type” SSOP16 NAME SSOP16 NAME 1 RES 9 P14/SI1/SB1/INT0/T0LCP 2 VSS1 10 P15/SCK1/INT1/T0HCP/CMP2O 3 OWP0 11 P16/AN4/T1PWML/CMP2IB(+) 4 VDD1 12 P17/AN5/T1PWMH/CMP2IA(-)/BUZ 5 P10/AN0/INT2/T0LCP/T0IN 13 P00/MP2OT0 6 P11/AN1/INT3/T0HCP/T0IN/CMP1IB(+) 14 P01/MP2OT0 7 P12/AN2/CMP1IA(-) 15 P02/MP2OT1/CKO 8 P13/SO1/AN3/CMP1O 16 P03/MP2OT1 No.A2055-5/19 LC87F0N04A System Block Diagram Interrupt control IR PLA Flash ROM Standby control Clock MRC generator RC PC RES Reset circuit (LVD/POR) Reset control WDT ACC B register C register Bus interface SIO1 Port 0 Timer 0 Port 1 Timer 1 ADC Base timer INT0-2 INT3 (Noise filter) MCPWM2 Comparator ALU PSW RAR RAM Stack pointer On-chip debugger No.A2055-6/19 LC87F0N04A Pin Description Pin Name I/O Description Option VSS1 - - power supply pin VDD1 - + power supply pin No No Port 0 I/O 4-bit I/O port Yes I/O specifiable in 1 bit units P00 to P03 Pull-up resistors can be turned on and off in 1 bit units. Pin functions P00: MP2OT0(PWM output) P01: MP2OT0 (PWM output) P02: MP2OT1(PWM output) / System clock output P03: MP2OT1 (PWM output) Port 1 I/O 8-bit I/O port Yes I/O specifiable in 1 bit units P10 to P17 Pull-up resistors can be turned on and off in 1 bit units. Pin functions P10: AN0(AD converter input) / INT2 input / HOLD reset input / timer 0 event input / timer 0L capture input P11: AN1(AD converter input) / INT3 input (with noise filter) / timer 0 event input / timer 0H capture input / CMP1(+) input P12: AN2(AD converter input) / CMP1(-) input P13: SIO1 data output / AN3(AD converter input) / CMP1 output P14: SIO1 data input / bus I/O / INT0 input / HOLD reset input / timer 0L capture input P15: SIO1 clock I/O / INT1 input / HOLD reset input / timer 0H capture input / CMP2 output P16: Timer 1PWML output / CMP2(+) input / AN4(AD converter input) P17: Timer 1PWMH output / beeper output / CMP2(-) input / AN5(AD converter input) Interrupt acknowledge type Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising & H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable Falling OWP0 I/O On-chip debugger (exclusive pin) No RES I/O External reset Input / internal reset output No No.A2055-7/19 LC87F0N04A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P03 Option selected in units of Option type 1 bit P10 to P17 Output type Pull-up resistor 1 CMOS Programmable 2 Nch-open drain Programmable User Option Table Option Name Port output type Option to be Applied on Flash-ROM Version Option Selected in Units of P00 to P03 1 bit Option Selection CMOS Nch-open drain P10 to P17 1 bit Detect function - Detect level - 7-level Power-On reset level - 8-level CMOS Nch-open drain Low-voltage detection reset function Power-on reset Enable:Use Disable:Not Used function Recommended Unused Pin Connections Recommended Unused Pin Connections Port Name Board Software P00 to P03 Open Output low P10 to P17 Open Output low On-chip Debugger Pin Connection Requirements Install and connect a limiting resistor (100) to the on-chip debugger dedicated pin (OWP0) on the user board and pull the pin down (100k). It is recommended to install a dedicated connector to accept the cable to the debugging tool (TCB87 Type C). The connector must accommodate three lines, i.e., VSS1, OWP0, and VDD1. VDD1 OWP0 VSS1 VDD Connector for the debugging tool 100 GND 100k No.A2055-8/19 LC87F0N04A Absolute Maximum Ratings at Ta = 25C, VSS1 =0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Maximum supply VDD max VDD1 Input voltage VI RES Input/output VIO Ports 0, 1 IOPH(1) Ports 0, 1 voltage voltage Low level output current High level output current Peak output Mean output IOMH(1) Ports 0, 1 current typ max unit -0.3 +6.5 -0.3 VDD+0.3 -0.3 VDD+0.3 V CMOS output select Per 1 applicable pin current min -10 CMOS output select Per 1 applicable pin -7.5 (Note 1-1) Total output IOAH(1) Ports 0 Total of all applicable pins -25 current IOAH(2) Ports 1 Total of all applicable pins -25 Peak output IOPL(1) Ports0, 1 Per 1 applicable pin mA current Mean output 20 IOML(1) Ports 0, 1 Per 1 applicable pin current 15 (Note 1-1) Total output IOAL(1) Ports 0 Total of all applicable pins 45 current IOAL(2) Ports 1 Total of all applicable pins 45 Pdmax SSOP16 Ta=-40 to +85C Power dissipation Package with thermal 238 resistance board mW (Note 1-2) Operating ambient Topr temperature Storage ambient temperature Tstg -40 +85 -55 +125 C Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: 76.1114.31.6tmm, glass epoxy) is used. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. No.A2055-9/19 LC87F0N04A Allowable Operating Conditions at Ta = -40C to +85C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Operating VDD(1) VDD1 0.291s tCYC 200s VHD VDD1 RAM and register contents sustaining typ 2.8 supply voltage Memory min sustained in HOLD mode. max unit 5.5 2.0 supply voltage High level VIH(1) Ports 1 input voltage VIH(2) Low level Ports 0 VIH(3) RES VIL(1) Ports 1 input voltage VIL(2) VIL(3) Instruction Ports 0 RES 2.8 to 5.5 0.3VDD 2.8 to 5.5 0.3VDD 2.8 to 5.5 0.75VDD 4.0 to 5.5 VSS 2.8 to 4.0 VSS 4.0 to 5.5 VSS 2.8 to 4.0 VSS 0.2VDD 2.8 to 5.5 VSS 0.25VDD 2.8 to 5.5 0.291 200 s 2.8 to 5.5 9.7 10.0 10.3 MHz 2.8 to 5.5 9.75 10.0 10.25 MHz 2.8 to 5.5 0.5 1.0 2.0 MHz 2.8 to 5.5 15 30 60 kHz VDD +0.7 VDD +0.7 V VDD 0.1VDD +0.4 0.2VDD 0.15VDD +0.4 tCYC cycle time (Note 2-1) Oscillation FmMRC(1) frequency range Internal High-speed RC oscillation. (Note 2-2) FmMRC(2) Internal High-speed RC oscillation. Ta=0C to 85C (Note 2-2) FmRC Internal Medium-speed RC oscillation FmSRC Internal Slow-speed RC oscillation for watchdog timer. Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmMRC at a division ratio of 1/1 and 6/FmMRC at a division ratio of 1/2. Note 2-2: When switching the system clock, allow an oscillation stabilization time of 100s or longer after the High-speed RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state. No.A2055-10/19 LC87F0N04A Electrical Characteristics at Ta = -40C to +85C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High level input IIH(1) current Ports 0, 1 Output disabled RES Pull-up resistor off VIN=VDD (Including output Tr's off leakage min typ 2.8 to 5.5 max 1 current) Low level input IIL(1) current Ports 0, 1 Output disabled RES Pull-up resistor off VIN=VSS (Including output Tr's off leakage unit A 2.8 to 5.5 -1 current) High level output VOH(1) voltage VOH(2) Ports 0, 1 IOH=-1mA 4.5 to 5.5 VDD-1 IOH=-0.35mA 2.8 to 5.5 VDD-0.4 VOH(3) Port0 IOH=-6mA 4.5 to 5.5 VDD-1 VOH(4) (Note 3-1) IOH=-1.4mA 2.8 to 5.5 VDD-0.4 Low level output VOL(1) Ports 0, 1 voltage VOL(2) Pull-up resistance Rpu(1) Ports 0, 1 IOL=10mA 4.5 to 5.5 IOL=1.4mA 2.8 to 5.5 VOH=0.9VDD 4.5 to 5.5 15 35 80 2.8 to 4.5 18 50 230 Rpu(2) Hysteresis voltage VHYS V 1.5 0.4 k P10(INT2), P11(INT3), 2.8 to 5.5 P14,P15, 0.1 VDD V RES Pin capacitance CP All pins For pins other than that under test: VIN=VSS f=1MHz 2.8 to 5.5 10 pF Ta=25C Note 3-1: When Ports0 selected MCPWM2. No.A2055-11/19 LC87F0N04A SIO1 Serial I/O Characteristics at Ta = -40C to +85C, VSS1 = 0V (Note 4) Input clock Frequency tSCK(3) Low level tSCKL(3) Specification Pin/ Symbol Conditions Remarks SCK1(P15) VDD[V] See Fig. 4. tCYC tSCK(4) SCK1(P15) CMOS output selected tSCKL(4) 2 2.8 to 5.5 pulse width High level 1/2 tSCK tSCKH(4) 1/2 pulse width Serial input Data setup time tsDI(2) SB1(P14), SI1(P14) Must be specified with respect to rising edge of SIOCLK. Data hold time unit 1 See Fig. 4. Low level max 1 tSCKH(3) Frequency typ 2 2.8 to 5.5 pulse width High level min pulse width Output clock Serial clock Parameter See Fig. 4. thDI(2) 0.05 2.8 to 5.5 0.05 tdD0(4) SO1(P13), Must be specified with SB1(P14) respect to falling edge of Serial output Output delay time s SIOCLK. Must be specified as the time to the beginning of (1/2)tCYC 2.8 to 5.5 +0.08 output state change in open drain output mode. See Fig. 4. Note 4: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta = -40C to +85C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High/low level tPIH(1) INT0(P14), Interrupt source flag can be set. pulse width tPIL(1) INT1(P15), Event inputs for timer 0 or 1 are INT2(P10) INT3(P11) when noise Interrupt source flag can be set. tPIL(2) filter time constant is Event inputs for timer 0 are INT3(P11) when noise Interrupt source flag can be set. tPIL(3) filter time constant is Event inputs for timer 0 are INT3(P11) when noise Interrupt source flag can be set. tPIL(4) filter time constant is Event inputs for timer 0 are tPIL(5) RES 1 2.8 to 5.5 2 max unit tCYC 2.8 to 5.5 64 2.8 to 5.5 256 2.8 to 5.5 200 enabled. tPIH(4) 1/128 2.8 to 5.5 enabled. tPIH(3) 1/32 typ enabled. tPIH(2) 1/1 min enabled. Resetting is enabled. µs No.A2055-12/19 LC87F0N04A AD Converter Characteristics at VSS1 = 0V <10bits AD Converter Mode/Ta = -40C to +85C > Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Resolution N AN0(P10) to Absolute ET AN3(P13) Conversion time AN5(P17) TCAD max See Conversion time calculation VAIN voltage range unit 10 bit 4 2.8 to 5.5 formulas. (Note 6-2) Analog input typ 2.8 to 5.5 (Note 6-1) AN4(P16) accuracy min 4.0 to 5.5 7.8 65.6 2.8 to 5.5 15 65.6 2.8 to 5.5 VSS VDD Analog port IAINH VAIN=VDD 2.8 to 5.5 input current IAINL VAIN=VSS 2.8 to 5.5 LSB s V 1 A -1 <8bits AD Converter Mode/Ta = -40C to +85C > Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Resolution N AN0(P10) to Absolute ET AN3(P13) Conversion time (Note 6-1) AN5(P17) TCAD See Conversion time calculation formulas. (Note 6-2) Analog input typ max VAIN voltage range unit 8 bit 1.5 2.8 to 5.5 AN4(P16) accuracy min 2.8 to 5.5 4.0 to 5.5 2.85 25.0 2.8 to 5.5 5.5 25.0 2.8 to 5.5 VSS VDD Analog port IAINH VAIN=VDD 2.8 to 5.5 input current IAINL VAIN=VSS 2.8 to 5.5 LSB s V 1 A -1 Conversion time calculation formulas: 10bits AD Converter Mode: TCAD(Conversion time) = ((40/(AD division ratio))+2)(1/3)tCYC 8bits AD Converter Mode: TCAD(Conversion time) = ((28/(AD division ratio))+2)(1/3)tCYC External Operating supply oscillation voltage range (FmMRC) (VDD) 10MHz AD division ratio System division ratio Cycle time (SYSDIV) (tCYC) 4.0V to 5.5V 1/1 2.8V to 5.5V 1/1 AD conversion time (ADDIV) (TCAD) 10bit AD 8bit AD 10bit AD 8bit AD 300ns 1/2 1/1 8.5s 2.9s 300ns 1/4 1/2 17s 5.8s Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: The first AD conversion is performed in the 10-bit AD conversion mode after a system reset. The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 10-bit conversion mode. No.A2055-13/19 LC87F0N04A Power-on Reset (POR) Characteristics at Ta = -40C to +85C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage POR release PORRL voltage Detection min typ max Select from option. 1.67V 1.55 1.67 1.79 (Note 7-1) 1.97V 1.85 1.97 2.09 2.07V 1.95 2.07 2.19 2.37V 2.25 2.37 2.49 2.57V 2.45 2.57 2.69 2.87V 2.75 2.87 2.99 3.86V 3.73 3.86 3.99 4.35V 4.21 4.35 4.49 0.7 0.95 unit V See Fig. 6. POUKS voltage (Note 7-2) unknown state Power supply Power supply rise PORIS rise time 100 time from 0V to 1.6V. ms Note7-1: The POR release level can be selected out of 8 levels only when the LVD reset function is disabled. Note7-2: POR is in an unknown state before transistors start operation. Low Voltage Detection Reset (LVD) Characteristics at Ta = -40C to +85C, VSS1=0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage LVD reset voltage LVDET (Note 8-2) Select from option. (Note 8-1) (Note 8-3) See Fig. 7. LVD hysteresys LVHYS width Detection voltage LVUKS unknown state Low voltage detection minimum width min max 1.91V 1.81 1.91 2.01 2.01V 1.91 2.01 2.11 2.31V 2.21 2.31 2.41 2.51V 2.41 2.51 2.61 2.81V 2.71 2.81 2.91 3.79V 3.69 3.79 3.89 4.28V 4.18 4.28 4.38 1.91V 55 2.01V 55 2.31V 55 2.51V 55 2.81V 60 3.79V 65 4.28V 65 unit V mV See Fig. 7. (Note 8-4) TLVDW typ 0.7 0.95 V LVDET-0.5V See Fig. 8. 0.2 ms (Reply sensitivity) Note8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled. Note8-2: LVD reset voltage specification values do not include hysteresis voltage. Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note8-4: LVD is in an unknown state before transistors start operation. No.A2055-14/19 LC87F0N04A Comparator Characteristics at Ta = -40C to +85C, VSS1 = 0V Parameter Input common- Symbol VCMIN Specification Pin/ Conditions Remarks VDD[V] min typ max unit P12(CMP1IA), mode voltage P11(CMP1IB), (Note9-1) P17(CMP2IA), 2.8 to 5.5 VDD -1.5V VSS V P16(CMP2IB) Offset voltage VCPOFF(1) P12(CMP1IA), Input common-mode voltage range P11(CMP1IB), CMP1 minus input P17(CMP2IA), = CMP1IA P16(CMP2IB) CMP2 minus input P12(CMP1IA), Input common-mode voltage range P11(CMP1IB), CMP1 minus input 2.8 to 5.5 20 mV 2.8 to 5.5 40 mV = CMP2IA VCPOFF(2) P17(CMP2IA), = CMP1vref (Note9-2) P16(CMP2IB) CMP2 minus input P13(CMP1O), Input common-mode voltage range P15(CMP2O) Input amplitude=100mV, = CMP2 vref (Note9-2) CMP response speed tCRT Over drive=50mV CMP1 minus input 2.8 to 5.5 200 ns = CMP1IA CMP2 minus input = CMP2IA Note9-1: When VDD=5V, input voltage is effective from 0 to 3.5V. Note9-2: Rang1: CMP1vref1= (CMP1vref-Register<3:0> + 1)/16 VDD 0.64 CMP2vref2= (CMP2vref-Register<3:0> + 1)/16 VDD 0.64 Rang2: CMP1vref1= (CMP1vref-Register<3:0> + 1)/64 VDD 0.64 CMP2vref2= (CMP2vref-Register<3:0> + 1)/64 VDD 0.64 *: Range1/Range2 setting by a register is common to comparators 1 and 2. No.A2055-15/19 LC87F0N04A Consumption Current Characteristics at Ta = -40C to +85C, VSS1 = 0V Parameter Normal mode Symbol IDDOP(1) Specification Pin/ Conditions Remarks VDD1 VDD[V] min typ max unit Internal Medium speed RC oscillation stopped. consumption System clock set to internal current 2.8 to 5.5 3.4 4.8 High speed RC oscillation(10MHz). (Note 10-1) 1/1 frequency division ratio (Note 10-2) mA Internal High speed RC oscillation stopped. IDDOP(2) System clock set to internal Medium speed RC oscillation. 2.8 to 5.5 0.2 0.4 2.8 to 5.5 1.6 2.3 1/2 frequency division ratio HALT mode IDDHALT(1) VDD1 HALT mode Internal Medium speed RC oscillation consumption stopped. current System clock set to internal (Note 10-1) High speed RC oscillation(10MHz). (Note 10-2) 1/1 frequency division ratio IDDHALT(2) VDD1 mA HALT mode Internal High speed RC oscillation stopped. System clock set to internal Medium speed 2.8 to 5.5 0.10 0.19 2.8 to 5.5 0.03 32 RC oscillation. 1/2 frequency division ratio HOLD mode IDDHOLD(1) VDD1 HOLD mode consumption current (Note 10-1) IDDHOLD(2) A HOLD mode LVD option selected (Note 10-2) 2.8 to 5.5 3 35 (Note 10-3) Note10-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note10-2: The consumption current values do not include operational current of LVD function if not specified. Note10-3: The amplifier / comparator circuit operates in the HOLD mode. F-ROM Programming Characteristics at Ta = +10C to +55C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Onboard IDDFW(1) VDD1 min typ max unit Only current of the Flash block. programming 2.8 to 5.5 5 10 mA 20 30 ms 40 60 s current Programming tFW(1) Erasing time time tFW(2) Programming time 2.8 to 5.5 0.5VDD Figure 1 AC Timing Measurement Point No.A2055-16/19 LC87F0N04A VDD Operating VDD lower limit 0V Power supply Reset time tPIL(5) RES Internal Medium speed RC oscillation Operating mode Unpredictable Reset Instruction execution Reset Time Figure 2 Reset Time VDD RRES RES CRES Note: External circuits for reset may vary depending on the usage of POR and LVD. Please refer to the user’s manual for more information. Figure 3 Reset Circuit No.A2055-17/19 LC87F0N04A SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 tSCK tSCKL tSCKH SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 4 Serial I/O Output Waveforms tPIL tPIH Figure 5 Pulse Input Timing Signal Waveform (a) POR release voltage (PORRL) (b) VDD Reset period 100s or longer Reset period Unknown-state (POUKS) RES Figure 6 Waveform observed when only POR is used (LVD not used) (RESET pin: Pull-up resistor RRES only) The POR function generates a reset only when power is turned on starting at the VSS level. No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an external reset circuit. A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100s or longer. No.A2055-18/19 LC87F0N04A LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD LVD reset voltage (LVDET) Reset period Reset period Reset period Unknown-state (LVUKS) RES Figure 7 Waveform observed when both POR and LVD functions are used (RESET pin: Pull-up resistor RRES only) Resets are generated both when power is turned on and when the power level lowers. A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level. VDD LVD release voltage LVD reset voltage LVDET-0.5V TLVDW VSS Figure 8 Low voltage detection minimum width (Example of momentary power loss/Voltage variation waveform) ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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