DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter General Description DA9213-A and DA9214-A are PMICs optimized for the supply of CPUs, GPUs, and DDR memory rails in automotive in-vehicle infotainment systems, Advanced Driver Assistance Systems (ADAS), navigation and telematics applications. The fast transient response (10 A/µs) and load regulation are optimized for the latest generation of multi core application processors. DA9213-A operates as a single four-phase buck converter delivering up to 20 A output current. DA9214-A integrates two dual-phase buck converters, capable of delivering 2x10 A output current. Each buck regulates a programmable output voltage in the range 0.3 - 1.57 V. With an external resistor divider the output voltage can be set to any voltage between 1.57 V and 4.3 V. The input voltage range of 2.8 – 5.5 V makes it suited for a wide variety of low voltage systems, including all Li-Ion battery powered applications. To guarantee the highest accuracy and to support multiple PCB routing scenarios without loss of performance, a remote sensing capability is implemented in both the DA9213-A and DA9214-A. The power devices are fully integrated, so no external FETs or Schottky diodes are needed. A programmable soft start-up can be enabled, which limits the inrush current from the input node and secures a slope controlled activation of the rail. The Dynamic Voltage Control (DVC) supports adaptive adjustment of the supply voltage depending 2 on the processor load, either via direct register writes through the communication interface (I C or SPI compatible) or via an input pin. DA9213-A and DA9214-A feature integrated over-temperature and over-current protection for increased system reliability without the need for external sensing components. The safety feature set is completed by a VDDIO under voltage lockout. 2 The configurable I C address selection via GPI allows multiple instances of DA9213-A and DA9214A to be placed in an application sharing the same communication interface with different addresses. Key Features ■ ■ ■ ■ ■ ■ ■ ■ 2.8 V to 5.5 V input voltage 1x 20 A DA9213-A 2x 10 A DA9214-A 3 MHz nominal switching frequency Max inductor height 1.2 mm ±1 % accuracy (static) ±3 % accuracy (dynamic) 0.3 V to 1.57 V output voltage 1.57 to 4.3 V with resistor divider ■ ■ ■ ■ ■ ■ ■ ■ ■ Dynamic Voltage Control (DVC) Automatic phase shedding Integrated power switches Remote sensing at point of load 2 I C/SPI compatible interface Adjustable soft start -40 to +105 ºC temperature range AEC-Q100 grade 2 qualified Package 66 VFBGA 0.5 mm pitch Applications ■ In-car infotainment ■ Navigation and telematics ■ Automotive display clusters ■ Mobile computing ■ Advanced Driver Assistance Systems (ADAS) ■ Industrial embedded systems Datasheet CFR0011-120-00 Revision 1.4 1 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter VDD_B2 VDD_B1 VDD_A2 VSYS VDD_A1 System Diagrams 1µF 4x 10µF FBAP IC_EN GPI0 GPI GPI1 GPI GPIO2 GPIO DIGITAL CORE OTP MEMORY 4x 0.22µH CTRL + DRIVE BIAS SUPERV OSC REGISTER SPACE PoL 4x 47µF nIRQ OUT VDDIO DVS 2/4-WIRE INTERFACE IN FBAN FBBP FBBN nCS/GPI4 GPIO IN SCL/SK SO/GPIO3 GPIO VSS_ANA SDA/SI 100nF 1µF VDD_B2 4x 10µF Buck A IC_EN GPI0 GPI GPI1 GPI GPIO2 VDD_B1 VDD_A2 VSYS VDD_A1 Figure 1: DA9213-A System Diagram GPIO DIGITAL CORE OTP MEMORY CTRL + DRIVE PoL 2x 47µF BIAS SUPERV OSC REGISTER SPACE DVS DAC Buck B nIRQ FBAP 2x 0.22µH OUT FBAN FBBP 2x 0.22µH VDDIO 2/4-WIRE INTERFACE 100nF CTRL + DRIVE PoL IN GPIO IN VSS_ANA GPIO 2x 47µF DVS DAC nCS/GPI4 SO/GPIO3 SCL/SK SDA/SI FBBN Figure 2: DA9214-A System Diagram Datasheet CFR0011-120-00 Revision 1.4 2 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Contents General Description ............................................................................................................................ 1 Key Features ........................................................................................................................................ 1 Applications ......................................................................................................................................... 1 System Diagrams ................................................................................................................................ 2 Contents ............................................................................................................................................... 3 Figures .................................................................................................................................................. 5 Tables ................................................................................................................................................... 5 1 Terms and Definitions ................................................................................................................... 6 2 Pinout ............................................................................................................................................. 7 3 Absolute Maximum Ratings ....................................................................................................... 10 4 Recommended Operating Conditions ....................................................................................... 10 5 Electrical Characteristics ........................................................................................................... 11 6 Efficiency Measurements ........................................................................................................... 18 7 Functional Description ............................................................................................................... 20 7.1 DC-DC Buck Converter ....................................................................................................... 23 7.1.1 Switching Frequency ........................................................................................... 24 7.1.2 Operation Modes and Phase Selection ............................................................... 24 7.1.3 Output Voltage Selection ..................................................................................... 24 7.1.4 Soft Start Up ........................................................................................................ 25 7.1.5 Current Limit ........................................................................................................ 25 7.1.6 Variable VOUT above 1.57 V .............................................................................. 25 7.2 Ports Description ................................................................................................................. 27 7.2.1 VDDIO.................................................................................................................. 27 7.2.2 IC_EN .................................................................................................................. 27 7.2.3 nIRQ..................................................................................................................... 27 7.2.4 GPIO Extender .................................................................................................... 27 7.3 Operating Modes ................................................................................................................. 30 7.3.1 ON Mode ............................................................................................................. 30 7.3.2 OFF Mode ............................................................................................................ 30 7.4 Control Interfaces ................................................................................................................ 30 7.4.1 4-WIRE Communication ...................................................................................... 30 7.4.2 2-WIRE Communication ...................................................................................... 35 7.4.3 Details of the 2-WIRE Control Bus Protocol ........................................................ 36 7.5 Internal Temperature Supervision ....................................................................................... 39 8 Register Definitions .................................................................................................................... 40 8.1 Register Map ....................................................................................................................... 40 8.2 Register Definitions ............................................................................................................. 42 8.2.1 Register Page Control ......................................................................................... 42 8.2.2 Register Page 0 ................................................................................................... 42 Datasheet CFR0011-120-00 Revision 1.4 3 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 8.2.3 8.2.4 9 8.2.2.1 System Control and Event ............................................................... 42 8.2.2.2 GPIO Control ................................................................................... 44 8.2.2.3 Regulators Control ........................................................................... 46 Register Page 1 ................................................................................................... 47 8.2.3.1 Regulators Settings ......................................................................... 47 Register Page 2 ................................................................................................... 52 8.2.4.1 Interface and OTP Settings (shared with DA9063) ......................... 52 8.2.4.2 OTP Fusing Registers ..................................................................... 53 8.2.4.3 Application Configuration Settings ................................................... 54 Application Information .............................................................................................................. 57 9.1 Capacitor Selection ............................................................................................................. 57 9.2 Inductor Selection ............................................................................................................... 58 10 Package Information ................................................................................................................... 59 10.1 Package Outlines ................................................................................................................ 59 11 Ordering Information .................................................................................................................. 60 Revision History ................................................................................................................................ 61 Datasheet CFR0011-120-00 Revision 1.4 4 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Figures Figure 1: DA9213-A System Diagram ................................................................................................... 2 Figure 2: DA9214-A System Diagram ................................................................................................... 2 Figure 3: Connection Diagram .............................................................................................................. 7 Figure 4: 66 VFBGA Power Derating Curve........................................................................................ 11 Figure 5: 2-WIRE Bus Timing .............................................................................................................. 16 Figure 6: 4-WIRE Bus Timing .............................................................................................................. 17 Figure 7: DA9213-A Efficiency vs Load, VOUT = 1.0 V, 0-20 A ......................................................... 18 Figure 8: DA9213-A Efficiency vs Load, VIN = 3.6 V, 0-20 A ............................................................. 18 Figure 9: DA9214-A Efficiency vs Load, VOUT = 1.0 V, 0-10 A ......................................................... 19 Figure 10: DA9214-A Efficiency vs Load, VIN = 3.6 V, 0-10 A ........................................................... 19 Figure 11: Interface of DA9213-A/14-A with DA9063 and the Host Processor................................... 20 Figure 12: Typical Application of DA9213-A........................................................................................ 21 Figure 13: Typical Application of DA9214-A........................................................................................ 22 Figure 14: Concept of Control of the Buck’s Output Voltage .............................................................. 25 Figure 15: Resistive Divider from VOUT to FBAN .............................................................................. 26 Figure 16: GPIO Principle of Operation (example paths) .................................................................... 29 Figure 17: Schematic of 4-WIRE and 2-WIRE Power Manager Bus .................................................. 31 Figure 18: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘0’) ............. 32 Figure 19: 4-WIRE Host Write and Read Timing (nCS_POL= ‘0’, CPOL = ‘0’, CPHA = ‘1’) .............. 33 Figure 20: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘0’) ............. 33 Figure 21: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘1’) ............. 34 Figure 22: Timing of 2-WIRE START and STOP Condition ................................................................ 36 Figure 23: 2-WIRE Byte Write (SDA Line) .......................................................................................... 37 Figure 24: Examples of 2-WIRE Byte Read (SDA Line) ..................................................................... 37 Figure 25: Examples of 2-WIRE Page Read (SDA Line) .................................................................... 37 Figure 26: 2-WIRE Page Write (SDA Line) ......................................................................................... 38 Figure 27: 2-WIRE Repeated Write (SDA Line) .................................................................................. 38 Figure 28: DA9213-A/14-A VFBGA Package Outline Drawing ........................................................... 59 Tables Table 1: Pin Description ........................................................................................................................ 8 Table 2: Pin Type Definition .................................................................................................................. 9 Table 3: Absolute Maximum Ratings ................................................................................................... 10 Table 4: Recommended Operating Conditions ................................................................................... 10 Table 5: Buck Converters Characteristics ........................................................................................... 11 Table 6: IC Performance and Supervision .......................................................................................... 14 Table 7: Digital I/O Characteristics ...................................................................................................... 14 Table 8: 2-WIRE Control Bus Characteristics ..................................................................................... 15 Table 9: 4-WIRE Control Bus Characteristics ..................................................................................... 17 Table 10: 4-WIRE Clock Configurations .............................................................................................. 31 Table 11: 4-WIRE Interface Summary ................................................................................................ 35 Table 12: Over-Temperature Thresholds ............................................................................................ 39 Table 13: Register Map ....................................................................................................................... 41 Table 14: Recommended Capacitor Types ......................................................................................... 57 Table 15: Recommended Inductor Types ........................................................................................... 58 Table 16: Ordering Information ........................................................................................................... 60 Datasheet CFR0011-120-00 Revision 1.4 5 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 1 Terms and Definitions AP CPU DDR DVC FET GPI GPU IC OTP PCB PMIC POL PWM Datasheet CFR0011-120-00 Application Processor Central Processing Unit Dual Data Rate Dynamic Voltage Control Field Effect Transistor General Purpose Input Graphic Processing Unit Integrated Circuit One Time Programmable memory Printed Circuit Board Power Management Integrated Circuit Point Of Load Pulse Width Modulation Revision 1.4 6 of 62 08-May-2017 © 2017 Dialog Semiconductor Datasheet CFR0011-120-00 1 2 VDD_A2 2 VSS_A2 LX_A2 VDD_A2 1 D E Revision 1.4 7 of 62 F LX_A2 VSS_A2 VSS_A1 VSS_A1 LX_A1 VDD_A1 C LX_A1 VDD_A1 3 3 VDD_A2 LX_A2 VSS_A2 VSS_A1 LX_A1 VDD_A1 4 4 VDD_A2 LX_A2 VSS_A2 VSS_A1 LX_A1 VDD_A1 5 nIRQ VSS FBAN FBAP NC 7 6 VSYS 7 IC_EN VDDIO FBBN/ NC nCS/ GPI4 VSS_ANA FBBP/ NC GPI1 GPI0/ TRK SO/ GPIO3 GPIO2 6 SCL/ SK 5 SDA/ SI 8 8 VDD_B2 LX_B2 VSS_B2 VSS_B1 LX_B1 VDD_B1 9 9 VDD_B2 LX_B2 VSS_B2 VSS_B1 LX_B1 VDD_B1 10 10 VDD_B2 LX_B2 VSS_B2 VSS_B1 LX_B1 VDD_B1 11 11 VDD_B2 LX_B2 VSS_B2 VSS_B1 LX_B1 VDD_B1 F E D C B A 66 balls Sensitive Analog Signals Quasi Static Digital Signals Noisy Digital Signals Power Signals High Power Noisy Signals High Power Signals see balls through package DA9213/14 2 B A DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Pinout Figure 3: Connection Diagram 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Table 1: Pin Description Pin Name Signal Name Second Function Type Description (See Table 2) B1, B2, B3, B4 LX_A1 AO Switching node for Buck A phase 1 E1, E2, E3, E4 LX_A2 AO Switching node for Buck A phase 2 B8, B9, B10, B11 LX_B1 AO Switching node for Buck B phase 1 E8, E9, E10, E11 LX_B2 AO Switching node for Buck B phase 2 A1, A2, A3, A4 VDD_A1 PS Supply voltage for Buck A phase 1 To be connected to VSYS F1, F2, F3, F4 VDD_A2 PS Supply voltage for Buck A phase 2 To be connected to VSYS A8, A9, A10, A11 VDD_B1 PS Supply voltage for Buck B phase 1 To be connected to VSYS F8, F9, F10, F11 VDD_B2 PS Supply voltage for Buck B phase 2 To be connected to VSYS F7 IC_EN DI Integrated Circuit (IC) Enable Signal F5 nIRQ DO Interrupt line towards the host E7 VDDIO PS I/O Voltage Rail C5 FBAP AI Positive sense node for the Buck A D5 FBAN AI Negative sense node for the Buck A C7 FBBP AI Positive sense node for the Buck B for DA9214-A NC AO Do not connect for DA9213-A FBBN AI Negative sense node for the Buck B for DA9214-A NC AO Do not connect for DA9213-A DI/AI General purpose input, input track D7 A7 GPI0 B7 GPI1 DI General purpose input B6 GPIO2 DIO General purpose input/output A5 SDA SI DIO 2-WIRE data, 4-WIRE data input/output A6 SCL SK DI 2-WIRE clock, 4-WIRE clock D6 nCS GPI4 DI 4-WIRE chip select, general purpose input C6 SO GPIO3 DIO 4-WIRE data output, general purpose input/output B5 VDDCORE AO Regulated supply for internal circuitry. Decouple with 150 nF (or 220 nF) F6 VSYS PS Supply for IC and input for voltage supervision E5 VSS VSS E6 VSS_ANA VSS Datasheet CFR0011-120-00 TRK Revision 1.4 8 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Pin Name Signal Name C1, C2, C3, C4, VSS_A1, D1, D2, D3, D4, C8, C9, C10, C11, VSS_A2 VSS_B1 D8, D9, D10, D11 VSS_B2 Second Function Type Description (See Table 2) VSS Connect together Table 2: Pin Type Definition Pin Type Description Pin Type Description DI Digital Input AI Analogue Input DO Digital Output AO Analogue Output DIO Digital Input/Output AIO Analogue Input/Output PS Power Supply VSS Ground Datasheet CFR0011-120-00 Revision 1.4 9 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 3 Absolute Maximum Ratings Table 3: Absolute Maximum Ratings Parameter Description TSTG Storage temperature -65 +150 °C TA_LIM Limiting ambient temperature -40 +105 °C Tj_MAX Maximum junction temperature +150 °C VDD_LIM Limiting supply voltage -0.3 5.5 V VPIN Limiting voltage at all pins except above -0.3 VDD + 0.3 (max 5.5) V VESD_HBM Electrostatic discharge voltage 2 kV Note 1 4 Conditions (Note 1) Min Typ Max Human Body Model Unit Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Table 4: Recommended Operating Conditions Parameter Description VDD Supply voltage Tj_OP Operating Junction Temperature VDDIO Input/output supply voltage PTOT Total power dissipation (Note 3) JA Thermal resistance junction to ambient (Note 3) Conditions (Note 1) Min Typ 2.8 1.2 Derating factor above TA = 70 °C: 34.8 mW/°C Max Unit 5.5 V 125 °C 3.6 (Note 2) V 1920 mW 28.7 °C/W Note 1 Within the specified limits, a life time of 10 years is guaranteed Note 2 VDDIO is not allowed to be higher than VDD Note 3 Obtained from simulation on a 2S2P 4L JEDEC Board (EIA/JESD51-2). Influenced by PCB technology and layout. Datasheet CFR0011-120-00 Revision 1.4 10 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 4.5 PD = (TJ - TA) / θJA θJA = 28.7 °C/W Still air (0 m/s) ▲TJ(WARN) = 125 °C TJ(CRIT) = 140 °C 4.0 3.5 PD (W) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 20 30 40 50 60 70 80 90 100 110 120 130 140 TA (°C) Figure 4: 66 VFBGA Power Derating Curve 5 Electrical Characteristics Table 5: Buck Converters Characteristics Parameter Description Conditions VDD Supply voltage VDD_x = VSYS 2.8 5.5 V VBUCK Buck output voltage (Note 1) IO = 0 to IO_MAX 0.3 1.57 V VOACC Output voltage accuracy Incl. static line/load reg and voltage ripple VBUCK ≥ 1 V -2.0 +2.0 % PWM mode Min Incl. static line/load reg and voltage ripple Typ Max ±20 Unit mV VBUCK < 1 V VBUCK = 1 V -1.0 +1.0 % -0.5 +0.5 % VDD = 3.8 V no load VBUCK = 1 V VDD = 3.8 V no load TA = 27 ºC Datasheet CFR0011-120-00 Revision 1.4 11 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Parameter Description Conditions VTR_LOAD Load regulation transient voltage (Note 2) DA9213-A Min Typ Max IO = 0 to 5 A, tr = 500 ns PWM 4-phase Unit % VBUCK ≥ 1 V VBUCK < 1 V ±2% ±20 mV DA9213-A IO = 0 to 5 A, tr = 500 ns ±3.5 % ±3.5 % 15 mV auto mode, ph shedding VBUCK = 1 V Load regulation transient voltage DA9214-A IO = 0 to 5 A, tr = 500 ns (Note 2) PWM 2-phase VBUCK = 1 V Line regulation transient voltage VDD = 3 to.3.6 V IO_MAX Maximum output current Per phase 5000 ILIM_MIN Minimum current limit BUCKA_ILIM -20% 4000 20% mA per phase (programmable) (Note 3) BUCKB_ILIM = 0000 Maximum current limit BUCKA_ILIM -20% 7000 20% mA per phase (programmable) (Note 3) BUCKB_ILIM Quiescent current @ synchronous rectification mode Per phase No load VTR_LINE ILIM_MAX IQ_PWM fSW Switching frequency tSTUP Start up time dt =10 µs IO = IO(MAX)/2 mA = 1111 17 mA 3 MHz 50 (Note 4) µs VDD = 3.7 V BUCKA_UP_CTRL BUCKB_UP_CTRL = 011 RO_PD Output pull-down resistance For each phase at the LX node @0.5 V, 150 200 Ω (see BUCKx_PD_DIS) RON_PMOS PMOS on-resistance incl. pin and routing 27 mΩ 19 mΩ VDD = 3.7 V per phase RON_NMOS NMOS on-resistance incl. pin and routing VDD = 3.7 V per phase PFM Mode VBUCK_PFM Buck output voltage in PFM Datasheet CFR0011-120-00 IO = 0 mA to IO_MAX Revision 1.4 12 of 62 0.3 1.57 V 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Parameter Description Conditions IMIN_PFM Minimum output current in PFM Static output voltage, no DVC IQ_PFM_A2 DA9214-A quiescent current No switching Buck A enabled VDD = 3.7 V (Note 5) DA9213-A quiescent current Buck enabled No switching VDD = 3.7 V IQ_PFM_A4 Min Typ 2 Max Unit mA 58 µA 72 µA 106 µA (Note 5) IQ_PFM_A2B2 DA9214-A quiescent current Buck A enabled No switching VDD = 3.7 V (Note 5) Buck B enabled Note 1 Programmable in 10 mV increments. Note 2 Additional to the dc accuracy. Inductor value 0.22 uH. The value is measured directly at COUT(EXT). In case of remote sensing, parasitics of PCB and external components may affect this value. Note 3 On-time > 50 ns. Note 4 Time from begining to end of the voltage ramp. Additional 10 µs typical delay, plus internal sync to the enable port. Note 5 For the total quiescent current of the IC, the IDD_ON should be added. Datasheet CFR0011-120-00 Revision 1.4 13 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Table 6: IC Performance and Supervision Parameter Description Conditions IDD_OFF Off state supply current IC_EN = 0 Min Typ 0.1 Max 1 Unit µA TA = 27 °C IDD_ON On state supply current IC_EN = 1 14 µA -50 mV Buck A/B off TA = 27 °C VTH_PG Power good threshold voltage VHYS_PG Power good hysteresis voltage 50 mV VTH_UVLO_V Under voltage lockout threshold @ VDD 2.0 V DD VTH_UVLO_IO Under voltage lockout threshold @ VDDIO VHYS_UVLO_I Under voltage lockout hysteresis @ VDDIO O referred to VBUCK 1.315 1.45 1.55 70 V mV TTH_WARN Thermal warning threshold temperature 110 125 140 °C TTH_CRIT Thermal critical threshold temperature 125 140 155 ºC TTH_POR Thermal power on reset threshold temperature 135 150 165 °C fOSC Internal oscillator frequency -7% 6.0 +7% MHz Table 7: Digital I/O Characteristics Parameter Description Conditions Min Typ Max VIH_EN HIGH level input voltage @ pin IC_EN VIL_EN LOW level input voltage @ pin IC_EN tEN Enable time I/F operating 750 µs RO_PU_GPO Pull up resistor @ GPO VDDIO = 1.8 V VGPO = 0 V 100 k RI_PD_GPI Pull down resistor @ GPI VDDIO = 1.8 V VGPI = VDDIO 150 k VIH GPI0-4, SCL, SDA, (2-WIRE mode) VLDOCORE mode VDDIO mode 1.1 Unit V 0.35 1.75 0.7*VDDIO V V HIGH level input voltage VIL GPI0-4, SCL, SDA, (2-WIRE mode) VLDOCORE mode VDDIO mode 0.75 0.3*VDDIO V LOW level input voltage Datasheet CFR0011-120-00 Revision 1.4 14 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Parameter Description VIH_4WIRE SK, nCS, SI Conditions Min Typ Max 0.7*VDDIO Unit V (4-WIRE Mode) HIGH level input voltage VIL_4WIRE SK, nCS, SI (4-WIRE Mode) 0.3*VDDIO V LOW level input voltage VOH VOL1 GPO2-3, SO (4-WIRE mode) HIGH level output voltage push-pull mode 0.8*VDDIO V @1mA VDDIO ≥ 1.5 V GPO2-3, SDA (2-WIRE mode) SO (4-WIRE mode) 0.3 V LOW level output voltage @IOL = 1 mA VOL3 SDA (2-WIRE Mode) LOW level output voltage @IOL = 3 mA 0.24 V VOL20 SDA (2-WIRE Mode) 0.4 V 10 pF LOW level output voltage @IOL = 20 mA CIN CLK, SDA 2.5 (2-WIRE Mode) input capacitance tSP CLK, SDA (2-WIRE Mode) Fast/Fast+ mode High Speed mode 0 0 50 10 ns Fast @ Cb<550pF HS @ 10<Cb<100pF 20+0.1Cb 10 120 80 ns HS @ Cb<400pF 20 160 spike suppression pulse width tfDA Fall time of SDA signal (2-WIRE Mode) Table 8: 2-WIRE Control Bus Characteristics Parameter Description tBUF Bus free time from STOP to START condition CB Bus line capacitive load Conditions Min Typ Max 0.5 Unit µs 150 pF 1000 kHz Standard/Fast/Fast+ Mode fSCL Clock frequency @ pin SCL 0 (Note 1) tSU_STA START condition set-up time 0.26 µs tH_STA START condition hold time 0.26 µs Datasheet CFR0011-120-00 Revision 1.4 15 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Parameter Description Conditions Min Typ Max Unit tW_CL Clock LOW duration 0.5 µs tW_CH Clock HIGH duration 0.26 µs tR Rise time Input requirement 1000 ns Input requirement 300 ns @ pin CLK and DATA tF Fall time @ pin CLK and DATA tSU_D Data set-up time 50 ns tH_D Data hold time 0 ns High Speed Mode fSCL_HS Clock frequency @ pin SCL 0 (Note 1) tSU_STA_HS START condition set-up time 160 ns tH_STA_HS START condition hold time 160 ns tW_CL_HS Clock LOW duration 160 ns tW_CH_HS Clock HIGH duration 60 ns tR_HS Rise time @ pin CLK and DATA Input requirement 160 ns tF_HS Fall time @ pin CLK and DATA Input requirement 160 ns tSU_D_HS Data set-up time 10 ns tH_D_HS Data hold time 0 ns tSU_STO_HS STOP condition set-up time 160 ns Note 1 3400 kHz Minimum clock frequency is 10 kHz if 2WIRE_TO is enabled Figure 5: 2-WIRE Bus Timing Datasheet CFR0011-120-00 Revision 1.4 16 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Table 9: 4-WIRE Control Bus Characteristics Parameter Description Label in Plot Min Typ Max Unit CB Bus line capacitive load 100 pF tC Cycle time 1 70 ns tSU_CS Chip select setup time 2, from CS active to first SK edge 20 ns tH_CS Chip select hold time 3, from last SK edge to CS idle 20 ns tW_CL Clock LOW duration 4 0.4 x tC ns tW_CH Clock HIGH duration 5 0.4 x tC ns tSU_SI Data input setup time 6 10 ns tH_SI Data input hold time 7 10 ns tV_SO Data output valid time 8 tH_SO Data output hold time 9 6 ns tW_CS Chip select HIGH duration 10 20 ns 22 (2) tSU_CS (3) tH_CS ns (10) tW_CS 70% nCS 30% (5) tW_CH (4) tW_CL (1) tC 70% SK 30% (6) tSU_SI (7) tH_SI 70% SI 30% (8) tV_SO (9) tH_SO 70% 30% SO Figure 6: 4-WIRE Bus Timing Datasheet CFR0011-120-00 Revision 1.4 17 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 6 Efficiency Measurements The efficiency measurements for DA9213-A and DA9214-A are shown with phase shedding enabled in each plot. Figure 7: DA9213-A Efficiency vs Load, VOUT = 1.0 V, 0-20 A Figure 8: DA9213-A Efficiency vs Load, VIN = 3.6 V, 0-20 A Datasheet CFR0011-120-00 Revision 1.4 18 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Figure 9: DA9214-A Efficiency vs Load, VOUT = 1.0 V, 0-10 A Figure 10: DA9214-A Efficiency vs Load, VIN = 3.6 V, 0-10 A Datasheet CFR0011-120-00 Revision 1.4 19 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 7 Functional Description Flexible configurability and the availability of different control schemes make both DA9213-A and DA9214-A the ideal single/dual buck companion ICs to expand the existing capabilities of a master PMIC such as DA9063. Due to the advanced compatibility between both DA9213-A and DA9214-A and the DA9063, they offer several advantages when they are operated together. These advantages include: ● DA9213-A and DA9214-A can be enabled and controlled by DA9063 during the power up sequence, thanks to DA9063’s dedicated output signals during power-up, and compatible input controls in bothDA9213-A and DA9214-A. ● DA9213-A and DA9214-A can be used in a completely transparent way for the host processor 2 and can share the same Control Interface (same SPI chip select or I C address), thanks to the compatible registers map. DA9213-A and DA9214-A has a dedicated register space for configuration and control which doesn’t conflict with DA9063. ● DA9213-A and DA9214-A supports a power-good configurable port for enhanced communication to the host processor and improved power-up sequencing. ● DA9213-A and DA9214-A can both share the same interrupt line with DA9063. In addition, the 2-WIRE / 4-WIRE interfaces allow DA9213-A and DA9214-A to fit to many standard PMU parts and power applications. Vdd nIRQ nSHUTDOWN SYS_EN nOFF PWR_EN nONKEY DA9063 Host Processor PWR1_EN LID OUT_32K GPIOs nRESET Control IF VCharger GPIO9 IC_EN DA9213-A/ DA9214-A Control IF nIRQ GPI1 (voltage set) GPI0 (enable) Figure 11: Interface of DA9213-A/14-A with DA9063 and the Host Processor As shown in Figure 11, a typical application case includes a host processor, a main PMIC (for example, DA9063) and DA9213-A or DA9214-A used as companion IC for the high power core supply. Datasheet CFR0011-120-00 Revision 1.4 20 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter The easiest way of controlling DA9213-A and DA9214-A is through the Control Interface. The master initiating the communication must always be the host processor that reads and writes to the main PMIC, and to the DA9213-A and DA9214-A registers. To poll the status of DA9213-A or DA9214-A, the host processor must access the dedicated register area through the Control Interface. DA9213-A and DA9214-A can additionally be controlled by means of hardware inputs. CORE VDDIO DA9213-A SCL SDA nIRQ VSEL (GPI1) EN (GPI0) LP_MODE DA9063 (PMIC) VIN VDD_A1 IC_EN GPIO9 (seq) VDD_A2 VDD_B1 VDD_B2 SENSE+ LX_A1 LX_A2 CPU / GPU / DDR VSYS LX_B1 VSS_ANA LX_B2 SENSEFBAP FBAN VDDIO I2C_ADDR_SEL (GPI4) Power Good (GPIO3) Ext Supply Figure 12: Typical Application of DA9213-A Figure 12 shows a typical use case of DA9213-A for the supply of CPU, GPU, or DDR rails. The IC is enabled and disabled by the main PMIC via IC_EN port as part of its sequencer. Once the IC is Datasheet CFR0011-120-00 Revision 1.4 21 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter enabled, the CORE application processor enables the buck converter with the EN1 signal and manages the output voltage selection with the VSEL signal. The VSEL signal can be shared between the main PMIC and the DA9213-A. Three GPI/GPIOs embedded in DA9213-A are used in this case: ● GPIO2 signals the insertion of an external charger in the application (through interrupt to the host processor) ● GPIO3 indicates a power-good-condition, either to proceed with the power up sequence or to enable an external supply connected to the port ● GPI4 is used for the I2C interface address hardware selection DA9214-A CORE VDDIO SCL SDA nIRQ EN_A (GPI0) EN_B (GPI1) VIN VDD_A1 VDD_A2 VDD_B1 SENSE+ CPU/ GPU SENSE+ DDR LX_A1 VDD_B2 LX_A2 SENSEVSYS FBAP FBAN VSS_ANA LX_B1 LX_B2 (LX_A3 in DA9215) SENSEFBBP FBBN VDDIO I2C_ADDR_SEL (GPI4) VSYS IC_EN Figure 13: Typical Application of DA9214-A Figure 13 shows a typical use case of DA9214-A for the simultaneous supply of a CPU and a GPU rail. The IC is always enabled because IC_EN is shorted to the battery voltage. The CORE application processor enables and disables the CPU/GPU and the DDR individually via dedicated ports on DA9214-A. Datasheet CFR0011-120-00 Revision 1.4 22 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 7.1 DC-DC Buck Converter DA9213-A is a four-phase 20 A high efficiency synchronous step-down DVC regulator, operating at a high frequency of typically 3 MHz. It supplies an output voltage of typically 1.0 V for a CPU rail, configurable in the range 0.3 – 1.57 V, with high accuracy in steps of 10 mV. DA9214-A contains two buck converters, Buck A and Buck B, each capable of delivering 10 A. To improve the accuracy of the delivered voltage, each buck converter is able to support a differential nsing of the configured voltage directly at the point of load via dedicated positive and negative sense pins. Both Buck A and Buck B have two voltage registers each. One defines the normal output voltage, while the other offers an alternative retention voltage. In this way different application power modes can easily be supported. The voltage selection can be operated either via GPI or via control interface to guarantee the maximum flexibility according to the specific host processor status in the application. When a buck is enabled, its output voltage is monitored and a power-good signal indicates that the buck output voltage has reached a level higher than the VTH(PG) threshold. The power-good is lost when the voltage drops below VTH(PG) - VHYS(PG), which is the level at which the signal is deasserted. The power good signalling should not be used in conjunction with fast start up rates, configured in BUCKx_UP_CTRL register fields and can be individually masked during DVC transitions using the PGA_DVC_MASK and PGB_DVC_MASK bits. For each of the buck converters 2 the status of the power-good indicator can be read back via I C from the PWRGOOD_A and PWRGOOD_B status bits. It can be also individually assigned to either GPIO2 or GPIO3 using BUCKA_PG_SEL and BUCKB_PG_SEL. For correct functionality, the GPIO ports need to be 2 configured as output. An I C write in GPIOx_MODE can overwrite the internal configuration so that a new update will be automatically done only when the internal power-good indicator changes status. The buck converters are capable of supporting DVC transitions that occur: ● When the active and selected A-voltage or B-voltage is updated to a new target value. ● When the voltage selection is changed from the A-voltage to the B-voltage (or B-voltage to the A-voltage) using VBUCKA_SEL and VBUCKB_SEL. The DVC controller operates in Pulse Width Modulation (PWM) mode with synchronous rectification. When the host processor changes the output voltage, the voltage transition of each buck converter can be individually signalled with a READY signal routed to either GPIO2 or GPIO3. The port has to be configured as GPO and selected for the functionality via READYA_CONF or READYB_CONF. In contrast to the power-good signal, the READY only informs the host processor about the completion of the digital DVC ramp without confirming that the target voltage has actually been reached. The slew rate of the DVC transition is individually programmed for each buck converter at 10mV per (4, 2, 1 or 0.5 µs) via control bit SLEW_RATE_A and SLEW_RATE_B. The typical supply current is in the order of 8 mA per phase (quiescent current and charge/discharge current) and drops to <1 µA when the buck is turned off. When the buck is disabled, a pull-down resistor (typically 150 Ω) for each phase is activated depending of the value stored in register bits BUCKA_PD_DIS and BUCKB_PD_DIS. Phases disabled using PHASE_SEL_A and PHASE_SEL_B will not have any pull-down. The pull-down resistor is always disabled at all phases when DA9213-A and DA9214-A are OFF. Datasheet CFR0011-120-00 Revision 1.4 23 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 7.1.1 Switching Frequency The switching frequency is chosen to be high enough to allow the use of a small 0.22 µH inductor (see a complete list of coils in the Application Information, Section 9). The buck switching frequency can be tuned using register bit OSC_TUNE. The internal 6 MHz oscillator frequency is tuned in steps of 180 kHz. This impacts the buck converter frequency in steps of 90 kHz and helps to mitigate possible disturbances to other HF systems in the application. 7.1.2 Operation Modes and Phase Selection The buck converters can operate in synchronous PWM mode and PFM mode. The operating mode is selected using register bits BUCKA_MODE and BUCKB_MODE. An automatic phase shedding can be enabled for each buck converter in PWM mode via EF _Ref370828148 \h \* MERGEFORMAT PH_SH_EN_A, PH_SH_EN_B, thereby automatically reducing or increasing the number of active phases depending on the output load current. For DA9214-A the phase shedding will automatically change between 1-phase and 2-phase operation at a typical current of 2.0 A. For DA9213-A the phase shedding will automatically change between 1phase and 4-phase operation at a typical current of 2.5 A. The PHASE_SEL_A and PHASE_SEL_B register fields limit the maximum number of active phases under any conditions. If the automatic operation mode is selected on BUCKA_MODE or BUCKB_MODE, the buck converters will automatically change between synchronous PWM mode and PFM depending on the load current. This improves the efficiency of the converters across the whole range of output load currents. 7.1.3 Output Voltage Selection The switching converter can be configured using either a 2-WIRE or a 4-WIRE interface. For security reasons, the re-programming of registers that can cause damage when wrongly programmed (for example, the voltage settings) can be disabled by asserting the control V_LOCK. When V_LOCK is asserted, reprogramming the registers 0xD0 to 0x14F from control interfaces is disabled. For each buck converter two output voltages can be pre-configured inside registers VBUCKA_A and VBUCKB_A, and registers VBUCKA_B and VBUCKB_B. The output voltage can be selected by either toggling register bits VBUCKA_SEL and VBUCKB_SEL or by re-programming the selected voltage control register. Both changes will result into ramped voltage transitions, during which the READY signal is asserted. After being enabled, the buck converter will by default use the register settings in VBUCKA_A and VBUCKB_A unless the output voltage selection is configured via the GPI port. If “00” has been selected in BUCKA_MODE or BUCKB_MODE, A-/B- voltage selection registers VBUCKx_x control the operation of the PWM and PFM modes. Regardless of the values programmed in the VBUCKx_A and VBUCKx_B registers, the registers VBUCKA_MAX, VBUCKB_MAX will individually limit the output voltage that can be set for each of the buck converters. The buck converter provides an optional hardware enable/disable via selectable GPI, and configured via control register bits BUCKA_GPI and BUCKB_GPI. A change of the output voltage from the state of a GPI is enabled via control register bits VBUCKA_GPI and VBUCKB_GPI. After detecting a rising or falling edge at the related GPIs, DA9213-A and DA9214-A will configure the buck converters according to their status. In addition to selecting between the A/B voltages, a track mode can be activated for Buck A to set the output voltage. In the DA9213-A, the track mode is applied to the 4-phase buck converter. This feature can be enabled on GPI0 via GPI0_PIN. The output voltage will be configured to follow the value applied at a selected GPI pin. The voltage applied at GPI0 must be in the same range as the Datasheet CFR0011-120-00 Revision 1.4 24 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter nominal output voltage selectable for the buck rail (see VBUCKA_A and VBUCKA_B registers). In Track Mode, only single ended remote sensing is possible. In Track Mode, the content of the VBUCKA_SEL bit is ignored, as well as VBUCKA_A and VBUCKA_B bits. They will become active again once the voltage track mode is disabled. The GPI0 does not generate any event in this case. Figure 14: Concept of Control of the Buck’s Output Voltage 7.1.4 Soft Start Up To limit in-rush current from VSYS, the buck converters can perform a soft-start after being enabled. The start-up behavior is a compromise between acceptable inrush current from the battery and turn-on time. In DA9213-A and DA9214-A different ramp times can be individually configured for each buck converter on register BUCKA_UP_CTRL and BUCKB_UP_CTRL. Rates higher than 20 mV/µs may produce overshoot during the start-up phase, so they should be considered carefully. A ramped power-down can be selected on register bits BUCKA_DOWN_CTRL and BUCKB_DOWN_CTRL. When no ramp is selected, the output node will be discharged only by the pull-down resistor, if enabled via BUCKA_PD_DIS and BUCKB_PD_DIS. 7.1.5 Current Limit The integrated current limit is meant to protect DA9213-A and DA9214-A power stages and the external coil from excessive current. The bucks’ current limit should be configured to be at least 40% higher than the required maximum continuous output current (see table below). When reaching the current limit, each buck converter generates an event and an interrupt to the host processor unless the interrupt has been masked using the OCx_MASK controls. These OCA_MASK and OCB_MASK control bits can be used to mask the generation of over-current events during DVC transitions. An extra masking time as defined in OCx_MASK will be automatically added to the DVC interval after the DVC has finished in order to ensure that the possible high current levels needed for DVC do not influence the event generation. 7.1.6 Variable VOUT above 1.57 V The whole product family is also available with an adjustable output voltage up to 4.3V. A resistive divider from VOUT to FBAN (or FBBN) can be used to set the output voltage higher than 1.57 V, see Figure 15. The specific variant DA921_S is optimized for variable output voltage and the VREF on FBAN (or FBBN) is set to 1.2 V. Datasheet CFR0011-120-00 Revision 1.4 25 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter The value of the output voltage VOUT is set by the selection of the resistive divider shown in equation 1. The total resistance of the divider resistors (R1+R2) should be less than 40 k. 𝑉𝑂𝑈𝑇 = (1 + 𝑅1 ) ∙ 𝑉𝑅𝐸𝐹 𝑅2 Equation 1 VOUT R1 FBAP R2 FBAN Figure 15: Resistive Divider from VOUT to FBAN For example, to program the output voltage VOUT to 1.8 V, suggest 10 kΩ on R1 and 20 kΩ on R2. Note 1 The resistors need to be properly selected since the output voltage accuracy will be directly affected by any errors on the resistors. The voltage across FBAP and FBAN (VREF) is guaranteed, but not the output voltage accuracy. CAUTION The followings are important notes that need to be considered before using resistive divider on DA9213-A and DA9214-A: 1. Please contact your region's Dialog representative when adopting the resistive divider technique. Dialog need to prepare a special OTP because incorrect OTP settings may result in a different output voltage than expected. 2. The voltage difference between input voltage and output voltage needs to be: above 1.2 V, VIN-VOUT > 1.2 V. 3. 4. The total resistance (R1+R2) is less than 40 k. It is recommended that the device is operated in PWM mode only. Datasheet CFR0011-120-00 Revision 1.4 26 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 7.2 Ports Description This section describes the functionality of each input / output port. 7.2.1 VDDIO VDDIO is an independent IO supply rail input to DA9213-A and DA9214-A that can be assigned to the power manager interface and to the GPIOs (see control PM_IF_V and GPI_V). The rail assignment determines the IO voltage levels and logical thresholds (see also the Digital I/O Characteristics in Table 7). 2 An integrated under voltage lockout circuit for the VDDIO prevents internal errors by disabling the I C communication when the voltage drops below VULO_IO. In that case the buck converters are also disabled and cannot be re-enabled (even via input port) until the VDDIO under-voltage condition has been resolved. At the exit of the VDDIO under voltage condition an event E_UVLO_IO is generated and the nIRQ line is driven active if the event is not masked. The VDDIO under-voltage circuit monitors voltages relative to a nominal voltage of 1.8V. If a different rail voltage is being used, the under-voltage circuit can be disabled via UVLO_IO_DIS. Note that the maximum speed at 4-WIRE interface is only available if the selected supply rail is greater than 1.6 V. 7.2.2 IC_EN IC_EN is a general enable signal for DA9213-A and DA9214-A turning on and off the internal circuitry (for example, the reference, the digital core, etc.). Correct control of this port has a direct impact on the quiescent current of the whole application. A low level of IC_EN allows the device to reach the minimum quiescent current. The voltage at this pin is continuously sensed by a dedicated analogue circuit. The host processor will be allowed to start the communication with DA9213-A and DA9214-A through the Control Interface and, for example to turn on the buck converters, a delay time of t EN after assertion of the IC_EN pin. If the bucks are enabled via OTP (see BUCKA_EN and BUCKB_EN controls), they will start up automatically after assertion of IC_EN. The IC_EN activation threshold is defined with a built in hysteresis to avoid glitching transitions that take place with unstable rising or falling edges. 7.2.3 nIRQ The nIRQ port indicates that an interrupt-causing event has occurred and that the event/status information is available in the related registers. The nIRQ is an output signal that can either be push-pull or open drain (selected via IRQ_TYPE). If an active high IRQ signal is required, it can be achieved by asserting control IRQ_LEVEL (recommended for push-pull mode). Examples of this type of information can be critical temperature and voltage, fault conditions, status changes at GPI ports, and so forth. The event registers hold information about the events that have occurred. Events are triggered by a status change at the monitored signals. When an event bit is set, the nIRQ signal is asserted unless this interrupt is masked by a bit in the IRQ mask register. The nIRQ will not be released until all event registers with asserted bits have been read and cleared. New events that occur during reading an event register are held until the event register has been cleared, ensuring that the host processor does not miss them. 7.2.4 GPIO Extender DA9213-A and DA9214-A includes a GPIO extender that offers up to five 5 V-tolerant general purpose input/output ports. Each port is controlled via registers from the host processor. Datasheet CFR0011-120-00 Revision 1.4 27 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter The GPIO3 and GPI4 ports are pin-shared with the 4-WIRE Control Interface. For instance, if GPIO3_PIN = 01, GPI4_PIN = 01 (Interface selected), the GPIO3 and GPI4 ports will be exclusively dedicated to output and chip-select signaling for 4-WIRE purposes. If the alternative function is selected, all GPIOs configuration as per registers 0x58 to 0x5A and 0x145 will be ignored. GPIs are supplied from the internal rail VDDCORE or VDDIO (selected via GPI_V) and can be configured to be active high or active low (selected via GPIOx_TYPE). The input signals can be debounced or directly change the state of the assigned status register GPIx to high or low, according to the setting of GPIOx_MODE. The debouncing time is configurable via control DEBOUNCE (10 ms default). Whenever the status has changed to its configured active state (edge sensitive), the assigned event register is set and the nIRQ signal is asserted (unless this nIRQ is masked, see also Figure 16). Whenever DA9213-A and DA9214-A is enabled and enters ON mode (also when enabled changing the setting of GPIOx_PIN) the GPI status bits are initiated towards their configured passive state. This ensures that already active signals are detected, and that they create an event immediately after the GPI comparators are enabled. The buck enable signal (BUCKx_EN) can be controlled directly via a GPI, if so configured in the BUCKA_GPI and BUCKB_GPI registers. If it is required that GPI ports do not generate an event when configured for the HW control of the switching regulator, the relative mask bit should be set. GPIs can alternatively be selected to toggle the VBUCKA_SEL and VBUCKB_SEL from rising and falling edges at these inputs. Apart from changing the regulator output voltage this also provides hardware control of the regulator mode (normal/low power mode) from the settings of BUCKA_SL_A, BUCKA_SL_B, BUCKB_SL_A, and BUCKB_SL_B (enabled if BUCKA_MODE or BUCKB_MODE = ‘00’). All GPI ports have the additional option of activating a 100 kΩ pull-down resistor via GPIOx_PUPD, which ensures a well-defined level in case the input is not actively driven. 2 If enabled via ADDR_SEL_CONF, the I C address selection can be assigned to a specific GPI. An active voltage level at the selected GPI configures the slave address of DA9213-A and DA9214-A to IF_BASE_ADDR1 while a passive voltage level configures the slave address to IF_BASE_ADDR2. If no GPI is selected then the IF_BASE_ADDR1 is automatically used. If defined as an output, GPIOs can be configured to be open-drain or push-pull. If configured as push-pull, the supply rail is VDDIO. By disabling the internal 120 kΩ pull-up resistor in open-drain mode, the GPO can also be supplied from an external rail. The output state will be assigned as configured by the GPIO register bit GPIOx_MODE. A specific power-good port for each of the buck converters can be configured via BUCKA_PG_SEL and BUCKB_PG_SEL. The respective port must be configured as GPO for correct operation. If assigned to the same GPO, it is necessary that the power-good indicators for Buck A and Buck B are both active (supply voltages in range) to assert the overall power-good. The signal will be released as soon as one of the single power-good signals is not active (that is, at least one supply is out of range). The power good signalling should not be used in conjunction with fast start up rates, configured in BUCKx_UP_CTRL register fields. Once enabled via RELOAD_FUNC_EN the GPIO0 can be used as input port to operate a partial OTP download. When the input level is changed to active, the registers 0x5D, 0x5E, 0xD1 to 0xDA are updated to their OTP default. This allows a complete buck re-configuration that resets all the changes done to those registers previously (soft reset). If the buck should be kept on during the soft reset, the OTP values for the enable bits should be asserted because they are also part of the reload. Datasheet CFR0011-120-00 Revision 1.4 28 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Whenever the GPIO unit is off (POR or OFF Mode) all ports are configured as open drain active high (pass device switched off, high impedance state). When leaving POR the pull-up or pull-down resistors will be configured from register GPIOx_PUPD. Interrupt mask: M_GPI0 Track Mode Input Reference Buffer GPIO0_TYPE: Active high/low Buck GPI0_MODE: Debounce on/off Status register Event register Debounce GPI NOR GPI0 GPIO0_PUPD Reserved E_GPI0 Rising or Falling edge GPI0_PIN nIRQ Reset NOR Reserved Buck HW control Event register write 100kΩ Regulator configure ... BUCK_ EN VBUCK_SEL VDD_IO Interrupt mask: M_GPI3 4-WIRE SO GPIO3_TYPE: Active high/low Status register GPIO3_MODE: Debounce on/off Event register Interface NOR GPI3 GPI E_GPI3 Rising or Falling edge Debounce Reset GPIO3_PIN Event register write GPIO3_PUPD VDD_IO GPIO3_PUPD 100kΩ 120kΩ GPO (Open drain) READY_EN READY signal asserted during DVC VDD_IO GPO (Push-pull) GPO3_MODE: 0 or 1 Figure 16: GPIO Principle of Operation (example paths) Datasheet CFR0011-120-00 Revision 1.4 29 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 7.3 7.3.1 Operating Modes ON Mode DA9213-A and DA9214-A are in ON Mode when the IC_EN port is higher than EN_ON and the supply voltage is higher than VTH (UVLO)(VDD). Once enabled, the host processor can start the communication with DA9213-A and DA9214-A via Control Interface after the tEN delay needed for internal circuit start up. If BUCKA_EN or BUCKB_EN is asserted when DA9213-A and DA9214-A are in ON Mode the power up of the related buck converter is initiated. If the bucks are controlled via GPI, the level of the controlling ports is checked when entering ON mode, so that an active level will immediately have effect on the buck. If BUCKA_EN or BUCKB_EN are not asserted and all controlling GPI ports are inactive, the buck converter will stay off with the output pull-down resistor enabled/disabled according to the setting of BUCKA_PD_DIS and BUCKB_PD_DIS. 7.3.2 OFF Mode DA9213-A and DA9214-A are in OFF Mode when the IC_EN port is lower than EN_OFF. In OFF Mode, the bucks are always disabled and the output pull-down resistors are disabled independently of BUCKA_PD_DIS and BUCKB_PD_DIS. All I/O ports of DA9213-A and DA9214-A are configured as high impedance. 7.4 Control Interfaces All the features of DA9213-A and DA9214-A can be controlled by SW through a serial control 2 interfaces. The communication is selectable to be either a 2-WIRE (I C compliant) or a 4-WIRE connection (SPI compliant) via control IF_TYPE, which will be selected during the initial OTP read. If 4-WIRE is selected, the GPIO3 and GPI4 are automatically configured as interface pins. Data is shifted into or out of DA9213-A and DA9214-A under the control of the host processor, which also provides the serial clock. In a normal application case the interface is only configured once from OTP values, which are loaded during the initial start-up of DA9213-A and DA9214-A. DA9213-A and DA9214-A react only on read/write commands where the transmitted register address (using the actual page bits as a MSB address range extensions) is within 0x50 to 0x67, 0xD0 to DF, 0x140 to 0x14F and (read only) 0x200 to 0x27F. Host access to registers outside these ranges will be ignored. This means there will be no acknowledge after receiving the register address in 2-WIRE Mode, and SO stays HI-Z in 4-WIRE Mode. During debug and production modes write access is available to page 4 (0x200 to 0x27F). DA9213-A and DA9214-A react only on write commands where the transmitted register address is 0x00, 0x80, 0x100 to0x106. The host processor must read the content of those registers before writing, thereby changing only the bit fields that are not marked as reserved (the content of the read back comes from the compatible PMIC, for example DA9063). If the STAND_ALONE bit is asserted (OTP bit), DA9213-A and DA9214-A also react to read commands. 7.4.1 4-WIRE Communication In 4-WIRE Mode the interface uses a chip-select line (nCS/nSS), a clock line (SK), data input (SI) and data output line (SO). The DA9213-A and DA9214-A register map is split into four pages that each contain up to 128 registers. The register at address zero on each page is used as a page control register. The default active page after turn-on includes registers 0x50 to 0x6F. Writing to the page control register changes the active page for all subsequent read/write operations unless an automatic return to page 0 was selected by asserting bit REVERT. Unless the REVERT bit was asserted after modifying the Datasheet CFR0011-120-00 Revision 1.4 30 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter active page, it is recommended to read back the page control register to ensure that future data exchange is accessing the intended registers. All registers outside the DA9213-A and DA9214-A range are write only, that is, the DA9213-A and DA9214-A will not answer to a read command and the data bus is tri-state (they are implicitly directed to DA9063). In particular the information contained in registers 0x105 and 0x106 is used by DA9213-A and DA9214-A to configure the control interface. They must be the same as the main PMIC (DA9063), so that a write to those registers configures both the main PMIC and DA9213-A and DA9214-A at the same time. The default OTP settings also need to be identical for a correct operation of the system. The 4-WIRE interface features a half-duplex operation, that is, data can be transmitted and received within a single 16-bit frame at enhanced clock speed (up to 14 MHz). It operates at the clock frequencies provided by the host. VDDIO VDDIO VDDIO SK Host SO processor SI VDDIO SK PMIC SI (slave) SO nCS/nSS nCS/nSS nCS/nSS Host processor VDDIO SK PMIC Peripheral SI device SCL SDA VDDIO 4-WIRE interface 2-WIRE interface SK SI Slave device SO nCS/nSS SCL SDA Peripheral device Figure 17: Schematic of 4-WIRE and 2-WIRE Power Manager Bus A transmission begins when initiated by the host. Reading and writing is accomplished by the use of an 8-bit command, which is sent by the host prior to the exchanged 8-bit data. The byte from the host begins shifting in on the SI pin under the control of the serial clock SK provided from the host. The first seven bits specify the register address (0x01 to 0x07) that will be written or read by the host. The register address is automatically decoded after receiving the seventh address bit. The command word ends with an R/W bit, which together with the control bit R/W_POL specifies the direction of the following data exchange. During register writing the host continues sending out data during the following eight SK clocks. For reading, the host stops transmitting and the 8-bit register is clocked out of DA9213-A and DA9214-A during the consecutive eight SK clocks of the frame. Address and data are transmitted with MSB first. The polarity (active state) of nCS is defined by control bit nCS_POL. nCS resets the interface when inactive and it has to be released between successive cycles. The SO output from DA9213-A and DA9214-A is normally in high-impedance state and active only during the second half of read cycles. A pull-up or pull-down resistor may be needed at the SO line if a floating logic signal can cause unintended current consumption inside other circuits. Table 10: 4-WIRE Clock Configurations Configurations CPHA Clock Polarity CPOL Clock Phase Output Data is Updated at SK Edge Input Data is Registered at SK Edge 0 (idle low) 0 Falling Rising 0 (idle low) 1 Rising Falling 1 (idle high) 0 Rising Falling 1 (idle high) 1 Falling Rising Datasheet CFR0011-120-00 Revision 1.4 31 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter DA9213-A and DA9214-A’s 4-WIRE interface offers two further configuration bits. Clock polarity (CPOL) and clock phase (CPHA) define when the interface will latch the serial data bits. CPOL determines whether SK idles high (CPOL = 1) or low (CPOL = 0). CPHA determines on which SK edge data is shifted in and out. With CPOL = 0 and CPHA = 0, DA9213-A and DA9214-A latch data on the SK rising edge. If the CPHA is set to 1 the data is latched on the SK falling edge. CPOL and CPHA states allow four different combinations of clock polarity and phase. Each setting is incompatible with the other three. The host and DA9213-A and DA9214-A must be set to the same CPOL and CPHA states to communicate with each other. 4-WIRE WRITE nCS SK SI A6 A5 A4 A3 A2 A1 A0 R/Wn D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 SO 4-WIRE READ nCS SK SI A6 SO A5 A4 A3 A2 A1 A0 R/Wn HI-Z D7 latch data Figure 18: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘0’) Datasheet CFR0011-120-00 Revision 1.4 32 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 4-WIRE WRITE nCS SK SI A6 A5 A4 A3 A2 A1 A0 R/Wn D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 SO 4-WIRE READ nCS SK SI A6 A5 A4 A3 A2 A1 A0 R/Wn HI-Z SO D7 latch data Figure 19: 4-WIRE Host Write and Read Timing (nCS_POL= ‘0’, CPOL = ‘0’, CPHA = ‘1’) 4-WIRE WRITE nCS SK SI A6 A5 A4 A3 A2 A1 A0 R/Wn D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 SO 4-WIRE READ nCS SK SI A6 SO A5 A4 A3 A2 A1 A0 R/Wn HI-Z D7 latch data Figure 20: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘0’) Datasheet CFR0011-120-00 Revision 1.4 33 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 4-WIRE WRITE nCS SK SI A6 A5 A4 A3 A2 A1 A0 R/Wn D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 SO 4-WIRE READ nCS SK SI SO A6 A5 A4 A3 A2 A1 A0 R/Wn HI-Z D7 latch data Figure 21: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘1’) Datasheet CFR0011-120-00 Revision 1.4 34 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Table 11: 4-WIRE Interface Summary Parameters Signal Lines nCS Chip select SI Serial input data Master out Slave in SO Serial output data Master in Slave out SK Transmission clock Interface Push-pull with tristate Supply voltage Selected from VDDIO 1.6 V to 3.3 V Data rate Effective read/write data Up to 7 Mbps Transmission Half-duplex MSB first 16 bit cycles 7-bit address, 1 bit read/write, 8-bit data CPOL Clock polarity CPHA Clock phase nCS_POL nCS is active low/high Configuration Note that reading the same register at high clock rates directly after writing it does not guarantee a correct value. It is recommended to keep a delay of one frame until re-accessing a register that has just been written (for example, by writing/reading another register address in between). 7.4.2 2-WIRE Communication The IF_TYPE bit in the INTERFACE2 register can be used to configure the DA9213-A and DA9214A control interface as a 2-WIRE serial data interface. In this case the GPIO3 and GPI4 are free for regular input/output functions. DA9213-A and DA9214-A has a configurable device write address (default: 0xD0) and a configurable device read address (default: 0xD1). See control IF_BASE_ADDR1 for details of configurable addresses. The ADDR_SEL_CONF bit is used to configure the device address as IF_BASE_ADDR1 or IF_BASE_ADDR2 depending on the voltage level applied at a configurable GPI port (see GPIO Extender). The SK port functions as the 2-WIRE clock and the SI port carries all the power manager bi-directional 2-WIRE data. The 2-WIRE interface is open-drain supporting multiple devices on a single line. The bus lines have to be pulled HIGH by external pull-up resistors (in the 2 kΩ to 20 kΩ range). The attached devices only drive the bus lines LOW by connecting them to ground. As a result two devices cannot conflict if they drive the bus simultaneously. In standard/fast mode the highest frequency of the bus is 400 kHz. The exact frequency can be determined by the application and does not have any relation to the DA9213-A and DA9214-A internal clock signals. DA9213-A and DA9214A will follow the host clock speed within the described limitations, and does not initiate any clock arbitration or slow down. An automatic interface reset can be triggered using control 2WIRE_TO if the clock signal stops to toggle for more than 35 ms. The interface supports operation compatible to Standard, Fast, Fast-Plus and High Speed mode of 2 the I C-bus specification Rev 4. Operation in high speed mode at 3.4 MHz requires mode changing in 2 order to set spike suppression and slope control characteristics to be compatible with the I C-bus specification. The high speed mode can be enabled on a transfer by transfer basis by sending the master code (0000 1XXX) at the beginning of the transfer. DA9213-A and DA9214-A do not make use of clock stretching, and deliver read data without additional delay up to 3.4 MHz. Alternatively, PM_IF_HSM configures the interface to use high speed mode continuously. In this case, the master code is not required at the beginning of every transfer. This reduces the Datasheet CFR0011-120-00 Revision 1.4 35 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter communication overhead on the bus but limits the slaves attachable to the bus to compatible devices. The communication on the 2-WIRE bus always takes place between two devices, one acting as the master and the other as the slave. The DA9213-A and DA9214-A will only operate as a SLAVE. In contrast to the 4-WIRE mode, the 2-WIRE interface has direct access to two pages of the register map (up to 256 addresses). The register at address zero on each page is used as a page control register (with the 2-WIRE bus ignoring the LSB of control REG_PAGE). Writing to the page control register changes the active page for all subsequent read/write operations unless an automatic return to page 0 was selected by asserting control REVERT. Unless REVERT was asserted after modifying the active page, it is recommended to read back the page control register to ensure that future data exchange is accessing the intended registers. In 2-WIRE operation DA9213-A and DA9214-A offer an alternative way to access register page 2 and page 3. It removes the need for preceding page selection writes by incrementing the device write/read address by one (default 0xD2/0xD3) for any direct access of page 2 and page 3 (page 0 and 1 access requires the basic write/read device address with the MSB of REG_PAGE to be ‘0’). 7.4.3 Details of the 2-WIRE Control Bus Protocol All data is transmitted across the 2-WIRE bus in groups of eight bits. To send a bit the SDA line is driven towards the intended state while the SCL is LOW (a low on SDA indicates a zero bit). Once the SDA has settled, the SCL line is brought HIGH and then LOW. This pulse on SCL clocks the SDA bit into the receiver’s shift register. A two-byte serial protocol is used containing one byte for address and one byte data. Data and address transfer are transmitted MSB first for both read and write operations. All transmissions begin with the START condition from the master while the bus is in IDLE state (the bus is free). It is initiated by a high to low transition on the SDA line while the SCL is in the high state (a STOP condition is indicated by a low to high transition on the SDA line while the SCL is in the high state). SCL SDA Figure 22: Timing of 2-WIRE START and STOP Condition The 2-WIRE bus is monitored by DA9213-A and DA9214-A for a valid SLAVE address whenever the interface is enabled. It responds immediately when it receives its own slave address. The acknowledge is done by pulling the SDA line low during the following clock cycle (white blocks marked with ‘A’ in Figure 23 to Figure 27). The protocol for a register write from master to slave consists of a start condition, a slave address with read/write bit and the 8-bit register address followed by eight bits of data terminated by a STOP condition. DA9213-A and DA9214-A respond to all bytes with Acknowledge. This is illustrated in Figure 23. Datasheet CFR0011-120-00 Revision 1.4 36 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter S SLAVEadr 7-bits W A REGadr 1-bit A DATA 8-bits Master to Slave P A 8-bits Slave to Master S = START condition P = STOP condition A = Acknowledge (low) W = Write (low) Figure 23: 2-WIRE Byte Write (SDA Line) When the host reads data from a register it first has to write to DA9213-A and DA9214-A with the target register address and then read from DA9213-A and DA9214-A with a Repeated START or alternatively a second START condition. After receiving the data, the host sends No Acknowledge and terminates the transmission with a STOP condition. This is illustrated in Figure 24. S SLAVEadr W A 7-bits S 1-bit SLAVEadr W A 7-bits 1-bit REGadr A Sr SLAVEadr 8-bits 7-bits REGadr A P S A 7-bits * DATA A P 8-bits SLAVEadr 8-bits Master to Slave R 1-bit R A 1-bit * DATA A P 8-bits Slave to Master S = START condition Sr = Repeated START condition P = STOP condition A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 24: Examples of 2-WIRE Byte Read (SDA Line) Consecutive (page) read out mode is initiated from the master by sending an Acknowledge instead of Not acknowledge after receipt of the data word. The 2-WIRE control block then increments the address pointer to the next 2-WIRE address and sends the data to the master. This enables an unlimited read of data bytes until the master sends a Not acknowledge directly after the receipt of data, followed by a subsequent STOP condition. If a non-existent 2-WIRE address is read out, the DA9213-A and DA9214-A will return code zero. This is illustrated in Figure 25. S SLAVEadr W A 7-bits 1 bit S SLAVEadr W 7-bits REGadr A Sr SLAVEadr R A 8-bits A REGadr 7-bits S A P Master to Slave S = START condition Sr = Repeat START condition P = STOP condition 8-bits SLAVEadr R A 7-bits 8-bits 1-bit 1-bit DATA 1-bit A DATA A 8-bits DATA * DATA A P 8-bits A 8-bits DATA * A P 8-bits Slave to Master A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 25: Examples of 2-WIRE Page Read (SDA Line) Note that the slave address after the Repeated START condition must be the same as the previous slave address. Consecutive (page) write mode is supported if the Master sends several data bytes following a slave register address. The 2-WIRE control block then increments the address pointer to the next 2-WIRE address, stores the received data and sends an Acknowledge until the master sends the STOP condition. This is illustrated in Figure 26. Datasheet CFR0011-120-00 Revision 1.4 37 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter S SLAVEadr W A 7-bits 1 bit REGadr A 8-bits Master to Slave DATA 8-bits A DATA 1-bit A 8-bits DATA A 8-bits ………. A P Repeated writes Slave to Master S = START condition Sr = Repeat START condition P = STOP condition A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 26: 2-WIRE Page Write (SDA Line) Via control WRITE_MODE an alternate write mode can be configured. Register addresses and data are sent in alternation like in Figure 27 to support host repeated write operations that access several non-consecutive registers. Data will be stored at the previously received register address. An update of WRITE_MODE cannot be done without interruption within a transmission frame. Thus, if not previously selected or not set as OTP default, the activation of Repeated Write must be done with a regular write on WRITE_MODE followed by a stop condition. The next frame after a start condition can be written in Repeated Write. S SLAVEadr W A 7-bits 1 bit REGadr 8-bits Master to Slave A DATA 8-bits A REGadr 1-bit 8-bits A DATA 8-bits A ………. A P Repeated writes Slave to Master S = START condition Sr = Repeat START condition P = STOP condition A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 27: 2-WIRE Repeated Write (SDA Line) If a new START or STOP condition occurs within a message, the bus will return to IDLE-mode. Datasheet CFR0011-120-00 Revision 1.4 38 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 7.5 Internal Temperature Supervision To protect DA9213-A and DA9214-A from damage due to excessive power dissipation, the internal temperature is continuously monitored. There are three temperature thresholds: Table 12: Over-Temperature Thresholds Temperature Threshold Typical Temperature Setting Interrupt Event Status Bit Masking Bit TEMP_WARN 125 °C E_TEMP_WARN TEMP_WARN M_TEMP_WARN TEMP_CRIT 140 °C E_TEMP_CRIT TEMP_CRIT M_TEMP_CRIT TEMP_POR 150 °C When the junction temperature reaches the TEMP_WARN threshold, DA9213-A and DA9214-A will assert the bit TEMP_WARN and will generate the event E_TEMP_WARN. If not masked using bit M_TEMP_WARN, the output port nIRQ will be asserted. The status bit TEMP_WARN will remain asserted as long as the junction temperature remains higher than TEMP_WARN. When the junction temperature increases further to TEMP_CRIT, DA9213-A and DA9214-A will immediately disable the buck converter, assert the bit TEMP_CRIT, and will generate the event E_TEMP_CRIT. If not masked via bit M_TEMP_CRIT, the output port nIRQ will be asserted. The status bit TEMP_CRIT will remain asserted as long as the junction temperature remains higher than TEMP_CRIT. The buck converter will be kept disabled as long as the junction temperature is above TEMP_CRIT. It will not be automatically re-enabled even after the temperature drops below the valid threshold (even if the controlling GPI is asserted). A direct write into BUCKA_EN or BUCKB_EN, or a toggling of the controlling GPI, is needed to enable the buck converter. Whenever the junction temperature exceeds TEMP_POR, a power on reset to the digital core is immediately asserted, which will stops all functionalities of DA9213-A and DA9214-A. This is needed to prevent possible permanent damage in the case of a rapid temperature increase. Datasheet CFR0011-120-00 Revision 1.4 39 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 8 8.1 Register Definitions Register Map Table 13 displays the register map, where all bits loaded from OTP are marked in bold. Datasheet CFR0011-120-00 Revision 1.4 40 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Table 13: Register Map A ddr F unc t io n 7 6 5 4 3 2 1 0 Register Page 0 REVERT WRITE_M ODE Reserved REG_P A GE 0x00 P A GE_CON Reserved 0x50 STA TUS_A Reserved Reserved Reserved GP I4 GP I3 GP I2 GP I1 GP I0 0x51 STA TUS_B RA M P _REA DY_B RA M P _REA DY_A OV_CURR_B OV_CURR_A TEM P _CRIT TEM P _WA RN P WRGOOD_B P WRGOOD_A 0x52 EVENT_A Reserved E_UVLO_IO Reserved E_GP I4 E_GP I3 E_GP I2 E_GP I1 E_GP I0 0x53 EVENT_B Reserved Reserved E_OV_CURR_B E_OV_CURR_A E_TEM P _CRIT E_TEM P _WA RN E_P WRGOODB E_P WRGOOD_A 0x54 M A SK_A Reserved M _ UV LO _ IO Reserved M _ G P I4 M _ G P I3 M _ G P I2 M _ G P I1 M _ G P I0 0x55 M A SK_B Reserved Reserved M _ O V _ C UR R _ B M _ O V _ C UR R _ A M _ T E M P _ C R IT M _ T E M P _ WA R N M _ P WR G O O D _ B M _ P WR G O O D _ A 0x56 CONTROL_A V _ LO C K 0x57 Reserved Reserved Reserved 0x58 GP IO0-1 G P I1_ M O D E G P I1_ T Y P E S LE W_ R A T E _ B S LE W_ R A T E _ A Reserved Reserved D E B O UN C IN G Reserved Reserved G P I1_ P IN G P I0 _ M O D E G P I0 _ T Y P E Reserved G P I0 _ P IN Reserved 0x59 GP IO2-3 G P IO 3 _ M O D E G P IO 3 _ T Y P E G P IO 3 _ P IN G P IO 2 _ M O D E G P IO 2 _ T Y P E G P IO 2 _ P IN 0x5A GP IO4 Reserved Reserved Reserved G P I4 _ M O D E G P I4 _ T Y P E G P I4 _ P IN 0x5B Reserved Reserved Reserved Reserved Reserved Reserved 0x5C Reserved Reserved Reserved Reserved Reserved Reserved 0x5D B UCKA _CONT Reserved V B UC KA _ G P I V B UC KA _ S E L B UC KA _ P D _ D IS B UC KA _ G P I B UC KA _ E N 0x5E B UCKB _CONT Reserved V B UC KB _ G P I V B UC KB _ S E L B UC KB _ P D _ D IS B UC KB _ G P I B UC KB _ E N Reserved Reserved Reserved Reserved Reserved Reserved Register Page 1 0x80 P A GE_CON REVERT WRITE_M ODE Reserved REG_P A GE B UC KB _ ILIM B UC KA _ ILIM 0xD0 B UCK_ILIM 0xD1 B UCKA _CONF B UC KA _ D O WN _ C T R L B UC KA _ UP _ C T R L 0xD2 B UCKB _CONF B UC KB _ D O WN _ C T R L B UC KB _ UP _ C T R L 0xD3 B UCK_CONF Reserved Reserved Reserved P H _SH _EN _B P H _SH _EN _A P H A S E _ S E L_ B 0xD4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0xD5 VB UCKA _M A X Reserved V B UC KA _ M A X 0xD6 VB UCKB _M A X Reserved V B UC KB _ M A X 0xD7 VB UCKA _A B UC KA _ S L_ A V B UC KA _ A 0xD8 VB UCKB _B B UC KA _ S L_ B V B UC KA _ B 0xD9 VB UCKB _A B UC KB _ S L_ A V B UC KB _ A 0xDA VB UCKB _B B UC KB _ S L_ B B UC KA _ M O D E B UC KB _ M O D E P H A S E _ S E L_ A Reserved V B UC KB _ B Register Page 2 REG_P A GE 0x100 P A GE_CON REVERT WRITE_M ODE Reserved Reserved Reserved 0x101 OTP _CONT Reserved Reserved Reserved Reserved P C_DONE OTP _A P P S_RD Reserved OTP _TIM 0x102 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x103 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x104 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x105 INTERFA CE R / W_ P O L CP HA C P OL nC S _ P O L 0x106 INTERFA CE2 IF _ T Y P E P M _ IF _ H S M P M _ IF _ F M P P M _ IF _ V Reserved Reserved Reserved Reserved 0x140 OTP _CONT2 O T P _ C O N F _ LO C K O T P _ A P P S _ LO C K Reserved Reserved Reserved Reserved Reserved Reserved 0x141 OTP _A DDR 0x142 OTP _DA TA 0x143 CONFIG_A Reserved Reserved Reserved G P I_ V Reserved 0x144 CONFIG_B UV LO _ IO _ D IS P GB _D VC _M A SK P GA _D VC _M A SK 0x145 CONFIG_C Reserved Reserved Reserved 0x146 CONFIG_D 0x147 CONFIG_E 0x148 CONFIG_F Datasheet CFR0011-120-00 IF _ B A S E _ A D D R 1 OTP _A DDR OTP _DA TA B UC KB _ P G _ S E L S T A N D _ A LO N E 2 WIR E _ T O OC B _M A SK G P I4 _ P UP D B UC KA _ P G _ S E L Reserved Reserved Reserved IF _ B A S E _ A D D R 2 G P IO 3 _ P UP D 41 of 62 G P IO 2 _ P UP D R EA D YB _C ON F IR Q _ LE V E L R E LO A D _ F UN C _ E N G P I1_ P UP D G P I0 _ P UP D R EA D YA _C ON F O S C _ T UN E Reserved Reserved Revision 1.4 IR Q _ T Y P E OC A _M A SK Reserved A D D R _ S E L_ C O N F 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 8.2 Register Definitions 8.2.1 Register Page Control Register Bit 0x00 PAGE_CON Type Label Description 7 R/W REVERT Resets REG_PAGE to 000 after read/write access has finished 6 R/W WRITE_MODE 2-WIRE multiple write mode (Note 1) 0: Page Write Mode 1: Repeated Write Mode 5:3 R/W (reserved) 2 IC 00x: Selects Register 0x00 to 0xFF 01x: Selects Register 0x100 to 0x17F 2:0 R/W SPI 000: Selects Register 0x00 to 0x7F REG_PAGE 001: Selects Register 0x80 to 0xFF 010: Selects Register 0x100 to 0x17F >010: Reserved for production and test Note 1 8.2.2 Not used for 4-WIRE-IF Register Page 0 8.2.2.1 System Control and Event The STATUS registers report the current value of the various signals at the time that it is read out. Register Bit Type Label 0x50 STATUS_A 7:5 R (reserved) 4 R GPI4 GPI4 level 3 R GPI3 GPI3 level 2 R GPI2 GPI2 level 1 R GPI1 GPI1 level 0 R GPI0 GPI0 level Register Bit Type Label Description 0x51 STATUS_B 7 R RAMP_READY_B De-asserted during Buck A DVC, power up and power down 6 R RAMP_READY_A De-asserted during Buck B DVC, power up and power down 5 R OV_CURR_B Asserted as long as the current limit for Buck B is hit 4 R OV_CURR_A Asserted as long as the current limit for Buck A is hit 3 R TEMP_CRIT Asserted as long as the thermal shutdown threshold is reached 2 R TEMP_WARN Asserted as long as the thermal warning threshold is reached Datasheet CFR0011-120-00 Description Revision 1.4 42 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Register Bit Type Label Description 1 R PWRGOOD_B Asserted as long as the Buck B output voltage is in range 0 R PWRGOOD_A Asserted as long as the Buck A output voltage is in range The EVENT registers hold information about events that have occurred in DA9213-A and DA9214-A. Events are triggered by a change in the status register which contains the status of monitored signals. When an EVENT bit is set in the event register, the IRQ signal is asserted unless the event is masked by a bit in the mask register. The IRQ triggering event register will be cleared from the host by writing back its read value. New events occurring during clearing will be delayed before they are passed to the event register, ensuring that the host controller does not miss them. Register Bit Type Label 0x52 7 R (reserved) EVENT_A 6 R E_UVLO_IO 5 R (reserved) 4 R E_GPI4 GPI4 event according to active state setting 3 R E_GPI3 GPI3 event according to active state setting 2 R E_GPI2 GPI2 event according to active state setting 1 R E_GPI1 GPI1 event according to active state setting 0 R E_GPI0 GPI0 event according to active state setting Register Bit Type Label Description 0x53 7:6 R (reserved) EVENT_B 5 R E_OV_CURR_B OV_CURR Buck B caused event 4 R E_OV_CURR_A OV_CURR Buck A caused event 3 R E_TEMP_CRIT TEMP_CRIT caused event 2 R E_TEMP_WARN TEMP_WARN caused event 1 R E_PWRGOOD_B PWRGOOD loss at Buck B caused event 0 R E_PWRGOOD_A PWRGOOD loss at Buck A caused event Register Bit Type Label Description 0x54 7 R/W (reserved) MASK_A 6 R/W M_UVLO_IO 5 R/W (reserved) 4 R/W M_GPI4 Masks nIRQ interrupt at GPI4 3 R/W M_GPI3 Masks nIRQ interrupt at GPI3 2 R/W M_GPI2 Masks nIRQ interrupt at GPI2 1 R/W M_GPI1 Masks nIRQ interrupt at GPI1 0 R/W M_GPI0 Masks nIRQ interrupt at GPI0 Datasheet CFR0011-120-00 Description UVLO_IO caused the event Mask UVLO_IO caused nIRQ Revision 1.4 43 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Register Bit Type Label Description 0x55 7:6 R/W (reserved) MASK_B 5 R/W M_OV_CURR_B OV_CURR Buck B caused event 4 R/W M_OV_CURR_A OV_CURR Buck A caused event 3 R/W M_TEMP_CRIT TEMP_CRIT caused event 2 R/W M_TEMP_WARN TEMP_WARN caused event 1 R/W M_PWRGOOD_B PWRGOOD Buck B caused event 0 R/W M_PWRGOOD_A PWRGOOD Buck A caused event Register Bit Type Label Description 0x56 7 R/W V_LOCK 0: Allows host writes into registers 0xD0 to 0x14F CONTROL_A 1: Disables register 0xD0 to 0x14F re-programming from control interfaces 6:5 R/W SLEW_RATE_B Buck B DVC slewing is executed at 00: 10mV every 4.0 µs 01: 10mV every 2.0 µs 10: 10mV every 1.0 µs 11: 10mV every 0.5 µs 4:3 R/W SLEW_RATE_A Buck A DVC slewing is executed at 00: 10mV every 4.0 µs 01: 10mV every 2.0 µs 10: 10mV every 1.0 µs 11: 10mV every 0.5 µs 0:2 R/W DEBOUNCE Input signals debounce time: 000: no debounce time 001: 0.1 ms 010: 1.0 ms 011: 10 ms 100: 50 ms 101: 250 ms 110: 500 ms 111: 1000 ms 8.2.2.2 GPIO Control Register Bit Type Label Description 0x58 GPI0-1 7 R/W GPI1_MODE 0: GPI: debouncing off 1: GPI: debouncing on 6 R/W GPI1_TYPE 0: GPI: active low 1: GPI: active high 5:4 R/W GPI1_PIN 3 R/W GPI0_MODE PIN assigned to: Datasheet CFR0011-120-00 00: GPI >00: Reserved 0: GPI: debouncing off 1: GPI: debouncing on Revision 1.4 44 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Register Bit Type Label 2 R/W GPI0_TYPE Description 0: GPI: active low 1: GPI: active high PIN assigned to: 1:0 R/W 00: GPI 01: Track enable GPI0_PIN 1x: Reserved Register Bit Type Label Description 0x59 GPIO2-3 7 R/W GPIO3_MODE 6 R/W GPIO3_TYPE 0: GPI: debouncing off GPO: Sets output to passive level 1: GPI: debouncing on GPO: Sets output to active level 0: GPI/GPO: active low 1: GPI/GPO: active high PIN assigned to: 5:4 R/W 00: GPI 01: Reserved GPIO3_PIN 10: GPO (Open drain) 11: GPO (Push-pull) 3 R/W GPIO2_MODE 2 R/W GPIO2_TYPE 0: GPI: debouncing off GPO: Sets output to passive level 1: GPI: debouncing on GPO: Sets output to active level 0: GPI/GPO: active low 1: GPI/GPO: active high PIN assigned to: 1:0 R/W GPIO2_PIN 00: GPI 01: Reserved 10: GPO (Open drain) 11: GPO (Push-pull) Register Bit Type Label 0x5A GPI4 7:4 R/W (reserved) 3 R/W GPI4_MODE 2 R/W GPI4_TYPE 1:0 Datasheet CFR0011-120-00 R/W GPI4_PIN Description 0: GPI: debouncing off 1: GPI: debouncing on 0: GPI: active low 1: GPI: active high PIN assigned to: 00: GPI 01: Reserved 1x: Reserved Revision 1.4 45 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 8.2.2.3 Regulators Control Register Bit Type Label 0x5D BUCKA_CON T 7 R/W (reserved) Description Selects the GPI that specifies the target voltage of VBUCKA. This is VBUCKA_A on active to passive transition, VBUCKA_B on passive to active transition. Active high/low is controlled by GPIx_TYPE. 6:5 R/W VBUCKA_GPI 00: Not controlled by GPIO 01: GPIO1 controlled 10: GPIO2 controlled 11: GPIO4 controlled 4 R/W VBUCKA_SEL Buck A voltage is selected from (ramping): 0: VBUCKA_A 1: VBUCKA_B 3 2:1 R/W R/W BUCKA_PD_DIS 0: Enable pull-down resistor of Buck A when the buck is disabled 1: Disable pull-down resistor of Buck A when the buck is disabled GPIO enables the Buck A on passive to active state transition, disables the Buck A on active to passive state transition 00: Not controlled by GPIO BUCKA_GPI 01: GPIO0 controlled 10: GPIO1 controlled 11: GPIO3 controlled 0 R/W BUCKA_EN Register Bit Type Label 0x5E 7 R/W (reserved) 0: Buck A disabled 1: Buck A enabled Description BUCKB_CON T Selects the GPI that specifies the target voltage of VBUCKB. This is VBUCKB_A on active to passive transition, VBUCKB_B on passive to active transition. Active high/low is controlled by GPIx_TYPE. 6:5 R/W VBUCKB_GPI 00: Not controlled by GPIO 01: GPIO1 controlled 10: GPIO2 controlled 11: GPIO4 controlled 4 R/W VBUCKB_SEL Buck A voltage is selected from (ramping): 0: VBUCKB_A 1: VBUCKB_B Datasheet CFR0011-120-00 3 R/W BUCKB_PD_DIS 2:1 R/W BUCKB_GPI 0: Enable pull-down resistor of Buck B when the buck is disabled 1: Disable pull-down resistor of Buck B when the buck is disabled GPIO enables the Buck B on passive to active state transition, disables the Buck B on active to passive state transition Revision 1.4 46 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Register Bit Type Label Description 00: Not controlled by GPIO 01: GPIO0 controlled 10: GPIO1 controlled 11: GPIO3 controlled 0 8.2.3 R/W 0: Buck B disabled BUCKB_EN 1: Buck B enabled Register Page 1 Register Bit Type Label Description 0x80 PAGE_CON 7 R/W REVERT Resets REG_PAGE to 000 after read/write access has finished 6 R/W WRITE_MODE 2-WIRE multiple write mode 0: Page Write Mode 1: Repeated Write Mode 5:3 R/W (reserved) 2 IC 00x: Selects Register 0x00 to 0xFF 01x: Selects Register 0x100 to 0x17F 2:0 R/W REG_PAGE SPI 000: Selects Register 0x00 to 0x7F 001: Selects Register 0x80 to 0xFF 010: Selects Register 0x100 to 0x17F >010: Reserved for production and test 8.2.3.1 Regulators Settings Register Bit Type Label Description 0xD0 Current limit per phase: BUCK_ILIM 0000: 4000 mA 0001: 4200 mA 0010: 4400 mA 7:4 R/W BUCKB_ILIM continuing through… 1001: 5800 mA to… 1110: 6800 mA 1111: 7000 mA Current limit per phase: 0000: 4000 mA 0001: 4200 mA 0010: 4400 mA 3:0 R/W BUCKA_ILIM continuing through… 1001: 5800 mA to… 1110: 6800 mA Datasheet CFR0011-120-00 Revision 1.4 47 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Register Bit Type Label Description 1111: 7000 mA Register Bit Type Label Description 0xD1 Buck A voltage ramping during power down BUCKA_CON F 000: 1.25 mV/µs 001: 2.5 mV/µs 7:5 R/W BUCKA_DOWN_ CTRL 010: 5 mV/µs 011: 10 mV/µs 100: 20 mV/µs 101: 30 mV/µs 110: 40 mV/µs 111: Reserved Buck A voltage ramping during start up 000: 1.25 mV/µs 001: 2.5 mV/µs 4:2 R/W BUCKA_UP_CTR L 010: 5 mV/µs 011: 10 mV/µs 100: 20 mV/µs (Note 2) 101: 30 mV/µs 110: 40 mV/µs 111: target voltage applied immediately (no soft start) 00: PFM/PWM mode controlled via voltage A and B registers 1:0 R/W BUCKA_MODE 01: Automatic mode 10: Buck A always operates in PWM mode 11: Automatic mode Note 2 Settings higher than 20 mV/µs may cause significant overshoot Register Bit Type Label Description 0xD2 Buck B voltage ramping during power down BUCKB_CON F 000: 1.25 mV/µs 001: 2.5 mV/µs 7:5 R/W BUCKB_DOWN_ CTRL 010: 5 mV/µs 011: 10 mV/µs 100: 20 mV/µs 101: 30 mV/µs 110: 40 mV/µs 111: Reserved Buck B voltage ramping during start up 000: 1.25 mV/µs 4:2 R/W BUCKB_UP_CTR L 001: 2.5 mV/µs 010: 5 mV/µs 011: 10 mV/µs 100: 20 mV/µs (Note 3) 101: 30 mV/µs 110: 40 mV/µs 111: target voltage applied immediately (no soft start) Datasheet CFR0011-120-00 Revision 1.4 48 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Register Bit 1:0 Type R/W Label Description BUCKB_MODE 00: PFM/PWM mode controlled via voltage A and B registers 01: Automatic mode 10: Buck B always operates in PWM mode 11: Automatic mode Note 3 Settings higher than 20mV/µs may cause significant overshoot Register Bit Type Label Description 0xD3 7:5 R/W (reserved) 4 R/W PH_SH_EN_B Enable current dependent phase shedding in PWM for Buck B 3 R/W PH_SH_EN_A Enable current dependent phase shedding in PWM for Buck A 2 R/W PHASE_SEL_B BUCK_CONF Phase selection for Buck B in PWM 1:0 R/W PHASE_SEL_A Register Bit Type Label 0xD5 VBUCKA_MA X 7 R/W (reserved) 0: 1 phase is selected 1: 2 phases are selected Phase selection for Buck A in PWM mode. Settings >01 apply only for DA9213-A otherwise the number of phases is limited to max 2 00: 1 phase is selected 01: 2 phases are selected 10: 3 phases are selected (uneven 0/90/180 phase shift) 11: 4 phases are selected Description Sets the maximum voltage allowed for Buck A (OTP programmed, access only in test mode) 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V 6:0 R VBUCKA_MAX Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Register Bit Type Label 0xD6 7 R/W (reserved) VBUCKB_MA 6:0 R VBUCKB_MAX Datasheet CFR0011-120-00 Description Sets the maximum voltage allowed for Buck B (OTP Revision 1.4 49 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Register Bit Type Label Description X programmed, access only in test mode) 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Register Bit Type Label Description BUCKA_SL_A 0: Configures Buck A to PWM mode whenever selecting A voltage setting 1: Configures Buck A to automatic mode whenever selecting A voltage setting 0xD7 VBUCKA_A 7 R/W 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V 6:0 R/W Continuing through… 1000110: 1.0 V VBUCKA_A to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Register 0xD8 VBUCKA_B Bit 7 Type R/W Label Description BUCKA_SL_B 0: Configures Buck A to PWM mode, whenever selecting B voltage setting 1: Configures Buck A to automatic mode, whenever selecting B voltage setting 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V 6:0 R/W VBUCKA_B Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Datasheet CFR0011-120-00 Revision 1.4 50 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Register Bit Type Label Description BUCKB_SL_A 0: Configures Buck B to PWM mode, whenever selecting A voltage setting 1: Configures Buck B to automatic mode, whenever selecting A voltage setting 0xD9 VBUCKB_A 7 R/W 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V 6:0 R/W Continuing through… 1000110: 1.0 V VBUCKB_A to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Register 0xDA VBUCKB_B Bit 7 Type R/W Label Description BUCKB_SL_B 0: Configures Buck B to PWM mode, whenever selecting B voltage setting 1: Configures Buck B to automatic mode, whenever selecting B voltage setting 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V 6:0 R/W VBUCKB_B Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Datasheet CFR0011-120-00 Revision 1.4 51 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 8.2.4 Register Page 2 Register Bit Type Label Description 0x100 PAGE_CON 7 R/W REVERT Resets REG_PAGE to 000 after read/write access has finished 6 R/W 2-WIRE multiple write mode 0: Page Write Mode WRITE_MODE 1: Repeated Write Mode 5:3 R/W (reserved) 2 IC 00x: Selects Register 0x00 to 0xFF 01x: Selects Register 0x100 to 0x17F 2:0 R/W SPI 000: Selects Register 0x00 to 0x7F REG_PAGE 001: Selects Register 0x80 to 0xFF 010: Selects Register 0x100 to 0x17F >010: Reserved for production and test 8.2.4.1 Interface and OTP Settings (shared with DA9063) Register Bit Type Label Description 0x101 OTP_CONT 7:4 R/W (reserved) 3 R/W PC_DONE Asserted from Power Commander software after the emulated OTP read has finished, automatically cleared when leaving emulated OTP read 2 R/W OTP_APPS_RD Reads on assertion application specific registers 0x105, 0x106, 0x143 to 0x149 and OTP_APPS_LOCK) from OTP 1 R/W (reserved) 0 R/W OTP_TIM OTP read timing: 0: normal read 1: marginal read (for OTP fuse verification) Register Bit Type Label Description 0x105 INTERFACE 4 MSB of 2-WIRE control interfaces base address XXXX0000 11010000 = 0xD0 write address of PM 2-WIRE interface (page 0 and 1) 11010001 = 0xD1 read address of PM 2-WIRE interface (page 0 and 1) 7:4 R/W IF_BASE_ADDR1 11010010 = 0xD2 write address of PM-2-WIRE interface (page 2 and 3) 11010011 = 0xD3 read address of PM-2-WIRE interface (page 2 and 3) Code ‘0000’ is reserved for unprogrammed OTP (triggers start-up with hardware default interface address) 3 Datasheet CFR0011-120-00 R/W R/W_POL 4-WIRE: Read/Write bit polarity 0: Host indicates reading access via R/W bit = ‘0’ Revision 1.4 52 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Register Bit Type Label Description 1: Host indicates reading access via R/W bit = ‘1’ 2 R/W CPHA 4-WIRE interface clock phase (see Table 10) 1 R/W CPOL 0 R/W nCS_POL 0: nCS is low active 1: nCS is high active Bit Type Label Description IF_TYPE 0: Power manager interface is 4-WIRE. Automatically configures GPIO3 and GPI4 as interface signals. The GPIO configuration is overruled. 4-WIRE interface clock polarity 0: SK is low during idle 1: SK is high during idle 4-WIRE chip select polarity Register 0x106 INTERFACE2 7 R/W 1: Power manager interface is 2-WIRE 8.2.4.2 6 R/W PM_IF_HSM Enables continuous high speed mode on 2-WIRE interface if asserted (no master code required) 5 R/W PM_IF_FMP Enables 2-WIRE interface operating with fast mode+ timings if asserted 4 R/W PM_IF_V 0:3 R/W (reserved) 0: Power manager interface in 2-WIRE mode is supplied from VDDCORE (4-WIRE always from VDDIO) 1: Power manager interface in 2-WIRE mode is supplied from VDDIO (4-WIRE always from VDDIO) OTP Fusing Registers Register Bit Type Label Description 0x140 OTP_CONT2 7 6 R/W R/W OTP_CONF_LOC K OTP_APPS_LOC K 0: Registers 0x54 to 0x5E and 0xD0 to 0xDA are not locked for OTP programming (should be selected for unmarked evaluation samples) 1: Registers 0x54 to 0x5E and 0xD0 to 0xDA are locked in OTP (no further fusing possible) 0: Registers 0x105, 0x106, 0x143 to 0x149 are not locked for OTP programming (should be selected for unmarked evaluation samples) 1: Registers 0x105, 0x106, 0x143 to 0x149 are locked in OTP (no further fusing possible) 5:0 R/W (reserved) Bit Type Label Description 7:0 R/W OTP_ADDR OTP Array address Register Bit Type Label Description 0x142 7:0 R/W OTP_DATA OTP read/write data Register 0x141 OTP_ADDR Datasheet CFR0011-120-00 Revision 1.4 53 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Register Bit Type Label Description OTP_DATA 8.2.4.3 OTP_DATA written to OTP_ADDR selects the IC and accepts unlock sequence (1 + 3 bytes) Application Configuration Settings Register Bit Type Label 0x143 CONFIG_A 7:5 R/W (reserved) 4 R/W 2WIRE_TO 3 R/W GPI_V Description Enables automatic reset of 2-WIRE interface if the clock stays low for >35 ms 0: Disabled 1: Enabled GPIs are supplied from: 0: VDDCORE 1: VDDIO 2 R/W (reserved) 1 R/W IRQ_TYPE 0 R/W IRQ_LEVEL nIRQ output port is: 0: Push-pull 1: Open drain (requires external pull-up resistor) nIRQ output port is: 0: Active low 1: Active high Register Bit Type Label Description 7 R/W UVLO_IO_DIS Disable the UVLO for the VDDIO rail and its comparator (suggested for rail voltages different to 1.8 V and to save quiescent current) PGB_DVC_MASK Power-good configuration for Buck B 0: Power-good signal not masked during DVC transitions 1: Power-good signal masked during DVC transitions (keep previous status) 0x144 CONFIG_B 6 R/W Power-good configuration for Buck A 5 R/W PGA_DVC_MASK 0: Power-good signal not masked during DVC transitions 1: Power-good signal masked during DVC transitions (keep previous status) Over Current configuration for Buck B 00: Event generation due to over current hit is always active during DVC transitions of the Buck converter 4:3 R/W OCB_MASK 01: Event generation due to over current hit is masked during DVC transitions of the buck converter + 2 µs extra masking at the end 10: Event generation due to over current hit is masked during DVC transitions of the buck converter + 10 µs extra masking at the end 11: Event generation due to over current hit is masked during DVC transitions of the buck converter + 50 µs extra masking at the end 2:1 Datasheet CFR0011-120-00 R/W OCA_MASK Over Current configuration for Buck A Revision 1.4 54 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Register Bit Type Label Description 00: Event generation due to over current hit is always active during DVC transitions of the buck converter 01: Event generation due to over current hit is masked during DVC transitions of the buck converter + 2 µs extra masking at the end 10: Event generation due to over current hit is masked during DVC transitions of the buck converter + 10 µs extra masking at the end 11: Event generation due to over current hit is masked during DVC transitions of the buck converter + 50 µs extra masking at the end 0 R/W RELOAD_FUNC_ EN Enable the OTP re-load function for GPIO0 when configured as input port Register Bit Type Label Description 0x145 CONFIG_C 7:5 R/W (reserved) 4 R/W GPI4_PUPD 3 R/W 0: GPI: pull-down resistor disabled 1: GPI: pull-down resistor enabled GPIO3_PUPD 0: GPI: pull-down resistor disabled GPO (open drain): pull up resistor disabled (external pull-up resistor) 1: GPI: pull-down resistor enabled GPO (open drain): pull up resistor 2 R/W GPIO2_PUPD 0: GPI: pull-down resistor disabled GPO (open drain): pull up resistor disabled (external pull-up resistor) 1: GPI: pull-down resistor enabled GPO (open drain): pull up resistor enabled Register 1 R/W GPI1_PUPD 0: GPI: pull-down resistor disabled 1: GPI: pull-down resistor enabled 0 R/W GPI0_PUPD 0: GPI: pull-down resistor disabled 1: GPI: pull-down resistor enabled Bit Type Label Description 0x146 CONFIG_D Selection of the PG signal for Buck B 00: none 7:6 R/W BUCKB_PG_SEL 01: GPO2 10: GPO3 11: reserved Selection of the PG signal for Buck A 5:4 R/W BUCKA_PG_SEL 00: none 01: GPO2 10: GPO3 11: reserved Selection of the READY signal for Buck B 3:2 R/W READYB_CONF 00: none 01: GPO2 10: GPO3 Datasheet CFR0011-120-00 Revision 1.4 55 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Register Bit Type Label Description 11: reserved Selection of the READY signal for Buck A 00: none 1:0 R/W READYA_CONF 01: GPO2 10: GPO3 11: reserved Register Bit Type Label Description 0: DA9213-A and DA9214-A is used as companion IC to DA9063 or DA9063-compliant 1: DA9213-A and DA9214-A is stand alone or as companion IC with another PMU not DA9063-compliant 0x147 CONFIG_E 7 R/W STAND_ALONE 6:5 R/W (reserved) 4:3 R/W (reserved) Tune the main 6 MHz oscillator frequency: 000: no tune 001: +180 kHz 010: +360 kHz 2:0 R/W OSC_TUNE 011: +540 kHz 100: +720 kHz 101: +900 kHz 110: +1080 kHz 111: +1260 kHz Register Bit Type Label Description 2 0x148 If a second I C address is to be selected on ADR_SEL_CONF, this field configures the second address. CONFIG_F 4 MSB of 2-WIRE control interfaces base address XXXX0000 11010000 = 0xD0 write address of PM 2-WIRE interface (page 0 and 1) 7:4 R/W IF_BASE_ADDR2 11010001 = 0xD1 read address of PM 2-WIRE interface (page 0 and 1) 11010010 = 0xD2 write address of PM-2-WIRE interface (page 2 and 3) 11010011 = 0xD3 read address of PM-2-WIRE interface (page 2 and 3) Code ‘0000’ is reserved for unprogrammed OTP (triggers start-up with hardware default interface address) 3:2 R (reserved) 2 1 R/W ADDR_SEL_CON F Selects the GPI for the alternative I C address selection: 00: none 01: GPI0 10: GPI1 11: GPI4 Datasheet CFR0011-120-00 Revision 1.4 56 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 9 Application Information The following recommended components are examples selected from requirements of a typical application. 9.1 Capacitor Selection Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a capacitor, especially for types with high capacitance at smallest physical dimension, the DC bias characteristic has to be taken into account. Table 14: Recommended Capacitor Types Application VOUT output bypass Value Size Temp Char Tol V-Rate Type 47 uF 1210 X7R +/-15 % +/-10 % 6.3 V Murata GCM32ER70J476KE19 22 uF 1206 X7R +/-15 % +/-10 % 6.3 V Murata GCM31CR70J226KE23 10 uF 0805 X7R +/-15 % +/-10 % 6.3 V Murata GCM21BR70J106KE22 VDDx bypass 10 uF 0805 X7R +/-15 % +/-10 % 10 V Murata GCM21BR71A106KE22 VSYS bypass 1 uF 0603 X7R +/-15 % +/-10 % 16 V Murata GCM188R71C105KA64 VDDIO bypass 100 nF 0402 X7R +/-15 % +/-10 % 50 V Murata GCM155R71H104KE02 Datasheet CFR0011-120-00 Revision 1.4 57 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 9.2 Inductor Selection Inductors should be selected based upon the following parameters: ● Rated max. current: usually a coil provides two current limits: The Isat specifies the maximum current at which the inductance drops by 30% of the nominal value. The Imax is defined by the maximum power dissipation and is applied to the effective current. ● DC resistance: critical for the converter efficiency and should therefore be minimized. Table 15: Recommended Inductor Types Application BUCK Datasheet CFR0011-120-00 Value Size Imax(dc) Isat Tol DC res Type 0.22 uH 2.5 mm x 2.0 mm x 1.0 mm 7.1 A 8.0 A +/-20% 12 mΩ TDK TFM252010ALMAR22MT AA 0.22 uH 2.5 mm x 2.0 mm x 1.2 mm 8.5 A 10 A +/-20% 8 mΩ TDK TFM252012ALMAR22MT AA 0.24 uH 2.0 mm x 1.6 mm x 1.0 mm 7.0 A 7.5 A +/-20% 15 mΩ TDK TFM201610ALMAR24MT AA 0.24 uH 2.0 mm x 1.6 mm x 1.2 mm 4.8 A 5.9 A +/-20% 16 mΩ TOKO DFE201612PDR24M 0.47 uH 2.5 mm x 2.0 mm x 1.0 mm 5.4 A 6.5 A +/-20% 20 mΩ TDK TFM252010ALMAR47MT AA 0.47 uH 2.5 mm x 2.0 mm x 1.2 mm 5.6 A 6.5 A +/-20% 19 mΩ TDK TFM252012ALMAR47MT AA 0.47 uH 2.5 mm x 2.0 mm x 1.2 mm 4.7 A 6.1 A +/-20% 21 mΩ TOKO DFE252012PDR47M 0.47 uH 2.0 mm x 1.6 mm x 1.0 mm 5.0 A 5.8 A +/-20% 28 mΩ TDK TFM201610ALMAR47MT AA 0.47 uH 2.0 mm x 1.6 mm x 1.2 mm 3.8 A 4.5 A +/-20% 26 mΩ TOKO DFE201612PDR47M 0.24 uH 2.0 mm x 1.6 mm x 1.2 mm 5.0 A 7.7 A +/-20% 16 mΩ Taiyo Yuden MEMK2016TR24MV 0.47 uH 2.0 mm x 1.6 mm x 1.2 mm 3.8 A 5.5 A +/-20% 28 mΩ Taiyo Yuden MEMK2016TR47MV 0.24 uH 2.5 mm x 2.0 mm x 1.2 mm 5.9 A 8.5 A +/-20% 13 mΩ Taiyo Yuden MEMK2520TR24MV 0.47 uH 2.5 mm x 2.0 mm x 1.2 mm 4.7 A 6.2 A +/-20% 21 mΩ Taiyo Yuden MEMK2520TR47MV Revision 1.4 58 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 10 Package Information 10.1 Package Outlines Figure 28: DA9213-A/14-A VFBGA Package Outline Drawing Datasheet CFR0011-120-00 Revision 1.4 59 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter 11 Ordering Information The ordering number consists of the part number followed by a suffix indicating the packing method. For details and availability, please consult Dialog Semiconductor’s customer portal or your local sales representative. Table 16: Ordering Information Part Number Package Package Description Comment Package Outline DA9213-xxFS1-A 66 VFBGA Tray Auto Grade 2 Figure 28 DA9213-xxFS2-A 66 VFBGA T&R, 5000pcs Auto Grade 2 DA9214-xxFS1-A 66 VFBGA Tray Auto Grade 2 DA9214-xxFS2-A 66 VFBGA T&R, 5000pcs Auto Grade 2 DA9213-xxFS1-AT 66 VFBGA Tray Auto Grade 2 with HighTemp screening DA9213-xxFS2-AT 66 VFBGA T&R, 5000pcs Auto Grade 2 with HighTemp screening DA9214-xxFS1-AT 66 VFBGA Tray Auto Grade 2 with HighTemp screening DA9214-xxFS2-AT 66 VFBGA T&R, 5000pcs Auto Grade 2 with HighTemp screening Datasheet CFR0011-120-00 Revision 1.4 60 of 62 Figure 28 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Revision History Revision Date Description 1.0 17-Nov-2016 Initial version. 1.1 10-Feb-2017 Updated specifications. 1.2 22-Feb-2017 Updated ordering information table and UVLO @VDDIO spec. 1.3 24-Mar-2017 Updated power dissipation spec. Added automotive disclamer. Added Tj_max. Added applications info. 1.4 08-May-2017 Updated power dissipation spec. Added Theta-JA and power derating curve. Status Definitions Revision Datasheet Status Product Status Definition 1.<n> Target Development This datasheet contains the design specifications for product development. Specifications may be changed in any manner without notice. 2.<n> Preliminary Qualification This datasheet contains the specifications and preliminary characterization data for products in pre-production. Specifications may be changed at any time without notice in order to improve the design. 3.<n> Final Production This datasheet contains the final specifications for products in volume production. The specifications may be changed at any time in order to improve the design, manufacturing and supply. Major specification changes are communicated via Customer Product Notifications. Datasheet changes are communicated via www.dialog-semiconductor.com. 4.<n> Obsolete Archived This datasheet contains the specifications for discontinued products. The information is provided for reference only. Datasheet CFR0011-120-00 Revision 1.4 61 of 62 08-May-2017 © 2017 Dialog Semiconductor DA9213-A and DA9214-A Auto Grade Multi-Phase 5A/Phase Buck Converter Disclaimer Suitability for use in automotive applications — This Dialog Semiconductor product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Dialog Semiconductor product can reasonably be expected to result in personal injury, death or severe property or environmental damage. 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Phone: +81 3 5425 4567 Hong Kong Dialog Semiconductor Hong Kong Phone: +852 3769 5200 China (Shanghai) Dialog Semiconductor China Phone: +86 21 5424 9058 The Netherlands Dialog Semiconductor B.V. Phone: +31 73 640 8822 Taiwan Dialog Semiconductor Taiwan Phone: +886 281 786 222 Korea Dialog Semiconductor Korea Phone: +82 2 3469 8200 Email: [email protected] Web site: www.dialog-semiconductor.com Datasheet CFR0011-120-00 Revision 1.4 62 of 62 08-May-2017 © 2017 Dialog Semiconductor