IDT IDT5V994JI 3.3v programmable skew pll clock driver turboclock-tm plus Datasheet

IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK™ PLUS
FEATURES:
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DESCRIPTION
Ref input is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Input frequency: 17.5MHz to 133MHz
Output frequency: 17.5MHz to 133MHz
2x, 4x, 1/2, and 1/4 outputs (of VCO frequency)
3-level inputs for skew control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <200ps cycle-to-cycle
Available in PLCC and TQFP packages
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IDT5V994
The IDT5V994 is a high fanout 3.3V PLL based clock driver intended for
high performance computing and data-communications applications. A key
feature of the programmable skew is the ability of outputs to lead or lag the
REF input signal. The IDT5V994 has eight programmable skew outputs in
four banks of 2. Skew is controlled by 3-level input signals that may be hardwired to appropriate HIGH-MID-LOW levels.
When the sOE pin is held low, all the outputs are synchronously enabled.
However, if sOE is held high, all the outputs except 3Q0 and 3Q1 are
synchronously disabled.
Furthermore, when the PE is held high, all the outputs are synchronized
with the positive edge of the REF clock input. When PE is held low, all the
outputs are synchronized with the negative edge of REF. The IDT5V994
has LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
sO E
1Q 0
Skew
Select
3
1Q 1
3
1F1:0
PE TEST
2Q 0
Skew
Select
3
REF
2Q 1
3
PLL
2F1:0
FB
3Q 0
Skew
Select
3
3Q 1
3
3F1:0
4Q 0
Skew
Select
3
4Q 1
3
4F1:0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
AUGUST 2002
1
c
2002
Integrated Device Technology, Inc.
DSC 5828/4
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
29
2F0
4F0
6
28
sO E
4F1
7
27
1F1
PE
8
26
1F0
V DDQ
9
25
V DDQ
4Q 1
10
24
1Q 0
4Q 0
11
23
1Q 1
G ND
12
22
G ND
G ND
13
21
G ND
PLCC
TOP VIEW
Description
Max
VDDQ, VDD Supply Voltage to Ground–0.5 to +4.6
VI
–0.5 to VDD+0.5
V
REF Input Voltage
–0.5 to +5.5
V
0.8
W
–65 to +150
°C
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter
CIN
Description
Input Capacitance
REF
G ND
TEST
2F1
2F0
29
28
27
26
25
3F1
1
24
sO E
4F0
2
23
1F1
4F1
3
22
1F0
PE
4
21
V DDQ
V DDQ
5
20
1Q 0
4Q 1
6
19
1Q 1
4Q 0
7
18
G ND
G ND
8
17
G ND
13
14
15
16
2Q 1
2Q 0
3Q 0
12
V DDQ
11
FB
10
V DDQ
9
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit tU which is of the
order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF1:0 control pins. In order
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF1:0 control pins.
Unit
DC Input Voltage
Storage Temperature Range
30
PROGRAMMABLE SKEW
V
Maximum Power Dissipation, TA = 85°C
TSTG
31
TQFP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
32
20
2Q0
19
2Q1
18
V DDQ
17
FB
16
V DDQ
3Q0
15
3Q1
14
V DD
30
V DD
31
3Q 1
32
5
3F0
1
3F1
G ND
REF
2
2F1
V DD
3
TEST
V DD
4
GND
3F0
PIN CONFIGURATIONS
Typ.
Max.
Unit
5
7
pF
NOTE:
1. Capacitance applies to all inputs except TEST, FS, and nF[1:0].
2
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
Type
Description
REF
IN
Reference Clock Input
FB
IN
Feedback Input
TEST (1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary
Table) remain in effect. Set LOW for normal operation.
sOE(1)
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act as output disable
controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation.
PE
IN
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference
nF[1:0]
IN
3-level inputs for selecting 1 of 9 skew taps or frequency functions
clock.
nQ[1:0]
OUT
Four banks of two outputs with programmable skew
VDDQ
PWR
Power supply for output buffers
VDD
PWR
Power supply for phase locked loop and other internal circuitry
GND
PWR
Ground
NOTE:
1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in
effect unless nF[1:0] = LL.
EXTERNAL FEEDBACK
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
By providing external feedback, the IDT5V994 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
Comments
Timing Unit Calculation (tU)
1/(16 x FNOM)
VCO Frequency Range (FNOM)(1,2)
70 to 133MHz
Skew Adjustment Range(2)
Max Adjustment:
±5.36ns
ns
±135°
Phase Degrees
±37.5%
% of Cycle Time
Example 1, FNOM = 80MHz
tU = 0.78ns
Example 2, FNOM = 100MHz
tU = 0.63ns
Example 3, FNOM = 133MHz
tU = 0.47ns
NOTES:
1. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs
will be FNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication
by using a divided output as the FB input. Using the nF[1:0] inputs allows a different method for frequency multiplication (see Control Summary Table for Feedback Signals).
2. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.
3
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
Skew (Pair #1, #2)
Skew (Pair #3)
Skew (Pair #4)
LL (1)
–4tU
Divide by 2
Divide by 2
LM
–3tU
–6tU
–6tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
MM
Zero Skew
Zero Skew
Zero Skew
MH
1tU
2tU
2tU
HL
2tU
4tU
4tU
HM
3tU
6tU
6tU
HH
4tU
Divide by 4
Inverted (2)
NOTES:
1. LL disables outputs if TEST = MID and sOE = HIGH.
2. When pair #4 is set to HH (inverted), sOE disables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW.
RECOMMENDED OPERATING RANGE
Symbol
Description
VDD/VDDQ
Power Supply Voltage
TA
Min.
Typ.
Max.
Unit
3
3.3
3.6
V
-40
+25
+85
°C
Ambient Operating Temperature
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Conditions
Min.
Max.
Unit
VIH
Input HIGH Voltage
Guaranteed Logic HIGH (REF, FB Inputs Only)
2
—
V
VIL
Input LOW Voltage
Guaranteed Logic LOW (REF, FB Inputs Only)
—
0.8
V
VDD−0.6
VIHH
Input HIGH Voltage
—
V
VIMM
Input MID Voltage(1)
3-Level Inputs Only
VDD/2−0.3
VDD/2+0.3
V
VILL
Input LOW Voltage(1)
3-Level Inputs Only
—
0.6
V
IIN
Input Leakage Current
VIN = VDD or GND
−5
+5
µA
(REF, FB Inputs Only)
VDD = Max.
(1)
3-Level Inputs Only
VIN = VDD
HIGH Level
3-Level Input DC Current
VIN = VDD/2
MID Level
(TEST, FS, nF[1:0], DS[1:0])
VIN = GND
LOW Level
—
+200
+50
—
µA
+100
µA
IPU
Input Pull-Up Current (PE)
VDD = Max., VIN = GND
−50
−200
−100
IPD
Input Pull-Down Current (sOE)
VDD = Max., VIN = VDD
—
VOH
Output HIGH Voltage
VDDQ = Min., IOH = −12mA
2.4
—
V
VOL
Output LOW Voltage
VDDQ = Min., IOL = 12mA
—
0.4
V
I3
µA
—
NOTE:
1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
4
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Test Conditions(1)
Symbol
Parameter
IDDQ
Quiescent Power Supply Current
VDD = Max., TEST = MID, REF = LOW,
Typ.
Max.
Unit
8
25
mA
PE = LOW, sOE = LOW
All outputs unloaded
∆IDD
Power Supply Current per Input HIGH
VDD = Max., VIN = 3V,
1
30
µA
IDDD
Dynamic Power Supply Current per Output
VDD/VDDQ = Max., CL = 0pF
55
90
µA/MHz
VDD/VDDQ = 3.3V , FREF = 83MHz, CL = 160pF(1)
31
—
VDD/VDDQ = 3.3V , FREF = 100MHz, CL = 160pF(1)
34
—
VDD/VDDQ = 3.3V , FREF = 133MHz, CL = 160pF(1)
39
—
I TOT
Total Power Supply Current
mA
NOTE:
1. For eight outputs, each loaded with 20pF.
INPUT TIMING REQUIREMENTS
Description(1)
Symbol
Min.
Max.
Unit
—
10
ns/V
Input clock pulse, HIGH or LOW
2
—
ns
Input duty cycle
10
90
%
17.5
133
MHz
tR, tF
Maximum input rise and fall times, 0.8V to 2V
tPWC
DH
FREF
Reference clock input frequency(2)
NOTES:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
2. The minimum reference clock input frequency is 70MHz if Q/2 or Q/4 are not used as feedback
5
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Min.
Typ.
Max.
Unit
FNOM
VCO Frequency Range
See Programmable Skew Range and Resolution Table
tRPWH
REF Pulse Width HIGH(1)
2
tRPWL
REF Pulse Width LOW
2
tU
(1)
Programmable Skew Time Unit
—
—
ns
—
—
ns
See Control Summary Table
tSKEWPR
Zero Output Matched-Pair Skew (xQ0, xQ1)(2,3)
—
0.05
0.2
ns
tSKEW0
Zero Output Skew (All Outputs)(4)
—
0.1
0.25
ns
tSKEW1
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
—
0.25
0.5
ns
tSKEW2
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)
—
0.3
1.2
ns
tSKEW3
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)(5)
—
0.25
0.5
ns
tSKEW4
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)
—
0.5
0.9
ns
—
—
0.75
ns
−0.25
−1.2
0
0.25
ns
0
1.2
ns
—
—
2
ns
tDEV
Device-to-Device Skew(2,6)
t(φ)
REF Input to FB Static Phase Offset)
(5)
(5)
(2)
(7)
tODCV
Output Duty Cycle Variation from 50%
tPWH
Output HIGH Time Deviation from 50%(8)
tPWL
Output LOW Time Deviation from 50%
—
—
2.5
ns
tORISE
Output Rise Time
0.15
1
1.8
ns
tOFALL
Output Fall Time
0.15
1
1.8
ns
tLOCK
PLL Lock Time
tJR
(9)
(10)
Cycle-to-Cycle Output Jitter (peak-to-peak)
—
—
0.5
ms
—
—
200
ps
NOTES:
1. Refer to Input Timing Requirements table for more detail.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSK(0) is the skew between outputs when they are selected for 0tU.
5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divideby-4 mode).
6. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
7. tφ is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.
8. Measured at 2V.
9. Measured at 0.8V.
10. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tφ is within specified limits.
6
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
AC TEST LOADS AND WAVEFORMS
V D DQ
150 Ω
Output
150 Ω
20p F
t O FA LL
t OR IS E
t PW H
2.0V
0.8V
tP W L
LVTTL Output Waveform
≤ 1ns
3.0V
2.0V
V TH = 1.5V
0.8V
0V
LVTTL Input Test Waveform
7
≤ 1ns
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
AC TIMING DIAGRAM
t R PW L
t R EF
t RP W H
REF
t (φ)
t O DC V
t O DC V
FB
t JR
Q
t S KEW PR
t SK EW 0, 1
t SKEW PR
t SK EW 0, 1
OTH ER Q
t S KEW 2
t SKE W 2
INV ER TED Q
t SK EW 3, 4
t SKEW 3, 4
t SK EW 3, 4
REF D IVIDED BY 2
t SK EW 1, 3, 4
t SK EW 2, 4
REF D IVIDED BY 4
NOTES:
PE:
The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge
of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated
with 75Ω to VDDQ/2.
tSKEWPR:
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSKEW0:
The skew between outputs when they are selected for 0tU.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
tODCV:
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tPWH is measured at 2V.
tPWL is measured at 0.8V.
tORISE and tOFALL are measured between 0.8V and 2V.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
8
IDT5V994
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XXXXX
Device Type
XX
Package
X
Package
I
-40°C to +85°C (Industrial)
J
PF
PFG
32-pin PLCC
32-pin TQFP
32-pin TQFP - Green
5V994
3.3V Programmable Skew PLL Clock
Driver TurboClock Plus
DATA SHEET DOCUMENT HISTORY
1/21/02 pages 1, 2, 4
CORPORATE HEADQUARTERS
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Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
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www.idt.com
9
for Tech Support:
[email protected]
(408) 654-6459
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