MC74HCT541A Octal 3-State Non-Inverting Buffer/Line Driver/ Line Receiver With LSTTL-Compatible Inputs http://onsemi.com High−Performance Silicon−Gate CMOS The MC74HCT541A is identical in pinout to the LS541. This device may be used as a level converter for interfacing TTL or NMOS outputs to high speed CMOS inputs. The HCT541A is an octal non−inverting buffer/line driver/line receiver designed to be used with 3−state memory address drivers, clock drivers, and other bus−oriented systems. This device features inputs and outputs on opposite sides of the package and two ANDed active−low output enables. Features • • • • • • • • MARKING DIAGRAMS 20 PDIP−20 N SUFFIX CASE 738 1 A1 A2 A3 Data Inputs A4 A5 18 1 3 17 20 4 16 5 15 6 14 7 13 8 12 Y3 Y4 Non-Inverting Outputs Y5 HCT 541A ALYWG G TSSOP−20 DT SUFFIX CASE 948E 20 1 1 20 SOEIAJ−20 F SUFFIX CASE 967 1 1 Y2 HCT541A AWLYYWWG 1 20 Y1 1 SOIC−20 DW SUFFIX CASE 751D LOGIC DIAGRAM 2 MC74HCT541AN AWLYYWWG 20 20 Output Drive Capability: 15 LSTTL Loads TTL/NMOS−Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1 mA In Compliance With the JEDEC Standard No. 7 A Requirements Chip Complexity: 134 FETs or 33.5 Equivalent Gates These Devices are Pb−Free and are RoHS Compliant 20 A WL, L YY, Y WW, W G or G 74HCT541A AWLYWWG = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) A6 A7 A8 Output Enables OE1 OE2 9 11 Y6 ORDERING INFORMATION Y7 See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Y8 1 19 © Semiconductor Components Industries, LLC, 2011 June, 2011 − Rev. 6 PIN 20 = VCC PIN 10 = GND 1 Publication Order Number: MC74HCT541A/D MC74HCT541A PINOUT: 20−LEAD PACKAGES VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 20 19 18 17 16 15 14 13 12 11 FUNCTION TABLE Inputs 1 2 3 4 5 6 7 8 9 10 OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND OE1 OE2 A L L H X L L X H L H X X Output Y L H Z Z Z = High Impedance X = Don’t Care (Top View) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit – 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 35 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air 750 500 mW Tstg Storage Temperature Range – 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP or SOIC Package 260 _C Plastic DIP† SOIC Package† Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min Max Unit 4.5 5.5 V 0 VCC V – 55 + 125 _C 0 500 ns DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Figure 1) http://onsemi.com 2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. MC74HCT541A DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition Guaranteed Limit VCC V −55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High−Level Input Voltage Vout = 0.1V or VCC − 0.1V |Iout| ≤ 20mA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low−Level Input Voltage Vout = 0.1V or VCC − 0.1V |Iout| ≤ 20mA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20mA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V 4.5 3.98 3.84 3.70 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 4.5 0.26 0.33 0.40 Vin = VIH or VIL VOL Maximum Low−Level Output Voltage |Iout| ≤ 6.0mA Vin = VIH or VIL |Iout| ≤ 20mA Vin = VIH or VIL |Iout| ≤ 6.0mA V Iin Maximum Input Leakage Current Vin = VCC or GND 5.5 ±0.1 ±1.0 ±1.0 mA IOZ Maximum 3−State Leakage Current Output in High Impedance State Vin = VIL or VIH Vout = VCC or GND 5.5 ±0.5 ±5.0 ±10.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0mA 5.5 4 40 160 mA DICC Additional Quiescent Supply Current Vin = 2.4V, Any One Input Vin = VCC or GND, Other Inputs Iout = 0mA 5.5 ≥ −55°C 25 to 125°C 2.9 2.4 mA 1. Total Supply Current = ICC + ΣDICC. AC CHARACTERISTICS (VCC = 5.0V, CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter −55 to 25°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 3) 23 28 32 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) 30 34 38 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) 30 34 38 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) 12 15 18 ns Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum 3−State Output Capacitance (Output in High Impedance State) 15 15 15 pF Typical @ 25°C, VCC = 5.0 V CPD 55 Power Dissipation Capacitance (Per Buffer)* * Used to determine the no−load dynamic power consumption: P D = CPD VCC http://onsemi.com 3 2f + ICC VCC . pF MC74HCT541A SWITCHING WAVEFORMS tf tr 3.0V 90% INPUT A 1.3V 10% GND tPLH tPHL 90% 1.3V OUTPUT Y 10% tTHL tTLH Figure 1. 3.0V OE1 or OE2 1.3V 1.3V GND tPZL OUTPUT Y tPLZ HIGH IMPEDANCE 1.3V 10% tPZH OUTPUT Y VOL tPHZ 90% VOH 1.3V HIGH IMPEDANCE Figure 2. TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance 1kW CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ and tPZH. *Includes all probe and jig capacitance Figure 3. Figure 4. http://onsemi.com 4 MC74HCT541A PIN DESCRIPTIONS INPUTS outputs are enabled and the device functions as a non−inverting buffer. When a high voltage is applied to either input, the outputs assume the high impedance state. A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9) — Data input pins. Data on these pins appear in non−inverted form on the corresponding Y outputs, when the outputs are enabled. OUTPUTS Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14, 13, 12, 11) — Device outputs. Depending upon the state of the output enable pins, these outputs are either non−inverting outputs or high−impedance outputs. CONTROLS OE1, OE2 (PINS 1, 19) — Output enables (active−low). When a low voltage is applied to both of these pins, the LOGIC DETAIL To 7 Other Buf fers VCC One of Eight Buffers INPUT A OUTPUT Y OE1 OE2 ORDERING INFORMATION Package Shipping† MC74HCT541ANG PDIP−20 (Pb−Free) 18 Units / Rail MC74HCT541ADWG SOIC−20 (Pb−Free) 38 Units / Rail MC74HCT541ADWR2G SOIC−20 (Pb−Free) 1000 / Tape & Reel MC74HCT541ADTR2G TSSOP−20* 2500 / Tape & Reel MC74HCT541AFG SOEIAJ−20 (Pb−Free) 40 Units / Rail MC74HCT541AFELG SOEIAJ−20 (Pb−Free) 2000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *These packages are inherently Pb−Free. http://onsemi.com 5 MC74HCT541A PACKAGE DIMENSIONS PDIP−20 N SUFFIX CASE 738−03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. −A− 20 11 1 10 B L C −T− K SEATING PLANE M N E G F J D 20 PL 20 PL 0.25 (0.010) 0.25 (0.010) M T A M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 M SOIC−20 DW SUFFIX CASE 751D−05 ISSUE G A 20 11 X 45 _ E h 1 10 20X B B 0.25 M T A S B S A L H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q B M D 18X e A1 SEATING PLANE C T http://onsemi.com 6 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74HCT541A PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B −U− PIN 1 IDENT 1 SECTION N−N 0.25 (0.010) N 10 M 0.15 (0.006) T U S N A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 7 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HCT541A PACKAGE DIMENSIONS SOEIAJ−20 F SUFFIX CASE 967−01 ISSUE A 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.81 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.032 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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