Freescale MC68SZ328P/D I.mx integrated portable system processor Datasheet

Freescale Semiconductor
Advance Information
MC9328MX1/D
Rev. 4, 08/2004
MC9328MX1/D
Rev. 3.0, 12/2003
MC9328MX1
(i.MX1) Integrated
Portable System
Processor
MC9328MX1
MC9328MX1
Package Information
Plastic Package
(MAPBGA–256)
Ordering Information
See Table 2 on page 5
1 Introduction
Motorola’s i.MX family of microprocessors has
demonstrated leadership in the portable handheld market.
Continuing this legacy, the i.MX series provides a leap in
performance with an ARM9™ microprocessor core and
highly integrated system functions. The i.MX products
specifically address the requirements of the personal,
portable product market by providing intelligent integrated
peripherals, an advanced processor core, and power
management capabilities.
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Signals and Connections . . . . . . . . . . . . . . . . . . . . 6
3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Pin-Out and Package Information . . . . . . . . . . . . 93
Contact Information . . . . . . . . . . . . . . . . . . . Last Page
The new MC9328MX1 features the advanced and powerefficient ARM920T™ core that operates at speeds up to
200 MHz. Integrated modules, which include an LCD
controller, static RAM, USB support, an A/D converter (with
touch panel control), and an MMC/SD host controller,
support a suite of peripherals to enhance any product seeking
to provide a rich multimedia experience. In addition, the
MC9328MX1 is the first Bluetooth™ technology-ready
applications processor. It is packaged in a 256-pin Mold
Array Process-Ball Grid Array (MAPBGA). Figure 1 on
page 2 shows the functional block diagram of the
MC9328MX1.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
This document contains information on a new product. Specifications and information herein are
subject to change without notice.
Introduction
System Control
JTAG/ICE
Bootstrap
Power
Control
Standard
System I/O
CGM
(DPLLx2)
GPIO
Connectivity
PWM
MC9328MX1
MMC/SD
Timer 1 & 2
CPU Complex
Memory Stick®
Host Controller
RTC
ARM9TDMI™
SPI 1 and
SPI 2
UART 1
Watchdog
Multimedia
D Cache
I Cache
UART 2 & 3
SSI/I2S 1 & 2
AIPI 1
Multimedia
Accelerator
Interrupt
Controller
VMMU
Video Port
I2C
USB Device
AIPI 2
DMAC
(11 Chnl)
Bus
Control
SmartCard I/F
EIM &
SDRAMC
Bluetooth
Accelerator
eSRAM
(128K)
Human Interface
Analog Signal
Processor
LCD Controller
Figure 1. MC9328MX1 Functional Block Diagram
1.1 Conventions
This document uses the following conventions:
•
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
•
Logic level one is a voltage that corresponds to Boolean true (1) state.
•
Logic level zero is a voltage that corresponds to Boolean false (0) state.
•
To set a bit or bits means to establish logic level one.
•
To clear a bit or bits means to establish logic level zero.
•
A signal is an electronic construct whose state conveys or changes in state convey information.
•
A pin is an external physical connection. The same pin can be used to connect a number of signals.
•
Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
•
Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
•
LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and
high bytes or words are spelled out.
•
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are
hexadecimal.
MC9328MX1 Advance Information, Rev. 4
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Freescale Semiconductor
Introduction
1.2 Features
To support a wide variety of applications, the MC9328MX1 provides a robust array of features, including the
following:
•
ARM920T Microprocessor Core
•
AHB to IP Bus Interfaces (AIPIs)
•
External Interface Module (EIM)
•
SDRAM Controller (SDRAMC)
•
DPLL Clock and Power Control Module
•
Three Universal Asynchronous Receiver/Transmitters (UART 1 UART 2 and UART 3)
•
Two Serial Peripheral Interfaces (SPI)
•
Two General-Purpose 32-bit Counters/Timers
•
Watchdog Timer
•
Real-Time Clock/Sampling Timer (RTC)
•
LCD Controller (LCDC)
•
Pulse-Width Modulation (PWM) Module
•
Universal Serial Bus (USB) Device
•
Multimedia Card and Secure Digital (MMC/SD) Host Controller Module
•
Memory Stick® Host Controller (MSHC)
•
SmartCard Interface Module (SIM)
•
Direct Memory Access Controller (DMAC)
•
Two Synchronous Serial Interfaces and Inter-IC Sound (SSI 1 and SSI 2/I2S) Module
•
Inter-IC (I2C) Bus Module
•
Video Port
•
General-Purpose I/O (GPIO) Ports
•
Bootstrap Mode
•
Analog Signal Processing (ASP) Module
•
Bluetooth Accelerator (BTA)
•
Multimedia Accelerator (MMA)
•
256-pin MAPBGA Package
1.3 Target Applications
The MC9328MX1 is targeted for advanced information appliances, smart phones, Web browsers, digital MP3
audio players, handheld computers based on the popular Palm OS platform, and messaging applications such as
Motorola's wireless cellular products, including the AccompliTM 008 GSM/GPRS interactive communicator.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
3
Introduction
1.4 Document Revision History
The following table provides revision history for this release. This history includes technical content revisions only
and not stylistic or grammatical changes.
Table 1. MC9328MX1 Data Sheet Revision History
Revision Location
Revision
Throughout
Clarified instances where BCLK signal is burst clock.
Table 4 on page 14
Maximum Ratings table replaced.
Section 3.3, “Power Sequence
Requirements” on page 15
Added reference to AN2537.
Section 3.12, “Bluetooth Accelerator”
on page 58
Added “Important” note regarding no software support for the BTA.
1.5 Product Documentation
The following documents are required for a complete description of the MC9328MX1 and are necessary to design
properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall
products, the following documents are helpful when used in conjunction with this manual.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MX1 Product Brief (order number MC9328MX1P/D)
MC9328MX1S Reference Manual (order number MC9328MX1SRM/D)
MC68VZ328 Product Brief (order number MC68VZ328P/D)
MC68VZ328 User’s Manual (order number MC68VZ328UM/D)
MC68VZ328 User’s Manual Addendum (order number MC68VZ328UMAD/D)
MC68SZ328 Product Brief (order number MC68SZ328P/D)
MC68SZ328 User’s Manual (order number MC68SZ328UM/D)
The Motorola manuals are available on the Motorola Semiconductors Web site at http://www.motorola.com/
semiconductors. These documents may be downloaded directly from the Motorola Web site, or printed versions
may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.
MC9328MX1 Advance Information, Rev. 4
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Freescale Semiconductor
Introduction
1.6 Ordering Information
Table 2 provides ordering information for the 256-lead mold array process ball grid array (MAPBGA) package.
Table 2. MC9328MX1 Ordering Information
Package Type
Frequency
Temperature
Solderball Type
Order Number
256-lead MAPBGA
200 MHz
0°C to 70°C
Standard
MC9328MX1VH20(R2)
256-lead MAPBGA
200 MHz
0°C to 70°C
Pb-free
MC9328MX1VM20(R2)
256-lead MAPBGA
200 MHz
-30°C to 70°C
Standard
MC9328MX1DVH20(R2)
256-lead MAPBGA
200 MHz
-30°C to 70°C
Pb-free
MC9328MX1DVM20(R2)
256-lead MAPBGA
150 MHz
-40°C to 85°C
Standard
MC9328MX1CVH15(R2)
256-lead MAPBGA
150 MHz
-40°C to 85°C
Pb-free
MC9328MX1CVM15(R2)
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
5
Signals and Connections
2 Signals and Connections
Table 3 identifies and describes the MC9328MX1 signals that are assigned to package pins. The signals are
grouped by the internal module that they are connected to.
Table 3. Signal Names and Descriptions
Signal Name
Function/Notes
External Bus/Chip Select (EIM)
A [24:0]
Address bus signals
D [31:0]
Data bus signals
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24]
EB1
Byte Strobe—Active low external enable byte signal that controls D [23:16]
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8]
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0]
OE
Memory Output Enable—Active low output enables external data bus
CS [5:0]
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by
the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
ECB
Active low input signal sent by flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
LBA
Active low signal sent by flash device causing the external burst device to latch the starting burst
address.
BCLK (burst clock)
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE
input signal by external DRAM.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the MC9328MX1 upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11].
These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles.
SDIBA [3:0]
SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A
[19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash
cycles.
MA [11:10]
SDRAM address signals
MA [9:0]
SDRAM address signals which are multiplex with address signals A [10:1]. MA [9:0] are selected on
SDRAM/SyncFlash cycles.
MC9328MX1 Advance Information, Rev. 4
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Freescale Semiconductor
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
DQM [3:0]
SDRAM data enable
CSD0
SDRAM/SyncFlash Chip Select signal which is multiplexed with the CS2 signal. These two signals
are selectable by programming the system control register.
CSD1
SDRAM/SyncFlash Chip Select signal which is multiplex with CS3 signal. These two signals are
selectable by programming the system control register. By default, CSD1 is selected, so it can be
used as SyncFlash boot chip select by properly configuring BOOT [3:0] input pins.
RAS
SDRAM/SyncFlash Row Address Select signal
CAS
SDRAM/SyncFlash Column Address Select signal
SDWE
SDRAM/SyncFlash Write Enable signal
SDCKE0
SDRAM/SyncFlash Clock Enable 0
SDCKE1
SDRAM/SyncFlash Clock Enable 1
SDCLK
SDRAM/SyncFlash Clock
RESET_SF
SyncFlash Reset
Clocks and Resets
EXTAL16M
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when internal oscillator circuit is shut
down.
XTAL16M
Crystal output
EXTAL32K
32 kHz crystal input
XTAL32K
32 kHz crystal output
CLKO
Clock Out signal selected from internal clock signals. Please refer to clock controller for internal
clock selection.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module and the clock control module) are reset.
RESET_OUT
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from
the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
POR
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally
generated by an external RC circuit designed to detect a power-up event.
JTAG
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
7
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge
of TCK.
System
BIG_ENDIAN
BIG_ENDIAN—This signal determines the memory endian configuration. BIG_ENDIAN is a static
pin to inner module. If the pin is driven logic-high the memory system is configured into big endian. If
it is driven logic-low the memory system is configured into little endian. The pin is not supposed to
be changed on the fly.
ETM
ETMTRACESYNC
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
ETMTRACECLK
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETMPIPESTAT [2:0]
ETM status signals which are multiplex with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0]
ETM packet signals which are multiplex with ECB, LBA, BCLK (burst clock), PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
CMOS Sensor Interface
CSI_D [7:0]
Sensor port data
CSI_MCLK
Sensor port master clock
CSI_VSYNC
Sensor port vertical sync
CSI_HSYNC
Sensor port horizontal sync
CSI_PIXCLK
Sensor port data latch clock
LCD Controller
LD [15:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
FLM/VSYNC
Frame Sync or Vsync—This signal also serves as the clock signal output for gate.
driver (dedicated signal SPS for Sharp panel HR-TFT).
LP/HSYNC
Line Pulse or H Sync
LSCLK
Shift Clock
ACD/OE
Alternate Crystal Direction/Output Enable
CONTRAST
This signal is used to control the LCD bias voltage as contrast control.
SPL_SPR
Program horizontal scan direction (Sharp panel dedicated signal).
MC9328MX1 Advance Information, Rev. 4
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Freescale Semiconductor
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
PS
Control signal output for source driver (Sharp panel dedicated signal).
CLS
Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal).
REV
Signal for common electrode driving signal preparation (Sharp panel dedicated signal).
SIM
SIM_CLK
SIM Clock
SIM_RST
SIM Reset
SIM_RX
Receive Data
SIM_TX
Transmit Data
SIM_PD
Presence Detect Schmitt trigger input
SIM_SVEN
SIM Vdd Enable
SPI
SPI1_MOSI
Master Out/Slave In
SPI1_MISO
Slave In/Master Out
SPI1_SS
Slave Select (Selectable polarity)
SPI1_SCLK
Serial Clock
SPI1_SPI_RDY
Serial Data Ready
SPI2_TXD
SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin however it does show up
as a primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16, “Serial
Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29, “GPIO Module and I/O Multiplexer
(IOMUX),” for information on how to bring this signal to the assigned pin.
SPI2_RXD
SPI2 master RxData input—This signal is multiplexed with a GPI/O pin however it does show up as
a primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16, “Serial
Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29, “GPIO Module and I/O Multiplexer
(IOMUX),” for information on how to bring this signal to the assigned pin.
SPI2_SS
SPI2 Slave Select—This signal is multiplexed with a GPI/O pin, however it does show up as a
primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16, “Serial
Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29, “GPIO Module and I/O Multiplexer
(IOMUX),” for information on how to bring this signal to the assigned pin.
SPI2_SCLK
SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin however it does show up as a
primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16, “Serial
Peripheral Interface Modules (SPI 1 and SPI 2),” and Chapter 29, “GPIO Module and I/O Multiplexer
(IOMUX),” for information on how to bring this signal to the assigned pin.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
9
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
General Purpose Timers
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers
simultaneously.
TMR2OUT
Timer 2 Output
USB Device
USBD_VMO
USB Minus Output
USBD_VPO
USB Plus Output
USBD_VM
USB Minus Input
USBD_VP
USB Plus Input
USBD_SUSPND
USB Suspend Output
USBD_RCV
USB RxD
USBD_OE
USB OE
USBD_AFE
USB Analog Front End Enable
Secure Digital Interface
SD_CMD
SD Command—If the system designer does not want to make use of the internal pull-up, via the
Pull-up enable register, a 4.7K–69K external pull up resistor must be added.
SD_CLK
MMC Output Clock
SD_DAT [3:0]
Data—If the system designer does not want to make use of the internal pull-up, via the Pull-up
enable register, a 50 K–69K external pull up resistor must be added.
Memory Stick Interface
MS_BS
Memory Stick Bus State (Output)—Serial bus control signal
MS_SDIO
Memory Stick Serial Data (Input/Output)
MS_SCLKO
Memory Stick Serial Clock (Output)—Serial Protocol clock output
MS_SCLKI
Memory Stick External Clock (Input)—Test clock input pin for SCLK divider. This pin is only for test
purposes, not for use in application mode.
MS_PI0
General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect
MS_PI1
General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect
UARTs – IrDA/Auto-Bauding
UART1_RXD
Receive Data
MC9328MX1 Advance Information, Rev. 4
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Freescale Semiconductor
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
UART1_TXD
Transmit Data
UART1_RTS
Request to Send
UART1_CTS
Clear to Send
UART2_RXD
Receive Data
UART2_TXD
Transmit Data
UART2_RTS
Request to Send
UART2_CTS
Clear to Send
UART2_DSR
Data Set Ready
UART2_RI
Ring Indicator
UART2_DCD
Data Carrier Detect
UART2_DTR
Data Terminal Ready
UART3_RXD
Receive Data
UART3_TXD
Transmit Data
UART3_RTS
Request to Send
UART3_CTS
Clear to Send
UART3_DSR
Data Set Ready
UART3_RI
Ring Indicator
UART3_DCD
Data Carrier Detect
UART3_DTR
Data Terminal Ready
Serial Audio Ports – SSI (configurable to I2S protocol)
SSI1_TXDAT
TxD
SSI1_RXDAT
RxD
SSI1_TXCLK
Transmit Serial Clock
SSI1_RXCLK
Receive Serial Clock
SSI1_TXFS
Transmit Frame Sync
SSI1_RXFS
Receive Frame Sync
SSI2_TXDAT
TxD
SSI2_RXDAT
RxD
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
11
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
SSI2_TXCLK
Transmit Serial Clock
SSI2_RXCLK
Receive Serial Clock
SSI2_TXFS
Transmit Frame Sync
SSI2_RXFS
Receive Frame Sync
I2C
I2C_SCL
I2C Clock
I2C_SDA
I2C Data
PWM
PWMO
PWM Output
ASP
UIN
Positive U analog input (for low voltage, temperature measurement)
UIP
Negative U analog input (for low voltage, temperature measurement)
PX1
Positive pen-X analog input
PY1
Positive pen-Y analog input
PX2
Negative pen-X analog input
PY2
Negative pen-Y analog input
R1A
Positive resistance input (a)
R1B
Positive resistance input (b)
R2A
Negative resistance input (a)
R2B
Negative resistance input (b)
RVP
Positive reference for pen ADC
RVM
Negative reference for pen ADC
AVDD
Analog power supply
AGND
Analog ground
BlueTooth
BT1
I/O clock signal
BT2
Output
MC9328MX1 Advance Information, Rev. 4
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Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name
Function/Notes
BT3
Input
BT4
Input
BT5
Output
BT6
Output
BT7
Output
BT8
Output
BT9
Output
BT10
Output
BT11
Output
BT12
Output
BT13
Output
TRISTATE
Sets all I/O pins to tristate; Can be used for flash loading and is pulled low for normal operations.
BTRF VDD
Power supply from external BT RFIC
BTRF GND
Ground from external BT RFIC
Noisy Supply Pins
NVDD
Noisy Supply for the I/O pins
NVSS
Noisy Ground for the I/O pins
Supply Pins – Analog Modules
AVDD
Supply for analog blocks
AVSS
Quiet GND for analog blocks
Internal Power Supply
QVDD
Power supply pins for silicon internal circuitry
QVSS
GND pins for silicon internal circuitry
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
13
Specifications
3 Specifications
This section contains the electrical specifications and timing diagrams for the MC9328MX1 processor.
3.1 Maximum Ratings
Table 4 provides information on maximum ratings which are those values beyond which damage to the device may
occur. Functional operation should be restricted to the limits listed in Recommended Operating Range Table 5 on
page 15 or the DC Characteristics table.
Table 4. Maximum Ratings1
Symbol
Rating
Minimum
Maximum
Unit
NVdd
DC I/O Supply Voltage
–
–
V
QVdd
DC Internal (core) Supply Voltage
–
–
V
AVdd
DC Analog Supply Voltage
–
–
V
DC Bluetooth Supply Voltage
–
–
V
-0.3
3.3
V
0
70
°C
BTRFVdd
Vdd
Supply voltage
TA
Maximum operating temperature range
MC9328MX1VH20/MC9328MX1VM20
TA
Maximum operating temperature range
MC9328MX1DVH20/MC9328MX1DVM20
-30
70
°C
TA
Maximum operating temperature range
MC9328MX1CVH15/MC9328MX1CVM15
-40
85
°C
VESD_HBM
ESD at human body model (HBM)
–
2000
V
VESD_MM
ESD at machine model (MM)
–
100
V
Latch-up current
–
200
mA
ILatchup
1.
2.
3.
Test
Storage temperature
-55
150
°C
Pmax
Power Consumption
8002
13003
mW
Voltages referenced to Vss and BTRFGND, which are both tied to the same potential.
A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from
the ARM core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches
from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core
running its heaviest OS application at 200MHz, and where the whole image is running out of SDRAM. QVDD at
2.0V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment,
max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA.
MC9328MX1 Advance Information, Rev. 4
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Freescale Semiconductor
Specifications
3.2 Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages. The MC9328MX1 processor has
multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic.
All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power
to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system.
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the
AVDD pins from other VDD pins.
BTRFVDD is the supply voltage for the Bluetooth interface signals. It is quite sensitive to the data transmit/receive
accuracy. Please refer to Bluetooth RF spec for special handling. If Bluetooth is not used in the system, these
Bluetooth pins can be used as general purpose I/O pins and BTRFVDD can be used as other NVDD pins.
For more information about I/O pads grouping per VDD, please refer to Table 3 on page 6.
Table 5. Recommended Operating Range 1
Symbol
Rating
Minimum
Maximum
Unit
2.70
3.30
V
NVDD
I/O supply voltage
NVDD
I/O supply voltage
1.70
3.30
V
QVDD
Internal supply voltage (Core =
150 MHz)
1.70
1.90
V
QVDD
Internal supply voltage (Core =
200 MHz)
1.80
2.00
V
AVDD
Analog supply voltage
1.70
3.30
V
BTRFVD
D1
Bluetooth I/O voltage (Bluetooth)
1.70
3.10
V
BTRFVD
D2
Bluetooth I/O voltage (Non Bluetooth
applications)
1.70
3.30
V
1.
MSHC, SPI, BTA, USBd, LCD and
CSI are only 3V interface
Voltages referenced to Vss and BTRFGND, which are both tied to the same potential.
3.3 Power Sequence Requirements
For required power-up and power-down sequencing, please refer to the "Power-Up Sequence" section of
application note AN2537 on the i.MX website page.
3.4 DC Electrical Characteristics
Table 6 contains both maximum and minimum DC characteristics of the MC9328MX1.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
15
Specifications
Table 6. Maximum and Minimum DC Characteristics
Number
or Symbol
Iop
Parameter
Minimum
Typical
Maximum
Unit
Full running operating current at 1.8V for
QVDD, 3.3V for NVDD/AVDD (Core = 96 MHz,
System = 96 MHz, MPEG4 decoding playback
from external memory card to both external SSI
audio decoder and TFT display panel, and OS
with MMU enabled memory system is running
on external SDRAM)
Please refer to application note: AN2537,
Power Performance of MC9328MX1.
–
QVDD at 1.8v
= 120mA; NVDD+AVDD
at 3.0v = 30mA
–
mA
Sidd1
Standby current (QVDD = 1.8V, temp = 25°C)
–
25
–
µA
Sidd2
Standby current (QVDD = 1.8V, temp = 55°C)
–
45
–
µA
Sidd3
Standby current (QVDD = 2.0V, temp = 25°C)
–
35
–
µA
Sidd4
Standby current (QVDD = 2.0V, temp = 55°C)
–
60
–
µA
VIH
Input high voltage
0.7VDD
–
Vdd+0.2
V
VIL
Input low voltage
–
–
0.4
V
VOH
Output high voltage (IOH = 2.0 mA)
0.7VDD
–
Vdd
V
VOL
Output low voltage (IOL = -2.5 mA)
–
–
0.4
V
IIL
Input low leakage current
(VIN = GND, no pull-up or pull-down)
–
–
±1
µA
IIH
Input high leakage current
(VIN = VDD, no pull-up or pull-down)
–
–
±1
µA
IOH
Output high current
(VOH = 0.8VDD, VDD = 1.8V)
–
–
4.0
mA
IOL
Output low current
(VOL = 0.4V, VDD = 1.8V)
−4.0
–
–
mA
IOZ
Output leakage current
(Vout = VDD, output is tri-stated)
–
–
±5
µA
Ci
Input capacitance
–
–
5
pF
Co
Output capacitance
–
–
5
pF
MC9328MX1 Advance Information, Rev. 4
16
Freescale Semiconductor
Specifications
3.5 AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are
specified relative to an appropriate edge of other signals. All timing specifications are specified at a system
operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an operating supply voltage
from VDD min to VDD max under an operating temperature from TL to TH. All timing is measured at 30 pF loading.
Table 7. Tri-State Signal Timing
Pin
TRISTATE
Parameter
Minimum
Maximum
Unit
–
20.8
ns
Time from TRISTATE activate until I/O becomes Hi-Z
Table 8. 32k/16M Oscillator Signal Timing
Parameter
Minimum
RMS
Maximum
Unit
EXTAL32k input jitter (peak to peak) for both System PLL and
MCUPLL
–
5
20
ns
EXTAL32k input jitter (peak to peak) for MCUPLL only
–
5
100
ns
800
–
–
ms
–
TBD
TBD
–
TBD
–
–
–
EXTAL32k startup time
EXTAL16M input jitter (peak to peak)
EXTAL16M startup time
Table 9. CLKO Rise/Fall Time (at 30pF Loaded)
Best
Case
Typical
Worst
Case
Units
Rise Time
0.80
1.00
1.40
ns
Fall Time
0.74
1.08
1.67
ns
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
17
Specifications
3.6 Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift
register comprised of the following:
•
32-bit data field
•
7-bit address field
•
A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field,
and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field
is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing
diagram for the ETM9 is shown in Figure 2. See Table 10 on page 18 for the ETM9 timing parameters used in
Figure 2.
2a
1
2b
3a
TRACECLK
3b
TRACECLK
(Half-Rate Clocking Mode)
Valid Data
Output Trace Port
Valid Data
4a
4b
Figure 2. Trace Port Timing Diagram
Table 10. Trace Port Timing Diagram Parameter Table
1.8V +/- 0.10V
Ref No.
3.0V +/- 0.30V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
CLK frequency
0
85
0
100
MHz
2a
Clock high time
1.3
–
2
–
ns
2b
Clock low time
3
–
2
–
ns
3a
Clock rise time
–
4
–
3
ns
3b
Clock fall time
–
3
–
3
ns
4a
Output hold time
2.28
–
2
–
ns
4b
Output setup time
3.42
–
3
–
ns
MC9328MX1 Advance Information, Rev. 4
18
Freescale Semiconductor
Specifications
3.7 DPLL Timing Specifications
Parameters of the DPLL are given in Table 11. In this table, Tref is a reference clock period after the pre-divider
and Tdck is the output double clock period.
Table 11. DPLL Specifications
Parameter
Test Conditions
Minimum
Typical
Maximum
Unit
Reference clock freq range
Vcc = 1.8V
5
–
100
MHz
Pre-divider output clock
freq range
Vcc = 1.8V
5
–
30
MHz
Double clock freq range
Vcc = 1.8V
80
–
220
MHz
Pre-divider factor (PD)
–
1
–
16
–
Total multiplication factor
(MF)
Includes both integer
and fractional parts
5
–
15
–
MF
integer part
–
5
–
15
–
MF
numerator
Should be less than the
denominator
0
–
1022
–
MF
denominator
–
1
–
1023
–
Pre-multiplier lock-in time
–
–
–
312.5
µsec
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-must lock-in time)
250
280
(56 µs)
300
Tref
Freq lock-in time after
partial reset
FOL mode for non-integer MF (does not
include pre-multi lock-in time)
220
250
(~50 µs)
270
Tref
Phase lock-in time after
full reset
FPL mode and integer MF (does not include
pre-multi lock-in time)
300
350
(70 µs)
400
Tref
Phase lock-in time after
partial reset
FPL mode and integer MF (does not include
pre-multi lock-in time)
270
320
(64 µs)
370
Tref
Freq jitter (p-p)
–
–
0.005
(0.01%)
0.01
2•Tdck
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
–
1.0
(10%)
1.5
ns
Power supply voltage
–
1.7
–
2.5
V
Power dissipation
FOL mode, integer MF,
fdck = 200 MHz, Vcc = 1.8V
–
–
4
mW
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
19
Specifications
3.8 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4.
NOTE:
Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up
to prevent forward biasing.
90% AVDD
1
POR
RESET_POR
10% AVDD
2
Exact 300ms
3
7 cycles @ CLK32
RESET_DRAM
4
HRESET
14 cycles @ CLK32
RESET_OUT
CLK32
HCLK
Figure 3. Timing Relationship with POR
MC9328MX1 Advance Information, Rev. 4
20
Freescale Semiconductor
Specifications
5
RESET_IN
14 cycles @ CLK32
HRESET
4
RESET_OUT
6
CLK32
HCLK
Figure 4. Timing Relationship with RESET_IN
Table 12. Reset Module Timing Parameter Table
1.8V +/- 0.10V
Ref
No.
3.0V +/- 0.30V
Parameter
Unit
Min
Max
Min
Max
note1
–
note1
–
–
300
300
300
300
ms
1
Width of input POWER_ON_RESET
2
Width of internal POWER_ON_RESET
(9600 *CLK32 at 32 KHz)
3
7K to 32K-cycle stretcher for SDRAM reset
7
7
7
7
Cycles of
CLK32
4
14K to 32K-cycle stretcher for internal system reset
HRESERT and output reset at pin RESET_OUT
14
14
14
14
Cycles of
CLK32
5
Width of external hard-reset RESET_IN
4
–
4
–
Cycles of
CLK32
6
4K to 32K-cycle qualifier
4
4
4
4
Cycles of
CLK32
1.
POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should
allow for crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence.
Through the process of supplying crystals for use with CMOS oscillators, crystal manufacturers have
developed a working knowledge of start-up time of their crystals. Typically, start-up times range from
400 ms to 1.2 seconds for this type of crystal.
If an external stable clock source (already running) is used instead of a crystal, the width of POR should
be ignored in calculating timing for the start-up process.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
21
Specifications
3.9 External Interface Module
The External Interface Module (EIM) handles the interface to devices external to the MC9328MX1, including
generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in
Figure 5, and Table 13 defines the parameters of signals.
(HCLK) Bus Clock
1a
1b
2a
2b
3a
3b
Address
Chip-select
Read (Write)
4a
OE (rising edge)
4b
4c
OE (falling edge)
4d
5a
EB (rising edge)
5b
5c
EB (falling edge)
5d
6a
LBA (negated falling edge)
6b
6a
LBA (negated rising edge)
6c
7a
BCLK (burst clock) - rising edge
7b
7c
7d
BCLK (burst clock) - falling edge
8b
Read Data
9a
8a
9b
Write Data (negated falling)
9a
9c
Write Data (negated rising)
10a
DTACK_B
10a
Figure 5. EIM Bus Timing Diagram
Table 13. EIM Bus Timing Parameter Table
1.8 ± 0.10V
Ref No.
1a
3.0 ± 0.3V
Unit
Parameter
Clock fall to address valid
Min
Typical
Max
Min
Typical
Max
2.48
3.31
9.11
2.4
3.2
8.8
ns
MC9328MX1 Advance Information, Rev. 4
22
Freescale Semiconductor
Specifications
Table 13. EIM Bus Timing Parameter Table (Continued)
1.8 ± 0.10V
Ref No.
3.0 ± 0.3V
Unit
Parameter
Min
Typical
Max
Min
Typical
Max
1b
Clock fall to address invalid
1.55
2.48
5.69
1.5
2.4
5.5
ns
2a
Clock fall to chip-select valid
2.69
3.31
7.87
2.6
3.2
7.6
ns
2b
Clock fall to chip-select invalid
1.55
2.48
6.31
1.5
2.4
6.1
ns
3a
Clock fall to Read (Write) Valid
1.35
2.79
6.52
1.3
2.7
6.3
ns
3b
Clock fall to Read (Write) Invalid
1.86
2.59
6.11
1.8
2.5
5.9
ns
4a
Clock1 rise to Output Enable Valid
2.32
2.62
6.85
2.3
2.6
6.8
ns
4b
Clock1 rise to Output Enable Invalid
2.11
2.52
6.55
2.1
2.5
6.5
ns
4c
Clock1 fall to Output Enable Valid
2.38
2.69
7.04
2.3
2.6
6.8
ns
4d
Clock1 fall to Output Enable Invalid
2.17
2.59
6.73
2.1
2.5
6.5
ns
5a
Clock1 rise to Enable Bytes Valid
1.91
2.52
5.54
1.9
2.5
5.5
ns
5b
Clock1 rise to Enable Bytes Invalid
1.81
2.42
5.24
1.8
2.4
5.2
ns
5c
Clock1 fall to Enable Bytes Valid
1.97
2.59
5.69
1.9
2.5
5.5
ns
5d
Clock1 fall to Enable Bytes Invalid
1.76
2.48
5.38
1.7
2.4
5.2
ns
6a
Clock1 fall to Load Burst Address Valid
2.07
2.79
6.73
2.0
2.7
6.5
ns
6b
Clock1 fall to Load Burst Address Invalid
1.97
2.79
6.83
1.9
2.7
6.6
ns
6c
Clock1 rise to Load Burst Address Invalid
1.91
2.62
6.45
1.9
2.6
6.4
ns
7a
Clock1 rise to Burst Clock rise
1.61
2.62
5.64
1.6
2.6
5.6
ns
7b
Clock1rise to Burst Clock fall
1.61
2.62
5.84
1.6
2.6
5.8
ns
7c
Clock1 fall to Burst Clock rise
1.55
2.48
5.59
1.5
2.4
5.4
ns
7d
Clock1 fall to Burst Clock fall
1.55
2.59
5.80
1.5
2.5
5.6
ns
8a
Read Data setup time
5.54
–
–
5.5
–
–
ns
8b
Read Data hold time
0
–
–
0
–
–
ns
9a
Clock1 rise to Write Data Valid
1.81
2.72
6.85
1.8
2.7
6.8
ns
9b
Clock1 fall to Write Data Invalid
1.45
2.48
5.69
1.4
2.4
5.5
ns
9c
Clock1 rise to Write Data Invalid
1.63
–
–
1.62
–
–
ns
DTACK setup time
2.52
–
–
2.5
–
–
ns
10a
1.
Clock refers to the system clock signal, HCLK, generated from the System DPLL
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
23
Specifications
3.9.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a
data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the
external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal
function when the external DTACK signal is used for data acknowledgement.
3.9.2 DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of
measure for this figure are found in the associated tables.
3.9.2.1 DTACK READ Cycle without DMA
(3)
Address
(2)
(8)
CS5
(1)
EB
(9)
programmable
min 0ns
(5)
OE
(4)
DTACK
(6)
(10)
Databus
(input to MX1)
(7)
Figure 6. DTACK READ Cycle without DMA
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz
(3.0 ± 0.3) V
Number
Unit
Characteristic
1
OE and EB assertion time
2
CS5 pulse width
3
OE negated to address inactive
4
DTACK asserted after CS5 asserted
Minimum
Maximum
See note 2
–
ns
3T
–
ns
46.44
–
ns
–
1019T
ns
MC9328MX1 Advance Information, Rev. 4
24
Freescale Semiconductor
Specifications
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
(3.0 ± 0.3) V
Number
Unit
Characteristic
Minimum
Maximum
5
DTACK asserted to OE negated
3T+2.2
4T+6.86
ns
6
Data hold timing after OE negated
0
–
ns
7
Data ready after DTACK asserted
0
T
ns
8
OE negated to CS negated
0.5T+0.24
0.5T+0.67
ns
9
OE negated after EB negated
0.5
1.5
ns
10
DTACK pulse width
1T
3T
ns
Note:
0. DTACK assert means DTACK become low level.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur
only when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
3.9.2.2 DTACK Read Cycle DMA Enabled
(4)
Address
(2)
(9)
CS5
(1)
EB
(10)
programmable
min 0ns
(3)
(6)
OE
RW (logic high)
(5)
DTACK
Databus
(input to MX1)
(7)
(11)
(8)
Figure 7. DTACK Read Cycle DMA Enabled
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
25
Specifications
Table 15. Parameters for Read Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
(3.0 ± 0.3) V
Number
Unit
Characteristic
Minimum
Maximum
See note 2
–
ns
3T
–
ns
1
OE and EB assertion time
2
CS pulse width
3
OE negated before CS5 is negated
0.5T+0.24
0.5T+0.67
ns
4
Address inactive before CS negated
–
0.93
ns
5
DTACK asserted after CS5 asserted
–
1019T
ns
6
DTACK asserted to OE negated
3T+2.2
4T+6.86
ns
7
Data hold timing after OE negated
0
–
ns
8
Data ready after DTACK is asserted
–
T
ns
9
CS deactive to next CS active
T
–
ns
10
OE negate after EB negate
0.5
1.5
ns
11
DTACK pulse width
1T
3T
ns
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only
when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MX1 Advance Information, Rev. 4
26
Freescale Semiconductor
Specifications
3.9.2.3 DTACK Write Cycle without DMA
(5)
Address
(1)
CS5
(2)
EB
(3)
programmable
min 0ns
(10)
programmable
min 0ns
(4)
(7)
RW
(6)
OE (logic high)
DTACK
(9)
(11)
Databus
(output from MX1)
(8)
Figure 8. DTACK Write Cycle without DMA
Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz
(3.0 ± 0.3) V
Number
Unit
Characteristic
Minimum
Maximum
1
CS5 assertion time
See note 2.
–
ns
2
EB assertion time
See note 2
–
ns
3
CS5 pulse width
3T
–
ns
4
RW negated before CS5 is negated
1.5T+0.58
1.5T+1.58
ns
5
RW negated to Address inactive
57.31
–
ns
6
DTACK asserted after CS5 asserted
–
1019T
ns
7
DTACK asserted to RW negated
2T+1.8
3T+5.26
ns
8
Data hold timing after RW negated
1.5T-0.59
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
EB negated before CS5 is negated
0.5T+0.74
0.5T+2.17
ns
11
DTACK pulse width
1T
3T
ns
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
27
Specifications
Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
(3.0 ± 0.3) V
Number
Unit
Characteristic
Maximum
Minimum
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
3.9.2.4 DTACK Write Cycle DMA Enabled
(5)
Address
(1)
CS5
(2)
EB
(3)
(10)
programmable
min 0ns
(11)
programmable
min 0ns
(4)
(7)
RW
(6)
OE (logic high)
DTACK
(9)
(12)
Databus
(output from MX1)
(8)
Figure 9. DTACK Write Cycle DMA Enabled
Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
(3.0 ± 0.3) V
Number
Unit
Characteristic
Minimum
Maximum
1
CS5 assertion time
See note 2
–
ns
2
EB assertion time
See note 2
–
ns
3
CS5 pulse width
3T
–
ns
4
RW negated before CS5 is negated
1.5T+0.58
1.5T+1.58
ns
5
Address inactive before CS negated
–
0.93
ns
6
DTACK asserted after CS5 asserted
–
1019T
ns
MC9328MX1 Advance Information, Rev. 4
28
Freescale Semiconductor
Specifications
Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz (Continued)
(3.0 ± 0.3) V
Number
Unit
Characteristic
Minimum
Maximum
7
DTACK asserted to RW negated
2T+1.8
3T+5.26
ns
8
Data hold timing after RW negated
1.5T-0.59
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
CS deactive to next CS active
T
–
ns
11
EB negate to CS negate
0.5T+0.74
0.5T+2.17
ns
12
DTACK pulse width
1T
3T
ns
Note:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
29
Specifications
3.9.3 EIM External Bus Timing
The following timing diagrams show the timing of accesses to memory or a peripheral.
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[0]
htrans
Seq/Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1
weim_hready
BCLK (burst clock)
ADDR
Last Valid Address
V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
V1
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 10. WSC = 1, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4
30
Freescale Semiconductor
Specifications
hclk
Internal signals - shown only for illustrative purposes
hsel_weim_cs[0]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata
Last Valid Data
Write Data (V1)
weim_hrdata
Unknown
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Address
V1
CS0
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
Write Data (V1)
Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
31
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[0]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS0
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
32
Freescale Semiconductor
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[0]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata
Last Valid Data
weim_hrdata
Write Data (V1 Word)
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1 + 2
Address V1
CS0
R/W
Write
LBA
OE
EB
DATA
1/2 Half Word
2/2 Half Word
Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
33
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[3]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR Last Valid Addr
Address V1
Address V1 + 2
CS[3]
R/W
Read
BA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
34
Freescale Semiconductor
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[3]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata Last Valid
Data
Write Data (V1 Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR Last Valid Addr
Address V1
Address V1 + 2
CS3
Write
R/W
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
35
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1 + 2
Address V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
36
Freescale Semiconductor
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
Valid
hwdata Last
Data
Write Data (V1 Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
37
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
38
Freescale Semiconductor
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Read
haddr
V1
hready
weim_hrdata
V1 Word
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
39
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata
Last Valid
Data
Write Data (V1 Word)
weim_hrdata
Unknown
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
40
Freescale Semiconductor
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
Valid
hwdata Last
Data
Unknown
Write Data (V1 Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
41
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Nonseq
hwrite
Read
Write
haddr
V1
V8
hready
hwdata
weim_hrdata
Last Valid Data
Write Data
Last Valid Data
Read Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V8
CS2
R/W
Write
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4
42
Freescale Semiconductor
Specifications
Read
Idle
Write
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Nonseq
hwrite
Read
Write
haddr
V1
V8
hready
hwdata
weim_hrdata
Write Data
Last Valid Data
Last Valid Data
Read Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V8
CS2
R/W
Read
Write
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
43
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[4]
htrans
Nonseq
hwrite
Write
haddr
V1
hready
hwdata Last Valid
Data
Write Data (Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
Write Data (1/2 Half Word)
Write Data (2/2 Half Word)
Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
44
Freescale Semiconductor
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[4]
htrans
Nonseq
Nonseq
hwrite
Read
Write
haddr
V1
V8
hready
hwdata
weim_hrdata
Last Valid Data
Write Data
Last Valid Data
Read Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V8
CS4
R/W
Write
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
45
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[4]
htrans
Nonseq
hwrite
Read
Read
haddr
V1
V2
Idle
Seq
hready
weim_hrdata
Last Valid Data
Read Data (V1)
Read Data (V2)
weim_hready
BCLK (burst clock)
ADDR
Last Valid
Address V1
Address V2
CNC
CS4
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
Read Data
(V1)
Read Data
(V2)
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4
46
Freescale Semiconductor
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[4]
htrans
Nonseq
hwrite
Read
Write
haddr
V1
V8
Idle
Nonseq
hready
hwdata
weim_hrdata
Last Valid Data
Write Data
Last Valid Data
Read Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V8
CNC
CS4
R/W
Read
Write
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
47
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Nonse
hwrite
Read
Read
haddr
V1
V5
Idle
hready
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V5
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 Word
V2 Word
V5 Word
V6 Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4
48
Freescale Semiconductor
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Seq
Seq
Seq
hwrite
Read
Read
Read
Read
haddr
V1
V2
V3
V4
Idle
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
V3 Word
V4 Word
weim_hready
BCLK (burst clock)
ADDR Last Valid Addr
Address V1
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 Word
V2 Word
V3 Word
V4 Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
49
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Nonseq
Seq
hwrite
Read
Read
haddr
V1
V2
Idle
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid
Address V1
Address V2
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
50
Freescale Semiconductor
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Non
seq
Seq
hwrite
Read
Read
haddr
V1
V2
Idle
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
BCLK (burst clock)
ADDR
Last
Address V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
51
Specifications
Internal signals - shown only for illustrative purposes
hclk
hsel_weim_cs[2]
htrans
Non
seq
Seq
hwrite
Read
Read
haddr
V1
V2
Idle
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
BCLK (burst clock)
ADDR
Last
Address V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4
52
Freescale Semiconductor
Specifications
LSCLK
LD[15:0]
1
Figure 33. SCLK to LD Timing Diagram
Table 18. LCDC SCLK Timing
3.0 +/- 0.3V
Num
1
Characteristic
SCLK to LD valid
Minimum
Maximum
–
3
Unit
ns
3.9.4 Non-TFT Panel Timing
T1
T1
VSYN
T3
T2
T4
XMAX
T2
HSYN
SCLK
Ts
LD[15:0]
Figure 34. Non-TFT Panel Timing
Table 19.
Symbol
Parameter
Non TFT Panel Timing Diagram
Allowed Register Minimum
Value
Actual Value
Unit
T1
HSYN to VSYN delay
0
HWAIT2+2
Tpix
T2
HSYN pulse width
0
HWIDTH+1
Tpix
T3
VSYN to SCLK
–
0<= T3<=Ts
–
T4
SCLK to HSYN
0
HWAIT1+1
Tpix
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
53
Specifications
•
VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all
these 3 signals are active high.
•
Ts is the shift clock period.
•
Ts = Tpix * (panel data bus width).
•
Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).
•
Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.
•
Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.
MC9328MX1 Advance Information, Rev. 4
54
Freescale Semiconductor
Specifications
3.10 Pen ADC Specifications
The specifications for the pen ADC are shown in Table 20 through Table 22.
Table 20. Pen ADC System Performance
Full Range Resolution1
13 bits
Non-Linearity Error1
4 bits
Accuracy 1
9 bits
1.
Tested under input = 0~1.8V at 25°C
Table 21. Pen ADC Test Conditions
Vp max
1800 mV
ip max
+7 µA
Vp min
GND
ip min
1.5 µA
Vn
GND
in
1.5 µA
Sample frequency
12 MHz
Sample rate
1.2 KHz
Input frequency
100 Hz
Input range
0–1800 mV
Note:
Ru1 = Ru2 = 200K
Table 22. Pen ADC Absolute Rating
ip max
+9.5 µA
ip min
-2.5 µA
in max
+9.5 µA
in min
-2.5 µA
3.11 ASP Touch Panel Controller
The following sections contain the electrical specifications of the ASP touch panel controller. The value of
parameters and their corresponding measuring conditions are mentioned as well.
3.11.1 Electrical Specifications
Test conditions: Temperature = 25º C, QVDD = 1800mV.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
55
Specifications
Table 23. ASP Touch Panel Controller Electrical Spec
Parameter
Minimum
Type
Maximum
Unit
Offset
–
32768
–
–
Offset Error
–
–
8199
–
Gain
–
13.65
–
mV-1
Gain Error
–
–
33%
–
DNL
8
9
–
Bits
INL
–
0
–
Bits
Accuracy (without missing code)
8
9
–
Bits
Operating Voltage Range (Pen)
–
–
QVDD
mV
Negative QVDD
–
QVDD
mV
–
10
–
Ohm
Operating Voltage Range (U)
On-resistance of switches SW[8:1]
Note that QVDD should be 1800mV.
3.11.2 Gain Calculations
The ideal mapping of input voltage to output digital sample is defined as follows:
Sample
G0
65535
Smax
C0
Vi
1800
-2400
2400
Figure 35. Gain Calculations
In general, the mapping function is:
S=G*V+C
Where V is input, S is output, G is the slope, and C is the y-intercept.
Nominal Gain G0 = 65535 / 4800 = 13.65mV-1
Nominal Offset C0 = 65535 / 2 = 32767
MC9328MX1 Advance Information, Rev. 4
56
Freescale Semiconductor
Specifications
3.11.3 Offset Calculations
The ideal mapping of input voltage to output digital sample is defined as:
Sample
G0
65535
Smax
C0
Vi
1800
-2400
2400
Figure 36. Offset Calculations
In general, the mapping function is:
S=G*V+C
Where V is input, S is output, G is the slope, and C is the y-intercept.
Nominal Gain G0 = 65535 / 4800 = 13.65mV-1
Nominal Offset C0 = 65535 / 2 = 32767
3.11.4 Gain Error Calculations
Gain error calculations are made using the information in this section.
Sample
Gmax
G0
65535
Smax
C0
Vi
- 2400
1800
2400
Figure 37. Gain Error Calculations
Assuming the offset remains unchanged, the mapping is rotated around y-intercept to determine the maximum gain
allowed. This occurs when the sample at 1800mV has just reached the ceiling of the 16-bit range, 65535.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
57
Specifications
Maximum Offset Gmax,
Gmax
= (65535 - C0) / 1800
= (65535 - 32767) / 1800
= 18.20
Gain Error Gr,
Gr
= (Gmax - G0) / G0 * 100%
= (18.20 - 13.65) / 13.65 * 100%
= 33%
3.12 Bluetooth Accelerator
IMPORTANT:
On-chip accelerator hardware is not supported by software. An external
Bluetooth chip interfaced to a UART is recommended.
The Bluetooth Accelerator (BTA) radio interface supports the Motorola Radio, MC13180 using an SPI interface.
This section provides the data bus timing diagrams and SPI interface timing diagrams shown in Figure 38 and
Figure 39 on page 59, and the associated parameters shown in Table 24 and Table 25 on page 59.
2
BT CLK (BT1)
7
Receive
FS (BT5)
1
PKT DATA (BT3)
3
4
RXTX_EN (BT9)
Transmit
8
PKT DATA (BT2)
5
6
Figure 38. Motorola MC13180 Data Bus Timing Diagram
Table 24. Motorola MC13180 Data Bus Timing Parameter Table
Ref No.
Parameter
Minimum
Typical
Maximum
Unit
1
FrameSync setup time relative to BT CLK rising edge1
–
4
–
ns
2
FrameSync hold time relative to BT CLK rising edge1
–
12
–
ns
MC9328MX1 Advance Information, Rev. 4
58
Freescale Semiconductor
Specifications
Table 24. Motorola MC13180 Data Bus Timing Parameter Table (Continued)
Ref No.
Parameter
Minimum
Typical
Maximum
Unit
3
Receive Data setup time relative to BT CLK rising edge1
–
6
–
ns
4
Receive Data hold time relative to BT CLK rising edge1
–
13
–
ns
5
Transmit Data setup time relative to RXTX_EN rising edge2
172.5
–
192.5
µs
6
TX DATA period
7
BT CLK duty cycle
40
–
60
%
8
Transmit Data hold time relative to RXTX_EN falling edge
4
–
10
µs
1.
2.
1000 +/- 0.02
ns
Please refer to Motorola 2.4 GHz RF Transceiver Module (MC13180) Technical Data documentation.
The setup and hold times of RX_TX_EN can be adjusted by programming Time_A_B register
(0x00216050) and RF_Status (0x0021605C) registers.
1
4
5
6
SPI CLK (BT13)
9
SPI_EN (BT11)
8
SPI_DATA_OUT (BT12)
3
SPI_DATA_IN (BT4)
7
2
Figure 39. SPI Interface Timing Diagram Using Motorola MC13180
Table 25. SPI Interface Timing Parameter Table Using Motorola MC13180
Ref No.
Parameter
Minimum
Maximum
Unit
1
SPI_EN setup time relative to rising edge of SPI_CLK
15
–
ns
2
Transmit data delay time relative to rising edge of SPI_CLK
0
15
ns
3
Transmit data hold time relative to rising edge of SPI_EN
0
15
ns
4
SPI_CLK rise time
0
25
ns
5
SPI_CLK fall time
0
25
ns
6
SPI_EN hold time relative to falling edge of SPI_CLK
15
–
ns
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
59
Specifications
Table 25. SPI Interface Timing Parameter Table Using Motorola MC13180 (Continued)
Ref No.
Parameter
Minimum
Maximum
Unit
7
Receive data setup time relative to falling edge of SPI_CLK1
15
–
ns
8
Receive data hold time relative to falling edge of SPI_CLK1
15
–
ns
9
SPI_CLK frequency, 50% duty cycle required1
–
20
MHz
1.
The SPI_CLK clock frequency and duty cycle, setup and hold times of receive data can be set by
programming SPI_Control (0x00216138) register together with system clock.
3.13 SPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a master,
two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input).
The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period Control Register
(PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or SPI 2. When the SPI 1
module is configured as a slave, the user can configure the SPI 1 Control Register (CONTROLREG1) to match the
external SPI master’s timing. In this configuration, SS becomes an input signal, and is used to latch data into or
load data out to the internal data shift registers, as well as to increment the data FIFO.
.
2
SS
5
3
1
SPIRDY
4
SCLK, MOSI, MISO
Figure 40. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
SS
SPIRDY
SCLK, MOSI, MISO
Figure 41. Master SPI Timing Diagram Using SPI_RDY Level Trigger
MC9328MX1 Advance Information, Rev. 4
60
Freescale Semiconductor
Specifications
SS (output)
SCLK, MOSI, MISO
Figure 42. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
SS (input)
SCLK, MOSI, MISO
Figure 43. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
SS (input)
6
7
SCLK, MOSI, MISO
Figure 44. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
Table 26. Timing Parameter Table for Figure 40 through Figure 44
Ref
No.
Parameter
Minimum
Maximum
Unit
2T 1
–
ns
3·Tsclk 2
–
ns
2·Tsclk
–
ns
0
–
ns
Tsclk + WAIT 3
–
ns
1
SPI_RDY to SS output low
2
SS output low to first SCLK edge
3
Last SCLK edge to SS output high
4
SS output high to SPI_RDY low
5
SS output pulse width
6
SS input low to first SCLK edge
T
–
ns
7
SS input pulse width
T
–
ns
1.
2.
3.
T = CSPI system clock period (PERCLK2).
Tsclk = Period of SCLK.
WAIT = Number of bit clocks (SCLK) or 32.768 KHz clocks per Sample
Period Control Register.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
61
Specifications
3.14 LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller
with various display configurations, refer to the LCD controller chapter of the MC9328MX1 Reference Manual.
LSCLK
LD[15:0]
1
Figure 45. SCLK to LD Timing Diagram
Table 27. LCDC SCLK Timing Parameter Table
Ref No.
1
Parameter
SCLK to LD valid
Minimum
Maximum
Unit
–
2
ns
Non-display region
T3
T1
VSYN
Display region
T4
T2
HSYN
OE
LD[15:0]
Line Y
Line 1
T5
T6
Line Y
T7
XMAX
HSYN
SCLK
OE
LD[15:0]
T8
(1,1)
(1,2)
(1,X)
VSYN
Figure 46. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Diagram
MC9328MX1 Advance Information, Rev. 4
62
Freescale Semiconductor
Specifications
Table 28. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table
Symbol
Description
Minimum
Corresponding Register Value
Unit
T1
End of OE to beginning of VSYN
T5+T6
+T7+T9
(VWAIT1·T2)+T5+T6+T7+T9
Ts
T2
HSYN period
XMAX+5
XMAX+T5+T6+T7+T9+T10
Ts
T3
VSYN pulse width
T2
VWIDTH·(T2)
Ts
T4
End of VSYN to beginning of OE
2
VWAIT2·(T2)
Ts
T5
HSYN pulse width
1
HWIDTH+1
Ts
T6
End of HSYN to beginning to T9
1
HWAIT2+1
Ts
T7
End of OE to beginning of HSYN
1
HWAIT1+1
Ts
T8
SCLK to valid LD data
-3
3
ns
T9
End of HSYN idle2 to VSYN edge
(for non-display region)
2
2
Ts
T9
End of HSYN idle2 to VSYN edge
(for Display region)
1
1
Ts
T10
VSYN to OE active (Sharp = 0),
when VWAIT2 = 0
1
1
Ts
T10
VSYN to OE active (Sharp = 1),
when VWAIT2 = 0
2
2
Ts
Note:
•
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
•
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 46, all 3 signals are active low.
•
The polarity of SCLK and LD[15:0] can also be programmed.
•
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 46, SCLK is
always active.
•
For T9 non-display region, VSYN is non-active. It is used as an reference.
•
XMAX is defined in pixels.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
63
Specifications
3.15 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal MMC/SD
module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of
FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and
the application (user programming).
3a
1
2
4b
3b
Bus Clock
4a
5b
5a
CMD_DAT Input
Valid Data
Valid Data
7
CMD_DAT Output
Valid Data
Valid Data
6b
6a
Figure 47. Chip-Select Read Cycle Timing Diagram
Table 29. SDHC Bus Timing Parameter Table
1.8V +/- 0.10V
Ref
No.
Parameter
1
3.0V +/- 0.30V
Unit
Min
Max
Min
Max
CLK frequency at Data transfer Mode (PP)1—10/30 cards
0
25/5
0
25/5
MHz
2
CLK frequency at Identification Mode2
0
400
0
400
KHz
3a
Clock high time1—10/30 cards
6/33
–
10/50
–
ns
3b
Clock low time1—10/30 cards
15/75
–
10/50
–
ns
4a
Clock fall time1—10/30 cards
–
10/50 (5.00)3
–
10/50
ns
4b
Clock rise time1—10/30 cards
–
14/67 (6.67)3
–
10/50
ns
5a
Input hold time3—10/30 cards
5.7/5.7
–
5/5
–
ns
5b
Input setup time3—10/30 cards
5.7/5.7
–
5/5
–
ns
6a
Output hold time3—10/30 cards
5.7/5.7
–
5/5
–
ns
6b
Output setup time3—10/30 cards
5.7/5.7
–
5/5
–
ns
7
Output delay time3
0
16
0
14
ns
1.
2.
3.
CL ≤ 100 pF / 250 pF (10/30 cards)
CL ≤ 250 pF (21 cards)
CL ≤ 25 pF (1 card)
MC9328MX1 Advance Information, Rev. 4
64
Freescale Semiconductor
Specifications
3.15.1 Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card response
to the host command starts after exactly NID clock cycles. For the card address assignment, SET_RCA is also
processed in the open-drain mode. The minimum delay between the host command and card response is NCR
clock cycles as illustrated in Figure 48. The symbols for Figure 48 through Figure 52 are defined in Table 30.
Table 30. State Signal Parameters for Figure 48 through Figure 52
Card Active
Symbol
Host Active
Definition
Symbol
Definition
Z
High impedance state
S
Start bit (0)
D
Data bits
T
Transmitter bit
(Host = 1, Card = 0)
*
Repetition
P
One-cycle pull-up (1)
Cyclic redundancy check bits (7 bits)
E
End bit (1)
CRC
NID cycles
Host Command
CMD S T
Content
CRC E Z
CID/OCR
******
Z ST
Content
ZZZ
Identification Timing
NCR cycles
Host Command
CMD S T
Content
CRC E Z
CID/OCR
******
Z ST
Content
ZZZ
SET_RCA Timing
Figure 48. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in Figure 49 on
page 66, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a period of
two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding card.
The other two diagrams show the separating periods NRC and NCC.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
65
Specifications
NCR cycles
Host Command
CMD S T
Content
Response
CRC E Z Z P
******
PST
Content
CRC E Z Z Z
Command response timing (data transfer mode)
NRC cycles
Response
CMD S T
Content
Host Command
CRC E Z
******
Z ST
Content
CRC E Z Z Z
Timing response end to next CMD start (data transfer mode)
NCC cycles
Host Command
CMD S T
Content
CRC E Z
Host Command
******
Z ST
Content
CRC E Z Z Z
Timing of command sequences (all modes)
Figure 49. Timing Diagrams at Data Transfer Mode
Figure 50 on page 67 shows basic read operation timing. In a read operation, the sequence starts with a single block
read command (which specifies the start address in the argument field). The response is sent on the SD_CMD lines
as usual. Data transmission from the card starts after the access time delay NAC , beginning from the last bit of the
read command. If the system is in multiple block read mode, the card sends a continuous flow of data blocks with
distance NAC until the card sees a stop transmission command. The data stops two clock cycles after the end bit of
the stop command.
MC9328MX1 Advance Information, Rev. 4
66
Freescale Semiconductor
Specifications
NCR cycles
Host Command
CMD S T
CRC E Z Z P ****** P S T
Content
DAT
Response
Z Z P ****** P S D D D D
Z****Z
CRC E Z
Content
*****
Read Data
NAC cycles
Timing of single block read
NCR cycles
Host Command
CMD S T
DAT
Content
Response
CRC E Z Z P ****** P S T
Z****Z
ZZP
******
Content
P S DDDD
CRC E Z
*****
P
P S DDDD
*****
Read Data
NAC cycles
*****
Read Data
NAC cycles
Timing of multiple block read
NCR cycles
Host Command
CMD S T
Response
CRC E Z Z P ****** P S T
Content
Content
CRC E Z
NST
DAT D D D D
*****
DDDDE Z Z Z
Valid Read Data
*****
Timing of stop command
(CMD12, data transfer mode)
Figure 50. Timing Diagrams at Data Read
Figure 51 on page 68 shows the basic write operation timing. As with the read operation, after the card response,
the data transfer starts after NWR cycles. The data is suffixed with CRC check bits to allow the card to check for
transmission errors. The card sends back the CRC check result as a CC status token on the data line. If there was a
transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC status (010) is returned.
The card expects a continuous flow of data blocks if it is configured to multiple block mode, with the flow
terminated by a stop transmission command.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
67
68
Z****Z
Z****Z
CRC E Z Z P
NWR cycles
CRC status
Timing of the multiple block write command
NWR cycles
Write Data
Content
DAT Z Z P P S
CRC E Z Z X X X X X X X X Z P P S
EZPPS
Content
Content
Status
PST
DAT Z Z P P S
CRC E Z Z S
******
Write Data
Content
******
Status
ES
L*L
EZ
PP P
ES
L*L
EZ
CRC status
Busy
CRC E Z Z X X X X X X X X X X X X X X X X Z
Status
PPP
CRC status
Busy
CRC E Z Z X X X X X X X X X X X X X X X X Z
CRC E Z Z S
Write Data
Content
Content
CRC E Z Z S
NWR cycles
Z ZZPPS
Z ZZPPS
CRC E Z Z P
Content
Response
******
Timing of the block write command
Content
NCR cycles
CMD E Z Z P
DAT
DAT
CMD S T
Host Command
Specifications
Figure 51. Timing Diagrams at Data Write
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
Freescale Semiconductor
Content
CRC E Z Z P
DAT Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z S L
DAT S L
DAT D D D D D D D Z Z S CRC E Z Z S L
Write Data
PST
******
Content
******
******
******
ST
Content
CRC E
Host Command
Stop transmission received after last data block.
Card becomes busy programming.
EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Stop transmission received after last data block.
Card becomes busy programming.
EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Stop transmission during CRC status transfer
from the card.
EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Stop transmission during data transfer
from the host.
EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
CRC E Z Z Z
Card Response
Busy (Card is programming)
******
NCR cycles
DAT D D D D D D D D D D D D D E Z Z S L
CMD S T
Host Command
Specifications
The stop transmission command may occur when the card is in different states. Figure 52 shows the different
scenarios on the bus.
Figure 52. Stop Transmission During Different Scenarios
MC9328MX1 Advance Information, Rev. 4
69
Specifications
Table 31. Timing Values for Figure 48 through Figure 52
Parameter
Symbol
Minimum
Maximum
Unit
MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL)
Command response cycle
NCR
2
64
Clock cycles
Identification response cycle
NID
5
5
Clock cycles
Access time delay cycle
NAC
2
TAAC + NSAC
Clock cycles
Command read cycle
NRC
8
–
Clock cycles
Command-command cycle
NCC
8
–
Clock cycles
Command write cycle
NWR
2
–
Clock cycles
Stop transmission cycle
NST
2
2
Clock cycles
TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register bit[111:104]
3.15.2 SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the interrupt
response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data in this mode. The
memory controller generates an interrupt according to this low and the system interrupt continues until the source
is removed (SD_DAT[1] returns to its high level).
In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt Period"
during the data access, and the controller must sample SD_DAT[1] during this short period to determine the IRQ
status of the attached card. The interrupt period only happens at the boundary of each block (512 bytes).
CMD
ST
DAT[1]
Content
CRC E Z Z P S
Interrupt Period
Response
S
EZZZ
Block Data
E
ZZZ
******
IRQ
S
Block Data
E
IRQ
For 4-bit
LH
DAT[1]
Interrupt Period
For 1-bit
Figure 53. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In this
mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the clock
running, and allows the user to submit commands as normal. After all commands are submitted, the user can switch
back to the data transfer operation and all counter and status values are resumed as access continues.
MC9328MX1 Advance Information, Rev. 4
70
Freescale Semiconductor
Specifications
CMD
DAT[1]
P S T CMD52
******
CRC E Z Z Z
******
S
Block Data
EZZL H
S
Block Data
E
S
Block Data
E Z Z L L L L L L L L L L L L L L L L L L L L L HZ S
Block Data
E
For 4-bit
DAT[2]
For 4-bit
Figure 54. SDIO ReadWait Timing Diagram
3.16 Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS, MS_SDIO,
and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in either four-state or
two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according to its
attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet transmissions occur.
During the BS1, BS2, and BS3 states, packet communications are executed. The BS1, BS2, and BS3 states are
regarded as one packet length and one communication transfer is always completed within one packet length (in
four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When an error
occurs during packet communication, the mode is shifted to two-state access mode, and the BS0 and BS1 bus states
are automatically repeated to avoid a bus collision on the SDIO.
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
71
Specifications
2
1
3
4
5
MS_SCLKI
6
8
7
MS_SCLKO
9
11
10
11
MS_BS
12
12
MS_SDIO (output)
14
13
MS_SDIO (input)
(RED bit = 0)
15
16
MS_SDIO (input)
(RED bit = 1)
Figure 55. MSHC Signal Timing Diagram
Table 32. MSHC Signal Timing Parameter Table
Ref No.
Parameter
Minimum
Maximum
Unit
1
MS_SCLKI frequency
–
25
MHz
2
MS_SCLKI high pulse width
20
–
ns
3
MS_SCLKI low pulse width
20
–
ns
4
MS_SCLKI rise time
–
3
ns
5
MS_SCLKI fall time
–
3
ns
6
MS_SCLKO frequency1
–
25
MHz
7
MS_SCLKO high pulse width1
20
–
ns
8
MS_SCLKO low pulse width1
15
–
ns
9
MS_SCLKO rise time1
–
5
ns
10
MS_SCLKO fall time1
–
5
ns
MC9328MX1 Advance Information, Rev. 4
72
Freescale Semiconductor
Specifications
Table 32. MSHC Signal Timing Parameter Table (Continued)
Ref No.
Parameter
Minimum
Maximum
Unit
11
MS_BS delay time1
–
3
ns
12
MS_SDIO output delay time1,2
–
3
ns
13
MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)3
18
–
ns
14
MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)3
0
–
ns
15
MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)4
23
–
ns
16
MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)4
0
–
ns
1.
2.
3.
4.
Loading capacitor condition is less than or equal to 30pF.
An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin,
because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick SDIO pin when the pin
direction changes.
If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.
If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
3.17 Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal
is passed through a divider and a prescaler before being input to the counter. The output is available at the pulsewidth modulator output (PWMO) external pin.
1
2a
3b
System Clock
2b
4b
3a
4a
PWM Output
Figure 56. PWM Output Timing Diagram
Table 33. PWM Output Timing Parameter Table
Ref
No.
1.8V +/- 0.10V
3.0V +/- 0.30V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
0
87
0
100
MHz
1
System CLK frequency1
2a
Clock high time1
3.3
–
5/10
–
ns
2b
Clock low time1
7.5
–
5/10
–
ns
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
73
Specifications
Table 33. PWM Output Timing Parameter Table (Continued)
Ref
No.
1.8V +/- 0.10V
3.0V +/- 0.30V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
3a
Clock fall time1
–
5
–
5/10
ns
3b
Clock rise time1
–
6.67
–
5/10
ns
4a
Output delay time1
5.7
–
5
–
ns
4b
Output setup time1
5.7
–
5
–
ns
1.
CL of PWMO = 30 pF
3.18 SDRAM Memory Controller
A write to an address within the memory region initiates the program sequence. The first command issued to the
SyncFlash is Load Command Register. A [7:0] determine which operation the command performs. For this write
setup operation, an address of 0x40 is hardware generated. The bank and other address lines are driven with the
address to be programmed. The next command is Active which registers the row address and confirms the bank
address. The third command supplies the column address, re-confirms the bank address, and supplies the data to be
written. SyncFlash does not support burst writes, therefore a Burst Terminate command is not required.
A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash is the
Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register operation. The
bank and other address lines are driven to the selected address. The second command is Active which sets up the
status register read. The bank and row addresses are driven during this command. The third command of the triplet
is Read. Bank and column addresses are driven on the address bus during this command. Data is returned from
memory on the low order 8 data bits following the CAS latency.
MC9328MX1 Advance Information, Rev. 4
74
Freescale Semiconductor
Specifications
1
SDCLK
2
3S
3
CS
3H
3S
RAS
3S
3H
CAS
3S
3H
3H
WE
4S
ADDR
4H
ROW/BA
COL/BA
8
5
6
DQ
Data
7
3S
DQM
3H
Note:
CKE is high during the read/write cycle.
Figure 57. SDRAM/SyncFlash Read Cycle Timing Diagram
Table 34. SDRAM Timing Parameter Table
1.8V
Ref
No.
3.0V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
SDRAM clock high-level width
2.67
–
4
–
ns
2
SDRAM clock low-level width
6
–
4
–
ns
3
SDRAM clock cycle time
10.4
–
10
–
ns
CS, RAS, CAS, WE, DQM setup time
3.42
–
3
–
ns
3S
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
75
Specifications
Table 34. SDRAM Timing Parameter Table (Continued)
Ref
No.
1.8V
3.0V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
3H
CS, RAS, CAS, WE, DQM hold time
2.28
–
2
–
ns
4S
Address setup time
3.42
–
3
–
ns
4H
Address hold time
2.28
–
2
–
ns
5
SDRAM access time (CL = 3)
–
6.84
–
6
ns
5
SDRAM access time (CL = 2)
–
6.84
–
6
ns
5
SDRAM access time (CL = 1)
–
22
–
22
ns
6
Data out hold time
2.85
–
2.5
–
ns
7
Data out high-impedance time (CL = 3)
–
6.84
–
6
ns
7
Data out high-impedance time (CL = 2)
–
6.84
–
6
ns
7
Data out high-impedance time (CL = 1)
–
22
–
22
ns
8
Active to read/write command period (RC = 1)
tRCD1
–
tRCD1
–
ns
1.
tRCD = SDRAM clock cycle time. The tRCD setting can be found in the MC9328MX1 reference manual.
MC9328MX1 Advance Information, Rev. 4
76
Freescale Semiconductor
Specifications
SDCLK
1
3
2
CS
RAS
6
CAS
WE
4
ADDR
5
7
/ BA
COL/BA
ROW/BA
8
9
DQ
DATA
DQM
Figure 58. SDRAM/SyncFlash Write Cycle Timing Diagram
Table 35. SDRAM Write Timing Parameter Table
1.8V
Ref
No.
3.3V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
SDRAM clock high-level width
2.67
–
4
–
ns
2
SDRAM clock low-level width
6
–
4
–
ns
3
SDRAM clock cycle time
10.4
–
10
–
ns
4
Address setup time
3.42
–
3
–
ns
5
Address hold time
2.28
–
2
–
ns
6
Precharge cycle period1
tRP2
–
tRP2
–
ns
7
Active to read/write command delay
tRCD2
–
tRCD2
–
ns
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
77
Specifications
Table 35. SDRAM Write Timing Parameter Table (Continued)
1.8V
Ref
No.
3.3V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
8
Data setup time
4.0
–
2
–
ns
9
Data hold time
2.28
–
2
–
ns
1.
2.
Precharge cycle timing is included in the write timing diagram.
tRP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference
manual.
SDCLK
1
3
2
CS
RAS
6
CAS
7
7
WE
4
ADDR
5
ROW/BA
BA
DQ
DQM
Figure 59. SDRAM Refresh Timing Diagram
Table 36. SDRAM Refresh Timing Parameter Table
Ref
No.
1
1.8V
3.3V
Parameter
Unit
SDRAM clock high-level width
Minimum
Maximum
Minimum
Maximum
2.67
–
4
–
ns
MC9328MX1 Advance Information, Rev. 4
78
Freescale Semiconductor
Specifications
Table 36. SDRAM Refresh Timing Parameter Table (Continued)
1.8V
Ref
No.
3.3V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
6
–
4
–
ns
2
SDRAM clock low-level width
3
SDRAM clock cycle time
10.4
–
10
–
ns
4
Address setup time
3.42
–
3
–
ns
5
Address hold time
2.28
–
2
–
ns
6
Precharge cycle period
tRP1
–
tRP1
–
ns
7
Auto precharge command period
tRC1
–
tRC1
–
ns
1.
tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference
manual.
SDCLK
CS
RAS
CAS
WE
ADDR
BA
DQ
DQM
CKE
Figure 60. SDRAM Self-Refresh Cycle Timing Diagram
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
79
Specifications
3.19 USB Device Port
Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers,
and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is identical to the bulk
data transfer mode, and no additional hardware is supplied to support it. This section covers the transfer modes and
how they work from the ground up.
Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet
transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of
packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is
no end-of-transfer.
USBD_AFE
(Output)
1
t VMO_ROE 4
t ROE_VPO
USBD_ROE
(Output)
tPERIOD
6
3
tVPO_ROE
USBD_VPO
(Output)
USBD_VMO
(Output)
USBD_SUSPND
(Output)
tROE_VMO
tFEOPT
2
5
USBD_RCV
(Input)
USBD_VP
(Input)
USBD_VM
(Input)
Figure 61. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX)
Table 37. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX)
Ref No.
Parameter
Minimum
Maximum
Unit
1
tROE_VPO; USBD_ROE active to USBD_VPO low
83.14
83.47
ns
2
tROE_VMO; USBD_ROE active to USBD_VMO high
81.55
81.98
ns
3
tVPO_ROE; USBD_VPO high to USBD_ROE deactivated
83.54
83.80
ns
4
tVMO_ROE; USBD_VMO low to USBD_ROE deactivated (includes SE0)
248.90
249.13
ns
5
tFEOPT; SE0 interval of EOP
160.00
175.00
ns
MC9328MX1 Advance Information, Rev. 4
80
Freescale Semiconductor
Specifications
Table 37. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX) (Continued)
Ref No.
6
Parameter
tPERIOD; Data transfer rate
Minimum
Maximum
Unit
11.97
12.03
Mb/s
USBD_AFE
(Output)
USBD_ROE
(Output)
USBD_VPO
(Output)
USBD_VMO
(Output)
USBD_SUSPND
(Output)
USBD_RCV
(Input)
1
tFEOPR
USBD_VP
(Input)
USBD_VM
(Input)
Figure 62. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX)
Table 38. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)
Ref
No.
1
Parameter
tFEOPR; Receiver SE0 interval of EOP
Minimum
Maximum
Unit
82
–
ns
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
81
Specifications
3.20 I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction,
Slave Acknowledge, Data, Data Acknowledge, and STOP.
SDA
5
3
4
SCL
2
1
6
Figure 63. Definition of Bus Timing for I2C
Table 39. I2C Bus Timing Parameter Table
1.8V +/- 0.10V
Ref
No.
3.0V +/- 0.30V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
182
–
160
–
ns
1
Hold time (repeated) START condition
2
Data hold time
0
171
0
150
ns
3
Data setup time
11.4
–
10
–
ns
4
HIGH period of the SCL clock
80
–
120
–
ns
5
LOW period of the SCL clock
480
–
320
–
ns
6
Setup time for STOP condition
182.4
–
160
–
ns
3.21 Synchronous Serial Interface
The MC9328MX1 processor contains two identical SSI modules. The transmit and receive sections of the SSI can
be synchronous or asynchronous. In synchronous mode, the transmitter and the receiver use a common clock and
frame synchronization signal. In asynchronous mode, the transmitter and receiver each have their own clock and
frame synchronization signals. Continuous or gated clock mode can be selected. In continuous mode, the clock
runs continuously. In gated clock mode, the clock functions only during transmission. The internal and external
clock timing diagrams are shown in Figure 65 through Figure 67 on page 84.
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used
in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division
multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These
distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices.
MC9328MX1 Advance Information, Rev. 4
82
Freescale Semiconductor
Specifications
1
STCK Output
2
4
STFS (bl) Output
6
8
STFS (wl) Output
12
11
10
STXD Output
31
32
SRXD Input
Note:
SRXD input in synchronous mode only.
Figure 64. SSI Transmitter Internal Clock Timing Diagram
1
SRCK Output
3
5
SRFS (bl) Output
7
9
SRFS (wl) Output
13
14
SRXD Input
Figure 65. SSI Receiver Internal Clock Timing Diagram
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
83
Specifications
15
16
17
STCK Input
18
20
STFS (bl) Input
24
22
STFS (wl) Input
28
27
26
STXD Output
34
33
SRXD Input
Note: SRXD Input in Synchronous mode only.
Figure 66. SSI Transmitter External Clock Timing Diagram
15
16
17
SRCK Input
19
21
SRFS (bl) Input
25
23
SRFS (wl) Input
30
29
SRXD Input
Figure 67. SSI Receiver External Clock Timing Diagram
Table 40. SSI 1 Timing Parameter Table
Ref
No.
1.8V +/- 0.10V
3.0V +/- 0.30V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
Internal Clock Operation1 (Port C Primary Function)2
1
STCK/SRCK clock period1
95
–
83.3
–
ns
2
STCK high to STFS (bl) high3
1.5
4.5
1.3
3.9
ns
MC9328MX1 Advance Information, Rev. 4
84
Freescale Semiconductor
Table 40. SSI 1 Timing Parameter Table (Continued)
NOTES
1.8V +/- 0.10V
Ref
No.
3.0V +/- 0.30V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
3
SRCK high to SRFS (bl) high3
-1.2
-1.7
-1.1
-1.5
ns
4
STCK high to STFS (bl) low3
2.5
4.3
2.2
3.8
ns
5
SRCK high to SRFS (bl) low3
0.1
-0.8
0.1
-0.8
ns
6
STCK high to STFS (wl) high3
1.48
4.45
1.3
3.9
ns
7
SRCK high to SRFS (wl) high3
-1.1
-1.5
-1.1
-1.5
ns
8
STCK high to STFS (wl) low3
2.51
4.33
2.2
3.8
ns
9
SRCK high to SRFS (wl) low3
0.1
-0.8
0.1
-0.8
ns
10
STCK high to STXD valid from high
impedance
14.25
15.73
12.5
13.8
ns
11a
STCK high to STXD high
0.91
3.08
0.8
2.7
ns
11b
STCK high to STXD low
0.57
3.19
0.5
2.8
ns
12
STCK high to STXD high impedance
12.88
13.57
11.3
11.9
ns
13
SRXD setup time before SRCK low
21.1
–
18.5
–
ns
14
SRXD hold time after SRCK low
0
–
0
–
ns
External Clock Operation (Port C Primary Function)2
15
STCK/SRCK clock period1
92.8
–
81.4
–
ns
16
STCK/SRCK clock high period
27.1
–
40.7
–
ns
17
STCK/SRCK clock low period
61.1
–
40.7
–
ns
18
STCK high to STFS (bl) high3
–
92.8
0
81.4
ns
19
SRCK high to SRFS (bl) high3
–
92.8
0
81.4
ns
20
STCK high to STFS (bl) low3
–
92.8
0
81.4
ns
21
SRCK high to SRFS (bl) low3
–
92.8
0
81.4
ns
22
STCK high to STFS (wl) high3
–
92.8
0
81.4
ns
23
SRCK high to SRFS (wl) high3
–
92.8
0
81.4
ns
24
STCK high to STFS (wl) low3
–
92.8
0
81.4
ns
25
SRCK high to SRFS (wl) low3
–
92.8
0
81.4
ns
26
STCK high to STXD valid from high
impedance
18.01
28.16
15.8
24.7
ns
27a
STCK high to STXD high
8.98
18.13
7.0
15.9
ns
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
85
Specifications
Table 40. SSI 1 Timing Parameter Table (Continued)
Ref
No.
1.8V +/- 0.10V
3.0V +/- 0.30V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
27b
STCK high to STXD low
9.12
18.24
8.0
16.0
ns
28
STCK high to STXD high impedance
18.47
28.5
16.2
25.0
ns
29
SRXD setup time before SRCK low
1.14
–
1.0
–
ns
30
SRXD hole time after SRCK low
0
–
0
–
ns
Synchronous Internal Clock Operation (Port C Primary Function)2
31
SRXD setup before STCK falling
32
SRXD hold after STCK falling
15.4
–
13.5
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (Port C Primary Function)2
33
SRXD setup before STCK falling
34
SRXD hold after STCK falling
1.
2.
3.
1.14
–
1.0
–
ns
0
–
0
–
ns
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a
non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (PC3 – PC8)
and Port B alternate function (PB14 – PB19). When SSI signals are configured as outputs, they can be
viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as
input, the SSI module selects the input based on status of the FMCR register bits in the Clock controller
module (CRM). By default, the input are selected from Port C primary function.
bl = bit length; wl = word length.
Table 41. SSI 2 Timing Parameter Table
Ref
No.
1.8V +/- 0.10V
3.0V +/- 0.30V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
Internal Clock Operation1 (Port B Alternate Function)2
1
STCK/SRCK clock period1
95
–
83.3
–
ns
2
STCK high to STFS (bl) high3
1.7
4.8
1.5
4.2
ns
3
SRCK high to SRFS (bl) high3
-0.1
1.0
-0.1
1.0
ns
4
STCK high to STFS (bl) low3
3.08
5.24
2.7
4.6
ns
5
SRCK high to SRFS (bl) low3
1.25
2.28
1.1
2.0
ns
MC9328MX1 Advance Information, Rev. 4
86
Freescale Semiconductor
Specifications
Table 41. SSI 2 Timing Parameter Table (Continued)
1.8V +/- 0.10V
Ref
No.
3.0V +/- 0.30V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
6
STCK high to STFS (wl) high3
1.71
4.79
1.5
4.2
ns
7
SRCK high to SRFS (wl) high3
-0.1
1.0
-0.1
1.0
ns
8
STCK high to STFS (wl) low3
3.08
5.24
2.7
4.6
ns
9
SRCK high to SRFS (wl) low3
1.25
2.28
1.1
2.0
ns
10
STCK high to STXD valid from high
impedance
14.93
16.19
13.1
14.2
ns
11a
STCK high to STXD high
1.25
3.42
1.1
3.0
ns
11b
STCK high to STXD low
2.51
3.99
2.2
3.5
ns
12
STCK high to STXD high impedance
12.43
14.59
10.9
12.8
ns
13
SRXD setup time before SRCK low
20
–
17.5
–
ns
14
SRXD hold time after SRCK low
0
–
0
–
ns
External Clock Operation (Port B Alternate Function)2
15
STCK/SRCK clock period1
92.8
–
81.4
–
ns
16
STCK/SRCK clock high period
27.1
–
40.7
–
ns
17
STCK/SRCK clock low period
61.1
–
40.7
–
ns
18
STCK high to STFS (bl) high3
–
92.8
0
81.4
ns
19
SRCK high to SRFS (bl) high3
–
92.8
0
81.4
ns
20
STCK high to STFS (bl) low3
–
92.8
0
81.4
ns
21
SRCK high to SRFS (bl) low3
–
92.8
0
81.4
ns
22
STCK high to STFS (wl) high3
–
92.8
0
81.4
ns
23
SRCK high to SRFS (wl) high3
–
92.8
0
81.4
ns
24
STCK high to STFS (wl) low3
–
92.8
0
81.4
ns
25
SRCK high to SRFS (wl) low3
–
92.8
0
81.4
ns
26
STCK high to STXD valid from high
impedance
18.9
29.07
16.6
25.5
ns
27a
STCK high to STXD high
9.23
20.75
8.1
18.2
ns
27b
STCK high to STXD low
10.60
21.32
9.3
18.7
ns
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
87
Specifications
Table 41. SSI 2 Timing Parameter Table (Continued)
Ref
No.
1.8V +/- 0.10V
3.0V +/- 0.30V
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
28
STCK high to STXD high impedance
17.90
29.75
15.7
26.1
ns
29
SRXD setup time before SRCK low
1.14
–
1.0
–
ns
30
SRXD hole time after SRCK low
0
–
0
–
ns
Synchronous Internal Clock Operation (Port B Alternate Function)2
31
SRXD setup before STCK falling
32
SRXD hold after STCK falling
18.81
–
16.5
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (Port B Alternate Function)2
33
SRXD setup before STCK falling
34
SRXD hold after STCK falling
1.
2.
3.
1.14
–
1.0
–
ns
0
–
0
–
ns
All the timings for both SSI modules are given for a non-inverted serial clock polarity (TSCKP/RSCKP =
0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
There is one set of I/O signals for the SSI2 module. They are from Port C alternate function (PC19 –
PC24). When SSI signals are configured as outputs, they can be viewed at Port C alternate function a.
When SSI signals are configured as inputs, the SSI module selects the input based on FMCR register bits
in the Clock controller module (CRM). By default, the input is selected from Port C alternate function.
bl = bit length; wl = word length
3.22 CMOS Sensor Interface
The CSI module consists of a control register to configure the interface timing, a control register for statistic data
generation, a status register, interface logic, a 32 × 32 image data receive FIFO, and a 16 × 32 statistic data FIFO.
3.22.1 Gated Clock Mode
Figure 68 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the
CSI is programmed to received data on the positive edge. Figure 69 on page 89 shows the timing diagram when the
CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative
edge. The parameters for the timing diagrams are listed in Table 42 on page 89.
MC9328MX1 Advance Information, Rev. 4
88
Freescale Semiconductor
Specifications
1
VSYNC
7
HSYNC
5
6
2
PIXCLK
Valid Data
DATA[7:0]
Valid Data
Valid Data
4
3
Figure 68. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
1
VSYNC
7
HSYNC
5
6
2
PIXCLK
Valid Data
DATA[7:0]
3
Valid Data
Valid Data
4
Figure 69. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 42. Gated Clock Mode Timing Parameters
Ref No.
Parameter
Minimum
Maximum
Unit
1
csi_vsync to csi_hsync
9 * THCLK
–
ns
2
csi_hsync to csi_pixclk
3
(Tp / 2) - 3
ns
3
csi_d setup time
1
–
ns
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
89
Specifications
Table 42. Gated Clock Mode Timing Parameters (Continued)
Ref No.
Parameter
Minimum
Maximum
Unit
1
–
ns
4
csi_d hold time
5
csi_pixclk high time
10.42
–
ns
6
csi_pixclk low time
10.42
–
ns
7
csi_pixclk frequency
0
48
MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and
setup time, according to:
Rising-edge latch data
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
3.22.2 Non-Gated Clock Mode
Figure 70 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the
CSI is programmed to received data on the positive edge. Figure 71 on page 91 shows the timing diagram when the
CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative
edge. The parameters for the timing diagrams are listed in Table 43 on page 91.
MC9328MX1 Advance Information, Rev. 4
90
Freescale Semiconductor
Specifications
1
VSYNC
6
5
4
PIXCLK
Valid Data
DATA[7:0]
2
Valid Data
Valid Data
3
Figure 70. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
1
VSYNC
6
4
5
PIXCLK
Valid Data
DATA[7:0]
2
Valid Data
Valid Data
3
Figure 71. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 43. Non-Gated Clock Mode Parameters
Ref No.
Parameter
Minimum
Maximum
Unit
9 * THCLK
–
ns
1
csi_vsync to csi_pixclk
2
csi_d setup time
1
–
ns
3
csi_d hold time
1
–
ns
4
csi_pixclk high time
10.42
–
ns
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
91
Specifications
Table 43. Non-Gated Clock Mode Parameters (Continued)
Ref No.
Parameter
5
csi_pixclk low time
6
csi_pixclk frequency
Minimum
Maximum
Unit
10.42
–
ns
0
48
MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and
setup time, according to:
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore:
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
MC9328MX1 Advance Information, Rev. 4
92
Freescale Semiconductor
Freescale Semiconductor
4 Pin-Out and Package Information
Table 44. MC9328MX1 BGA Pin Assignments
1
2
3
A
VSS SD_DAT3 SD_CLK
B
4
VSS
5
6
7
8
9
10
11
12
13
14
15
16
MC9328MX1 Advance Information, Rev. 4
USBD_AFE NVDD4
VSS
UART1_RTS UART1_RXD
NVDD3
BT5
BT3
QVDD4
RVP
UIP
NC
A24 SD_DAT1 SD_CMD SIM_TX
USBD_OE
SSI_RXCLK
SSI_TXCLK
SPI1_SCLK
BT11
BT7
BT1
VSS
RVM
UIN
NC
C
A23 D31
SD_DAT0 SIM_PD
USBD_RCV UART2_
CTS
UART1_TXD
BTRFGND BT8
BTRFVDD
NC
AVDD2
VSS
R1B
D
A22 D30
D29
SIM_SVEN USBD_
SUSPND
USBD_VPO USBD_VMO SSI_RXDAT SPI1_SPI_RDY BT13
BT6
NC
NC
NC
R1A
R2B
E
A20 A21
D28
D26
SD_DAT2
USBD_VM
UART2_RTS SSI_TXDAT
SPI1_SS
BT12
BT4
NC
NC
PY2
PX2
R2A
F
A18 D27
D25
A19
A16
SIM_RST
UART2_TXD SSI_TXFS
SPI1_MISO
BT10
BT2
REV
PY1
PX1
LSCLK
SPL_SPR
G
A15 A17
D24
D23
D21
SIM_RX
SIM_CLK
UART1_CTS SPI1_MOSI
BT9
CLS
CONTRAST ACD/OE
LP/HSYNC
FLM/VSYNC LD1
H
A13 D22
A14
D20
NVDD1
NVDD1
VSS
VSS
QVDD1
PS
LD0
LD2
LD4
LD5
LD9
LD3
J
A12 A11
D18
D19
NVDD1
NVDD1
VSS
NVDD1
VSS
VSS
LD6
LD7
LD8
LD11
QVDD3
VSS
K
A10 D16
A9
D17
NVDD1
VSS
VSS
NVDD1
NVDD2
NVDD2
LD10
LD12
LD13
LD14
TMR2OUT
LD15
L
A8
A7
D13
D15
D14
NVDD1
VSS
CAS
TCK
TIN
PWMO
CSI_MCLK
CSI_D0
CSI_D1
CSI_D2
CSI_D3
M
A5
D12
D11
A6
SDCLK
VSS
RW
MA10
RAS
RESET_IN BIG_
CSI_D4
ENDIAN
CSI_HSYNC CSI_VSYNC CSI_D6
CSI_D5
N
A4
EB1
D10
D7
A0
D4
PA17
D1
DQM1
RESET_
SF
RESET_ BOOT2
OUT
CSI_PIXCLK CSI_D7
TMS
TDI
P
A3
D9
EB0
CS3
D6
ECB
D2
D3
DQM3
SDCKE1
BOOT3
TRST
I2C_SCL
I2C_SDA
XTAL32K
D0
DQM0
SDCKE0 POR
BOOT1
TDO
QVDD2
EXTAL32K
DQM2
SDWE
CLKO
TRISTATE
EXTAL16M
XTAL16M
VSS
USBD_VP
UART2_RXD SSI_RXFS
R
EB2 EB3
A1
CS4
D8
D5
LBA
BCLK1
T
VSS A2
OE
CS5
CS2
CS1
CS0
MA11
1.
BOOT0
AVDD1
burst clock
Pin-Out and Package Information
93
Pin-Out and Package Information
4.1 MAPBGA Package Dimensions
Figure 72 illustrates the MAPBGA 14 mm × 14 mm × 1.30 mm package, which has 0.8 mm spacing between the
pads. The device designator for the MAPBGA package is VH.
Figure 72. MC9328MX1 MAPBGA Mechanical Drawing
MC9328MX1 Advance Information, Rev. 4
94
Freescale Semiconductor
NOTES
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
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MC9328MX1/D
Rev. 4
08/2004