DS26F32MQML Quad Differential Line Receivers General Description The DS26F32 is a quad differential line receiver designed to meet the requirements of EIA Standards RS-422 and RS423, and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission. The DS26F32 offers improved performance due to the use of state-of-the-art L-FAST bipolar technology. The L-FAST technology allows for higher speeds and lower currents by utilizing extremely short gate delay times. Thus, the DS26F32 features lower power, extended temperature range, and improved specifications. The device features an input sensitivity of 200 mV over the input common mode range of ± 7.0V. The DS26F32 provides an enable function common to all four receivers and TRISTATE ® outputs with 8.0 mA sink capability. Also, a fail-safe input/output relationship keeps the outputs high when the inputs are open. The DS26F32 offers optimum performance when used with the DS26F31 Quad Differential Line Driver. Features n Input voltage range of ± 7.0V (differential or common mode) ± 0.2V sensitivity over the input voltage range n High input impedance n Operation from single +5.0V supply n Input pull-down resistor prevents output oscillation on unused channels n TRI-STATE outputs, with choice of complementary enables, for receiving directly onto a data bus Ordering Information NS Part Number SMD Part Number NS Package Number DS26F32ME/883 5962–7802005M2A E20A Package Description DS26F32MJ/883 5962–7802005MEA J16A 16LD Ceramic DIP DS26F32MW/883 5962–7802005MFA W16A 16LD Ceramic FLatpack DS26F32MWG/883 5962–7802005MZA WG16A DS26F32MER-QML 5962R7802005M2A E20A 20LD Leadless Chip Carrier DS26F32MJR-QML 5962R7802005QEA J16A 16LD Ceramic DIP DS26F32MWR-QML 5962R7802005QFA W16A 16LD Ceramic FLatpack DS26F32MJ-QMLV 5962–7802005VEA J16A 16LD Ceramic DIP DS26F32MW-QMLV 5962–7802005VFA W16A 16LD Ceramic FLatpack DS26F32MWG-QMLV 5962–7802005VZA WG16A DS26F32MJRQMLV 5962R7802005VEA 100k rd(Si) J16A 16LD Ceramic DIP DS26F32MWRQMLV 5962R7802005VFA 100k rd(Si) W16A 16LD Ceramic FLatpack DS26F32MWGRQMLV 5962R7802005VZA 100k rd(Si) WG16A 20LD Leadless Chip Carrier 16LD Ceramic SOIC 16LD Ceramic SOIC 16LD Ceramic SOIC TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS201633 www.national.com DS26F32MQML Quad Differential Line Receivers March 2006 DS26F32MQML Connection Diagrams 20163307 20-Lead Ceramic Leadless Chip Carrier See NS Package Number E20A 20163301 Top View 16-Lead Ceramic DIP Pictured See NS Package Number WG16A, J16A or W16A Function Table (Each Receiver) Differential Inputs Enables E E OUT VID ≥ 0.2V H X H X L H H X L X L L L H Z VID ≤ −0.2V X H = High Level L = Low Level X = Immaterial www.national.com Outputs VID = (V I+) − (VI−) 2 DS26F32MQML Absolute Maximum Ratings (Note 1) Storage Temperature Range −65˚C ≤ TA ≤ +150˚C Operating Temperature Range −55˚C ≤ TA ≤ +125˚C Lead Temperature (soldering, 60 sec) 300˚C Supply Voltage 7.0V Common Mode Voltage Range Differential Input Voltage ± 25V ± 25V Enable Voltage 7.0V Output Sink Current Maximum Power Dissipation (PD 50 mA maxat 25˚C (Note 2), (Note 3) 500 mW Thermal Resistance θJA Ceramic DIP 100˚C/W Ceramic Flatpack 142˚C/W Leadless Chip Carrier 87˚C/W θJC Junction-to- case See MIL-STD-1835 Recommended Operating Range −55˚C ≤ TA ≤ +125˚C Operating Temperature Supply Voltage 4.5V to 5.5V Radiation Features DS26F32MJRQMLV 100 krads (Si) DS26F32MWRQMLV 100 krads (Si) DS26F32MWGRQMLV 100 krads (Si) Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description 1 Static tests at 25 2 Static tests at 125 3 Static tests at -55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at -55 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at -55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at -55 12 Settling time at 25 13 Settling time at 125 14 Settling time at -55 3 Temp ˚C www.national.com DS26F32MQML DS26F32 Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified. DC: VCC = 5V Symbol IIn (Note 7) Parameter Input Current Max Units Subgroups Pin under test VCC = 4.5V, VI = 15V Other inputs -15V ≤ VI ≤ +15V 2.3 mA 1, 2, 3 Pin under test VCC = 5.5V, VI = -15V Other inputs -15V ≤ VI ≤ +15V -2.8 mA 1, 2, 3 -360 µA 1, 2, 3 10 µA 1, 2, 3 Conditions Notes Min IIL Logical "0" Enable Current VCC = 5.5V, VEn = 0.4V IIH Logical "1" Enable Current VCC = 5.5V, VI = 2.7V II Logical "1" Enable Current VCC = 5.5V, VI = 5.5V 50 µA 1, 2, 3 VIK Input Clamp Voltage (Enable) VCC = 4.5V, II = -18mA -1.5 V 1, 2, 3 VOH Logical "1" Output Voltage VCC = 4.5V, IOH = -440µA, ∆VI = 1V, VEn = .8 = VEn V 1, 2, 3 VOL Logical "0" Output Voltage VCC = 4.5V, VEn =0.8V = VEn, IOL = 4mA, ∆VI = -1V 0.4 V 1, 2, 3 VCC = 4.5V, VEn = 8V = VEn, IOL = 8mA, ∆VI = -1V .45 V 1, 2, 3 2.5 ICC Supply Current VCC = 5.5V, All VI = Gnd, VEn = 0V, VEn = 2V 50 mA 1, 2, 3 IOZ Off-State Output Current VCC = 5.5V, VO = 0.4V, VEn = 0.8V, VEn = 2V -20 µA 1, 2, 3 VCC = 5.5V, VO = 2.4V, VEn = 0.8V, VEn = 2V 20 µA 1, 2, 3 RI Input Resistance -15 ≤ VCM ≤ 15V KΩ 1, 2, 3 VTh Differential Input Voltage VCC = 4.5V, VOUT = VOL or VOH -7V ≤ VCM ≤ 7V, VEn = VEn = 2.5V (Note 4) -0.2 0.2 V 1, 2, 3 VCC = 5.5V, VOUT = VOL or VOH -7V ≤ VCM ≤ 7V, VEn = VEn = 2.5V (Note 4) -0.2 0.2 V 1, 2, 3 0.8 V 1, 2, 3 2.0 V 1, 2, 3 -15 mA 1, 2, 3 mA 1, 2, 3 14 VIL Logical "0" Input Voltage (Enable) VCC = 5.5V (Note 4) VIH Logical "1" Input Voltage (Enable) VCC = 4.5V (Note 4) ISC Min Output Short Circuit Current VCC = 4.5V, VO = 0V, ∆VI = 1V ISC Max Output Short Circuit Current VCC = 5.5V, VO = 0V, ∆VI = 1V www.national.com 4 -85 DS26F32MQML DS26F32 Electrical Characteristics (Continued) AC Parameters The following conditions apply, unless otherwise specified. AC: Symbol VCC = 5V (Note 7) Parameter Conditions tPHL Units (Note 6) 23 nS 9 (Note 6) 31 nS 10, 11 CL = 15pF (Note 5) 22 nS 9 (Note 5) 30 nS 10, 11 CL = 50pF (Note 6) 23 nS 9 (Note 6) 31 nS 10, 11 (Note 5) 22 nS 9 (Note 5) 30 nS 10, 11 (Note 6) 18 nS 9 (Note 6) 29 nS 10, 11 (Note 5) 16 nS 9 (Note 5) 27 nS 10, 11 CL = 50pF (Note 6) 20 nS 9 (Note 6) 29 nS 10, 11 CL = 15pF (Note 5) 18 nS 9 (Note 5) 27 nS 10, 11 CL = 50pF (Note 6) 55 nS 9 (Note 6) 62 nS 10, 11 CL = 5pF (Note 5) 20 nS 9 (Note 5) 27 nS 10, 11 (Note 6) 30 nS 9 (Note 6) 42 nS 10, 11 (Note 5) 18 nS 9 (Note 5) 30 nS 10, 11 CL = 15pF tPZH Enable Time CL = 50pF CL = 15pF tPZL tPHZ tPLZ Enable Time Disable Time Disable Time CL = 50pF CL = 5pF Min Subgroups Max CL = 50pF tPLH Notes DC Drift Parameters This section applies to -QMLV devices only. Devices shall be read & recorded at TA = 25˚C before and after each burn-in and shall not change by more than the limits indicated. The delta rejects shall be included in the PDA calculation. Symbol Parameter Conditions Notes Min Max Units Subgroups VOH Logical "1" Output Voltage VCC = 4.5V, IOH = -440µA, ∆VI = 1V, VEn = 0.8V = VEn -250 250 mV 1 VOL Logical "0" Output Voltage VCC = 4.5V, IOL = 4mA, ∆VI = -1V, VEn = 0.8V = VEn -45 45 mV 1 VCC = 4.5V, IOL = 8mA, ∆ VI = -1V, VEn = 0.8V = VEn -45 45 mV 1 Pin under test VCC = 4.5V, VI = 15V Other inputs -15V ≤ VI ≤ +15V -0.28 0.28 mA 1 Pin under test VCC = 5.5V, VI = -15V Other inputs -15V ≤ VI ≤ +15V -0.28 0.28 mA 1 II Input Current 5 www.national.com DS26F32MQML Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: Derate J package 10.0mW/˚C above +25˚C, derate W package 7.1mW/˚C above +25˚C, derate E package 11.5mW/˚C above +25˚C. Note 3: Power dissipation must be externally controlled at elevated temperatures. Note 4: Parameter tested go-no-go only. Note 5: Tested at 50pF guarantees limit at 15pF & 5pF. Note 6: Tested at 50pF, system capacitance exceeds 5pF to 15pF. Note 7: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in Mil-Std-883, Method 1019.5, Condition A 20163302 FIGURE 1. Logic Symbol 20163303 FIGURE 2. Load Test Circuit for Three-State Outputs 20163304 FIGURE 3. Propagation Delay (Notes 8, 9, 10) www.national.com 6 DS26F32MQML 20163305 Note 8: Diagram shown for ENABLE Low. Note 9: S1 and S2 of Load Circuit are closed except where shown. Note 10: Pulse Generator of all Pulses: Rate ≤ 1.0 MHz, ZO = 50Ω, tr ≤ 6.0 ns, tf ≤ 6.0 ns. Note 11: All diodes are IN916 or IN3064. Note 12: C L includes probe and jig capacitance. FIGURE 4. Enable and Disable Times (Notes 8, 9, 10) Typical Application 20163306 FIGURE 5. 7 www.national.com DS26F32MQML Revision History Released 03/01/06 www.national.com Revision A Section Originator New Release, Corporate format L. Lytle 8 Changes 1 MDS data sheet converted into one Corp. data sheet format. MNDS26F32M-X-RH Rev 0C0 will be archived. DS26F32MQML Physical Dimensions inches (millimeters) unless otherwise noted 20LD Leadless Chip Carrier (E) NS Package Number E20A Ceramic Dual-In-Line Package (J) NS Package Number J16A 9 www.national.com DS26F32MQML Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16LD Ceramic Flatpack (W) NS Package Number W16A 16LD Ceramic SOIC (WG) NS Package Number WG16A www.national.com 10 DS26F32MQML Quad Differential Line Receivers Notes National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. Leadfree products are RoHS compliant. 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