ON NCV7340D14R2G High speed low power can transceiver Datasheet

NCV7340
High Speed Low Power CAN
Transceiver
Description
The NCV7340 CAN transceiver is the interface between a
controller area network (CAN) protocol controller and the physical
bus and may be used in both 12 V and 24 V systems. The transceiver
provides differential transmit capability to the bus and differential
receive capability to the CAN controller.
The NCV7340 is a new addition to the CAN high−speed transceiver
family and is an improved drop−in replacement for the AMIS−42665.
Due to the wide common−mode voltage range of the receiver inputs,
the NCV7340 is able to reach outstanding levels of electromagnetic
susceptibility (EMS). Similarly, extremely low electromagnetic
emission (EME) is achieved by the excellent matching of the output
signals.
Features
• Compatible with the ISO 11898 Standard (ISO 11898−2, ISO
11898−5 and SAE J2284)
• Low Quiescent Current
• High Speed (up to 1 Mbps)
• Ideally Suited for 12 V and 24 V Industrial and Automotive
•
•
•
•
•
•
•
•
MARKING
DIAGRAM
8
8
NV7340−x
FALYW G
G
1
SOIC−8
CASE 751AZ
1
NV7340− = Specific Device Code
x = 3 (NCV7340D13R2G)
= 2 (NCV7340D12R2G)
= 4 (NCV7340D14R2G)
F
= Fab Location Code*
*For NCV7340D14R2G only
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN ASSIGNMENT
1
8
2
7
TxD
STB
GND
3
VCC
NCV7340
•
•
•
•
Applications
Extremely Low Current Standby Mode with Wakeup via the Bus
Low EME Common−Mode Choke is No Longer Required
Voltage Source via VSPLIT Pin for Stabilizing the Recessive Bus
Level (Further EMC Improvement)
No Disturbance of the Bus Lines with an Un−powered Node
Transmit Data (TxD) Dominant Time−out Function
Thermal Protection
Bus Pins Protected Against Transients in an Automotive
Environment
Bus and VSPLIT Pins Short−Circuit Proof to Supply Voltage and
Ground
Logic Level Inputs Compatible with 3.3 V Devices
Up to 110 Nodes can be Connected to the Same Bus in Function of
Topology
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
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CANH
6
CANL
5
4
VSPLIT
RxD
NCV7340DxxR2G
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Typical Applications
• Automotive
• Industrial Networks
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 8
1
Publication Order Number:
NCV7340/D
NCV7340
Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES
Min
Max
Unit
VCC
Symbol
Power supply voltage
Parameter
Conditions
4.75
5.25
V
VSTB
DC voltage at pin STB
0
VCC
V
VTxD
DC voltage at pin TxD
0
VCC
V
VRxD
DC voltage at pin RxD
0
VCC
V
VCANH
DC voltage at pin CANH
0 < VCC < 5.25 V; no time limit
−50
+50
V
VCANL
DC voltage at pin CANL
0 < VCC < 5.25 V; no time limit
−50
+50
V
VSPLIT
DC voltage at pin VSPLIT
0 < VCC < 5.25 V; no time limit
−40
+40
V
VO(dif)(bus_dom)
Differential bus output voltage in
dominant state
42.5 W < RLT < 60 W
1.5
3
V
CM−range
Input common−mode range for
comparator
Guaranteed differential receiver threshold
and leakage current
−35
+35
V
Cload
Load capacitance on IC outputs
15
pF
tpd(rec−dom)
Propagation delay TxD to RxD
See Figure 7
60
230
ns
tpd(dom−rec)
Propagation delay TxD to RxD
See Figure 7
60
245
ns
TJ
Junction temperature
−40
150
°C
BLOCK DIAGRAM
VCC
3
VCC
TxD
NCV7340
1
Timer
VCC
STB
RxD
GND
8
4
Thermal
shutdown
COMP
2
COMP
Figure 1. Block Diagram
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2
5
VSPLIT
6
Driver
control
Wakeup
Filter
CANH
VCC
VSPLIT
Mode &
wakeup
control
7
CANL
NCV7340
TYPICAL APPLICATION
Application Schematics
VBAT
IN
5V−reg
OUT
VCC
VCC
3
STB
RxD
4
TxD
CANH
NCV7340
CAN
controller
RLT = 60 W
7
8
5
6
1
VSPLIT
CANL
2
GND
CLT = 47 nF
RLT = 60 W
GND
Figure 2. Application Diagram
Pin Description
1
GND
2
VCC
3
RxD
4
NCV7340
TxD
8
STB
7
CANH
6
CANL
5
VSPLIT
Figure 3. NCV7340 Pin Assignment
Table 2. PIN FUNCTION DESCRIPTION
Pin
Name
Description
1
TxD
Transmit data input; low input → dominant driver; internal pullup current
2
GND
Ground
3
VCC
Supply voltage
4
RxD
Receive data output; dominant transmitter → low output
5
VSPLIT
Common−mode stabilization output
6
CANL
Low−level CAN bus line (low in dominant mode)
7
CANH
High−level CAN bus line (high in dominant mode)
8
STB
Standby mode control input
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3
CAN
BUS
NCV7340
FUNCTIONAL DESCRIPTION
Operating Modes
NCV7340 provides two modes of operation as illustrated
in Table 3. These modes are selectable through pin STB.
Split Circuit
The VSPLIT pin is operational only in normal mode. In
standby mode this pin is floating. The VSPLIT can be
connected as shown in Figure 2 or, if it’s not used, can be left
floating. Its purpose is to provide a stabilized DC voltage of
0.5 x VCC to the bus avoiding possible steps in the
common−mode signal therefore reducing EME. These
unwanted steps could be caused by an un−powered node on
the network with excessive leakage current from the bus that
shifts the recessive voltage from its nominal 0.5 x VCC
voltage.
Table 3. OPERATING MODES
Pin RXD
Pin
STB
Mode
Low
Normal
Bus dominant
Bus recessive
High
Standby
Wakeup request
detected
No wakeup
request detected
Low
High
Wakeup
When a valid wakeup (dominant state longer than tWake)
is received during the standby mode the RxD pin is driven
low. The wakeup detection is not latched: RxD returns to
High state after twakedr when the bus signal is released back
to recessive – see Figure 4. Wake−up behavior in case of a
permanent dominant − due to, for example, a bus short −
represents the only difference between the circuit functional
sub−versions listed in the Ordering Information table. When
the standby mode is entered while a dominant is present on
the bus, the “unconditioned bus wake−up” versions will
signal a bus−wakeup immediately after the state transition
(signal RxD1 in Figure 4). The other version will signal
bus−wakeup only after the initial dominant is released
(signal RxD2 in Figure 4). In this way it’s ensured, that a
CAN bus can be put to a low−power mode even if the nodes
have a level sensitivity to RxD pin and a permanent
dominant is present on the bus.
Normal Mode
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give extremely low EME.
Standby Mode
In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
monitors the bus lines for CAN bus activity. The bus lines
are terminated to ground and supply current is reduced to a
minimum, typically 10 mA. When a wake−up request is
detected by the low−power differential receiver, the signal
is first filtered and then verified as a valid wake signal after
a time period of tdwakerd, the RxD pin is driven low by the
transceiver to inform the controller of the wake−up request.
>tWake
<tWake
CANH
CANL
STB
RxD2
(NCV7340−4)
RxD1
(NCV7340−2, 3)
tdwakerd
tdwakedr
tWake(RxD)
normal
standby
time
Figure 4. NCV7340 Wakeup Behavior
Overtemperature Detection
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when the temperature decreases below the shutdown
threshold and pin TxD goes high. The thermal protection
circuit is particularly needed when a bus line short circuits.
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 160°C. Because the
transmitter dissipates most of the power, the power
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4
NCV7340
TxD Dominant Time−out Function
Fail Safe Features
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
internal timer value tdom(TxD), the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant time−out time (tdom(TxD)) defines the
minimum possible bit rate to 40 kbps.
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 5). Pins TxD and STB are pulled high internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
VCC supply be removed.
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (Pin 2). Positive currents flow into the IC. Sinking current means the current is flowing
into the pin; sourcing current means the current is flowing out of the pin.
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Conditions
Supply voltage
Min
Max
Unit
−0.3
+6
V
VCANH
DC voltage at pin CANH
0 < VCC < 5.25 V; no time limit
−50
+50
V
VCANL
DC voltage at pin CANL
0 < VCC < 5.25 V; no time limit
−50
+50
V
VSPLIT
DC voltage at pin VSPLIT
0 < VCC < 5.25 V; no time limit
−40
+40
V
VTxD
DC voltage at pin TxD
−0.3
6
V
VRxD
DC voltage at pin RxD
−0.3
6
V
VSTB
DC voltage at pin STB
−0.3
6
V
Vesd
Electrostatic discharge voltage at all pins
Note 1
Note 2
−6
−500
6
500
kV
V
Electrostatic discharge voltage at CANH and CANL pins
Note 3
−12
12
kV
Transient voltage, see Figure 5
Note 5
−150
100
V
Static latchup at all pins
Note 4
120
mA
Vschaff
Latchup
Tstg
Storage temperature
−55
+150
°C
TA
Ambient temperature
−40
+125
°C
TJ
Maximum junction temperature
−40
+170
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
2. Standardized charged device model ESD pulses when tested according to ESD−STM5.3.1−1999.
3. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330 W resistor.
4. Static latchup immunity: Static latchup protection level when tested according to EIA/JESD78.
5. Pulses 1, 2a, 3a and 3b according to ISO 7637 part 3. Verification by external test house.
Table 5. THERMAL CHARACTERISTICS
Symbol
Parameter
Conditions
Value
Unit
RqJA_1
Thermal Resistance Junction−to−Air, 1S0P PCB (Note 6)
Free air
125
K/W
RqJA_2
Thermal Resistance Junction−to−Air, 2S2P PCB (Note 7)
Free air
75
K/W
6. Test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
7. Test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.
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5
NCV7340
Table 6. CHARACTERISTICS VCC = 4.75 V to 5.25 V; TJ = −40 to +150°C; RLT = 60 W unless specified otherwise.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY (Pin VCC)
ICC
Supply current in normal mode
Dominant; VTxD = 0 V
Recessive; VTxD = VCC
57
7.5
75
10
mA
ICCS
Supply current in standby mode
TJ,max = 100°C
10
15
mA
TRANSMITTER DATA INPUT (Pin TxD)
VIH
High−level input voltage
Output recessive
2.0
−
VCC
V
VIL
Low−level input voltage
Output dominant
−0.3
−
+0.8
V
IIH
High−level input current
VTxD = VCC
−5
0
+5
mA
IIL
Low−level input current
VTxD = 0 V
−350
−200
−75
mA
Ci
Input capacitance
Not tested
−
5.0
10
pF
V
TRANSMITTER MODE SELECT (Pin STB)
VIH
High−level input voltage
Standby mode
2.0
−
VCC
VIL
Low−level input voltage
Normal mode
−0.3
−
+0.8
V
IIH
High−level input current
VSTB = VCC
−5
0
+5
mA
IIL
Low−level input current
VSTB = 0 V
−10
−4
−1
mA
Ci
Input capacitance
Not tested
−
5.0
10
pF
RECEIVER DATA OUTPUT (Pin RxD)
Ioh
High−level output current
normal mode
VRxD = VCC – 0.4 V
−1
−0.4
−0.1
mA
Iol
Low−level output current
VRxD = 0.4 V
2
6
12
mA
Voh
High−level output voltage
standby mode
IRxD = −100 mA
VCC –
1.1
VCC –
0.7
VCC –
0.4
V
BUS LINES (Pins CANH and CANL)
Vo(reces) (norm)
Recessive bus voltage on pins CANH and
CANL
VTxD = VCC; no load
normal mode
2.0
2.5
3.0
V
Vo(reces) (stby)
Recessive bus voltage on pins CANH and
CANL
VTxD = VCC; no load
standby mode
−100
0
100
mV
Io(reces) (CANH)
Recessive output current at pin CANH
−35 V < VCANH < +35 V;
0 V < VCC < 5.25 V
−2.5
−
+2.5
mA
Io(reces) (CANL)
Recessive output current at pin CANL
−35 V < VCANL < +35 V;
0 V < VCC < 5.25 V
−2.5
−
+2.5
mA
ILI(CANH)
Input leakage current to pin CANH
VCC = 0 V
VCANL = VCANH = 5 V
−10
0
10
mA
ILI(CANL)
Input leakage current to pin CANL
VCC = 0 V
VCANL = VCANH = 5 V
−10
0
10
mA
Vo(dom) (CANH)
Dominant output voltage at pin CANH
VTxD = 0 V
3.0
3.6
4.25
V
Vo(dom) (CANL)
Dominant output voltage at pin CANL
VTxD = 0 V
0. 5
1.4
1.75
V
Vo(dif) (bus_dom)
Differential bus output voltage (VCANH −
VCANL)
VTxD = 0 V; dominant;
42.5 W < RLT < 60 W
1.5
2.25
3.0
V
Vo(dif) (bus_rec)
Differential bus output voltage (VCANH −
VCANL)
VTxD = VCC; recessive; no
load
−120
0
+50
mV
Io(sc) (CANH)
Short circuit output current at pin CANH for
the NCV7340D13(R2)G
VCANH = 0 V; VTxD = 0 V
−100
−70
−45
mA
Short circuit output current at pin CANH for
NCV7340D12(R2)G & NCV7340D14(R2)G
VCANH = 0 V; VTxD = 0 V
−120
−70
−45
mA
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6
NCV7340
Table 6. CHARACTERISTICS VCC = 4.75 V to 5.25 V; TJ = −40 to +150°C; RLT = 60 W unless specified otherwise.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Short circuit output current at pin CANL for
the NCV7340D13(R2)G
VCANL = 36 V; VTxD = 0 V
45
70
100
mA
Short circuit output current at pin CANL for
NCV7340D12(R2)G & NCV7340D14(R2)G
VCANL = 36 V; VTxD = 0 V
45
70
120
mA
Vi(dif) (th)
Differential receiver threshold voltage (see
Figure 6)
−5 V < VCANL < +12 V;
−5 V < VCANH < +12 V;
0.5
0.7
0.9
V
Vihcm(dif) (th)
Differential receiver threshold voltage for
high common−mode (see Figure 6)
−35 V < VCANL < +35 V;
−35 V < VCANH < +35 V;
0.40
0.7
1.0
V
Vi(dif) (th)_STDBY
Differential receiver threshold voltage in
standby mode (see Figure 6)
−12 V < VCANL < +12 V;
−12 V < VCANH < +12 V;
0.4
0.8
1.15
V
Ri(cm) (CANH)
Common−mode input resistance at pin
CANH
15
26
37
kW
Ri(cm) (CANL)
Common−mode input resistance at pin
CANL
15
26
37
kW
Ri(cm) (m)
Matching between pin CANH and pin CANL
common mode input resistance
−0.8
0
+0.8
%
Ri(dif)
Differential input resistance
50
75
kW
Ci(CANH)
Input capacitance at pin CANH
VTxD = VCC; not tested
7.5
20
pF
Ci(CANL)
Input capacitance at pin CANL
VTxD = VCC; not tested
7.5
20
pF
Ci(dif)
Differential input capacitance
VTxD = VCC; not tested
3.75
10
pF
−
0.7 x
VCC
BUS LINES (Pins CANH and CANL)
Io(sc) (CANL)
VCANH = VCANL
25
COMMON−MODE STABILIZATION (Pin VSPLIT)
VSPLIT
Reference output voltage at pin VSPLIT
Normal mode;
−500 mA < ISPLIT < 500 mA
ISPLIT(i)
VSPLIT leakage current
Standby mode
−5
+5
mA
ISPLIT(lim)
VSPLIT limitation current
Normal mode
1.3
5.0
mA
junction temperature rising
150
160
185
°C
0.3 x
VCC
THERMAL SHUTDOWN
TJ(sd)
Shutdown junction temperature
TIMING CHARACTERISTICS (see Figures 7 and 8)
td(TxD−BUSon)
Delay TxD to bus active
Cl = 100 pF between
CANH to CANL
20
85
135
ns
td(TxD−BUSoff)
Delay TxD to bus inactive
Cl = 100 pF between
CANH to CANL
5.0
60
105
ns
td(BUSon−RXD)
Delay bus active to RxD
Crxd = 15 pF
25
55
105
ns
td(BUSoff−RXD)
Delay bus inactive to RxD
Crxd = 15 pF
30
100
105
ns
tpd(rec−dom)
Propagation delay TxD to RxD from
recessive to dominant
Cl = 100 pF between
CANH to CANL
60
230
ns
td(dom−rec)
Propagation delay TxD to RxD from
dominant to recessive
Cl = 100 pF between
CANH to CANL
60
245
ns
td(stb−nm)
Delay standby mode to normal mode
tWake
Dominant time for wake−up via bus
5.0
7.5
10
ms
Vdif(dom) > 1.4 V
0.75
2.5
5.0
ms
Vdif(dom) > 1.2 V
0.75
3
5.8
ms
tdwakerd
Delay to flag wake event (recessive to
dominant transitions) (See Figure 4)
Valid bus wake up event,
CRxD = 15 pF
1.0
3.4
10
ms
tdwakedr
Delay to flag end of wake event (dominant
to recessive transition) (See Figure 4)
Valid bus wake up event,
CRxD = 15 pF
0.5
2.9
6.0
ms
tWake(RxD)
Minimum pulse width on RxD (See Figure 4)
5 ms twake, CRxD = 15 pF
0.5
tdom(TxD)
TxD dominant time for time out
VTxD = 0 V
300
650
1000
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7
ms
ms
NCV7340
MEASUREMENT SETUPS AND DEFINITIONS
+5 V
100 nF
VCC
3
NCV7340
1
RxD
CANH
7
TxD
4
1 nF
5
V SPLIT
Transient
Generator
1 nF
6
CANL
2
8
15 pF
GND
STB
Figure 5. Test Circuit for Automotive Transients
VRxD
High
Low
Hysteresis
0.9
0.5
Vi(dif)(hys)
Figure 6. Hysteresis of the Receiver
+5 V
100 nF
VCC
3
7
TxD
RxD
NCV7340
1
4
RLT
VSPLIT
60 W
6
CLT
100 pF
CANL
2
8
15 pF
5
CANH
STB
GND
Figure 7. Test Circuit for Timing Characteristics
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8
NCV7340
HIGH
LOW
TxD
CANH
CANL
dominant
Vi(dif) =
VCANH − VCANL
0.9V
0.5V
recessive
RxD
0.7 x VCC
0.3 x VCC
td(TxD−BUSon)
td(TxD−BUSoff)
td(BUSon−RxD)
tpd(rec−dom)
tpd(dom−rec)
td(BUSoff−RxD)
Figure 8. Timing Diagram for AC Characteristics
DEVICE ORDERING INFORMATION
Part Number
NCV7340D12G
NCV7340D12R2G
NCV7340D13G
NCV7340D13R2G
NCV7340D14G
NCV7340D14R2G
Description
Temperature
Range
Package Type
96 Tube / Tray
HS LP CAN Transceiver
(Unconditioned Bus Wakeup)
EMC Improved
HS LP CAN Transceiver
(Unconditioned Bus Wakeup)
Shipping†
3000 / Tape & Reel
−40°C to +125°C
SOIC 150 8 (Mate Sn, JEDEC
MS−012)
(Pb−Free)
96 Tube / Tray
3000 / Tape & Reel
96 Tube / Tray
HS LP CAN Transceiver
(Bus Wakeup Inactive in
Case of Bus Fault)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NCV7340
PACKAGE DIMENSIONS
SOIC 8
CASE 751AZ
ISSUE O
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10
NCV7340
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http://onsemi.com
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ON Semiconductor Website: www.onsemi.com
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NCV7340/D