Fairchild NDS355AN N-channel logic level enhancement mode field effect transistor Datasheet

January 1997
NDS355AN
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
SuperSOTTM-3 N-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and
other battery powered circuits where fast
switching, and low in-line power loss are needed in a very small
outline surface mount package.
1.7A, 30 V, RDS(ON) = 0.125 Ω @ VGS = 4.5 V
RDS(ON) = 0.085 Ω @ VGS = 10 V.
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOTTM-3 design for superior
thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
_______________________________________________________________________________
D
S
G
Absolute Maximum Ratings
T A = 25°C unless otherwise noted
Symbol
Parameter
NDS355AN
Units
VDSS
VGSS
Drain-Source Voltage
30
V
Gate-Source Voltage - Continuous
±20
V
ID
Maximum Drain Current - Continuous
1.7
A
(Note 1a)
- Pulsed
PD
Maximum Power Dissipation
10
(Note 1a)
(Note 1b)
TJ,TSTG
Operating and Storage Temperature Range
0.5
W
0.46
-55 to 150
°C
250
°C/W
75
°C/W
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
© 1997 Fairchild Semiconductor Corporation
NDS355AN Rev.C
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
IDSS
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
30
V
TJ =125°C
1
µA
10
µA
IGSSF
Gate - Body Leakage, Forward
VGS = 20 VDS = 0 V
100
nA
IGSSR
Gate - Body Leakage, Reverse
VGS = -20 V, VDS = 0 V
-100
nA
2
V
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
RDS(ON)
Static Drain-Source On-Resistance
VGS = 4.5 V, ID = 1.7 A
1
TJ =125°C
0.5
TJ =125°C
VGS = 10 V, ID = 1.9 A
1.6
1.2
1.5
0.105
0.125
0.16
0.23
0.065
0.085
6
Ω
ID(ON)
On-State Drain Current
VGS = 4.5 V, VDS = 5 V
gFS
Forward Transconductance
VDS = 5 V, ID= 1.7 A
3.5
A
S
VDS = 15 V, VGS = 0 V,
f = 1.0 MHz
195
pF
135
pF
48
pF
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
td(on)
Turn - On Delay Time
tr
Turn - On Rise Time
td(off)
tf
td(on)
Turn - On Delay Time
tr
Turn - On Rise Time
td(off)
tf
Qg
Total Gate Charge
Q gs
Gate-Source Charge
Q gd
Gate-Drain Charge
(Note 2)
VDD = 10 V, ID = 1 A,
VGS = 10 V, RGEN = 6 Ω
10
20
ns
13
25
ns
Turn - Off Delay Time
13
25
ns
Turn - Off Fall Time
4
10
ns
10
20
ns
32
60
ns
Turn - Off Delay Time
10
20
ns
Turn - Off Fall Time
5
10
ns
3.5
5
nC
VDD = 5 V, ID = 1 A,
VGS = 4.5 V, RGEN = 6 Ω
VDS = 10 V, ID = 1.7 A,
VGS = 5 V
0.8
nC
1.7
nC
NDS355AN Rev.C
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.42
A
10
A
1.2
V
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Drain-Source Diode Forward Current
ISM
Maximum Pulsed Drain-Source Diode Forward Current
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS =0.42 A (Note 2)
0.8
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
PD (t ) =
T J−TA
R θJ A(t )
=
T J−TA
R θJ C+RθCA(t )
= I 2D (t ) × RDS (ON )
TJ
Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper.
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.
1a
1b
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS355AN Rev.C
Typical Electrical Characteristics
2
VGS =10V
6.0
DRAIN-SOURCE
R DS(on) , NORMALIZED
ON-RESISTANCE
I D , DRAIN-SOURCE CURRENT (A)
10
5.0
7.0
4.5
8
4.0
6
3.5
4
2
0
3.0
0
0.5
1
1.5
2
2.5
1.8
1.6
4.0
1.2
4.5
1
5.0
6.0
0.8
7
10
0.6
0.4
3
VGS = 3.5V
1.4
0
2
I
VDS , DRAIN-SOURCE VOLTAGE (V)
R DS(on) , NORMALIZED
1.4
1.2
1
0.8
0.6
-50
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
125
150
DRAIN-SOURCE ON-RESISTANCE
ID = 1.6A
VGS = 4.5V
10
V GS = 4.5 V
1.8
1.6
TJ = 125°C
1.4
1.2
25°C
1
-55°C
0.8
0.6
0.4
0
1
J
Figure 3. On-Resistance Variation
with Temperature.
2
3
I D , DRAIN CURRENT (A)
4
5
Figure 4. On-Resistance Variation
with Drain Current and Temperature.
1.2
Vth , NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE
5
V DS = 5.0V
4
I D, DRAIN CURRENT (A)
R DS(ON), NORMALIZED
8
2
1.6
DRAIN-SOURCE ON-RESISTANCE
4
6
, DRAIN CURRENT (A)
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
Figure 1. On-Region Characteristics.
3
2
T = -55°C
J
25°C
1
125°C
0
D
1
1.5
V
GS
2
2.5
3
, GATE TO SOURCE VOLTAGE (V)
3.5
Figure 5. Transfer Characteristics.
4
V DS= V GS
I D = 250µA
1.1
1
0.9
0.8
0.7
0.6
-50
-25
0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)
125
150
Figure 6. Gate Threshold Variation
with Temperature.
NDS355AN Rev.C
5
1.12
I S , REVERSE DRAIN CURRENT (A)
BV DSS , NORMALIZED
DRAIN-SOURCE BREAKDOWN VOLTAGE
Typical Electrical Characteristics (continued)
I D = 250µA
1.08
1.04
1
0.96
0.92
-50
-25
0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)
125
Figure 7. Breakdown Voltage Variation with
Temperature.
0.001
0
0.2
0.4
0.6
0.8
1
VSD , BODY DIODE FORWARD VOLTAGE (V)
, GATE-SOURCE VOLTAGE (V)
C iss
200
100
C oss
f = 1 MHz
V GS = 0V
GS
60
C rss
0.5
1
2
5
10
V , DRAIN TO SOURCE VOLTAGE (V)
10V
15V
6
4
2
0
0.2
VDS = 5V
I D = 1.6A
8
20
30
0
2
DS
Figure 9. Capacitance Characteristics.
t d(on)
t d(off)
tf
90%
90%
VOUT
10%
DUT
G
8
t off
tr
V OUT
D
R GEN
6
t on
RL
V IN
4
Q g , GATE CHARGE (nC)
Figure 10. Gate Charge Characteristics.
VDD
VGS
1.2
V
CAPACITANCE (pF)
-55°C
0.01
10
300
20
0.1
25°C
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature.
500
40
TJ = 125°C
0.1
0.0001
150
V GS = 0V
1
10%
INVERTED
90%
S
V IN
50%
50%
10%
PULSE WIDTH
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
NDS355AN Rev.C
30
7
V DS = 5.0V
6
T J = -55°C
100
10
I D, DRAIN CURRENT (A)
25°C
5
125°C
4
3
2
1
T
IMI
)L
(ON
S
RD
5
3
10m
10
0.3
0.03
2
4
6
ID , DRAIN CURRENT (A)
8
10
STEADY-STATE POWER DISSIPATION (W)
1
0.8
1a
1b
0.4
0.2
0
4.5"x5" FR-4 Board
TA = 25 oC
Still Air
0
0.2
us
s
s
s
0.5
1
2
5
10
V , DRAI N-SOURCE VOLTAGE (V)
20 30
50
DS
Figure 13. Transconductance Variation with Drain
Current and Temperature.
0.6
0.01
0.1
0.1
0.2
0.3
2oz COPPER MOUNTING PAD AREA (in 2 )
Figure 14. Maximum Safe Operating Area.
I D , STEADY-STATE DRAIN CURRENT (A)
0
0m
1s
DC
V GS = 4.5V
SINGLE PULSE
RθJA =See Note1b
TA = 25°C
0.1
g
0
1m
1
FS
, TRANSCONDUCTANCE (SIEMENS)
Typical Electrical Characteristics (continued)
2
1.8
1.6
1a
1.2
0.4
4.5"x5" FR-4 Board
o
TA = 25 C
Still Air
VGS = 4.5V
1b
1.4
0
Figue 15. SuperSOTTM _ 3 Maximum
Steady-State Power Dissipation versus Copper
Mounting Pad Area.
0.1
0.2
0.3
2oz COPPER MOUNTING PAD AREA (in2 )
0.4
Figure 16. Maximum Steady-State Drain
Current versus Copper Mounting Pad Area.
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
0.5
D = 0.5
R θJA (t) = r(t) * R θJA
R θJA = See Note 1b
0.2
0.2
0.1
0.1
0.05
0.05
0.02
0.01
0.005
P(pk)
0.02
t1
0.01
t2
TJ - TA = P * R θJA (t)
Single Pulse
Duty Cycle, D = t1 /t2
0.002
0.001
0.0001
0.001
0.01
0.1
t 1 , TIME (sec)
1
10
100
300
Figure 17. Transient Thermal Response Curve.
Note : Characterization performed using the conditions described in note 1b. Transient thermal response will
change depending on the circuit board design.
NDS355AN Rev.C