8745BI-21 1:1 Differential-to-LVDS Zero Delay Clock Generator Datasheet General Description Features The 8745BI-21 is a highly versatile 1:1 LVDS Clock Generator. The 8745BI-21 has a fully integrated PLL and can be configured as a zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider and Output Divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clock. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. • One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair • • Differential CLK, nCLK input pair • • • • Output frequency range: 31.25MHz to 700MHz • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • • • • • • • Cycle-to-cycle jitter: 30ps (maximum) Pin Assignments CLK nCLK MR nFB_IN FB_IN SEL2 VDDO nQFB QFB GND 1 2 3 4 5 6 7 8 9 10 SEL1 SEL0 VDD PLL_SEL VDDA SEL3 GND Q nQ VDDO 20 19 18 17 16 15 14 13 12 11 CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Input frequency range: 31.25MHz to 700MHz VCO range: 250MHz to 700MHz External feedback for “zero delay” clock regeneration with configurable frequencies Output skew: 40ps (maximum) Static phase offset: 25ps ± 125ps Full 3.3V supply voltage -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package For functional replacement part use 8T49N285 8745BI-21 Block Diagram PLL_SEL Pullup ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 7 MR 8 nc 9 24 GND 23 Q 22 nQ FB_IN Pulldown FB_IN Pullup 21 VDDO 20 GND 19 QFB SEL0 Pulldown 18 nQFB SEL1 Pulldown 17 VDDO QFB QFB ©2017 Integrated Device Technology, Inc. 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 SEL2 Pulldown 10 11 12 13 14 15 16 SEL3 Pulldown nc 6 nc nc nCLK 5mm x 5mm x 0.925mm package body K Package Top View GND 4 5 SEL2 nc CLK FB_IN 3 O PO SE D nc ICS8745BI-21 32 Lead VFQFN nFB_IN 2 PR SEL1 VDD 1 1 PLL 32 31 30 29 28 27 26 25 SEL0 0 Q Q nc nc CLK Pulldown CLK Pullup nc SEL3 VDDA PLL_SEL nc VDD 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm package body M Package Top View MR Pulldown 1 Revision E, January 10, 2017 8745BI-21 Datasheet Table 1. Pin Descriptions Number Name Type Description 1 CLK Input Pulldown 2 nCLK Input Pullup Non-inverting differential clock input. Inverting differential clock input. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go low and the inverted output nQ to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 3 MR Input Pulldown 4 nFBIN Input Pullup Inverting differential feedback input to phase detector for regenerating clocks with “Zero Delay.” 5 FBIN Input Pulldown Non-inverted differential feedback input to phase detector for regenerating clocks with “Zero Delay.” 6, 15, 19, 20 SEL2, SEL3, SEL0 SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 7, 11 VDDO Power Output supply pins. 8, 9 nQFB/QFB Output Differential feedback output pair. LVDS interface levels. 10, 14 GND Power Power supply ground. 12, 13 nQ/Q Output Differential output pair. LVDS interface levels. 16 VDDA Power Analog supply pin. 17 PLL_SEL Input 18 VDD Power Pullup PLL select. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels. Core supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ©2017 Integrated Device Technology, Inc. Test Conditions 2 Minimum Typical Maximum Units Revision E, January 10, 2017 8745BI-21 Datasheet Function Tables Table 3A. Control Input Function Table Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Q, nQ 0 0 0 0 250 - 700 ÷1 0 0 0 1 125 - 350 ÷1 0 0 1 0 62.5 - 175 ÷1 0 0 1 1 31.25 - 87.5 ÷1 0 1 0 0 250 - 700 ÷2 0 1 0 1 125 - 350 ÷2 0 1 1 0 62.5 - 175 ÷2 0 1 1 1 250 - 700 ÷4 1 0 0 0 125 - 350 ÷4 1 0 0 1 250 - 700 ÷8 1 0 1 0 125 - 350 x2 1 0 1 1 62.5 - 175 x2 1 1 0 0 31.25 - 87.5 x2 1 1 0 1 62.5 - 175 x4 1 1 1 0 31.25 - 87.5 x4 1 1 1 1 31.25 - 87.5 x8 *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz. ©2017 Integrated Device Technology, Inc. 3 Revision E, January 10, 2017 8745BI-21 Datasheet Table 3B. PLL Bypass Function Table Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q, nQ 0 0 0 0 ÷4 0 0 0 1 ÷4 0 0 1 0 ÷4 0 0 1 1 ÷8 0 1 0 0 ÷8 0 1 0 1 ÷8 0 1 1 0 ÷16 0 1 1 1 ÷16 1 0 0 0 ÷32 1 0 0 1 ÷64 1 0 1 0 ÷2 1 0 1 1 ÷2 1 1 0 0 ÷4 1 1 0 1 ÷1 1 1 1 0 ÷2 1 1 1 1 ÷1 ©2017 Integrated Device Technology, Inc. 4 Revision E, January 10, 2017 8745BI-21 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA D Item SE Package Thermal Impedance, JA 20 Lead SOIC package 32 Lead VFQFN package O PO 46.2C/W (0 lfpm) 37C/W (0 mps) -65C to 150C PR Storage Temperature, TSTG DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 128 mA IDDA Analog Supply Current 18 mA IDDO Output Supply Current 62 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current IIL Input Low Current SEL[0:3], MR VDD = VIN = 3.465V 150 µA PLL_SEL VDD = VIN = 3.465V 5 µA SEL[0:3], MR VDD = 3.465V, VIN = 0V -5 µA PLL_SEL VDD = 3.465V, VIN = 0V -150 µA ©2017 Integrated Device Technology, Inc. 5 Revision E, January 10, 2017 8745BI-21 Datasheet Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter IIH Input High Current IIL Test Conditions Minimum Typical Maximum Units CLK, FB_IN VDD = VIN = 3.465V 150 µA nCLK, nFB_IN VDD = VIN = 3.465V 5 µA CLK, FB_IN VDD = 3.465V, VIN = 0V -5 µA nCLK, nFB_IN VDD = 3.465V, VIN = 0V -150 µA Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Minimum Typical Maximum Units 320 440 550 mV 0 50 mV 1.2 1.35 V 25 mV Maximum Units 700 µA 700 V 1.05 Table 5. Input Frequency Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter FIN Input Frequency Test Conditions Minimum PLL_SEL = 1 31.25 Typical CLK, nCLK ©2017 Integrated Device Technology, Inc. PLL_SEL = 0 6 Revision E, January 10, 2017 8745BI-21 Datasheet AC Electrical Characteristics Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical Maximum Units 700 MHz PLL_SEL = 0V, f 700MHz 2.9 3.4 4.0 ns PLL_SEL = 3.3V -100 25 150 ps Output Skew; NOTE 3, 5 40 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 5, 6 30 ps ±52 ps 1 ms 700 ps 55 % tPD Propagation Delay; NOTE 1 tsk(Ø) Static Phase Offset; NOTE 2, 5 tsk(o) tjit() Phase Jitter; NOTE 4, 5, 6 tL PLL Lock Time t R / tF Output Rise/Fall Time; NOTE 7 odc Output Duty Cycle 20% to 80% 200 45 50 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested. ©2017 Integrated Device Technology, Inc. 7 Revision E, January 10, 2017 8745BI-21 Datasheet Parameter Measurement Information VDD SCOPE VDD, 3.3V±5% POWER SUPPLY + Float GND – nCLK Q V V Cross Points PP VDDA, CMR CLK VDDO nQ GND 3.3V LVDS Output Load AC Test Circuit Differential Input Level nCLK VOH nQx CLK VOL Qx nFB_IN FB_IN nQy VOL Qy ➤ ➤ t(Ø) VOH Phase Jitter and Static Phase Offset Output Skew nQ nQ Q 80% tcycle n VOD tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Q 20% 20% tR Cycle-to-Cycle Jitter ©2017 Integrated Device Technology, Inc. 80% tF Output Rise/Fall Time 8 Revision E, January 10, 2017 8745BI-21 Datasheet Parameter Measurement Information, continued nQ nCLK Q CLK nQ Q tPD Output Duty Cycle Propagation Delay Offset Voltage Setup Differential Output Voltage Setup ©2017 Integrated Device Technology, Inc. 9 Revision E, January 10, 2017 8745BI-21 Datasheet Applications Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 8745BI-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ©2017 Integrated Device Technology, Inc. 10 Revision E, January 10, 2017 8745BI-21 Datasheet Differential Clock Input Interface Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. 3.3V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 3.3V 2.5V 3.3V 3.3V 2.5V R4 120Ω R3 120Ω *R3 Zo = 60Ω CLK CLK Zo = 60Ω nCLK HCSL *R4 nCLK Differential Input SSTL R1 120Ω Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ©2017 Integrated Device Technology, Inc. R2 120Ω Differential Input Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver 11 Revision E, January 10, 2017 8745BI-21 Datasheet Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVDS Output All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached. CLK/nCLK Input For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVDS Driver Termination A general LVDS interface is shown in Figure 4. Standard termination for LVDS type output structure requires both a 100 parallel resistor at the receiver and a 100 differential transmission line environment. In order to avoid any transmission line reflection issues, the 100 resistor must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 4 can be used with either type of output structure. If using a non-standard termination, it is recommended to contact IDT and confirm if the output is a current source or a voltage source type structure. In addition, since these outputs are LVDS compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. + LVDS Driver 100Ω LVDS Receiver – 100Ω Differential Transmission Line Figure 4. Typical LVDS Driver Termination ©2017 Integrated Device Technology, Inc. 12 Revision E, January 10, 2017 8745BI-21 Datasheet VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ©2017 Integrated Device Technology, Inc. 13 Revision E, January 10, 2017 8745BI-21 Datasheet Schematic Example The schematic of the 8745BI-21 layout example is shown in Figure 6A. The 8745BI-21 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. 3.3V (155.52 MHz) U1 Zo = 50 Ohm Zo = 50 Ohm SEL2 VDDO 3.3V PECL Driver R8 50 R9 50 RU4 1K RU5 SP RU6 1K RU7 SP PLL_SEL SEL0 SEL1 SEL2 SEL3 RD4 SP SEL1 SEL0 VDD PLL_SEL VDDA SEL3 RD5 1K RD6 SP C1 0.1uF R7 VDD 10 C11 0.01u VDDO C16 10u (77.76 MHz) + Bypass capacitors located near the power pins (U1-7) VDDO C4 0.1uF RD3 SP 20 19 18 17 16 15 14 13 12 11 R10 50 VDD RU3 1K SEL1 SEL0 VDDI PLL_SEL VDDA SEL3 GND Q nQ VDDO CLK nCLK MR nFB_IN FB_IN SEL2 VDDO nQFB QFB GND ICS8745B-21 R2 100 SP = Space (i.e. not intstalled) 1 2 3 4 5 6 7 8 9 10 R4 100 VDD=3.3V (U1-11) - LVDS_input VDDO=3.3V C2 0.1uF Zo = 100 Ohm Differential RD7 1K SEL[3:0] = 0101, Divide by 2 Figure 6A. 8745BI-21 LVDS Zero Delay Buffer Schematic Example ©2017 Integrated Device Technology, Inc. 14 Revision E, January 10, 2017 8745BI-21 Datasheet The following component footprints are used in this layout example. restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. All the resistors and capacitors are size 0603. Power and Grounding • The differential 50 output traces should have the same length. Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. Clock Traces and Termination Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be • Make sure no other signal traces are routed between the clock trace pair. • The matching termination resistors should be located as close to the receiver input pins as possible. U1 ICS8745B-21 GND VDDO C1 VDD C16 VDDA C11 VIA C4 R7 100 O hm Differential Traces C2 Figure 6B. PCB Board Layout for 8745BI-21 ©2017 Integrated Device Technology, Inc. 15 Revision E, January 10, 2017 8745BI-21 Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 8745BI-21. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8745BI-21 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (128mA + 18mA) = 506mW • Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 62mA = 215mW Total Power_MAX = 506mW + 215mW = 721mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 46.2°C/W per Table 7A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.721W * 46.2°C/W = 118.3°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7A. Thermal Resistance JA for 20 Lead SOIC, Forced Convection JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. PR O PO SE D Table 7B. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ©2017 Integrated Device Technology, Inc. 0 37.0°C/W 16 1 2.5 32.4°C/W 29.0°C/W Revision E, January 10, 2017 8745BI-21 Datasheet Reliability Information Table 8A. JA vs. Air Flow Table for a 20 Lead SOIC JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Table 8B. JA vs. Air Flow Table for a 32 Lead VFQFN Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 PR O PO SE D JA vs. Air Flow 37.0°C/W 1 2.5 32.4°C/W 29°C/W Transistor Count The transistor count for 8745BI-21 is: 2772 Package Outline and Package Dimensions Package Outline - M Suffix for 20 Lead SOIC Table 9A. Package Dimensions for 20 Lead SOIC 300 Millimeters All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 2.65 A1 0.10 A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 12.60 13.00 E 7.40 7.60 e 1.27 Basic H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 0° 7° Reference Document: JEDEC Publication 95, MS-013, MS-119 ©2017 Integrated Device Technology, Inc. 17 Revision E, January 10, 2017 8745BI-21 Datasheet Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N L N Anvil Anvil Singulation Singula tion e (Ty p.) 2 If N & N 1 are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D e N &N Odd 0. 08 Chamfer 4x 0.6 x 0.6 max OPTIONAL Th er mal Ba se D2 2 C D2 PR O PO SE D C Bottom View w/Type A ID Bottom View w/Type C ID 2 1 2 1 CHAMFER 4 RADIUS N N-1 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 9B. Package Dimensions NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9B. JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ©2017 Integrated Device Technology, Inc. 18 Revision E, January 10, 2017 8745BI-21 Datasheet Ordering Information Table 10. Ordering Information Marking ICS8745BMI-21 ICS8745BMI-21 ICS8745BMI-21LF ICS8745BMI-21LF ICS745BI21L ICS745BI21L O PO SE D Part/Order Number 8745BMI-21 8745BMI-21T 8745BMI-21LF 8745BMI-21LFT 8745BKI-21LF 8745BKI-21LFT Package 20 Lead SOIC 20 Lead SOIC “Lead-Free” 20 Lead SOIC “Lead-Free” 20 Lead SOIC “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tube Tape & Reel Tube Tape & Reel Tray Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C PR NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. Revision History Sheet Rev B Table Page T4D 5 LVDS DC Characteristics Table - modified VOS 0.90V min. to 1.05V min, 1.15V typical to 1.2V typical, and 1.4V max. to 1.35V max. 3/17/04 T6 7 12 15 AC Characteristics Table - changed tPD max limit from 3.9ns to 4.0ns. Added Recommendations for Unused Input & Output Pins. Added Power Considerations section. Updated format throughout the datasheet. 4/17/07 Pin Assignment - corrected lineup of pin names. Control Input Function Table - deleted “z” from 1st row of SEL3 column. PLL Bypass Function Table - deleted “z” from 1st row of SEL3 column Differential DC Characteristics Table - updated NOTES. AC Characteristics Table - added thermal note. Power Supply Filtering Technique - updated paragraph. Updated Differential Clock Input Interface. Ordering Information Table - added “LF” marking. Deleted “ICS” prefix in Part/Order number column. Updated Header/Footer of datasheet. 1/25/10 T10 1 3 4 6 7 10 11 17 Added 32 Lead VFQFN proposed pin assignment. Absolute Maximum Ratings - added 32 Lead VFQN Package Thermal Impedance. Updated Wiring the Differential Input to Accept Single-ended Levels. Updated LVDS Output Termination. Added VFQFN EPad Thermal Release section. Added proposed 32 Lead VFQFN Thermal Resistance table. Added proposed 32 Lead VFQFN theta ja table. Added proposed 32 Lead VFQFN Package Outline and Dimensions. Ordering Information Table added proposed 32 Lead VFQFN ordering information. 7/28/10 T7B T8B T9B T10 1 5 10 12 13 16 17 18 19 1 Product Discontinuation Notice - Last time buy expires November 2, 2016. PDN# CQ-15-05. 11/6/15 Per PDN# CQ-15-05 obsolete datasheet. 1/10/17 C C T3A T 3B T4C T6 D D E Description of Change ©2017 Integrated Device Technology, Inc. 19 Date Revision E, January 10, 2017 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. 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