® DSP101 DSP102 DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS FEATURES DESCRIPTION ● ZERO-CHIP INTERFACE TO STANDARD DSP ICs: AD, AT&T, MOTOROLA, TI The DSP101 and DSP102 are high performance sampling analog-to-digital converters designed for simplicity of use with modern digital signal processing ICs. Both are complete with all interface logic for use directly with DSP ICs, and provide full sampling and conversion at rates up to 200kHz. ● SINGLE CHANNEL: DSP101 ● DUAL CHANNEL: DSP102 Two Serial Outputs or Cascade to Single 32-Bit Word ● SAMPLING RATE TO 200kHz ● DYNAMIC SPECIFICATIONS: Signal/(Noise + Distortion) = 88dB; Spurious-Free Dynamic Range = 94dB; THD = –91dB ● SERIAL OUTPUT DATA COMPATIBLE WITH 16-, 24-, AND 32-BIT DSP IC FORMATS The DSP101 offers a single conversion channel, with 18 bits of serial data output, allowing the user to drive 16-bit, 24-bit, or 32-bit DSP ports. The DSP102 offers two complete conversion channels, with either two full 18-bit output ports, or a mode to cascade two 16-bit conversions into a 32-bit port as one word. Both the DSP101 and DSP102 are packaged in standard, low-cost 28-pin plastic DIP packages. Each is offered in two performance grades to match application requirements. Convert Command Control Logic Analog Input Channel A Select Sync Format Channel A User Tag In 18-Bit Sampling ADC Channel A Data/ Cascaded Data Sync Reference Bit Clock Channel B Data Analog Input Channel B 18-Bit Sampling ADC Channel B User Tag In Cascade Channel B on DSP102 Only International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1990 Burr-Brown Corporation • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-1068C Printed in U.S.A. October. 1993 SPECIFICATIONS ELECTRICAL At TA = 0°C to 70°C, ±2.75V input signal, sampling frequency (fS) = 200kHz, VA+ = VD = +5V, VA– = –5V, 16MHz external clock on OSC1, CLKOUT tied to CLKIN, 8MHzdata transfer clock on XCLK, data analysis band-limited to 20kHz, unless otherwise specified. DSP101JP DSP102JP PARAMETER CONDITIONS MIN TYP RESOLUTION DSP101KP DSP102KP MAX MIN TYP 18 ANALOG INPUT Voltage Range Impedance Capacitance ±2.75V 1 20 THROUGHPUT SPEED Complete Cycle Throughput Rate Acquisition + Conversion fIN = 1kHz fIN = 1kHz (–60dB) fIN = 25kHz fIN = 1kHz fIN = 1kHz fIN = 1kHz Total Harmonic Distortion Spurious-Free Dynamic Range Signal-to-Noise Ratio (SNR) DC ACCURACY Gain Error Gain Error Mismatch Integral Linearity Differential Linearity Integral Linearity Error Differential Linearity Error No Missing Codes Bipolar Zero Error (3) Bipolar Zero Mismatch (3) Power Supply Sensitivity 5 83 86 32 82 –90 92 88 89 84 SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Overvoltage Recovery POWER SUPPLIES Rated Voltage VA+ VA– VD Power Consumption Supply Current IA+ IA– ID 86 –86 92 87 30 100 1 5 DIGITAL OUTPUTS Format Coding Logic Levels (Except OSC2) VOL VOH OSC2 Conversion Clock (CLKOUT) Drive Capability V kΩ pF * 88 * * –91 94 89 ±5 ±2 Sufficient to meet AC Accuracy Specifications Sufficient to meet AC Accuracy Specifications ±0.003 * ±0.002 * 14 * ±2 ±2 –60 * –60 * DSP102 Channels –5.25V < VA– < –4.75V +4.75V < VA+, VD+ < +5.25V IL = ±10µA IH = ±10µA Bits * DSP102 Channels ±2.75V Input Range ±2.75V Input Range ±0.7V Input Range ±0.7V Input Range ±0.7V Input Range DIGITAL INPUTS Logic Levels (Except OSC1) VIL VIH OSC1 Clock Frequency Data Transfer Clock (XCLK) Frequency Duty Cycle Conversion Clock (CLKIN) Frequency Duty Cycle UNITS * * * * 200 AC ACCURACY(1) Signal-to-(Noise + Distortion) Ratio MAX 0 +2.4 –89 * * 0.1 40 50 12 60 * * 0.5 25 33 5.33 55 * * dB(2) dB dB dB dB dB % % % % Bits mV mV dB dB * * * * +0.8 * +5 * 74HC Compatible 16 µs kHz ns ps, rms µs µs * * V V MHz * * * MHz % * * MHz % * * V V Serial; MSB first; 16/18-bit and Cascaded 32-bit Mode Binary Two’s Complement ISINK = 4mA ISOURCE = 4mA 0 +2.4 +0.4 * +5 * Can only be used to drive crystal oscillator. ±2mA * +4.75 –5.25 +4.75 XCLK = OSC1 = 12MHz XCLK = OSC1 = 12MHz TEMPERATURE RANGE Specification Storage 0 –65 +5 –5 +5 250 +5.25 –4.75 +5.25 425 30 –18 5 45 –25 15 +70 +125 * * * * * mA * * * * * * * * V V V mW * * * * * * mA mA mA * * oC oC NOTES: (1) All dynamic specifications are based on 2048-point FFTs, using four-term Blackman-Harris window. (2) All specifications in dB are referred to a fullscale input, ±2.75Vp-p. (3) Adjustable to zero with external potentiometer. ® DSP101/102 2 TYPICAL PERFORMANCE CURVES At TA = +25°C, VA+ = VD+ = +5V, VA– = VD– = –5V, Sampling Frequency fS = 200kHz; External Clock Input at OSC1 = 80fS = 16MHz, XCLK = 40fS = 8MHz; Using 2048 Point FFT; Data analysis limited to 0 to 20kHz band; Unless otherwise specified. SINAD means Signal-to-(Noise + Distortion) Ratio. SNR means Signal-to-Noise Ratio excluding harmonics thru the 8th. THD means Total Harmonic Distortion thru 8th harmonic. SFDR means Spurious Free Dynamic Range, including harmonics. FREQUENCY SPECTRUM of ±2.75V, 20kHz INPUT (Using Four-Term Blackman-Harris Window) FREQUENCY SPECTRUM of ±2.75V, 1kHz INPUT (Average of 12 FFTs, No Window Used) 0 0 –20 Magnitude (dB) Magnitude (dB) –30 –60 –40 –60 –80 –90 –100 –120 –120 0 25 50 75 0 100 25 50 75 100 Frequency (kHz) Frequency (kHz) FREQUENCY SPECTRUM of ±2.75V, 451kHz INPUT (Using Four-Term Blackman-Harris Window) INTERMODULATION DISTORTION WITH 1kHz AND 3kHz INPUTS (Using Four-Term Blackman-Harris Window) 0 0 –20 –20 Magnitude (dB) Magnitude (dB) Undersampling –40 –60 –80 –40 –60 –80 –100 –100 –120 –120 0 25 50 75 0 100 25 50 75 100 Frequency (kHz) Frequency (kHz) DSP102 CHANNEL SEPARATION ON CHANNEL B WITH ±2.75V, 1kHz INPUT ON CHANNEL A DYNAMIC PERFORMANCE vs TEMPERATURE 80 0 –80 Magnitude (dB) –20 –40 –60 –80 –100 85 –85 SINAD 90 SNR 95 –95 SFDR 100 –120 0 25 50 75 –55 –40 –25 100 –90 THD THD (dB) SINAD, SNR and SFDR (dB) fIN = 1kHz, ±2.75V 0 25 70 85 –100 125 Ambient Temperature (°C) Frequency (kHz) ® 3 DSP101/102 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VA+ = VD+ = +5V, VA– = VD– = –5V, Sampling Frequency fS = 200kHz; External Clock Input at OSC1 = 80fS = 16MHz, XCLK = 40fS = 8MHz; Using 2048 Point FFT; Data analysis limited to 0 to 20kHz band; Unless otherwise specified. DYNAMIC PERFORMANCE vs TEMPERATURE (fS = 180kHz Asychronous to 12.288MHz Crystal Between OSC1 and OSC2) DYNAMIC PERFORMANCE vs TEMPERATURE (Data Analysis Over Full 0 to 100kHz Band) 70 75 –70 –75 fIN = 1kHz, ±2.75V 80 –80 SINAD –85 THD 90 –90 SNR 95 –95 –80 SINAD 85 90 –90 THD 95 –95 SFDR 100 0 25 70 85 SFDR 100 –100 –55 –40 –25 –55 –40 –25 125 25 70 85 –100 125 DYNAMIC PERFORMANCE vs CONVERSION RATE (Data Analysis over Full 0 to fS/2 Band, OSC1 = 12.288MHz, XCLK = 3.072MHz) HISTOGRAM OF 5k CONVERSION RESULTS ON DSP102 (Both Inputs Grounded) 2500 70 fIN = 1kHz, ±2.75V (0dB) SINAD, SNR and SFDR (dB) SINAD 2000 Channel A Channel B 1000 500 0 75 FFF7 0000 0V –70 –75 SNR 80 –80 85 –85 THD 90 –90 SFDR 95 –95 100 Code FFF1 Voltage –1.26mV 000E 1.17mV –100 0 30 60 90 120 150 180 Conversion Rate (kHz) Output Code and Equivalent Voltage (Binned at 16-bit level) SINAD vs INPUT FREQUENCY (Data Analysis over Full 0 to 100kHz Band) TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 100 –60 ±2.75V Input (0dB) 80 ±2.75V Input (0dB) Total Harmonic Distortion (dB) 90 ±0.275V Input (–20dB) 70 SINAD (dB) Number of Conversions Yielding This Code 0 Ambient Temperature (°C) Ambient Temperature (°C) 1500 –85 SNR 60 50 40 ±2.75mV Input (–60dB) 30 20 –70 –80 –90 10 0 –100 0.1 1 10 100 1 Input Frequency (kHz) ® DSP101/102 10 100 Input Frequency (kHz) 4 1000 THD (dB) 85 80 THD (dB) –75 SINAD, SNR and SFDR (dB) 75 THD (dB) SINAD, SNR and SFDR (dB) fIN = 1kHz, ±2.75V TYPICAL DSP102 FFT SETUP DSP102 Brüel & Kjaer 6 Pole, Model 1049 1kHz 150kHz Digital Signal ±2.75V Low-Pass Generator Filter 27 REF CASC 0.1µF 1/2 OPA2604 150Ω 2 VINA OSC1 220pF 1 + 1/2 OPA2604 SSF 150Ω CLKIN 10µF 25 220pF CLKOUT VPOTA VINB CONV 26 + XCLK VPOTB 10µF SYNC SOUTA 22 +5V 12 13 16MHz TTL Oscillator 11 10 ÷80 21 200kHz 16 8MHz ÷2 Burr-Brown ZPB34 DSP Processor 15 20 FFT Software ABSOLUTE MAXIMUM RATINGS DSP101 PIN ASSIGNMENTS VA+ to Analog Common .................................................................... +7V VA– to Analog Common .................................................................... –7V VD to Digital Common ........................................................................ +7V Analog Common to Digital Common ................................................... ±1V Control Inputs to Digital Common ............................... –0.5 to VD + 0.5V Analog Input Voltage .......................................................................... ±5V Maximum Junction Temperature .................................................... 150oC Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ............................................... +300oC Thermal Resistance, θJA, Plastic DIP ............................................ 50oC/W DSP101 PIN CONFIGURATION Top View DIP VPOT 1 28 AGND VIN 2 27 REF MSB 3 26 CAP VOS 4 25 VA – 5 24 VA + 6 DGND 7 23 DSP101 22 DGND PIN # NAME DESCRIPTION 1 VPOT 2 3 4 5 6 7 8 9 10 11 VIN MSB VOS VA– VA+ DGND DGND VD CLKIN CLKOUT Trim Reference Out. 10µF Tantalum to AGND. Voltage on this pin is approximately 2.75V. Analog In. MSB Adjust In. VOS Adjust In. –5V Analog Power. +5V Analog Power. Digital Ground. Digital Ground. +5V Digital Power. Conversion Clock In. Conversion Clock Out. Can drive multiple DSP101/DSP102s to synchronize conversion. 12 SSF 13 OSC1 Oscillator Point 1 Input/External Clock In. If using external clock, drive with 74HC logic levels. Connect to DGND if not used. 14 OSC2 Oscillator Point 2 Output. Provides drive for crystal oscillator. Make no electrical connection if using external clock. 15 SYNC Data Synchronization Out. Active High when SSF is HIGH; active Low when SSF is LOW. 16 XCLK Data Transfer Clock In. TAG User Tag In. Data clocked into this pin is appended to the conversion results on SOUT. See timing diagram (Figure 1). 17 18 DGND 8 21 CONV VD 9 20 SOUT CLKIN 10 19 CLKOUT 11 18 SSF 12 17 OSC1 13 16 XCLK OSC2 14 15 SYNC No Internal Connection. 19 TAG Select Synch Format In. If HIGH, SYNC will be active High. If LOW, SYNC will be active Low. See timing diagram (Figure 1). No Internal Connection. 20 SOUT Serial Data Out. MSB first, Binary Two’s Complement format. 21 CONV Convert Command In. Falling edge puts converter into hold state, initiates conversion, and transmits previous conversion results to DSP IC with appropriate SYNC pulse. 22 23 24 25 26 DGND 27 REF 28 AGND Digital Ground. No Internal Connection. No Internal Connection. No Internal Connection. Bypass Capacitor. 10µF Tantalum to AGND. Voltage on this pin is approximately 2.7V. Reference Bypass. 0.1µF Ceramic to AGND. Voltage on this pin is approximately 3.8V. Analog Ground. CAP ® 5 DSP101/102 DSP102 PIN CONFIGURATION DSP102 PIN ASSIGNMENTS Top View DIP VPOTA 1 28 AGND VINA 2 27 REF PIN # NAME DESCRIPTION 1 VPOTA VINA MSBA VOSA VA– VA+ DGND DGND VD CLKIN CLKOUT Channel A Trim Reference Out. 10µF Tantalum to AGND. Voltage on this pin is approximately 2.75V. Channel A Analog In. Channel A MSB Adjust In. Channel A VOS Adjust In. –5V Analog Power. +5V Analog Power. Digital Ground. Digital Ground. +5V Digital Power. Conversion Clock In. Conversion Clock Out. Can drive multiple DSP101/ DSP102s to synchronize conversion. MSBA 3 26 VPOTB VOSA 4 25 VINB VA– 5 24 MSBB VA+ 6 23 VOSB 2 3 4 5 6 7 8 9 10 11 12 SSF Select Synch Format In. If HIGH, SYNC will be active High. If LOW, SYNC will be active Low. See timing diagram (Figure 1). 13 OSC1 Oscillator Point 1 Input / External Clock In. If using external clock, drive with 74HC logic levels. Connect to DGND if not used. 14 OSC2 Oscillator Point 2 Output. Provides drive for crystal oscillator. Make no electrical connection if using external clock. 15 SYNC Data Synchronization Out. Active High when SSF is HIGH; active Low when SSF is LOW. 16 XCLK Data Transfer Clock In. 17 SOUTB 18 TAGA Channel A User Tag In. Data clocked into this pin is appended to the conversion results of SOUTA. See timing diagram (Figure 1). 19 TAGB PACKAGE DRAWING NUMBER(1) Channel B User Tag In. Data clocked into this pin is appended to the conversion results of SOUTB. See timing diagram (Figure 1). 20 SOUTA 215 215 215 215 Channel A Serial Data Out. MSB first, Binary Two’s Complement format. If CASC is HIGH, 32 bits of data output, with first 16 bits being Channel A data. 21 CONV Convert Command In. Falling edge puts converter into hold state, initiates conversion, and transmits previous conversion results to DSP IC with appropriate SYNC pulse. 22 CASC Select Cascade Mode In. If HIGH, DSP102 transmits a 32-bit word on SOUTA, with the first 16 bits being data on Channel A. If LOW, DSP102 transmits data for both channels simultaneously. 23 24 25 26 VOSB MSBB VINB VPOTB 27 REF 28 AGND Channel B VOS Adjust In. Channel B MSB Adjust In. Channel B Analog In. Channel B Trim Reference Out. 10µF Tantalum to AGND. Voltage on this pin is approximately 2.75V. Reference Bypass. 0.1µF Ceramic to AGND. Voltage on this pin is approximately 3.8V. Analog Ground. DSP102 DGND 7 22 CASC DGND 8 21 CONV 9 20 SOUTA VD CLKIN 10 19 TAGB CLKOUT 11 18 TAGA SSF 12 17 SOUTB OSC1 13 16 XCLK OSC2 14 15 SYNC PACKAGE INFORMATION MODEL PACKAGE DSP101JP DSP101KP DSP102JP DSP102KP 28-Pin 28-Pin 28-Pin 28-Pin Plastic Plastic Plastic Plastic DIP DIP DIP DIP NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION NUMBER OF CHANNELS MODEL DSP101JP DSP101KP DSP102JP DSP102KP 1 1 2 2 SIGNAL-TO(NOISE + DIST.) RATIO dB min 83 86 83 86 Channel B Serial Data Out. MSB first, Binary Two’s Complement format. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DSP101/102 6 FIGURE 1. DSP101 and DSP102 Timing. ® 7 DSP101/102 SYMBOL SOUTA CONV XCLK 186 62 84 62 10 20 83 50 24 40 t1 +40 3 t12 2000 1050 1340 0 667 2 t1 15 15 15 MAX Channel A Data Bit 2 t4 TAG Bit 2 Bit 2 MIN Bit 1 (MSB) t9 t11 t9 XCLK period. Duty Cycle 50% ±10% Convert Command LOW Time Convert Period (CASC = LOW on DSP102) Convert Period (CASC = HIGH on DSP102) SYNC Active Delay after Convert Falling Edge SYNC LOW to HIGH Delay from XCLK Rising SYNC HIGH to LOW Delay from XCLK Rising SOUTA/B Data Valid Delay from XCLK Rising SOUTA/B Data Valid After from XCLK Rising TAGA/B Data Setup before XCLK Rising TAGA/B Data Hold after XCLK Rising OSC1 Period.(2) Duty Cycle 50% ± 10% CLKOUT Period. Duty Cycle 33% ± 10% CLKIN Period. Duty Cycle 33% ± 20% CLKIN HIGH CLKIN LOW t8 TAG Bit 1 t10 Bit 1 (MSB) DESCRIPTION (CL = 50pF) (CASC = HIGH) t2 t1 t8 t6 t7 t3 ns ns t1 t1 ns ns ns ns ns ns ns ns ns ns UNITS Bit 16 (LSB) Bit 16 NOTES: (1) When using a DSP IC in a 16-bit mode, these data bits will be ignored by the processor. (2) fOSC1 must be at least 72 times faster than the conversion rate. (t3, t4 ≥ 72 t12) t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 (CASC = LOW on DSP102) DSP102 Cascade Mode (CASC = HIGH) TAGA/B SOUTA/B t7 SYNC (SSF = LOW) t5 t6 t2 t1 SYNC (SSF = HIGH) CONV XCLK (1) CLKIN CLKOUT OSC1 Channel B Data Bit 18 (2) (LSB) Bit 16 TAG Bit 1 t12 t15 Conversion Clock Timing (2) Bit 1 (MSB) Bit 17 t14 t13 t16 TAG Bit 2 t2 t2 THEORY OF OPERATION A unique Tag feature allows additional digital data to be appended to the conversion results, so that a single data word contains conversion results plus other signal information, such as gain settings or multiplexer channel settings in front of the converter. The DSP101 and DSP102 are sampling analog-to-digital converters optimized for handling dynamic signals. They have complete logic interface circuitry for ease of use with standard digital signal processing ICs, and transmit data words in a serial stream. The successive approximation conversion architecture is combined with an inherently sampling switched capacitor array to provide maximum user flexibility over sampling and conversion timing. The DSP101 and DSP102 are pipelined internally. When the user gives a convert command at time (t), two actions are initiated. First, the internal sample/holds are switched to the hold state, and a conversion cycle is initiated. At the same time, the DSP101 or DSP102 transmits a synchronization pulse and starts shifting out the conversion results from the previous convert command at (t-1) using the system bit clock. The data from the conversion at time (t) is shifted out of the converter after the next convert command is received. The DSP101 and DSP102 are high-resolution A/D converters complete with sampling capability and on-board references. They can acquire and convert analog signals at up to a 200kHz sampling rate. Both operate from ±5V supplies, and have full-scale analog input ranges of ±2.75V. BASIC OPERATION Figure 2 shows the minimum connections required to operate the DSP101. The falling edge of a convert command on pin 21 puts the internal sampling capacitor array into the hold state. The falling edge on pin 21 also starts the process to initiate a conversion and transmit data from the previous conversion, synchronizing both appropriately to the 10MHz clock input on pin 13. Figure 1 shows the timing relationship between the convert command, the output data, and the synchronization pulse. Both the DSP101 and the DSP102 are 18-bit A/Ds internally. When the DSP IC is programmed to accept 16-bit word lengths, the processor will ignore the last two data bits transmitted from the DSP101 or DSP102. A Cascade Mode on the DSP102 can be invoked to transmit data for both conversion channels over a single serial line as a 32-bit word. In this mode, the first 16 bits of data transmitted after the Sync pulse contain data from channel A, followed by 16 bits of information from channel B, allowing a single 32-bit word to contain data for both channels. In this basic system, the 10MHz clock is used both to generate a 3.33MHz conversion clock and as the data transfer bit clock for outputting data. Per Figure 1, there must be at least 72 clock pulses on pin 13 between convert commands, so that this circuit can sample and convert at up to 138kHz. DSP101 + 10µF 1 VPOT 2 (1) (1) AGND 28 VIN REF 27 3 MSB CAP 26 4 VOS NC 25 (1) 5 VA– NC 24 (1) 6 VA+ NC 23 (1) 7 DGND DGND 22 8 DGND CONV 21 9 VD SOUT 20 10 CLKIN NC 19 11 CLKOUT TAG 18 12 SSF NC 17 13 OSC1 XCLK 16 14 OSC2 SYNC 15 0.1µF ±2.75 Analog Input 10Ω(2) –5V + –5V + 10µF 10µF + 10µF +5V + Convert Command Serial Data Output 10µF +5V 10MHz, 50% (±10%) 74HC Logic Level Clock Input (1) NOTES: (1) Leave Unconnected. (2) Protection from power supply momentary overrange. FIGURE 2. DSP101 Basic Operation. ® DSP101/102 8 (1) (1) Synch Pulse = Analog Ground Bit Clock = Digital Ground The convert command at pin 21 causes a Sync pulse to be output on pin 15, followed by the data from the previous conversion output on pin 20. The Sync pulse will be HIGH for one bit clock cycle, since pin 12 is tied HIGH. (A LOW Sync pulse will be output on pin 15 if pin 12 is tied LOW.) Data is serially transmitted in an MSB-first data stream, in Binary Two’s Complement format. Both the Sync pulse (pin 15) and the data stream (pin 20) are synchronized to the bit clock (at pins 13 and 16), with the timing relationships shown in Figure 1. CLKIN periods between convert commands, the A/D will have had sufficient time to acquire a new input sample to full rated accuracy. DATA FORMAT AND INPUT LEVELS The DSP101 and DSP102 output serial data, MSB first, in Binary Two’s Complement format. In the Cascade Mode on the DSP102, the serial data will first contain 16 bits of data for channel A, MSB-first, followed by channel B data, again MSB-first. The analog input levels that generate specific output codes are shown in Table I. After the 18 bits of data from the previous conversion have been transmitted, pin 20 will continue to clock out LOWs until a new convert command restarts the process, since pin 18 (the Tag input) is grounded. If pin 18 is tied HIGH, pin 20 will clock out HIGHs between conversion cycles. As with all standard A/Ds, the first output transition will occur at an analog input voltage 1/2 LSB above negative full scale (–2.75V + 1/2 LSB) and the last transition will occur 3/2 LSB below positive full scale (+2.75V – 3/2 LSB.) See Figure 3. CONVERSION A falling edge on pin 21 (CONV) puts the internal sampling capacitors in the hold state with minimum aperture jitter, initiates a conversion synchronized to the conversion clock, and outputs the data from the previous conversion with an appropriate Sync pulse. On the DSP102, a single convert command simultaneously samples both channels. The timing relationship between the convert command, Sync and the output data is shown in Figure 1. Both Sync and the output data are synchronized to XCLK, the system bit clock. Following a convert command falling edge, pin 21 must be held LOW at least 50ns. 1FFFFH Digital Output (18-bit Words) 1FFFEH Convert commands can be sent to the DSP101 and DSP102 completely asynchronous to other clocks in the system. This allows external events to be used to trigger conversions. 00001H 00000H –2.75V –20.98µV 3FFFFH +2.749979V 0.00V 20001H From Figure 1, it can be seen that two different clocking conditions must be considered in determining the minimum acceptable time between convert commands. First, there need to be a minimum of 24 XCLK periods between convert commands, to allow internal synchronization and transmission of Sync and the data. (In the Cascade Mode on the DSP102, there need to be at least 40 XCLK periods between convert commands, to allow transmission of the 32-bit data words.) When used with DSP processors programmed for data words longer than 16 bits, the transmission time to the processor may determine the minimum time between convert commands. 20000H FIGURE 3. Analog Input to Digital Output Diagram. DIGITAL OUTPUT (BINARY TWO’S COMPLEMENT) DESCRIPTION ANALOG INPUT 16-BIT WORDS BINARY CODE (HEX) 18-BIT WORDS (HEX) Least Significant Bit 5.5V (LSB = ) 2n The second limitation on convert commands is the requirement that the internal analog-to-digital converter be given enough time to complete a conversion, shift the data to the output register, and acquire a new sample. This condition is met by having a minimum of 24 CLKIN periods between convert commands, or a minimum of 72 clock cycles on OSC1, if it is used to generate the conversion clock (CLKOUT driving CLKIN). 16-bit Words 18-bit Words 84µV 21µV Input Range ±2.75V + Full Scale (2.75V–1LSB) +2.749916V +2.749979V 011…111 0V 000…000 One LSB below Bipolar Zero –84µV –21µV 111…111 – Full Scale –2.75V 100…000 Bipolar Zero (Midscale) SIGNAL ACQUISITION After a conversion is completed, the DSP101 or DSP102 will switch back to the sampling mode. With at least 24 7FFF 1FFFF 0000 00000 FFFF 3FFFF 8000 20000 TABLE I. Ideal Input Voltage vs Output Code. ® 9 DSP101/102 18-bit Shift Register D Channel A Conversion Results from SAR CLKIN CONV 18-bit Register RCK 18 (LSB) Shift/Load(1) D1 16 14 12 10 8 6 4 2 1 (MSB) SOUTA XCLK TAGA D1 E D2 18-bit Shift Register CASC 18-bit Shift Register TAGB D1 SOUTB XCLK (LSB) 18 Shift/Load(1) 16 14 12 8 6 4 2 18-bit Register RCK CONV 10 (MSB) 1 CLKIN D Channel B Conversion Results from SAR 18-bit Shift Register NOTE: (1) Signal internal to DSP101/DSP102 which also generates SYNC pulse. FIGURE 4. Output Structure of DSP102. DATA TRANSFER The internal A/Ds generate 18 bits of data, transmitting the data MSB first. When read by a DSP IC programmed to accept 16 bits of data, the first 16 MSB bits of data from the DSP101, or each channel of the DSP102, will be shifted into the processor’s input shift register, and the last two least significant bits of data from the A/D will be ignored, although they will still be present on the serial data line. When the DSP processor is programmed to accept words of more than 16-bit length (typically 24-bit or 32-bit), the DSP101 and DSP102 will transmit the full 18-bit conversion results, after which the information input on the TAG input (or TAGA and TAGB on the DSP102) will be appended to the output word. (See Tag Feature below.) the conversion clock may also be independent of the bit clock. The DSP101 and DSP102 internally synchronize the output data, Sync pulse, and Tag inputs to the bit clock. In the Cascade Mode, the DSP102 will first transmit the 16 MSBs from channel A, followed by the full 18 bits from channel B, although DSP processors programmed to accept 32 bits of data will ignore the final two bits of information on Channel B. See the DSP102 Cascade Mode section below for details of the Cascade mode. When a convert command is received, the internal logic generates an appropriate Sync pulse, synchronized to XCLK, as shown in Figure 1. The output Sync pulse will be active High or active Low depending on whether a HIGH or a LOW, respectively, is input at SSF (pin 12). While the convert command, conversion clock and bit clock can be asynchronous, system performance is usually enhanced by synchronizing all of them to a system master clock, whenever the application permits. This minimizes changes in digital loads and currents when the critical S/H transition and A/D bit decisions are occurring. Within the DSP101 and DSP102 themselves, running asynchronous convert commands, conversion clocks and bit clocks typically degrades performance only several dB, as shown in the various typical performance curves, but the system board design can easily have more effect. The convert command also causes the conversion results from the previous conversion to be loaded into the output shift register, synchronous to XCLK. Figure 4 shows the operation of the internal data shift registers on the DSP102. The DSP101 is basically similar, but includes only the top of the figure, showing the SOUTA path. DATA SYNCHRONIZATION A convert command both initiates a conversion and starts the process for transmitting data from the previous conversion. Convert commands can come at any time, completely asynchronous to the conversion clock or the bit clock, and ® DSP101/102 10 During the internal successive approximation conversion process, the conversion results are shifted into the input shift registers of the output stage on the DSP102. A new convert command latches that data into the 18-bit parallel latches shown. The internal signal that also generates the Sync pulse, labeled “Shift/Load” in Figure 4, synchronously loads the conversion data into the output shift register on the rising edge of XCLK. The conversion results are then clocked out of the shift register on subsequent rising edges of XCLK. long enough for internal analog circuitry to settle sufficiently between bit decisions to insure rated accuracy. Bit decisions in the A/D are then made on the rising edge of CLKIN. To other DSP102's CLKIN for synchronous operation DSP101 or DSP102 SAR Clock Control DATA TRANSFER CLOCK XCLK is the data transfer clock, or bit clock, for the system, and is an input for the DSP101 or DSP102. This input is TTL- and 74HC-level compatible. The serial data and SYNC outputs are synchronized internally to this clock, with data valid on the rising edge of XCLK, per the timing shown in Figure 1. Data input on pin 18 (TAG) on the DSP101, or on pins 18 and 19 on the DSP102 (TAGA and TAGB), will be clocked into the output shift register on the rising edge of XCLK, as discussed in the Tag Feature section. ÷3 CLKIN 10 CLKOUT 11 OSC1 OSC2 13 14 1MΩ CONVERSION CLOCK The analog-to-digital converter sections in the DSP101 and DSP102 were designed to provide accurate conversions under worst case conditions of supplies, temperatures, etc. In order to achieve a full 200kHz sampling capability, they were designed to use a 33% duty cycle conversion clock (CLKIN on pin 10) as shown in Figure 1. The clock is LOW 12.288MHz 10pF 10pF Crystal is CTS Knight MP122 12.288MHz, 20pF load, series resonant mode. FIGURE 5. DSP101 or DSP102 Conversion Clock Circuit. DSP101 or DSP102 + (1) AGND 28 2 REF 27 3 VPOTB 26 1 VPOTA 10µF 4 25 0.1µF + 10µF (1) 10Ω(2) –5V Analog +5V Analog + 10µF + +5V Digital 10µF 5 VA – 24 6 VA + 23 7 DGND 22 8 DGND 21 9 VD 20 0.01µF 10 19 11 18 12 17 13 16 = Analog Ground 14 15 = Digital Ground NOTES: (1) Pin 1 and pin 26 must be bypassed with 10µF tantalum capacitors, on both the DSP101 and DSP102. (2) Protection from power supply momentary overrange. FIGURE 6. DSP101 or DSP102 Power Supply Connections. ® 11 DSP101/102 When a convert command is received, the DSP101 or DSP102 immediately switches the sampling capacitors to the hold state, and then internally gates the conversion clock to the A/D appropriately. Allowing a minimum of 24 CLKIN pulses between conversions insures that there is sufficient time for complete, accurate conversions, and allows the input sampling capacitor to fully acquire the next sample, regardless of the timing between the convert command and CLKIN. If CLKOUT is not used, both it and OSC2 should be left unconnected, and OSC1 should be grounded. TAG FEATURE Figure 4 shows the implementation of the TAG feature on the DSP101 and DSP102. When a convert command is received, the internal Shift/Load signal loads conversion result data into the output shift register synchronous to XCLK. Between convert commands, the information input on TAG (on the DSP101) or on TAGA and TAGB (on the DSP102) will be clocked into the output shift register on the rising edges of XCLK. Since this is an 18-bit shift register, the data input on the Tag lines will be output on SOUT (DSP101) or SOUTA and SOUTB (DSP102) delayed by 18 bit clocks. In most applications, CLKIN (pin 10) can be driven from a 50% duty cycle clock without performance degradation. During characterization of the DSP101 and DSP102, the performance of a number of parts was measured under various conditions with a 4.8MHz, 50% duty cycle input to CLKIN at a full 200kHz conversion rate without noticeable degradation. The Tag Feature can be used in various ways. The Tag inputs can be tied HIGH or LOW to differentiate between two converters in a system. As discussed in the Applications section below, the Tag feature can be used to append to the serial output data word information on multiplexer channel address, or other digital data related to the input signal (such as the setting on a programmable gain amplifier.) Another option would be to daisy-chain multiple DSP101 or DSP102 converters, linking the serial output of one to the Tag input of the next. This can simplify the transmission of data from multiple A/Ds over a single optical isolation channel. OSCILLATOR INPUTS AND CLKOUT The DSP101 or DSP102 can generate a 33% duty cycle conversion clock output on CLKOUT (pin 11). This is accomplished by dividing by three a clock from either an external 74HC-level clock or from a crystal oscillator. CLKOUT can deliver ±2mA, and can be used to drive multiple DSP101 or DSP102 CLKINs. See Figure 1 for the timing relationship between OSC1 and CLKOUT. To use an external 74HC-level clock, drive the clock into OSC1 (pin 13), and leave OSC2 (pin 14) unconnected. DSP102 CASCADE MODE If pin 22 (CASC) is tied HIGH, the DSP102 will be in the Cascade Mode. In this mode, when a convert command is received, the DSP102 will transmit a 32-bit data word on pin To use a crystal oscillator to generate the conversion clock, refer to Figure 5. Connect the oscillator between OSC1 and OSC2. OSC2 provides the drive for the crystal oscillator. This pin cannot be used elsewhere in the system. DSP101 or DSP102(1) +5V + 2.2µF 1/2 8 3 + OPA2604 1 2 – Analog Input A –5V + 1 VPOTA 2 VINA 28 10µF 150Ω 220pF 4 + 2.2µF REF 27 3 VPOTB 26 4 VINB 25 0.1µF + 10µF 150Ω 5 24 6 23 7 22 8 21 220pF 7 + 1/2 – OPA2604 5 Analog Input B 6 Leave out on DSP101(1) 9 20 10 19 11 18 12 17 13 16 14 15 FIGURE 7. DSP101 or DSP102 Input Buffering. ® DSP101/102 12 NOTE: (1) On DSP101, pin 25 is not internally connected. Pin 26 must still be bypassed with the 10µF Tantalum capacitor. NOISE AND BIPOLAR ZERO ERROR The equivalent input noise and bipolar zero error of the DSP101 and DSP102 is shown in the typical performance section for both channels on a DSP102. The inputs to both channels were grounded, and the results of 5,000 conversions was recorded. The data shown is binned at the 16-bit level. The noise results from all sources in the circuit, including clocks, reference noise, etc. 20 (SOUTA) containing data for both input channels in two 16-bit words. Referring to Figure 1, the first 16 bits of data will be the results for channel A, followed by 16 bits of information for channel B. The data will be transferred MSB first. A convert command at time (t) will initiate the transmission of the results of the conversion initiated at time (t – 1). From the descriptions above of the internal shift registers shown in Figure 4, it can be seen that the DSP102 in the Cascade Mode actually continues to shift out data after the 32nd bit of the data word. The next two bits clocked out will be the last two data bits from the full 18-bit conversion on channel B, after which the information output on SOUTA will be the information clocked into TAGB 35 bit clock cycles earlier. In the Cascade mode on the DSP102, SOUTB will still output channel B conversion data and tag data as usual. In a theoretically ideal converter with no offset and no noise, the results of all 5,000 conversion for each channel would lie in the bin corresponding to bipolar zero, code 0000. The typical DSP101 or DSP102 will have offset errors in the range of 1 to 2mV, and the two channels on the DSP102 will be matched closer than 2mV. The DSP102 shown in the typical performance section has the worst offset, –0.8mV, on channel A, with channel B being less than 1mV different, and the three sigma noise on either channel being less than 250µV. ANALOG PERFORMANCE INPUT BANDWIDTH From the typical performance curves, it can be seen that there is very little degradation in Signal-to-(Noise + Distortion) for input signals up to 100kHz. The wideband sampling input typically maintains a 60dB Signal-to-(Noise + Distortion) Ratio undersampling 500kHz input signals. LINEARITY The DSP101 and DSP102 are optimized for signal processing applications with wide dynamic range requirements. Linearity is trimmed for best performance in the range around 0V, which is critical for handling low amplitude signals. The DSP101 and DSP102 typically have integral and differential non-linearity below ±0.003% in the input range of ±0.7V, with there being no missing codes at the 14-bit level in this range. Over the full ±2.75V input range, the largest non-linearities are centered around the bit #2 transition points at +1.375V and –1.375V levels. LAYOUT CONSIDERATIONS Because of the high resolution, linearity and speed of the DSP101 and DSP102, system design problems such as ground path resistance, contact resistance and power supply quality become very important. DSP101 or DSP102(1) 1 + 10µF 47kΩ 25kΩ VPOTA 28 0.1µF 150kΩ 47kΩ 0.01µF 2 3 MSBA 4 VOSA REF 27 VPOTB 26 25 25kΩ 5 MSBB 24 6 VOSB 23 0.01µF + 150kΩ 47kΩ 47kΩ 10µF 25kΩ 0.01µF 25kΩ 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 0.01µF Leave out on DSP101(1) NOTE: (1) On DSP101, pins 23 and 24 are not internally connected. Pin 26 must still be bypassed with the 10µF Tantalum capacitor. FIGURE 8. DSP101 or DSP102 Optional MSB and Offset Adjust. ® 13 DSP101/102 POWER SUPPLY DECOUPLING All of the supplies should be decoupled to the appropriate grounds using tantalum capacitors in parallel with ceramic capacitors, as shown in Figure 6. For optimum performance of any high resolution A/D, all of the supplies should be as clean as possible. If separate digital and analog supplies are available in a system, care should be taken to insure that the difference between the analog and the digital supplies is not more than 0.5V for more than a few hundred milliseconds, as may occur at power-on. Optimal dynamic performance is achieved by soldering the parts directly into boards, to keep the A/Ds as close as possible to ground. The use of sockets will often degrade AC performance. Zero-Insertion-Force sockets are particularly poor because longer lead lengths create inductance. Short traces on the board, and bypass capacitors as close as possible to the A/D, will further improve dynamic performance. GROUNDS To achieve the maximum performance from the DSP101 or DSP102, care should be taken to minimize the effect of changes in current flowing in the system grounds, particularly while bit decisions are being made in the successive approximation converter’s comparator. Pin 28 (AGND) on both the DSP101 and the DSP102 is the most critical, and care should be taken to make this pin as close as possible to the same potential as the system analog ground. INPUT SIGNAL CONDITIONING To avoid introducing distortion, the DSP101 and DSP102 analog inputs must be driven by a source with low impedance over the input bandwidth needed in the application. Op amps such as the NE5532 or Burr-Brown’s OPA2604 work well over audio bandwidths. Figure 7 shows an appropriate input driver circuit. The 150Ω and 220pF shown on the input help reduce the dynamic load on the input signal conditioning amp in front of the A/D, since all switched capacitor array architectures exhibit fast changes in input current load as the input sampling switch is opened and closed. These dynamic changes in the load can affect any signal conditioning circuit at the input. Other R and C combinations can be Whenever possible, it is strongly recommended that separate analog and digital ground planes be used. With an LSB level of 84µV at the 16-bit level, and one-quarter of that at the 18-bit level, the currents switched in a typical DSP system can easily corrupt the accuracy of the A/Ds unless great care is taken to analyze and design for current flows. DSP101 74HC594(1) 14 20 Serial Data SOUT QA 12 SSF +5V +5V 16 XCLK 10 13 11 SR CLK 9 QH QH TTL Bit Clock SYNC 15 RCK 14 D1 Serial Data QA +5V +5V 2 9 D2 CLR CLK Q7 8 +5V 10 13 SR CLR R CLR 13 11 SR CLK QH 74HC164 1 +5V +5V 2 9 RCK 12 15 1 2 3 4 5 6 7 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) 12 D1 D2 CLR 74HC74 HC04 CLK Q7 NOTE: (1) Substituting 74HC595s provides three state outputs, with pin 13 (OE) used to enable the parallel data lines. 8 3 13 2 +5V 4 1 12 10 RD 13 FIGURE 9. Driving a 16-bit Parallel Port from the DSP101. ® DSP101/102 D15 (LSB) D14 D13 D12 D11 D10 D9 D8 74HC594(1) 74HC164 1 SR CLR R CLR 15 1 2 3 4 5 6 7 14 CLK1 Q1 5 D1 S1 R1 D2 S2 CLK2 R2 Q2 11 9 Data Valid Signal used, but the resistor should not exceed 200Ω, or the output settling time of the signal conditioning amplifier may be too long. 18-bit level.) This will center the offset at 1/2 LSB below 0V, which is respectively –42µV or –10µV at the 16- and 18-bit levels. The offset can also be adjusted by providing a sine wave to the A/D input. Using FFT, or even simple averaging of several thousand conversion results at a time, the trimpots can be adjusted until there is no DC offset of the signal. EXTERNAL ADJUSTMENTS All of the specifications for the DSP101 and DSP102, plus the typical performance curves, are based on the performance of these A/Ds without external trims. In most applications, external trims are not required. Grounding the input, or providing the sine wave, as far in front of the A/D as possible allows offset from intervening signal conditioning components to be also corrected by this procedure. OFFSET ADJUST Where required by specific applications, offsets can be adjusted using the circuit of Figure 8. When not adjusted, VOS (pin 4) on the DSP101, and VOSA (pin 4) and VOSB (pin 23) on the DSP102, should be left open. If these pins are connected to traces on the board, they should be bypassed to ground with 0.01µF capacitors, as close as possible to the A/D. MSB ADJUST In most applications, adjustment of the Most Significant Bit weight will not be required. When not adjusted, MSB (pin 3) on the DSP101, and MSBA (pin 3) and MSBB (pin 24) on the DSP102, should be left open. If these pins are connected to traces on the board, they should be bypassed to ground with 0.01µF capacitors, as close as possible to the A/D. To trim offset, one alternative is to ground the analog input while converting continually. Then adjust the trimpot (on VOS for the DSP101, on VOSA and VOSB for the DSP102) until the output code is toggling between the codes FFFF and 0000 (Hex) at the 16-bit level (3FFFF and 00000 at the MSB (pin 3) on the DSP101, and MSBA (pin 3) and MSBB (pin 24) on the DSP102, are internally connected to a resistor divider network that is used to laser-trim the weight DSP101 HI-508A 4 Analog Inputs(1) 5 6 7 12 11 10 9 21 In1 In2 Out In3 In4 EN 2 2 6 OPA627 2 VIN SOUT TAG +5V 20 Serial Data Out 18 C1 In5 In6 In7 A1 16 A 15 12 220pF 1 A0 In8 CONV R1 150Ω 3 8 SSF XCLK SYNC 16 15 2 NOTE: (1) Must be low source impedance with unused inputs tied to ground. 6 5 4 3 9 15 74HC163 CO 11 QD 12 C QC 13 B QB 14 A QA 1 LD CL 74HC574 D 9 8 7 6 5 CLK ET EP 2 10 7 4 +5V 3 2 8D 8Q 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2D 2Q 1D 1Q 74HC166 12 14 13 12 14 11 15 10 16 5 17 4 18 3 19 2 1 CLK OE 11 1 H QH 13 G +5V F 4.7kΩ E R2 C4 D 1000pF C B 15 A R/C SI 14 74HC221 CE 2 15 S/L 1 CLK CI CL 7 6 9 B Q A Q 13 4 CL 3 +5V +5V Convert Command (Positive Edge Triggered) FIGURE 10. A Complete Eight-Channel Analog Input System Using the DSP202 and the HI-508A. ® 15 DSP101/102 of the MSB capacitor in the CDAC. These pins are nominally at +100mV after laser-trimming during manufacturing. They can handle external inputs up to about one diode drop below ground (–0.6V) before internal clamping circuitry is triggered. (t) is valid one conversion cycle plus 17 XCLK clocks later (at t+1 plus 17 times XCLK). A convert command at time (t+1) generates a Sync and begins transmitting serial data from SOUT. The serial data is shifted into the 74HC594 shift registers, and Sync is shifted through the 74HC164 shift registers. The Q1 output of the 74HC74 dual D-type flip-flops clocks the conversion data into the output register of the 74HC594s, and triggers a data valid signal on its Q2 output. The user can then read the data at any time before the next conversion is started, and the Read signal will reset the data valid output from Q2. Figure 8 shows an appropriate circuit for adjusting the weight of the most significant bit to minimize differential non-linearity at the critical major-carry transition. To adjust, provide a small amplitude sine wave to the selected A/D input pin while converting continually, and adjust for maximum Signal-to-(Noise + Distortion) ratio, using appropriate signal analysis software. In many systems, galvanic isolation of signals is required. Using opto-couplers on the serial data lines in Figure 9 allows a fully isolated system to be built using a DSP101 and only three couplers across the barrier (for serial data, XCLK and SYNC.) GAIN ADJUST If circuit gain needs to be adjusted in hardware, rather than in system software, appropriate trimpots should be included in the analog signal conditioning section in front of the DSP101 or DSP102. No specific gain adjust circuitry is included in the parts. MULTIPLEXING INPUTS TO THE DSP101 Figure 10 shows a complete circuit for sequentially scanning eight analog input channels with a single DSP101, and using the Tag feature on the DSP101 to append the multiplexer channel address to the serial output conversion results. APPLICATIONS The circuit in Figure 10 includes the required digital logic and timing logic. The 74HC163 counter provides the scan sequence to the Burr-Brown HI-508A analog multiplexer. In order to allow the HI-508A enough time to switch to the next channel and settle before the DSP101 begins a conversion, a 74HC221 one-shot introduces a 3µs delay for the DSP101 convert command input. INTERFACING DSP101 TO PARALLEL PORTS Figure 9 shows a circuit for converting the serial output data from the DSP101 into 16 bits of parallel data, within the timing constraints of the serial bit-stream from the DSP101. In many applications, this circuit can be easily incorporated into gate arrays or other programmed logic circuits already used in the system, since the extra gate count is not high. The Burr-Brown OPA627 provides a low impedance source for the DSP101, buffering it from the output impedance of This circuit adds an additional pipeline delay to the conversion data, so that the parallel data from a conversion at time TTL Bit Clock Digital Signal Processor IC DSP101 XCLK 2 ±2.75V Analog Input VIN SOUT SYNC SSF CONV DSP PROCESSOR DSP32C, DSP16 DSP56001 DSP56001 TMS320C25/C30 ADSP2101/2105 16 CLKR 20 12 11 SYNC SSF(2) SSF (2) 9 SWL (3) 10 15 Conversion Rate Generator SYNC FORMAT SERIAL I/O WORD Active Low Active High Active High Active High Active High 16 24 16 16 16 Bits Bits Bits Bits Bits FIGURE 11. Analog Input and Analog Output System. ® DSP101/102 13 DATA OUT SYNC 21 12 XCLK DATA IN 15 (1) DSP201 16 SSF(2) SWL(3) LOW HIGH HIGH HIGH HIGH HIGH LOW HIGH HIGH HIGH XCLK SIN VOUT 21 SYNC SSF SWL CONV (1) See Burr-Brown DSP201/DSP202 product data sheet for full description of this DAC. ±3V Analog Output the multiplexer. This unity-gain buffer minimizes distortion, taking full advantage of the resolution and bandwidth of the DSP101. DSP101 shift register (discussed in another section of this data sheet.) Figure 10 was developed and tested using a Burr-Brown ZPB34 DSP board, which contains an AT&T DSP32C, so that the SYNC output is programmed to be active LOW. The circuit needs to be modified for DSP processors from ADI, TI, and Motorola, which use active HIGH Sync pulses. For these processors, tie SSF (pin 12) on the DSP101 HIGH, and use a 74HC04 hex inverter to invert the Sync signal to the 74HC574 and 74HC166. The 74HC574D register delays the multiplexer address data by one conversion before appending the channel data to the serial conversion results from the DSP101. This attaches the channel address to the correct conversion results. Since the channel scanning shown in Figure 10 is sequential, this delay latch could be left out and software could recognize that the time (t) conversion results have the MUX address from the time (t-1) conversion appended. However, for systems using non-sequential scan lists, this delay latch is essential to maintain the conversion data and channel address integrity. The same basic circuit can be duplicated to drive two channels in a DSP102, or can be easily modified for more or less than eight channels of analog input. The 74HC166 synchronous loading shift register loads the channel address tag data into the shift register on the rising edge of the bit clock, in conjunction with the Sync output of the DSP101. The channel address tag data is then clocked into the DSP101 Tag input (pin 18) by the bit clock, while the conversion data is clocked out the other end of the USING DSP101 AND DSP102 WITH TEXAS INSTRUMENTS DSP ICS Figures 11 thru 17 show various ways to use the DSP101 and DSP102 with DSP ICs from the Texas Instruments TMS320Cxx series. For simplicity, all of these circuits are TTL Bit Clock DSP102 TMS320C30 XCLK SYNC ±2.75V Analog Input Channel A ±2.75V Analog Input Channel B 2 25 VINA SOUTA VINB SOUTB CASC SSF CONV 16 CLKR 15 FSR-0 FSR-1 DR-0 20 17 DR-1 22 12 +5V 21 Conversion Rate Generator FIGURE 12. Using DSP102 with TMS320C30. TTL Bit Clock DSP102 XCLK SYNC ±2.75V Analog Input Channel A ±2.75V Analog Input Channel B 2 25 VINA VINB SOUTA SOUTB CASC NOTE: Serial port 0 programmed for 32-bit data. SSF CONV TMS320C30 16 CLKR -0 15 FSR-0 20 17 22 12 DR-0 NC +5V +5V 21 Conversion Rate Generator FIGURE 13. Using DSP102 with TMS320C30 in Cascade Mode. ® 17 DSP101/102 based on using the TME320Cxx in the mode where SSF (Select Synch Format, pin 12) is tied HIGH, so that there is an active High synchronization pulse generated by the DSP101 or DSP102 after receiving a convert command. The synchronization pulse can be changed to active Low simply by making SSF LOW, where appropriate, without changing the basic operation of the A/Ds. In all cases, the DSP101 and DSP102 will transmit data MSB-first, and the TMS320Cxx needs to be programmed for this. Figure 11 shows a circuit for using the TMS320C25 or TMS320C30 in a complete analog input and analog output system using the DSP101 along with the Burr-Brown DSP201 D/A. TTL Bit Clock DSP102 XCLK ±2.75V Analog Input Channel A 2 ±2.75V Analog Input 25 Channel B SOUTA VINA SOUTB SYNC VINB SSF CASC DSP202 (3) TMS320C30 16 CLKR-0 CLKR-1 20 DR-0 17 12 13 DX-0 DR-1 15 12 CLKX-0 CLKX-1 14 DX-1 11 FSX-0 FSX-1 FSR-0 FSR-1 +5V +5V 22 +5V 9 10 16 CONV 21 15 Conversion Rate Generator (1) XCLK SINA SINB SYNC VOUTA VOUTB 21 ±3V Analog Output Channel A 5 ±3V Analog Output Channel B SSF SWL CASC CONV NOTES: (1) Sample rate on DSP102 and DSP202 may differ. (2) Analog Devices ADSP2101 may be used. SPORT1 and SPORT2 are used for serial MSB first communication. (3) See Burr-Brown DSP201/DSP202 product data sheet for full description of this DAC. FIGURE 14. Two-Channel Analog Input and Output System with TMS320C30. TTL Bit Clock DSP102 XCLK SOUTA ±2.75V Analog Input Channel A 2 ±2.75V Analog Input 25 Channel B VINA SOUTB VINB SYNC SSF CASC DSP202 (4) TMS320C30 16 CLKR-0 20 17 DR-0 22 13 DX-0 14 NC 15 12 12 CLKX-0 FSR-0 11 FSX-0 +5V +5V +5V +5V +5V CONV 21 Conversion Rate Generator (2) 9 10 16 15 XCLK SINA SINB VOUTA SYNC VOUTB 21 ±3V Analog Output Channel A 5 ±3V Analog Output Channel B SSF SWL CASC CONV NOTES: (1) Program TMS320C30 for 32-bit mode. (2) Sample rate on DSP102 and DSP202 may differ. (3) DSP32C may be used in this mode. (4) See Burr-Brown DSP201/202 product data sheet for full description of this DAC. FIGURE 15. Two-Channel Analog Input and Output System with TMS320C30 in Cascade Mode. ® DSP101/102 18 USING TMS320C31 TO GENERATE ALL CONTROL SIGNALS Figure 17 shows a circuit for using the TMS320C31 with a DSP102 and a Burr-Brown DSP202 D/A to provide a two channel analog I/O system. The flexibility of the TMS320C31 allows it to generate the data transfer clock (XCLK) and the Convert Command, minimizing additional circuitry and synchronizing the timing signals to the processor’s master clock. In this circuit, the DSP102 and DSP202 are used in their Cascade modes, transmitting and receiving two channels of data in a single 32-bit word. (See the Cascade Mode section above.) Table II shows how to set up the circuit in Figure 17 for a 44.1kHz conversion rate for both channels of the DSP102 A/D and both channels of the DSP202 D/A. Both inputs and outputs will be simultaneously converted. TTL Bit Clock DSP101 XCLK SYNC 2 ±2.75V Analog Input VIN SOUT SSF CONV TMS320C25 16 XCLK 15 FSX 20 TXD 12 +5V 21 Conversion Rate Generator NOTES: (1) TMS320C25 FSR external, 16-bit data. FIGURE 16. Using DSP101 with TMS320C25. DSP102 ±2.75V Analog Input Channel A XCLK VINA CLKR0 DR0 SOUTA SOUTB ±2.75V Analog Input Channel B VINB CLKX0 XCLK DX0 SINA SINB FSX0 SYNC NC FSR0 SYNC TCLK0 OSC2 DSP202 TMS3200C31 SSF +5V +5V SSF +5V SWL +5V CASC VOUTA ±3V Analog Output Channel A VOUTB ±3V Analog Output Channel B OSC1 1MΩ CASC +5V CONV CONV 12.288MHz 10pF 10pF FIGURE 17. Two Channel Analog I/O Using TMS320C31. SERIAL PORT Port Global Control Register FSX/DX/CLKX Port Control Register FSR/DR/CLKR Port Control Register Receive/Transmit Timer Control Register 0x0EBC040 0x00000111 0x00000111 0x0000000F TIMER Timer Global Control Register Timer Period Register 0x000002C1 0x000000B5 NOTE: Assumes TMS320C31 has 32MHz Master Clock. TABLE II. TMS320C31 Register Settings for 44.1kHz Conversion Rate in Figure 17. ® 19 DSP101/102 USING DSP101 AND DSP102 WITH MOTOROLA DSP ICS Figure 18 shows how to use the DSP101 with a Motorola DSP56001. Using the DSP102 requires using two DSP56001s. The DSP56001 needs to be programmed to receive data MSB-first with SYNC in the Bit Mode. DSP102 with the DSP16 and DSP32C in different modes. The AT&T processors need to be programmed to accept data MSB-first, and the DSP101 or DSP102 needs to have SSF (pin 12) tied LOW, so that an appropriate active Low synchronization pulse will be transmitted by the A/D after a convert command is received. SSF (pin 12) needs to be tied HIGH for using either the DSP101 or the DSP102 with DSP56001s. This will cause the DSP101 or DSP102 to transmit an appropriate active High synchronization pulse on SYNC (pin 15) after a convert command is received by the A/D. Timing is shown in Figure 1. Figures 19 and 20 show the DSP32C and DSP16 respectively used with the DSP101 to handle a single analog input channel. Figure 21 shows how to transmit to a single DSP32C conversion results from both DSP102 channels in a single 32-bit word, using the Cascade mode on the A/D. Figure 11 indicates how to build a complete analog input and analog output system using a DSP32C or DSP16 with a DSP101 and a Burr-Brown DSP201 D/A. USING DSP101 AND DSP102 WITH AT&T DSP ICS Figures 11, 19, 20, and 21 show how to use the DSP101 and TTL Bit Clock DSP56001 DSP101 XCLK SYNC ±2.75V Analog Input 2 SOUT VIN SSF CONV 16 SCK 15 FSR (SC2) 20 12 SRD +5V 21 Conversion Rate Generator NOTES: (1) DSP56001 programmed for MSB bit first data. (2) DSP56001 data may be either 16-bit or 24-bit. FIGURE 18. Using DSP101 with DSP56001. TTL Bit Clock DSP32C DSP101 XCLK SYNC ±2.75V Analog Input 2 VIN SOUT SSF CONV 16 ICK 15 ILD 20 DATA IN 12 21 Conversion Rate Generator NOTE: (1) DSP32C programmed for MSB bit first 16-bit data. FIGURE 19. Using DSP101 with DSP32C. ® DSP101/102 20 USING DSP101 AND DSP102 WITH ADI DSP ICS When using the DSP101 or DSP102 with the fixed-point ADSP21xx series, the processors need to be programmed to receive data MSB-first. The same basic circuit can be used to connect a DSP101 to the ADSP2101. Figure 11 indicates how to build a complete analog I/O system using either the ADSP2101 or the ADSP2105 with a DSP101 and a Burr-Brown DSP201 D/A. Figure 22 shows how to use the DSP102 with an ADSP2101 to provide a two-channel simultaneous sampling system. The two serial ports on the ADSP2101 can also be used with the DSP102 and the Burr-Brown DSP202 D/A to make two complete analog I/O channels, as indicated in footnote 2 of Figure 14. Figure 23 shows the connections required to generate an analog input channel using an ADSP2105 with the DSP101. TTL Bit Clock DSP101 XCLK SOUT 2 ±2.75V Analog Input DSP16 16 ICK 20 DATA IN VIN SYNC SSF CONV 15 ILD 12 21 Conversion Rate Generator NOTE: DSP16 programmed for MSB bit first, 16-bit data. FIGURE 20. Using DSP101 with DSP16. TTL Bit Clock DSP32C DSP102 XCLK SYNC ±2.75V Analog Input Channel A ±2.75V Analog Input Channel B 2 25 VINA VINB SOUTA SOUTB CASC SSF CONV 16 ICK 15 ILD 20 17 22 DATA IN NC +5V 12 21 Conversion Rate Generator NOTES: (1) DSP32C programmed 32-bit data MSB bit first. (2) Data format is Channel A, 16 bits, MSB first, then Channel B. FIGURE 21. Using DSP102 with DSP32C in Cascade Mode. ® 21 DSP101/102 TTL Bit Clock DSP102 XCLK SYNC ±2.75V Analog Input Channel A ±2.75V Analog Input Channel B 2 25 VINA SOUTA VINB SOUTB CASC SSF CONV ADSP-2101 16 SCLK-0 SCLK-1 RFS-0 RFS-1 DR-0 15 20 17 DR-1 22 12 +5V 21 Conversion Rate Generator FIGURE 22. Using DSP102 with ADSP-2101. TTL Bit Clock DSP101 XCLK SOUT ±2.75V Analog Input 2 ADSP-2105 16 SCLK 20 DR 15 RFS VIN SYNC SSF CONV 12 +5V 21 Conversion Rate Generator FIGURE 23. Using DSP101 with ADSP-2105. DEM-DSP102/202 EVALUATION BOARD An evaluation fixture, the DEM-DSP102/202, is available to simplify evaluation of the DSP101 and DSP102, and the companion digital-to-analog converters, the single DSP201 and dual DSP202. The DEM-DSP102/202 comes complete with a socketed DSP102 and DSP202, a breadboard area, TTL I/O headers and differential line drivers for data trans- fer options, a complete clocking circuit for the conversion clock and bit clock, and analog filter modules. The board makes it easy to go from design concept to working prototype of a DSP-based system, offering two complete analog I/O channels. Contact your local Burr-Brown representative for a full data sheet on the DEM-DSP102/202. ® DSP101/102 22